OPA604 OPA 604 OPA 604 SBOS019A – JANUARY 1992 – SEPTEMBER 2003 FET-Input, Low Distortion OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● LOW DISTORTION: 0.0003% at 1kHz LOW NOISE: 10nV/√Hz HIGH SLEW RATE: 25V/µs WIDE GAIN-BANDWIDTH: 20MHz UNITY-GAIN STABLE WIDE SUPPLY RANGE: VS = ±4.5 to ±24V PROFESSIONAL AUDIO EQUIPMENT PCM DAC I/V CONVERTERS SPECTRAL ANALYSIS EQUIPMENT ACTIVE FILTERS TRANSDUCER AMPLIFIERS DATA ACQUISITION ● DRIVES 600Ω LOAD ● DUAL VERSION AVAILABLE (OPA2604) (7) V+ DESCRIPTION The OPA604 is a FET-input operational amplifier designed for enhanced AC performance. Very low distortion, low noise and wide bandwidth provide superior performance in high quality audio and other applications requiring excellent dynamic performance. New circuit techniques and special laser trimming of dynamic circuit performance yield very low harmonic distortion. The result is an op amp with exceptional sound quality. The lownoise FET input of the OPA604 provides wide dynamic range, even with high source impedance. Offset voltage is laser-trimmed to minimize the need for interstage coupling capacitors. The OPA604 is available in 8-pin plastic mini-DIP and SO-8 surface-mount packages, specified for the –25°C to +85°C temperature range. (+) (3) (–) (2) Distortion Rejection Circuitry(1) Output Stage(1) (6) VO (5) (1) (4) V– NOTE: (1) Patents Granted: #5053718, 5019789 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1992-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... ±25V Input Voltage ............................................................... (V–)–1V to (V+)+1V Output Short Circuit to Ground ................................................ Continuous Operating Temperature .................................................. –40°C to +100°C Storage Temperature ...................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) AP .......................................... +300°C Lead Temperature (soldering, 3s) AU ............................................ +260°C PIN CONFIGURATION Top View 2 DIP, SOIC Any integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Offset Trim 1 8 No Internal Connection PACKAGE/ORDERING INFORMATION –In 2 7 +VS +In 3 6 Output For the most current package and ordering information, see to the Package Option Addendum at the end of this data sheet. –VS 4 5 Offset Trim OPA604 www.ti.com SBOS019A ELECTRICAL CHARACTERISTICS TA = +25°C, VS = ±15V, unless otherwise noted. OPA604AP, AU PARAMETER OFFSET VOLTAGE Input Offset Voltage Average Drift Power Supply Rejection INPUT BIAS CURRENT(1) Input Bias Current Input Offset Current CONDITION MIN TYP MAX UNITS ±5 80 ±1 ±8 100 mV µV/°C dB VS = ±5 to ±24V VCM = 0V VCM = 0V NOISE Input Voltage Noise Noise Density: f = 10Hz f = 100Hz f = 1kHz f = 10kHz Voltage Noise, BW = 20Hz to 20kHz Input Bias Current Noise Current Noise Density, f = 0.1Hz to 20kHz INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection VCM = ±12V ±12 80 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.01% 0.1% Total Harmonic Distortion + Noise (THD+N) OUTPUT Voltage Output Current Output Short Circuit Current Output Resistance, Open-Loop VO = ±10V, RL = 1kΩ 80 G = 100 20VPP, RL = 1kΩ G = –1, 10V Step 15 G = 1, f = 1kHz VO = 3.5Vrms, RL = 1kΩ RL = 600Ω VO = ±12V POWER SUPPLY Specified Operating Voltage Operating Voltage Range Current ±11 ±4.5 TEMPERATURE RANGE Specification Storage Thermal Resistance(2), θJA 50 ±3 pA pA 25 15 11 10 1.5 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVPP 4 fA/√Hz ±13 100 V dB 1012 || 8 1012 || 10 Ω || pF Ω || pF 100 dB 20 25 1.5 1 0.0003 MHz V/µs µs µs % ±12 ±35 ±40 25 V mA mA Ω ±15 ±5.3 –25 –40 ±24 ±7 +85 +125 90 V V mA °C °C °C/W NOTES: (1) Typical performance, measured fully warmed-up. (2) Soldered to circuit board—see text. OPA604 SBOS019A www.ti.com 3 TYPICAL CHARACTERISTICS TA = +25°C, VS = ±15V, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 THD + N (%) 0.1 Measurement BW = 80kHz See “Distortion Measurements” for description of test method. VO G = 100V/V 0.01 See “Distortion Measurements” for description of test method. 1kΩ 0.01 THD + N (%) VO = 3.5Vrms 1kΩ 0.1 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE f = 1kHz Measurement BW = 80kHz 0.001 G = 10V/V 0.001 G = 1V/V 0.0001 20 100 1k 10k 0.0001 0.1 20k 1 10 100 Frequency (Hz) Output Voltage (VPP) OPEN-LOOP GAIN/PHASE vs FREQUENCY INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY 0 120 1k 1k –90 40 –135 G 20 100 10 10 Current Noise 1 –20 10 100 1k 10k 100k 1M 1 10M 10 100 INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE 100 100 10 Input Offset Current –50 –25 0 25 50 75 1 100 10nA Input Bias Current (pA) 1nA Input Bias Current 1nA 1 –75 1 1M 100k INPUT BIAS AND INPUT OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10nA Input Offset Current (pA) 100nA 10 10k Frequency (Hz) Frequency (Hz) 10nA 1k 1nA Input Bias Current 1nA 100 100 10 Input Offset Current 0.1 125 10 –15 Ambient Temperature (°C) –10 –5 0 5 10 Input Offset Current (pA) 1 Input Bias Current (pA) 100 Voltage Noise –180 0 4 Current Noise (fA/ Hz) φ 60 Phase Shift (Degrees) Voltage Gain (dB) –45 80 Voltage Noise (nV/ Hz) 100 1 15 Common-Mode Voltage (V) OPA604 www.ti.com SBOS019A TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VS = ±15V, unless otherwise noted. COMMON-MODE REJECTION vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TIME FROM POWER TURN-ON 120 1nA 100 Common-Mode Rejection (dB) Input Bias Current (pA) VS = ±24V VS = ±15V VS = ±5V 10 110 100 90 80 –15 1 0 1 2 3 4 5 –10 Time After Power Turn-On (min) POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY 80 80 CMR –PSR 60 60 40 40 20 20 1k 10k 100k 10 1M CMR 100 PSR 90 AOL 80 70 0 10M 10 5 15 20 Frequency (Hz) Supply Voltage (±VS) GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 28 15 110 AOL, PSR, CMR (dB) 100 100 5 AOL, PSR, AND CMR vs SUPPLY VOLTAGE 100 0 10 0 120 120 +PSR Common-Mode Rejection (dB) Power Supply Rejection (dB) 120 –5 Common-Mode Voltage (V) 25 28 33 30 29 Slew Rate 20 25 16 21 12 5 10 15 20 25 20 20 16 12 –75 17 25 Gain-Bandwidth G = +100 –50 –25 0 15 25 50 75 100 10 125 Temperature (°C) Supply Voltage (±VS) OPA604 SBOS019A 24 Slew Rate (V/µs) Gain-Bandwidth G = +100 Gain-Bandwidth (MHz) 24 Slew Rate (V/µs) Gain-Bandwidth (MHz) Slew Rate www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VS = ±15V, unless otherwise noted. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY SETTLING TIME vs CLOSED-LOOP GAIN 30 5 VO = 10V Step RL = 1kΩ CL = 50pF VS = ±15V Output Voltage (Vp-p) Settling Time (µs) 4 3 0.01% 2 0.1% 20 10 1 0 0 –1 –10 –100 100k 10k –1000 1M 10M Closed-Loop Gain (V/V) Frequency (Hz) SUPPLY CURRENT vs TEMPERATURE LARGE-SIGNAL TRANSIENT RESPONSE +10 VS = ±15V 6 Output Voltage (V) Supply Current (mA) 7 VS = ±24V 5 VS = ±5V 4 3 −75 −50 −25 0 25 50 75 100 –10 125 5 0 10 Ambient Temperature (°C) SMALL-SIGNAL TRANSIENT RESPONSE SHORT-CIRCUIT CURRENT vs TEMPERATURE Short-Circuit Current (mA) 60 Output Voltage (V) +100 –100 ISC+ and ISC– 50 40 30 20 0 1 –75 2 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 6 OPA604 www.ti.com SBOS019A TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VS = ±15V, unless otherwise noted. MAXIMUM POWER DISSIPATION vs TEMPERATURE POWER DISSIPATION vs SUPPLY VOLTAGE 1.4 0.5 Worst case sine wave RL = 600Ω 0.40 0.35 Total Power Dissipation (W) Power Dissipation (W) 0.45 Typical high-level music RL = 600Ω 0.30 0.25 0.20 No signal or no load 0.15 θJ-A = 90°C/W Soldered to Circuit Board (see text) 1.2 1.0 0.8 0.6 Maximum Specified Operating Temperature 85°C 0.4 0.2 0.10 0 0.05 6 8 10 12 14 16 18 20 22 0 24 APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA604 offset voltage is laser-trimmed and will require no further trim for most applications. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. The OPA604 can replace many other amplifiers by leaving the external null circuit unconnected. The OPA604 is unity-gain stable, making it easy to use in a wide range of circuitry. Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins. In most cases, a 1µF tantalum capacitor at each power supply pin is adequate. +VCC 7 2 OPA604 3 5 4 6 ±50mV Typical Trim Range 75 100 125 150 Op amp distortion can be considered an internal error source which can be referred to the input. Figure 2 shows a circuit which causes the op amp distortion to be 101 times greater than normally produced by the op amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for error correction is reduced by a factor of 101. This extends the measurement limit, including the effects of the signal-source purity, by a factor of 101. Note that the input signal and load applied to the op amp are the same as with conventional feedback without R3. Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency where the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were made with the Audio Precision System One, which greatly simplifies such repetitive measurements. The measurement technique can, however, be performed with manual distortion measurement instruments. CAPACITIVE LOADS NOTE: (1) 50kΩ to 1MΩ Trim Potentiometer (100kΩ Recommended) FIGURE 1. Offset Voltage Trim. DISTORTION MEASUREMENTS The distortion produced by the OPA604 is below the measurement limit of virtually all commercially available equipment. A special test circuit, however, can be used to extend the measurement capabilities. The dynamic characteristics of the OPA604 have been optimized for commonly encountered gains, loads and operating conditions. The combination of low closed-loop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations. Load capacitance reacts with the op amp’s open-loop output resistance to form an additional pole in the feedback loop. Figure 3 shows various circuits which preserve phase margin with capacitive load. For details of analysis techniques and applications circuits, refer to application bulletin AB-028 (SBOA015) located at www.ti.com. OPA604 SBOS019A 50 1 (1) –VCC 25 Ambient Temperature (°C) Supply Voltage, ±VS (V) www.ti.com 7 For the unity-gain buffer, Figure 3a, stability is preserved by adding a phase-lead network, RC and CC. Voltage drop across RC will reduce output voltage swing with heavy loads. An alternate circuit, Figure 3b, does not limit the output with low load impedance. It provides a small amount of positive feedback to reduce the net feedback factor. Input impedance of this circuit falls at high frequency as op amp gain rolloff reduces the bootstrap action on the compensation network. Figures 3c and 3d show compensation techniques for noninverting amplifiers. Like the follower circuits, the circuit in Figure 3d eliminates voltage drop due to load current, but at the penalty of somewhat reduced input impedance at high frequency. Figures 3e and 3f show input lead compensation networks for inverting and difference amplifier configurations. NOISE PERFORMANCE Op amp noise is described by two parameters—noise voltage and noise current. The voltage noise determines the noise performance with low source impedance. Low noise bipolar-input op amps such as the OPA27 and OPA37 provide very low voltage noise. But if source impedance is greater than a few thousand ohms, the current noise of R1 bipolar-input op amps react with the source impedance and will dominate. At a few thousand ohms source impedance and above, the OPA604 will generally provide lower noise. POWER DISSIPATION The OPA604 is capable of driving a 600Ω load with powersupply voltages up to ±24V. Internal power dissipation is increased when operating at high power supply voltage. The typical characteristic curve, Power Dissipation vs Power Supply Voltage, shows quiescent dissipation (no signal or no load) as well as dissipation with a worst case continuous sine wave. Continuous high-level music signals typically produce dissipation significantly less than worst-case sine waves. Copper leadframe construction used in the OPA604 improves heat dissipation compared to conventional plastic packages. To achieve best heat dissipation, solder the device directly to the circuit board and use wide circuit board traces. OUTPUT CURRENT LIMIT Output current is limited by internal circuitry to approximately ±40mA at 25°C. The limit current decreases with increasing temperature as shown in the typical curves. R2 SIG. DIST. GAIN GAIN R1 R2 R3 101 ∞ 5kΩ 50Ω 10 101 500Ω 5kΩ 500Ω 100 101 50Ω 5kΩ ∞ 1 R3 OPA604 Generator Output VO = 10Vp-p (3.5Vrms) Analyzer Input Audio Precision System One Analyzer(1) RL 1kΩ IBM PC or Compatible NOTE: (1) Measurement BW = 80kHz FIGURE 2. Distortion Test Circuit. 8 OPA604 www.ti.com SBOS019A (a) (b) CC 820pF RC ei CC 0.47µF 750Ω CL 5000pF CC = eo OPA604 eo OPA604 R2 RC 2kΩ 10Ω CL 5000pF ei 120 X 10–12 CL RC = CC = R2 4CL X 1010 – 1 CL X 103 RC (c) (d) R1 R2 R1 R2 10kΩ 10kΩ 2kΩ 2kΩ CC RC 20Ω 24pF CC 0.22µF RC eo OPA604 ei CL 5000pF 50 CL R2 CC = OPA604 eo ei 25Ω RC = CC = CL 5000pF R2 2CL X 1010 – (1 + R2/R1) CL X 103 RC (e) (f) R2 R1 R2 2kΩ 2kΩ e1 2kΩ R1 RC 20Ω ei 2kΩ eo OPA604 RC 20Ω OPA604 CC 0.22µF CL 5000pF CC 0.22µF R3 R4 2kΩ 2kΩ eo CL 5000pF e2 RC = R2 2CL X 1010 – (1 + R2/R1) RC = CC = 103 CL X RC CC = R2 2CL X 1010 – (1 + R2/R1) CL X 103 RC NOTE: Design equations and component values are approximate. User adjustment is required for optimum performance. FIGURE 3. Driving Large Capacitive Loads. OPA604 SBOS019A www.ti.com 9 R4 22kΩ C3 R1 R2 100pF R3 VIN 2.7kΩ 22kΩ C1 3000pF OPA604 10kΩ VO C2 2000pF fp = 20kHz FIGURE 4. Three-Pole Low-Pass Filter. R1 R5 OPA604 VO VIN 6.04kΩ 2kΩ R2 4.02kΩ R2 4.02kΩ C3 1000pF 1 Low-pass 3-pole Butterworth f–3dB = 40kHz 2 OPA2604 1 2 OPA2604 C1 1000pF R4 5.36kΩ See Application Bulletin AB-026 for information on GIC filters. C2 1000pF FIGURE 5. Three-Pole Generalized Immittance Converter (GIC) Low-Pass Filter. 1 7.87kΩ 2 10kΩ 10kΩ OPA2604 – VIN 100pF OPA604 VO G=1 + 1 7.87kΩ 100kHz Input Filter 2 OPA2604 10kΩ 10kΩ FIGURE 6. Differential Amplifier with Low-Pass Filter. 10 OPA604 www.ti.com SBOS019A 100Ω 10kΩ NOTE: (1) C1 ≈ COUT 2π Rf fc RF = Internal feedback resistance = 1.5kΩ fC = Crossover frequency = 8MHz G = 101 (40dB) 10 OPA604 5 PCM63 20-bit 6 D/A Converter 9 Piezoelectric Transducer 1MΩ(1) C1(1) OPA604 VO = ±3Vp To low-pass filter. NOTE: (1) Provides input bias current return path. FIGURE 7. High Impedance Amplifier. FIGURE 8. Digital Audio DAC I-V Amplifier. OPA604 A2 I2 R4 OPA604 R3 51Ω 51Ω A1 VIN IL = I1 + I2 R2 I1 VOUT Load R1 VOUT = VIN (1+R2/R1) FIGURE 9. Using Two OPA604 Op Amps to Double the Output Current to a Load. OPA604 SBOS019A www.ti.com 11 SOUND QUALITY The following discussion is provided, recognizing that not all measured performance behavior explains or correlates with listening tests by audio experts. The design of the OPA604 included consideration of both objective performance measurements, as well as an awareness of widely held theory on the success and failure of previous op amp designs. I1 800µA R2 75Ω R1 75Ω R5 500Ω J1 J2 J3 1 VBE = 1kHz + DC Bias FFT IC VO IC V (mA) BE 0 1 0.65 VBE (V) 0 3fO 4fO 1 2 3 4 Frequency (kHz) 5fO 5 VGS –ID (mA) log (VO) VO ID fO 0 1 0 VGS (V) 0 2fO 3fO 4fO 1 2 3 4 Frequency (kHz) Q1 Q3 Output Stage Q2 Q4 R11 10kΩ R3 1kΩ R4 1kΩ R8 3kΩ R9 3kΩ THE OPA604 DESIGN The OPA604 uses FETs throughout the signal path, including the input stage, input-stage load, and the important phase-splitting section of the output stage. Bipolar transistors are used where their attributes, such as current capability are important, and where their transfer characteristics have minimal impact. The topology consists of a single folded-cascode gain stage followed by a unity-gain output stage. Differential input transistors J1 and J2 are special large-geometry, P-channel JFETs. Input stage current is a relatively high 800µA, providing high transconductance and reducing voltage noise. Laser trimming of stage currents and careful attention to symmetry yields a nearly symmetrical slew rate of ±25V/µs. The drains of J1 and J2 are cascoded by Q1 and Q2, driving the input stage loads, FETs J3 and J4. Distortion reduction circuitry (patented) linearizes the openloop response and increases voltage gain. The 20MHz bandwidth of the OPA604 further reduces distortion through the user-connected feedback loop. VGS = 1kHz + DC Bias FFT 1 2fO R10 10kΩ J5 The JFET input stage holds input bias current to approximately 50pA or roughly 3000 times lower than common bipolar-input audio op amps. This dramatically reduces noise with high-impedance circuitry. log (VO) fO 0 J4 Distortion Rejection Circuitry SOUND QUALITY Many audio experts believe that the sound quality of a high performance FET op amp is superior to that of bipolar op amps. A possible reason for this is that bipolar designs generate greater odd-order harmonics than FETs. To the human ear, odd-order harmonics have long been identified as sounding more unpleasant than even-order harmonics. FETs, like vacuum tubes, have a square-law I-V transfer function which is more linear than the exponential transfer function of a bipolar transistor. As a direct result of this square-law characteristic, FETs produce predominantly even-order harmonics. Figure 10 shows the transfer function of a bipolar transistor and FET. Fourier transformation of both transfer functions reveals the lower odd-order harmonics of the FET amplifier stage. 200µA R7 4kΩ (+) (–) The sound quality of an op amp is often the crucial selection criteria—even when a data sheet claims exceptional distortion performance. By its nature, sound quality is subjective. Furthermore, results of listening tests can vary depending on application and circuit configuration. Even experienced listeners in controlled tests often reach different conclusions. I2 R6 500Ω The output stage consists of a JFET phase-splitter loaded into high speed all-NPN output drivers. Output transistors are biased by a special circuit to prevent cutoff, even with full output swing into 600Ω loads. 5fO 5 FIGURE 10. I-V and Spectral Response of NPN and JFET. 12 OPA604 www.ti.com SBOS019A PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA604AP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA604APG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA604AU ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA604AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA604AU/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA604AUE4 ACTIVE SOIC D 8 100 CU NIPDAU Level-3-260C-168 HR Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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