Revised December 1998 74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs General Description Features The ACTQ563 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The ACTQ563 is functionally identical to the ACTQ573, but with inverted outputs. The ACTQ563 utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. ■ ICC and IOZ reduced by 50% ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Improved latch-up immunity ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors ■ Outputs source/sink 24 mA ■ Faster prop delays than standard ACT563 ■ Functionally identical to the ACTQ573 but with inverted outputs Ordering Code: Order Number Package Number 74ACTQ563PC N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP IEEE/IEC Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010631.prf www.fairchildsemi.com 74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs January 1990 74ACTQ563 Functional Description the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches. The ACTQ563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on Function Table Inputs Internal Outputs Q O Function X X Z High-Z L H Z High-Z LE D H X H H H H H L Z High-Z H L X NC Z Latched L H L H H Transparent L H H L L Transparent L L X NC NC OE Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Junction Temperature (TJ) PDIP −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V Recommended Operating Conditions −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) −0.5V to VCC + 0.5V Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 140°C 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t −0.5V to VCC + 0.5V 125 mV/ns VIN from 0.8V to 2.0V DC Output Source ± 50 mA or Sink Current (IO) VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) −65°C to +150°C DC Latchup Source ± 300 mA or Sink Current DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V Conditions VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = − 50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 4.86 4.76 IOH = − 24 mA (Note 2) Maximum LOW Level 4.5 0.001 0.1 0.1 IOUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 0.36 0.44 5.5 VOL VIN = VIL or VIH 4.5 V IOL = 24 mA 5.5 0.36 0.44 IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA IOL = 24 mA (Note 2) VI = VCC, GND IOZ Maximum 3-STATE 5.5 ± 0.25 ± 2.5 µA VI = VIL, VIH 1.5 mA VI = VCC − 2.1V VOLD = 1.65V Max VO = VCC, GND Leakage Current ICCT Maximum ICC/Input 5.5 0.6 IOLD Minimum Dynamic 5.5 75 mA IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 40.0 µA VIN = VCC or GND VOLP Quiet Output 5.0 4.0 1.1 1.5 V Maximum Dynamic VOL VOLV Quiet Output Figure 1, Figure 2 (Note 4)(Note 5) 5.0 −0.6 −1.2 V Figure 1, Figure 2 (Note 4)(Note 5) Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. 3 www.fairchildsemi.com 74ACTQ563 Absolute Maximum Ratings(Note 1) 74ACTQ563 DC Electrical Characteristics (Continued) Note 6: Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3V. Input-under-test switching; 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 4 TA = +25°C Symbol TA = −40°C to +85°C CL = 50 pF VCC Parameter CL = 50 pF (Note 7) Min Typ Max Min Max tPHL Propagation Delay 3.3 2.5 8.5 11.5 2.5 12.0 tPLH Dn to On 5.0 1.5 5.5 7.5 1.5 8.0 tPLH Propagation Delay 3.3 2.5 8.5 13.0 2.5 13.5 tPHL LE to On 5.0 2.0 6.0 8.5 2.0 9.0 tPZL Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 5.0 1.5 6.0 8.5 1.5 9.0 tPZH Output Disable Time tPHZ tPLZ 3.3 1.0 9.0 14.5 1.0 15.0 5.0 1.0 6.5 9.5 1.0 10.0 tOSHL Output to Output Skew (Note 8) 3.3 1.0 1.5 1.5 tOSLH Dn to On 5.0 0.5 1.0 1.0 Units ns ns ns ns ns Note 7: Voltage Range 5.0 is 5.0V ±0.5V and 3.3 is 3.3V ± 0.3V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 9) tS tH tW TA = −40°C to +85°C CL = 50 pF Typ Setup Time, HIGH or LOW 3.3 0 3.0 3.0 Dn to LE 5.0 0 3.0 3.0 Hold Time, HIGH or LOW 3.3 0 1.5 1.5 Dn to LE 5.0 0 1.5 1.5 LE Pulse Width, HIGH Units Guaranteed Minimum 3.3 2.0 4.0 4.0 5.0 2.0 4.0 4.0 ns ns ns Note 9: Voltage Range 5.0 is 5.0V ±0.5V and 3.3V is 3.3 ± 0.3V. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 42 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74ACTQ563 AC Electrical Characteristics 74ACTQ563 FACT Noise Characteristics VOLP/VOLV and VOHP/VOHV: The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with a n oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted