Revised November 1999 74ACTQ16540 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description Features The ACTQ16540 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. ■ Utilizes Fairchild FACT Quiet Series technology The ACTQ16540 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance. ■ Outputs source/sink 24 mA ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin output skew ■ Separate control logic for each byte ■ Additional specs for multiple output switching ■ Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number 74ACTQ16540SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ACTQ16540MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Description Names OEn Output Enable Input (Active LOW) I0–I15 Inputs O0–O15 Outputs FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010927 www.fairchildsemi.com 74ACTQ16540 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs May 1991 74ACTQ16540 Functional Description Truth Tables The ACTQ16540 contains sixteen inverting buffers with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Inputs OE1 Outputs OE2 I0–I7 L L H L H X X Z X H X Z L L L H Inputs OE3 www.fairchildsemi.com 2 Outputs OE4 I8–I15 O8–O15 L L H L H X X Z X H X Z L L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram O0–O7 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) Minimum Input Edge Rate (∆V/∆t) VCC @ 4.5V, 5.5V ± 50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 50 mA per Output Pin 125 mV/ns VIN from 0.8V to 2.0V DC VCC or Ground Current −65°C to +150°C Storage Temperature 0V to VCC −40°C to +85°C Operating Temperature (TA) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) VO = −0.5V 4.5V to 5.5V Input Voltage (VI) DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC (V) TA = +25°C Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.5 ± 5.0 µA ± 0.1 ± 1.0 µA VI = VCC, GND 1.5 mA VI = VCC − 2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOZ Maximum 3-STATE Leakage Current IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 ICC Max Quiescent Supply Current 5.5 IOLD Minimum Dynamic IOHD Output Current (Note 3) VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VOHP Maximum Overshoot VOHV Minimum VCC Droop 0.6 8.0 5.5 IOL = 24 mA (Note 2) 5.0 0.5 0.8 V 5.0 −0.5 −1.0 V 5.0 VOH + 1.0 VOH + 1.5 V 5.0 VOH − 1.0 VOH − 1.8 V VI = VIL, VIH VO = VCC, GND VOHD = 3.85V Min Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) VIHD Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7) VILD Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7) Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (VILD). 3 www.fairchildsemi.com 74ACTQ16540 Absolute Maximum Ratings(Note 1) 74ACTQ16540 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 8) tPLH Propagation Delay tPHL Data to Output tPZH Output Enable tPZL Time tPHZ Output Disable tPLZ Time 5.0 5.0 5.0 Typ TA = −40°C to +85°C CL = 50 pF Min Max Min Units Max 2.7 4.9 7.3 2.7 7.8 3.0 5.1 7.3 3.0 7.8 2.5 4.8 7.4 2.5 7.9 2.7 5.3 8.0 2.7 8.5 2.5 5.4 8.3 2.5 8.7 2.3 5.0 7.4 2.3 7.9 ns ns ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. Extended AC Electrical Characteristics TA = −40°C to +85°C Symbol Parameter CL = 50 pF TA = −40°C to +85°C VCC 16 Outputs Switching CL = 250 pF (V) (Note 10) (Note 11) (Note 9) tPLH Propagation Delay, tPHL Data to Output tPZH Output Enable Time 5.0 5.0 tPZL tPHZ Output Disable Time 5.0 tPLZ tOSHL Pin to Pin Skew, (Note 14) HL Data to Output tOSLH Pin to Pin Skew, (Note 14) LH Data to Output tOST Pin to Pin Skew, (Note 14) LH/HL Data to Output Min Max Min Max 4.0 Typ 12.6 5.6 15.5 4.0 10.0 5.6 13.6 3.2 10.8 3.4 10.8 3.8 9.5 3.1 9.2 (Note 12) (Note 13) Units ns ns ns 5.0 1.2 ns 5.0 2.5 ns 5.0 4.3 ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 13: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 30 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition for active and enable. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the word generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ16540 FACT Noise Characteristics 74ACTQ16540 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A www.fairchildsemi.com 6 74ACTQ16540 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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