PIC17C75X
High-Performance 8-Bit CMOS EPROM Microcontrollers
Devices included in this data sheet:
Pin Diagrams
LCC
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
VDD
NC
VSS
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
• PIC17C752
• PIC17C756
• Only 58 single word instructions to learn
• All single cycle instructions (121 ns) except for
program branches and table reads/writes which
are two-cycle
• Operating speed:
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
✯
Memory
Program (x16)
Data (x8)
PIC17C752
8K
454
PIC17C756
16K
902
• Hardware Multiplier
• Interrupt capability
• 16 level deep hardware stack
• Direct, indirect, and relative addressing modes
• Internal/external program memory execution
• Capable of addressing 64K x 16 program memory
space
Peripheral Features:
• 50 I/O pins with individual direction control
• High current sink/source for direct LED drive
- RA2 and RA3 are open drain, high voltage
(12V), high current (60 mA), I/O pins
• Four capture input pins
- Captures are 16-bit, max resolution 121 ns
• Three PWM outputs
- PWM resolution is 1- to 10-bits
• TMR0: 16-bit timer/counter with
8-bit programmable prescaler
• TMR1: 8-bit timer/counter
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Two Universal Synchronous Asynchronous
Receiver Transmitters (USART/SCI)
- Independant baud rate generators
• 10-bit, 12 channel analog-to-digital converter
• Synchronous Serial Port (SSP) with SPI™ and
I2C™ modes (including I2C master mode)
1997 Microchip Technology Inc.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIC17C75X
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Device
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
NC
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RF1/AN5
RF0/AN4
AVDD
AVSS
RG3/AN0/VREF+
RG2/AN1/VREFRG1/AN2
RG0/AN3
NC
VSS
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
✯
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
Microcontroller Core Features:
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out Reset
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
CMOS Technology:
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range (2.5V to 6.0V)
• Commercial and Industrial temperature ranges
• Low-power consumption
- < 5 mA @ 5V, 4 MHz
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
Preliminary
DS30264A-page 1
PIC17C75X
PIC17C75X IN 68-PIN LCC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
VDD
NC
VSS
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
Pin Diagrams Cont.’d
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIC17C75X
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF1/AN5
RF0/AN4
AVDD
AVSS
RG3/AN0/VREF+
RG2/AN1/VREFRG1/AN2
RG0/AN3
NC
VSS
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
NC
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
DS30264A-page 2
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
PIC17C75X IN 64-PIN TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIC17C75X
Top View
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF1/AN5
RF0/AN4
AVDD
AVSS
RG3/AN0/VREF+
RG2/AN1/VREFRG1/AN2
RG0/AN3
VSS
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
58
57
56
55
54
53
52
51
50
49
64
63
62
61
60
59
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0
VDD
VSS
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
Pin Diagrams Cont.’d
Applicable to 14 x 14 mm TQFP
Pin Diagrams Cont.’d
PIC17C75X IN 64-PIN Y-SHRINK DIP
1997 Microchip Technology Inc.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIC17C75X
VDD
RC0/AD0
RD7/AD15
RD6/AD14
RD5/AD13
RD4/AD12
RD3/AD11
RD2/AD10
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RF1/AN5
RF0/AN4
AVDD
AVSS
RG3/AN0/VREF+
RG2/AN1/VREFRG1/AN2
RG0/AN3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Preliminary
VSS
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RA4/RX1/DT1
RA5/TX1/CK1
RG6/RX2/DT2
RG7/TX2/CK2
RG5/PWM3
RG4/CAP3
VDD
VSS
DS30264A-page 3
PIC17C75X
Table of Contents
1.0 Overview ........................................................................................................................................................................................ 5
2.0 Device Varieties ............................................................................................................................................................................. 7
3.0 Architectural Overview ................................................................................................................................................................... 9
4.0 On-chip Oscillator Circuit ............................................................................................................................................................. 15
5.0 Reset............................................................................................................................................................................................ 21
6.0 Interrupts...................................................................................................................................................................................... 29
7.0 Memory Organization................................................................................................................................................................... 39
8.0 Table Reads and Table Writes .................................................................................................................................................... 55
9.0 Hardware Multiplier ...................................................................................................................................................................... 61
10.0 I/O Ports....................................................................................................................................................................................... 65
11.0 Overview of Timer resources ....................................................................................................................................................... 85
12.0 Timer0 .......................................................................................................................................................................................... 87
13.0 Timer1, Timer2, Timer3, PWMs and Captures ............................................................................................................................ 91
14.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules...................................................................... 107
15.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 123
16.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 167
17.0 Special Features of the CPU ..................................................................................................................................................... 177
18.0 Instruction Set Summary............................................................................................................................................................ 183
19.0 Development Support ................................................................................................................................................................ 219
20.0 PIC17C752/756 Electrical Characteristics ................................................................................................................................. 223
21.0 PIC17C752/756 DC and AC Characteristics ............................................................................................................................. 249
22.0 Packaging Information ............................................................................................................................................................... 261
Appendix A: Modifications .............................................................................................................................................................. 265
Appendix B: Compatibility .............................................................................................................................................................. 265
Appendix C: What’s New................................................................................................................................................................ 266
Appendix D: What’s Changed ........................................................................................................................................................ 266
Appendix E: I2C Overview........................................................................................................................................................... 267
Appendix F: Status and Control Registers ..................................................................................................................................... 273
Appendix G: PIC16/17 Microcontrollers ......................................................................................................................................... 293
Pin Compatibility ................................................................................................................................................................................ 302
Index .................................................................................................................................................................................................. 303
On-Line Support................................................................................................................................................................................. 317
Reader Response .............................................................................................................................................................................. 318
PIC17C75X Product Identification System......................................................................................................................................... 319
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error, please use the reader
response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30264A-page 4
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
1.0
OVERVIEW
This data sheet covers the PIC17C75X group of the
PIC17CXXX family of microcontrollers. The following
devices are discussed in this data sheet:
• PIC17C752
• PIC17C756
The PIC17C75X devices are 68-Pin, EPROM-based
members of the versatile PIC17CXXX family of
low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC17CXXX has enhanced
core features, 16-level deep stack, and multiple internal
and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a
16-bit wide instruction word with a separate 8-bit wide
data path. The two stage instruction pipeline allows all
instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 58
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance. For mathematical intensive applications
all devices have a single cycle 8 x 8 Hardware Multiplier.
PIC17CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC17C75X devices have up to 902 bytes of RAM and
50 I/O pins. In addition, the PIC17C75X adds several
peripheral features useful in many high performance
applications including:
•
•
•
•
Four timer/counters
Four capture inputs
Three PWM outputs
Two independant Universal Synchronous Asynchronous Receiver Transmitters (USARTs)
• An A/D converter (12 channel, 10-bit resolution)
• A Synchronous Serial Port
(SPI and I2C w/ Master mode)
•
•
•
•
Microprocessor
Microcontroller
Extended microcontroller
Protected microcontroller
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
Brown-out Reset circuitry has also been added to the
device. This allows a device reset to occur if the device
VDD falls below the Brown-out voltage trip point
(BVDD). The chip will remain in Brown-out Reset until
VDD rises above BVDD.
Table 1-1 lists the features of the PIC17CXXX devices.
A UV-erasable CERQUAD-packaged version (compatible with PLCC) is ideal for code development while the
cost-effective One-Time Programmable (OTP) version
is suitable for production in any volume.
The PIC17C75X fits perfectly in applications that
require extremely fast execution of complex software
programs. These include applications ranging from
precise motor control and industrial process control to
automotive, instrumentation, and telecom applications.
The EPROM technology makes customization of application programs (with unique security codes, combinations, model numbers, parameter storage, etc.) fast
and convenient. Small footprint package options
(including die sales) make the PIC17C75X ideal for
applications with space limitations that require high
performance.
An In-circuit Serial Programming (ISP) feature allows:
• Flexibility of programming the software code as
one of the last steps of the manufacturing process
High speed execution, powerful peripheral features,
flexible I/O, and low power consumption all at low cost
make the PIC17C75X ideal for a wide range of embedded control applications.
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LF oscillator is for low frequency crystals and minimizes power
consumption, XT is a standard crystal, and the EC is for
external clock input.
The SLEEP (power-down) mode offers additional
power saving. Wake-up from SLEEP can occur through
several external and internal interrupts and device
resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software malfunction.
1997 Microchip Technology Inc.
There are four configuration options for the device
operational mode:
1.1
Family and Upward Compatibility
The PIC17CXXX family of microcontrollers have architectural enhancements over the PIC16C5X and
PIC16CXX families. These enhancements allow the
device to be more efficient in software and hardware
requirements. Refer to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXXX devices (Appendix B).
1.2
Development Support
The PIC17CXXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler, and
fuzzy logic support tools. For additional information see
Section 19.0.
Preliminary
DS30264A-page 5
PIC17C75X
TABLE 1-1:
PIC17CXXX FAMILY OF DEVICES
Features
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
PIC17C752
PIC17C756
Maximum Frequency
of Operation
Operating Voltage Range
Program Memory (EPROM)
( x16)
(ROM)
Data Memory (bytes)
Hardware Multiplier (8 x 8)
Timer0
(16-bit + 8-bit postscaler)
Timer1 (8-bit)
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
A/D channels (10-bit)
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
2.5 - 6.0V
2K
232
Yes
Yes
2.5 - 6.0V
16 K
232
Yes
Yes
2.5 - 6.0V
4K
454
Yes
Yes
2.5 - 6.0V
4K
454
Yes
Yes
2.5 - 6.0V
8K
454
Yes
Yes
3.0 - 6.0V
8K
454
Yes
Yes
3.0 - 6.0V
16K
902
Yes
Yes
Yes
Yes
Yes
2
2
1
-
Yes
Yes
Yes
2
2
1
-
Yes
Yes
Yes
2
2
1
-
Yes
Yes
Yes
2
2
1
-
Yes
Yes
Yes
2
2
1
-
Yes
Yes
Yes
4
3
2
12
Yes
Yes
Yes
Yes
4
3
2
12
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
Yes
Yes
Yes
11
Yes
33
25 mA
Yes
Yes
Yes
11
Yes
33
25 mA
Yes
Yes
Yes
11
Yes
33
25 mA
Yes
Yes
Yes
11
Yes
33
25 mA
Yes
Yes
Yes
18
Yes
Yes
Yes
50
25 mA
Yes
Yes
Yes
18
Yes
Yes
Yes
50
25 mA
SSP (SPI/I2C w/Master mode)
Power-on Reset
Watchdog Timer
External Interrupts
Interrupt Sources
Code Protect
Brown-out Reset
In-circuit Serial Programming
I/O Pins
I/O High Current
Source
Capability
Sink
25 mA(1)
25 mA(1)
40-pin DIP
40-pin DIP
Package Types
44-pin PLCC 44-pin PLCC
44-pin MQFP 44-pin MQFP
44-pin TQFP 44-pin TQFP
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
DS30264A-page 6
25 mA(1)
25 mA(1)
25 mA(1)
25 mA(1)
40-pin DIP
40-pin DIP
40-pin DIP
64-pin DIP
44-pin PLCC 44-pin PLCC 44-pin PLCC 68-pin LCC
44-pin MQFP 44-pin MQFP 44-pin MQFP 68-pin TQFP
44-pin TQFP 44-pin TQFP 44-pin TQFP
Preliminary
25 mA(1)
64-pin DIP
68-pin LCC
68-pin TQFP
1997 Microchip Technology Inc.
PIC17C75X
2.0
DEVICE VARIETIES
2.1
Each device has a variety of frequency ranges and
packaging options. Depending on application and production requirements, the proper device option can be
selected using the information in the PIC17C75X Product Selection System section at the end of this data
sheet. When placing orders, please use the
“PIC17C75X Product Identification System” at the back
of this data sheet to specify the correct part number.
When discussing the functionality of the device, memory technology and voltage range does not matter.
The UV erasable version, offered in CERQUAD package, is optimal for prototype development and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes.
Microchip's programming of the PIC17C75X. Third
party programmers also are available; refer to the Third
Party Guide for a list of sources.
2.2
There are three memory type options. These are specified in the middle characters of the part number.
1.
2.
3.
C, as in PIC17C756. These devices have
EPROM type memory.
CR, as in PIC17CR756. These devices have
ROM type memory.
F, as in PIC17F756. These devices have Flash
type memory.
All these devices operate over the standard voltage
range. Devices are also offered which operate over an
extended voltage range (and reduced frequency
range). Table 2-1 shows all possible memory types and
voltage range designators for a particular device.
These designators are in bold typeface.
TABLE 2-1:
DEVICE MEMORY
VARIETIES
Voltage Range
Standard
Extended
PIC17CXXX
PIC17LCXXX
PIC17CRXXX
PIC17LCRXXX
PIC17FXXX
PIC17LFXXX
Not all memory technologies are available
for a particular device.
Memory Type
EPROM
ROM
Flash
Note:
UV Erasable Devices
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must be programmed.
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 7
PIC17C75X
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
ROM devices do not allow serialization information in
the program memory space.
For information on submitting ROM code, please contact your regional sales office.
Note:
2.6
Presently, NO ROM versions of the
PIC17C75X devices are available.
Flash Memory Devices
These devices are electrically erasable and, therefore,
can be offered in the low cost plastic package. Being
electrically erasable, these devices can be erased and
reprogrammed in-circuit. These devices are the same
for prototype development, pilot programs, as well as
production.
Note:
Presently, NO Flash versions of the
PIC17C75X devices are available.
DS30264A-page 8
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC17CXXX can be attributed to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC17CXXX uses a modified Harvard architecture.
This architecture has the program and data accessed
from separate memories. So, the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC17CXXX opcodes are 16-bits wide, enabling single
word instructions. The full 16-bit wide program memory
bus fetches a 16-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions execute in a
single cycle (121 ns @ 33 MHz), except for program
branches and two special instructions that transfer data
between program and data memory.
The PIC17CXXX can address up to 64K x 16 of program memory space.
The PIC17C752 integrates 8K x 16 of EPROM program memory on-chip.
The PIC17C756 integrates 16K x 16 EPROM program
memory.
Program execution can be internal only (microcontroller or protected microcontroller mode), external only
(microprocessor mode) or both (extended microcontroller mode). Extended microcontroller mode does not
allow code protection.
The PIC17CXXX can directly or indirectly address its
register files or data memory. All special function registers, including the Program Counter (PC) and Working
Register (WREG), are mapped in the data memory.
The PIC17CXXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC17CXXX simple yet efficient. In addition, the learning curve is
reduced significantly.
One of the PIC17CXXX family architectural enhancements from the PIC16CXX family allows two file registers to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register. Thus
increasing performance and decreasing program
memory usage.
The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature.
The WREG register is an 8-bit working register used for
ALU operations.
All PIC17C75X devices have an 8 x 8 hardware multiplier. This multiplier generates a 16-bit result in a single
cycle.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the ALUSTA register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
Although the ALU does not perform signed arithmetic,
the Overflow bit (OV) can be used to implement signed
math. Signed arithmetic is comprised of a magnitude
and a sign bit. The overflow bit indicates if the magnitude overflows and causes the sign bit to change state.
That is if the result of the signed operation is greater
then 128 (7Fh) or less then -127 (FFh). Signed math
can have greater than 7-bit values (magnitude), if more
than one byte is used. The use of the overflow bit only
operates on bit6 (MSb of magnitude) and bit7 (sign bit)
of the value in the ALU. That is, the overflow bit is not
useful if trying to implement signed math where the
magnitude, for example, is 11-bits. If the signed math
values are greater than 7-bits (15-, 24- or 31-bit), the
algorithm must ensure that the low order bytes ignore
the overflow status bit.
Care should be taken when adding and subtracting
signed numbers to ensure that the correct operation is
executed. Example 3-1 shows an item that must be
taken into account when doing signed arithmetic on an
ALU which operates as an unsigned machine.
EXAMPLE 3-1:
SIGNED MATH
Hex Value
Signed Value
Math
Unsigned Value
Math
FFh
+ 01h
= ?
-127
+
1
= -126 (FEh)
255
+
1
=
0 (00h);
Carry bit = 1
Signed math requires the result to be FEh
(-126). This would be accomplished by
subtracting one as opposed to adding one.
A simplified block diagram is shown in Figure 3-1. The
descriptions of the device pins are listed in Table 3-1.
The PIC17CXXX devices contain an 8-bit ALU and
working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 9
PIC17C75X
FIGURE 3-1:
PIC17C75X BLOCK DIAGRAM
PORTA
RA0/INT
RA1/T0CKI
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
WREG<8>
BITOP
Clock
Generator
Q1, Q2,
Q3, Q4
IR<16>
OSC1,
OSC2
Power-on
Reset
Brown-out VDD, VSS
Reset
PORTB
8 x 8 mult
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
RB7/SDO
Chip_reset
& Other
Control
Signals
ALU
PRODH PRODL
Shifter
Test
8
8
BSR <7:4>
IR <7:0>
PORTC
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
16
F1
F9
12
RAM
Address
Buffer
Data RAM
17C756
902 x 8
17C752
454 x 8
PORTD
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
Test Mode
Select
IR Latch <16>
8
IR<7>
Watchdog
Timer
MCLR, VSS
Read/write
Decode
for
Registers
Mapped
in Data
Space
Instruction
Decode
Control Outputs
ROM Latch <16>
Decode
8
AD<15:0>
PORTC,
PORTD
BSR
Literal
Table
Latch <16>
Data Latch
Program
Memory
(EPROM)
17C756
16K x 16
17C752
8K x 16
PORTE
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
ALE,
WR,
OE,
PORTE
Address
Latch
Table Pointer<16>
PCLATH<8>
System Bus Interface
Data Latch
16
16
PORTF
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
PCH
PCL
16
Stack
16 x 16
16
Data Bus<8>
Timer0
Timer2
USART1
PWM1
PWM3
Capture2
10-bit
A/D
IR<7>
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREFRG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
DS30264A-page 10
SSP
Timer1
Timer3
USART2
PWM2
Preliminary
Capture1
Capture3
Capture4
Interrupt
Module
1997 Microchip Technology Inc.
PIC17C75X
TABLE 3-1:
Name
OSC1/CLKIN
PINOUT DESCRIPTIONS
DIP
No.
Oscillator input in crystal/resonator or RC oscillator mode.
External clock input in external clock mode.
OSC2/CLKOUT
48
51
40
O
—
Oscillator output. Connects to crystal or resonator in crystal
oscillator mode. In RC oscillator or external clock modes
OSC2 pin outputs CLKOUT which has one fourth the frequency (FOSC/4) of OSC1 and denotes the instruction cycle
rate.
MCLR/VPP
15
16
7
I/P
ST
Master clear (reset) input or Programming Voltage (VPP)
input. This is the active low reset input to the chip.
PORTA is a bi-directional I/O Port except for RA0 and RA1
which are input only.
RA0/INT
56
60
48
I
ST
RA0 can also be selected as an external interrupt
input. Interrupt can be configured to be on positive or
negative edge.
RA1/T0CKI
41
44
33
I
ST
RA1 can also be selected as an external interrupt
input, and the interrupt can be configured to be on positive or negative edge. RA1 can also be selected to be
the clock input to the Timer0 timer/counter.
RA2/SS/SCL
42
45
34
I/O
ST
RA2 can also be used as the slave select input for the
SPI or the clock input for the I2C bus.
High voltage, high current, open drain input/output port
pin.
RA3/SDI/SDA
43
46
35
I/O
ST
RA3 can also be used as the data input for the SPI or
the data for the I2C bus.
High voltage, high current, open drain input/output port
pin.
RA4/RX1/DT1
40
43
32
I/O †
ST
RA4 can also be selected as the USART1 (SCI) Asynchronous Receive or USART1 (SCI) Synchronous
Data.
RA5/TX1/CK1
39
42
31
I/O †
ST
RA5 can also be selected as the USART1 (SCI) Asynchronous Transmit or USART1 (SCI) Synchronous
Clock.
PORTB is a bi-directional I/O Port with software configurable weak pull-ups.
RB0/CAP1
55
59
47
I/O
ST
RB0 can also be the Capture1 input pin.
RB1/CAP2
54
58
46
I/O
ST
RB1 can also be the Capture2 input pin.
RB2/PWM1
50
54
42
I/O
ST
RB2 can also be the PWM1 output pin.
RB3/PWM2
53
57
45
I/O
ST
RB3 can also be the PWM2 output pin.
RB4/TCLK12
52
56
44
I/O
ST
RB4 can also be the external clock input to Timer1 and
Timer2.
RB5/TCLK3
51
55
43
I/O
ST
RB5 can also be the external clock input to Timer3.
RB6/SCK
44
47
36
I/O
ST
RB6 can also be used as the master/slave clock for the
SPI.
RB7/SDO
45
48
37
I/O
ST
RB7 can also be used as the data output for the SPI.
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
†
47
PLCC TQFP I/O/P Buffer
Description
No.
No. Type Type
50
39
I
ST
The output is only available by the Peripheral operation.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 11
PIC17C75X
TABLE 3-1:
Name
PINOUT DESCRIPTIONS
DIP
No.
PLCC TQFP I/O/P Buffer
Description
No.
No. Type Type
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
2
63
62
61
60
58
58
57
3
67
66
65
64
63
62
61
58
55
54
53
52
51
50
49
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
10
9
8
7
6
5
4
3
11
10
9
8
7
6
5
4
2
1
64
63
62
61
60
59
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PORTC is a bi-directional I/O Port.
This is also the least significant byte (LSB) of the 16-bit
wide system bus in microprocessor mode or extended
microcontroller mode. In multiplexed system bus configuration, these pins are address output as well as
data input or output.
PORTD is a bi-directional I/O Port.
This is also the most significant byte (MSB) of the
16-bit system bus in microprocessor mode or extended
microprocessor mode or extended microcontroller
mode. In multiplexed system bus configuration these
pins are address output as well as data input or output.
PORTE is a bi-directional I/O Port.
In microprocessor mode or extended microcontroller
mode, RE0 is the Address Latch Enable (ALE) output.
Address should be latched on the falling edge of ALE
output.
RE1/OE
12
13
4
I/O
TTL
In microprocessor or extended microcontroller mode,
RE1 is the Output Enable (OE) control output (active
low).
RE2/WR
13
14
5
I/O
TTL
In microprocessor or extended microcontroller mode,
RE2 is the Write Enable (WR) control output (active
low).
RE3/CAP4
14
15
6
I/O
ST
RE3 can also be the Capture4 input pin.
PORTF is a bi-directional I/O Port.
RF0/AN4
26
28
18
I/O
ST
RF0 can also be analog input 4.
RF1/AN5
25
27
17
I/O
ST
RF1 can also be analog input 5.
RF2/AN6
24
26
16
I/O
ST
RF2 can also be analog input 6.
RF3/AN7
23
25
15
I/O
ST
RF3 can also be analog input 7.
RF4/AN8
22
24
14
I/O
ST
RF4 can also be analog input 8.
RF5/AN9
21
23
13
I/O
ST
RF5 can also be analog input 9.
RF6/AN10
20
22
12
I/O
ST
RF6 can also be analog input 10.
RF7/AN11
19
21
11
I/O
ST
RF7 can slso be analog input 11.
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
RE0/ALE
†
11
12
3
I/O
TTL
The output is only available by the Peripheral operation.
DS30264A-page 12
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 3-1:
PINOUT DESCRIPTIONS
Name
DIP
No.
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
32
31
30
34
33
32
24
23
22
I/O
I/O
I/O
ST
ST
ST
RG3/AN0/VREF+
29
31
21
I/O
ST
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
35
36
38
38
39
41
27
28
30
I/O
I/O
I/O
ST
ST
ST
RG7/TX2/CK2
37
40
29
I/O
ST
TEST
16
17
8
I
ST
VSS
AVSS
17,
33,
49,
64
1,
18,
34,
46
28
AVDD
27
VDD
NC
PLCC TQFP I/O/P Buffer
Description
No.
No. Type Type
19, 9, 25,
36,53, 41, 56
68
P
PORTG is a bi-directional I/O Port.
RG0 can also be analog input 3.
RG1 can also be analog input 2.
RG2 can also be analog input 1, or
the ground reference voltage
RG3 can also be analog input 0, or
the positive reference voltage
RG4 can also be the Capture3 input pin.
RG5 can also be the PWM3 output pin.
RG6 can also be selected as the USART2 (SCI) Asynchronous Receive or USART2 (SCI) Synchronous
Data.
RG7 can also be selected as the USART2 (SCI) Asynchronous Transmit or USART2 (SCI) Synchronous
Clock.
Test mode selection control input. Always tie to VSS for normal operation.
Ground reference for logic and I/O pins.
2, 20,
10,
37,
26,
49, 38, 57
P
Positive supply for logic and I/O pins.
Ground reference for A/D converter.
This pin MUST be at the same potential as VSS.
Positive supply for A/D converter.
This pin MUST be at the same potential as VDD.
No Connect. Leave these pins unconnected.
30
20
P
29
19
P
1, 18,
35, 52
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
†
-
The output is only available by the Peripheral operation.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 13
PIC17C75X
NOTES:
DS30264A-page 14
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
4.0
ON-CHIP OSCILLATOR
CIRCUIT
4.1.2
The internal oscillator circuit is used to generate the
device clock. Four device clock periods generate an
internal instruction clock (TCY). There are four modes
that the oscillator can operate in. These are selected by
the device configuration bits during device programming. These modes are:
• LF
• XT
• EC
• RC
Low Frequency (FOSC <= 2 MHz)
Standard Crystal/Resonator Frequency
(2 MHz <= FOSC <= 33 MHz)
External Clock Input
(Default oscillator configuration)
External Resistor/Capacitor
(FOSC <= 4 MHz)
4.1.2.1
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interrupt.
Several oscillator options are made available to allow
the part to fit the application. The RC oscillator option
saves system cost while the LF crystal option saves
power. Configuration bits are used to select various
options.
Oscillator Configurations
4.1.1
OSCILLATOR TYPES
In XT or LF modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 4-2). The
PIC17CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications.
For frequencies above 20 MHz, it is common for the
crystal to be an overtone mode crystal. Use of overtone
mode crystals require a tank circuit to attenuate the
gain at the fundamental frequency. Figure 4-3 shows
an example circuit.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 96 ms (nominal) on power-up only, designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
reset circuitry.
4.1
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
OSCILLATOR / RESONATOR START-UP
As the device voltage increases from Vss, the oscillator
will start its oscillations. The time required for the oscillator to start oscillating depends on many factors.
These include:
•
•
•
•
•
•
Crystal / resonator frequency
Capacitor values used (C1 and C2)
Device VDD rise time.
System temperature
Series resistor value (and type) if used
Oscillator mode selection of device (which selects
the gain of the internal oscillator inverter)
Figure 4-1 shows an example of a typical oscillator /
resonator start-up. The peak-to-peak voltage of the
oscillator waveform can be quite low (less than 50% of
device VDD) when the waveform is centered at VDD/2
(refer to parameter number D033 and D043 in the electrical specification section).
FIGURE 4-1:
OSCILLATOR / RESONATOR
START-UP
CHARACTERISTICS
The PIC17CXXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
LF
XT
EC
RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
VDD
•
•
•
•
The main difference between the LF and XT modes is
the gain of the internal inverter of the oscillator circuit
which allows the different frequency ranges.
For more details on the device configuration bits, see
Section 17.0.
1997 Microchip Technology Inc.
Preliminary
Crystal Start-up Time
Time
DS30264A-page 15
PIC17C75X
FIGURE 4-2:
CRYSTAL OR CERAMIC
RESONATOR OPERATION (XT
OR LF OSC CONFIGURATION)
FIGURE 4-3:
CRYSTAL OPERATION,
OVERTONE CRYSTALS (XT
OSC CONFIGURATION)
C1
OSC1
OSC1
SLEEP
C1
XTAL
C2
SLEEP
RF
OSC2
OSC2
Note1
C2
PIC17CXXX
To internal
logic
To filter the fundamental frequency
1 =
(2πf)2
LC2
See Table 4-1 and Table 4-2 for recommended values of
C1 and C2.
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
Note 1: A series resistor (Rs) may be required for
AT strip cut crystals.
TABLE 4-1:
CAPACITOR SELECTION
FOR CERAMIC
RESONATORS
TABLE 4-2:
Oscillator
Type
Resonator
Frequency
Capacitor Range
C1 = C2 (1)
LF
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
15 - 68 pF
10 - 33 pF
22 - 68 pF
33 - 100 pF
33 - 100 pF
XT
Note 1: These values include all board capacitances on this pin. Actual capacitor value
depends on board capacitance
Resonators Used:
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
Resonators used did not have built-in capacitors.
Osc
Type
LF
XT
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
PIC17CXXX
0.1 µF
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Freq
C1 (3)
C2 (3)
32 kHz(1)
1 MHz
2 MHz
2 MHz
4 MHz
8 MHz (2)
16 MHz
25 MHz
32 MHz (3)
100-150 pF
10-33 pF
10-33 pF
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10
100-150 pF
10-33 pF
10-33 pF
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10
Higher capacitance increases the stability of the oscillator
but also increases the start-up time and the oscillator current. These values are for design guidance only. RS may be
required in XT mode to avoid overdriving the crystals with
low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal manufacturer for appropriate values for external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.
2: RS of 330Ω is required for a capacitor combination of 15/15 pF.
3: These values include all board capacitances on this pin. Actual capacitor value
depends on board capacitance
Crystals Used:
32.768 kHz
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
25 MHz
32 MHz
DS30264A-page 16
Preliminary
Epson C-001R32.768K-A
ECS-10-13-1
ECS-20-20-1
ECS-40-20-1
ECS ECS-80-S-4
ECS-80-18-1
ECS-160-20-1
CTS CTS25M
CRYSTEK HF-2
± 20 PPM
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
TBD
± 50 PPM
± 50 PPM
1997 Microchip Technology Inc.
PIC17C75X
4.1.3
EXTERNAL CLOCK OSCILLATOR
4.1.4
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the
OSC1/CLKIN pin is hi-impedance and the OSC2/CLKOUT pin is the CLKOUT output (4 TOSC).
FIGURE 4-4:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
CLKOUT
(FOSC/4)
OSC1
PIC17CXXX
OSC2
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 4-5 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could
be used for external oscillator designs.
FIGURE 4-5:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
PIC17CXXX
74AS04
4.7k
OSC1
74AS04
10k
XTAL
10k
20 pF
20 pF
Figure 4-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 4-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330 kΩ
330 kΩ
74AS04
74AS04
To Other
Devices
74AS04
PIC17CXXX
OSC1
0.1 µF
XTAL
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 17
PIC17C75X
4.1.5
RC OSCILLATOR
4.1.5.1
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, oscillator frequency will
vary from unit to unit due to normal process parameter
variation. Furthermore, the difference in lead frame
capacitance between package types will also affect
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation due
to tolerance of external R and C components used.
Figure 4-7 shows how the R/C combination is connected to the PIC17CXXX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values (e.g.
1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
RC START-UP
As the device voltage increases, the RC will immediately start its oscillations once the pin voltage levels
meet the input threshold specifications (parameter
number D032 and D042 in the electrical specification
section). The time required for the RC to start oscillating depends on many factors. These include:
•
•
•
•
Resistor value used
Capacitor value used
Device VDD rise time
System temperature
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package
lead frame capacitance.
See Section 21.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation
will affect RC frequency more for large R) and for
smaller C (since variation of input capacitance will
affect RC frequency more).
See Section 21.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for
given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 4-8 for
waveform).
FIGURE 4-7:
RC OSCILLATOR MODE
VDD
PIC17CXXX
Rext
OSC1
Internal
clock
Cext
VSS
OSC2/CLKOUT
Fosc/4
DS30264A-page 18
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
4.2
Clocking Scheme/Instruction Cycle
4.3
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 4-1).
A fetch cycle begins with the program counter incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 4-8:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 4-1:
PC
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 19
PIC17C75X
NOTES:
DS30264A-page 20
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
5.0
RESET
Note:
The PIC17CXXX differentiates between various kinds
of reset:
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
Brown-out Reset
WDT Reset (normal operation)
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state” on Power-on Reset (POR), Brown-out Reset
(BOR), on MCLR or WDT Reset and on MCLR reset
during SLEEP. A WDT Reset during SLEEP, is viewed
as the resumption of normal operation. The TO and PD
bits are set or cleared differently in different reset situations as indicated in Table 5-3. These bits are used in
software to determine the nature of the reset. See
Table 5-4 for a full description of reset states of all registers.
FIGURE 5-1:
While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 5-1.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR
Module
Brown-out
Reset
WDT
Module
WDT
Time_Out
Reset
VDD rise
detect
S
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
R
OST
Q
10-bit Ripple counter
OSC1
PWRT
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
1997 Microchip Technology Inc.
Enable PWRT
10-bit Ripple counter
Enable OST
On-chip
RC OSC†
Power_Up
(Enable the PWRT timer
only during Power_Up)
(Power_Up) + (Wake_Up) (XT + LF)
(Enable the OST if it is Power_Up or Wake_Up
from SLEEP and OSC type is XT or LF)
Preliminary
DS30264A-page 21
PIC17C75X
5.1
5.1.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST), and Brown-out Reset
(BOR)
5.1.2
POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in reset
until VDD is above the trip point (in the range of 1.4V 2.3V). The devices produce an internal reset for both
rising and falling VDD. To take advantage of the POR,
just tie the MCLR/VPP pin directly (or through a resistor)
to VDD. This will eliminate external RC components
usually needed to create Power-on Reset. A minimum
rise time for VDD is required. See Electrical Specifications for details.
Figure 5-2 and Figure 5-3 show two possible POR circuits.
FIGURE 5-2:
USING ON-CHIP POR
VDD
MCLR
PIC17CXXX
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
VDD
D
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the POR signal and after the first rising edge of
MCLR (detected high). The Power-up Timer operates
on an internal RC oscillator. The chip is kept in RESET
as long as the PWRT is active. In most cases the
PWRT delay allows VDD to rise to an acceptable level.
The power-up time delay will vary from chip to chip and
with VDD and temperature. See DC parameters for
details.
5.1.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay after MCLR is
detected high or a wake-up from SLEEP event occurs.
The OST time-out is invoked only for XT and LF oscillator modes on a Power-on Reset or a Wake-up from
SLEEP.
The OST counts the oscillator pulses on the
OSC1/CLKIN pin. The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds. This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of the time-out is a function of the crystal/resonator frequency.
VDD
FIGURE 5-3:
POWER-UP TIMER (PWRT)
Figure 5-4 shows the operation of the OST circuit. In
this figure the oscillator is of such a low frequency that
OST time out occurs after the power-up timer time-out.
FIGURE 5-4:
OSCILLATOR START-UP
TIME
POR or BOR Trip Point
R
R1
VDD
MCLR
C
PIC17CXXX
MCLR
OSC2
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers
down.
2: R < 40 kΩ is recommended to ensure
that the voltage drop across R does not
exceed 0.2V (max. leakage current spec.
on the MCLR/VPP pin is 5 µA). A larger
voltage drop will degrade VIH level on the
MCLR/VPP pin.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress
(EOS).
DS30264A-page 22
TOSC1
TOST
OST TIME_OUT
PWRT TIME_OUT
TPWRT
INTERNAL RESET
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example the low
frequency crystal start-up time is larger than power-up
time (TPWRT).
Tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the Oscillator Start-up Timer
(ost).
TOST = 1024TOSC.
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
5.1.4
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specification. The use of an external RC delay is sufficient for
many of these applications.
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resonators. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are associated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
TABLE 5-1:
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization conditions for all the registers.
TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up
Wake up from
SLEEP
MCLR Reset
BOR
XT, LF
Greater of: 96 ms or 1024TOSC
1024TOSC
—
—
EC, RC
Greater of: 96 ms or 1024TOSC
—
—
—
TABLE 5-2:
STATUS BITS AND THEIR SIGNIFICANCE
Event
POR
BOR (1)
TO
PD
0
0
1
1
Power-on Reset
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
1
1
0
1
WDT Reset during normal operation
1
1
0
0
WDT Wake-up during SLEEP
1
1
1
1
MCLR Reset during normal operation
1
0
x
x
Brown-out Reset
0
0
0
x
Illegal, TO is set on POR
0
0
x
0
Illegal, PD is set on POR
x
x
1
1
CLRWDT instruction executed
Note 1: When BOR is enabled, else the BOR status bit is unknown
TABLE 5-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
PCH:PCL
CPUSTA (4)
OST Active
Power-on Reset
0000h
--11 1100
Yes
Brown-out Reset
0000h
--11 1101
No
MCLR Reset during normal operation
0000h
--11 1111
No
MCLR Reset during SLEEP
0000h
--11 1011
Yes (2)
Event
WDT Reset during normal operation
WDT Wake-up during SLEEP
(3)
Interrupt wake-up from SLEEP
GLINTD is set
GLINTD is clear
0000h
--11 0111
No
0000h
--11 0011
Yes (2)
PC + 1
--11 1011
Yes (2)
PC + 1 (1)
--10 1011
Yes (2)
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
mid-range devices.
4: When BOR is enabled, else the BOR status bit is unknown.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 23
PIC17C75X
In Figure 5-5, Figure 5-6 and Figure 5-7, TPWRT >
TOST, as would be the case in higher frequency crystals. For lower frequency crystals, (i.e., 32 kHz) TOST
would be greater.
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-7:
SLOW RISE TIME (MCLR TIED TO VDD)
Minimum VDD operating voltage
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30264A-page 24
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Address
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
INDF0
00h
N.A.
N.A.
N.A.
FSR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000h
0000h
PC + 1(2)
PCLATH
03h
0000 0000
0000 0000
uuuu uuuu
ALUSTA
04h
1111 xxxx
1111 uuuu
1111 uuuu
05h
0000 000-
0000 000-
0000 000-
Register
Unbanked
T0STA
(3)
1100(4)
qquu(4)
--uu qquu(4)
CPUSTA
06h
--11
INTSTA
07h
0000 0000
INDF1
08h
N.A.
FSR1
09h
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
0Ah
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0L
0Bh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0H
0Ch
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLPTRL
0Dh
0000 0000
0000 0000
uuuu uuuu
TBLPTRH
0Eh
0000 0000
0000 0000
uuuu uuuu
BSR
0Fh
0000 0000
0000 0000
uuuu uuuu
PORTA
10h
0-xx xxxx
0-uu uuuu
u-uu uuuu
DDRB
11h
1111 1111
1111 1111
uuuu uuuu
PORTB
12h
xxxx xxxx
uuuu uuuu
uuuu uuuu
RCSTA1
13h
0000 -00x
0000 -00u
uuuu -uuu
RCREG1
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA1
15h
0000 --1x
0000 --1u
uuuu --uu
TXREG1
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
SPBRG1
17h
xxxx xxxx
uuuu uuuu
uuuu uuuu
DDRC
10h
1111 1111
1111 1111
uuuu uuuu
PORTC
11h
xxxx xxxx
uuuu uuuu
uuuu uuuu
DDRD
12h
1111 1111
1111 1111
uuuu uuuu
PORTD
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
DDRE
14h
---- 1111
---- 1111
---- uuuu
PORTE
15h
---- xxxx
---- uuuu
---- uuuu
PIR1
16h
x000 0010
u000 0010
uuuu uuuu(1)
PIE1
17h
0000 0000
0000 0000
uuuu uuuu
--11
0000 0000
N.A.
uuuu uuuu(1)
N.A.
Bank 0
Bank 1
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 25
PIC17C75X
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
MCLR Reset
WDT Reset
(Cont.’d)
Wake-up from SLEEP
through interrupt
Address
Power-on Reset
Brown-out Reset
TMR1
10h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR2
11h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
12h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3H
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR1
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR2
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR3/CA1L
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR3/CA1H
17h
xxxx xxxx
uuuu uuuu
uuuu uuuu
10h
xx-- ----
uu-- ----
uu-- ----
PW2DCL
11h
xx0- ----
uu0- ----
uuu- ----
PW1DCH
12h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PW2DCH
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA2L
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA2H
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TCON1
16h
0000 0000
0000 0000
uuuu uuuu
TCON2
17h
0000 0000
0000 0000
uuuu uuuu
PIR2
10h
000- 0010
000- 0010
uuu- uuuu(1)
PIE2
11h
000- 0000
000- 0000
uuu- uuuu
Unimplemented
12h
---- ----
---- ----
---- ----
RCSTA2
13h
0000 -00x
0000 -00u
uuuu -uuu
RCREG2
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA2
15h
0000 --1x
0000 --1u
uuuu --uu
TXREG2
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
SPBRG2
17h
xxxx xxxx
uuuu uuuu
uuuu uuuu
DDRF
10h
1111 1111
1111 1111
uuuu uuuu
PORTF
11h
xxxx xxxx
uuuu uuuu
uuuu uuuu
DDRG
12h
1111 1111
1111 1111
uuuu uuuu
PORTG
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
14h
0000 -0-0
0000 -0-0
uuuu uuuu
ADCON1
15h
000- 0000
000- 0000
uuuu uuuu
ADRESL
16h
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRESH
17h
xxxx xxxx
xxxx xxxx
uuuu uuuu
Register
Bank 2
Bank 3
PW1DCL
Bank 4
Bank 5
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
DS30264A-page 26
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
MCLR Reset
WDT Reset
(Cont.’d)
Wake-up from SLEEP
through interrupt
Address
Power-on Reset
Brown-out Reset
SSPADD
10h
0000 0000
0000 0000
uuuu uuuu
SSPCON1
11h
0000 0000
0000 0000
uuuu uuuu
SSPCON2
12h
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
13h
0000 0000
0000 0000
uuuu uuuu
SSPBUF
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
Unimplemented
15h
---- ----
---- ----
---- ----
Unimplemented
16h
---- ----
---- ----
---- ----
Unimplemented
17h
---- ----
---- ----
---- ----
PW3DCL
10h
xxx- ----
uuu- ----
uuu- ----
PW3DCH
11h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA3L
12h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA3H
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA4L
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CA4H
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TCON3
16h
-000 0000
-000 0000
-uuu uuuu
Unimplemented
17h
---- ----
---- ----
---- ----
PRODL
18h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODH
19h
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
Bank 6
Bank 7
Unbanked
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: If Brown-out is enabled, else the BOR bit is unknown.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 27
PIC17C75X
5.1.5
FIGURE 5-8:
BROWN-OUT RESET (BOR)
PIC17C75X devices have an on-chip Brown-out Reset
circuitry. This circuitry places the device into a reset
when the device voltage falls below a trip point (BVDD).
This ensures that the device does not continue program execution outside the valid operation range of the
device. Brown-out resets are typically used in AC line
applications or large battery applications where large
loads may be switched in (such as automotive).
Note:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
10k
MCLR
PIC17CXXX
40 kΩ
Before using the on-chip brown-out for a
voltage supervisory function, please
review the electrical specifications to
ensure that they meet your requirements.
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below BVDD (Typically 4.0V,
parameter D005 in electrical specification section), for
greater than parameter D035, the brown-out situation
will reset the chip. A reset is not guaranteed to occur if
VDD falls below BVDD for less than parameter D035.
The chip will remain in Brown-out Reset until VDD rises
above BVDD. The Power-up Timer will now be invoked
and will keep the chip in reset an additional 96 ms. If
VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
96 ms time delay. Figure 5-10 shows typical Brown-out
situations.
FIGURE 5-9:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
PIC17CXXX
40 kΩ
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
In some applications the Brown-out reset trip point of
the device may not be at the desired level. Figure 5-8
and Figure 5-9 are two examples of external circuitry
that may be implemented. Each needs to be evaluated
to determine if they match the requirements of the
application.
VDD •
R1
R1 + R2
= 0.7V
FIGURE 5-10: BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD Max.
BVDD Min.
96 ms
VDD
Internal
Reset
BVDD Max.
BVDD Min.
< 96 ms
96 ms
VDD
Internal
Reset
DS30264A-page 28
BVDD Max.
BVDD Min.
96 ms
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
6.0
INTERRUPTS
The PIC17C75X devices have 18 sources of interrupt:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
External interrupt from the RA0/INT pin
Change on RB7:RB0 pins
TMR0 Overflow
TMR1 Overflow
TMR2 Overflow
TMR3 Overflow
USART1 Transmit buffer empty
USART1 Receive buffer full
USART2 Transmit buffer empty
USART2 Receive buffer full
SSP Interrupt
SSP I2C bus collision interrupt
A/D conversion complete
Capture1
Capture2
Capture3
Capture4
T0CKI edge occurred
•
•
•
•
There are six registers used in the control and status of
interrupts. These are:
•
•
•
•
•
•
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupts, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts which
all vector to the same address). These sources are:
CPUSTA
INTSTA
PIE1
PIR1
PIE2
PIR2
External interrupt from the RA0/INT pin
TMR0 Overflow
T0CKI edge occurred
Any peripheral interrupt
When program execution vectors to one of these interrupt vector addresses (except for the peripheral interrupts), the interrupt flag bit is automatically cleared.
Vectoring to the peripheral interrupt vector address
does not automatically clear the source of the interrupt.
In the peripheral interrupt service routine, the source(s)
of the interrupt can be determined by testing the interrupt flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid infinite
interrupt requests.
When an interrupt condition is met, that individual interrupt flag bit will be set regardless of the status of its corresponding mask bit or the GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could be
one instruction cycle longer.
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Memory Organization section.
FIGURE 6-1:
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is
“POPed”, and the GLINTD bit is cleared (to re-enable
interrupts).
INTERRUPT LOGIC
PIR1 / PIE1
RBIF
RBIE
TMR3IF
TMR3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA2IF
CA2IE
T0IF
T0IE
CA1IF
CA1IE
INTF
INTE
TX1IF
TX1IE
RC1IF
RC1IE
SSPIF
SSPIE
PIR2 / PIE2
INTSTA
Wake-up (If in SLEEP mode)
or terminate long write
Interrupt to CPU
T0CKIF
T0CKIE
PEIF
PEIE
BCLIF
BCLIE
GLINTD (CPUSTA<4>)
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 29
PIC17C75X
6.1
Interrupt Status Register (INTSTA)
Note:
The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in flag bits, and contains the individual interrupt enable bits (not for the
peripherals).
The PEIF bit is a read only, bit wise OR of all the peripheral flag bits in the PIR registers (Figure 6-5 and
Figure 6-6).
T0IF, INTF, T0CKIF, and PEIF get set by
their specified condition, even if the corresponding interrupt enable bit is clear (interrupt disabled) or the GLINTD bit is set (all
interrupts disabled).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
FIGURE 6-2:
R-0
PEIF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
DS30264A-page 30
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
6.2
Peripheral Interrupt Enable Register1
(PIE1) and Register2 (PIE2)
These registers contains the individual enable bits for
the peripheral interrupts.
FIGURE 6-3:
PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
bit7
bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
R = Readable bit
W = Writable bit
-n = Value at POR reset
TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 31
PIC17C75X
FIGURE 6-4:
PIE2 REGISTER (ADDRESS: 11h, BANK 4)
R/W - 0 R/W - 0
SSPIE BCLIE
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
ADIE
U-0
—
R/W - 0
CA4IE
R/W - 0
CA3IE
R/W - 0
TX2IE
SSPIE: Synchronous Serial Port Interrupt Enable
1 = Enable SSP Interrupt
0 = Disable SSP Interrupt
R/W - 0
RC2IE
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
ADIE: A/D Module Interrupt Enable
1 = Enable A/D Module Interrupt
0 = Disable A/D Module Interrupt
Unimplemented: Read as ‘0’
CA4IE: Capture4 Interrupt Enable
1 = Enable Capture4 Interrupt
0 = Disable Capture4 Interrupt
CA3IE: Capture3 Interrupt Enable
1 = Enable Capture3 Interrupt
0 = Disable Capture3 Interrupt
TX2IE: USART2 Transmit Interrupt Enable
1 = Enable USART2 Transmit Interrupt
0 = Disable USART2 Transmit Interrupt
RC2IE: USART2 Receive Interrupt Enable
1 = Enable USART2 Receive Interrupt
0 = Disable USART2 Receive Interrupt
DS30264A-page 32
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
6.3
Peripheral Interrupt Request
Register1 (PIR1) and Register2 (PIR2)
Note:
These registers contains the individual flag bits for the
peripheral interrupts.
FIGURE 6-5:
These bits will be set by the specified condition, even if the corresponding interrupt
enable bit is cleared (interrupt disabled), or
the GLINTD bit is set (all interrupts disabled). Before enabling an interrupt, the
user may wish to clear the interrupt flag to
ensure that the program does not immediately branch to the peripheral interrupt service routine.
PIR1 REGISTER (ADDRESS: 16h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF TX1IF RC1IF
bit7
bit0
bit 7:
bit 6:
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (software must end the mismatch condition)
0 = None of the PORTB inputs have changed
TMR3IF: TMR3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = TMR3 overflowed
0 = TMR3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
bit 4:
TMR2IF: TMR2 Interrupt Flag bit
1 = TMR2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: TMR1 Interrupt Flag bit
If TMR1 is in 8-bit mode (T16 = 0)
1 = TMR1 value has rolled over to 0000h from equalling the period register (PR1) value
0 = TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1) value
0 = TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1) value
bit 3:
bit 2:
bit 1:
bit 0:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
TX1IF: USART1 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART1 Transmit buffer is empty
0 = USART1 Transmit buffer is full
RC1IF: USART1 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART1 Receive buffer is full
0 = USART1 Receive buffer is empty
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 33
PIC17C75X
FIGURE 6-6:
PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W - 0 R/W - 0
SSPIF BCLIF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
ADIF
U-0
—
R/W - 0
CA4IF
R/W - 0
CA3IF
R-1
TX2IF
R-0
RC2IF
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occured, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave / Master
A transmission/reception has taken place.
I2C Master
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = An SSP interrupt condition has occurred.
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I2C master mode
0 = No bus collision has occurred
ADIF: A/D Module Interrupt Flag
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
CA3IF: Capture3 Interrupt Flag
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag (State controlled by hardware)
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag (State controlled by hardware)
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
DS30264A-page 34
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
6.4
Interrupt Operation
6.5
RA0/INT Interrupt
Global Interrupt Disable bit, GLINTD (CPUSTA<4>),
enables all unmasked interrupts (if clear) or disables all
interrupts (if set). Individual interrupts can be disabled
through their corresponding enable bits in the INTSTA
register. Peripheral interrupts need either the global
peripheral enable PEIE bit disabled, or the specific
peripheral enable bit disabled. Disabling the peripherals via the global peripheral enable bit, disables all
peripheral interrupts. GLINTD is set on reset (interrupts
disabled).
The external interrupt on the RA0/INT pin is edge triggered. Either the rising edge, if INTEDG bit
(T0STA<7>) is set, or the falling edge, if INTEDG bit is
clear. When a valid edge appears on the RA0/INT pin,
the INTF bit (INTSTA<4>) is set. This interrupt can be
disabled by clearing the INTE control bit (INTSTA<0>).
The INT interrupt can wake the processor from SLEEP.
See Section 17.4 for details on SLEEP operation.
The RETFIE instruction allows returning from interrupt
and re-enables interrupts at the same time.
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge, if the T0SE bit
(T0STA<6>) is set, or the falling edge, if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 17.4 for details on
SLEEP operation.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector. There are four interrupt
vectors which help reduce interrupt latency.
The peripheral interrupt vector has multiple interrupt
sources. Once in the peripheral interrupt service routine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The peripheral interrupt
flag bit(s) must be cleared in software before
re-enabling interrupts to avoid continuous interrupts.
The PIC17C75X devices have four interrupt vectors.
These vectors and their hardware priority are shown in
Table 6-1. If two enabled interrupts occur “at the same
time”, the interrupt of the highest priority will be serviced first. This means that the vector address of that
interrupt will be loaded into the program counter (PC).
TABLE 6-1:
Address
0008h
0010h
0018h
0020h
INTERRUPT
VECTORS/PRIORITIES
Vector
External Interrupt on
RA0/INT pin (INTF)
TMR0 overflow interrupt
(T0IF)
External Interrupt on T0CKI
(T0CKIF)
Peripherals (PEIF)
Priority
1 (Highest)
2
3
4 (Lowest)
Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GLINTD bit.
Note 2: Before disabling any of the INTSTA enable
bits, the GLINTD bit should be set
(disabled).
6.6
6.7
T0CKI Interrupt
Peripheral Interrupt
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit, and is a bit wise OR of all the
flag bits in the PIR registers AND’ed with the corresponding enable bits in the PIE registers. Some of the
peripheral interrupts can wake the processor from
SLEEP. See Section 17.4 for details on SLEEP operation.
6.8
Context Saving During Interrupts
During an interrupt, only the returned PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt; e.g. WREG, ALUSTA and the
BSR registers. This requires implementation in software.
Example 6-2 shows the saving and restoring of information for an interrupt service routine. This is for a simple interrupt scheme, where only one interrupt may
occur at a time (no interrupt nesting). The SFRs are
stored in the non-banked GPR area.
Example 6-2 shows the saving and restoring of information for a more complex interrupt service routine.
This is useful where nesting of interrupts is required. A
maximum of 6 levels can be done by this example. The
BSR is stored in the non-banked GPR area, while the
other registers would be stored in a particular bank.
Therefore 6 saves may be done with this routine (since
there are 6 non-banked GPR registers). These routines
require a dedicated indirect addressing register, FSR0
has been selected for this.
The PUSH and POP code segments could either be in
each interrupt service routine or could be subroutines
that were called. Depending on the application, other
registers may also need to be saved.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 35
PIC17C75X
FIGURE 6-7:
INT PIN / T0CKI PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OSC2
RA0/INT or
RA1/T0CKI
INTF or
T0CKIF
GLINTD
PC
System Bus
Instruction
Fetched
PC
PC
Instruction
executed
DS30264A-page 36
PC + 1
Inst (PC)
Addr
Inst (PC+1)
Inst (PC)
YY
Addr (Vector)
Addr
Inst (PC+1)
Dummy
Addr
Inst (Vector)
Dummy
Preliminary
Addr
RETFIE
YY + 1
Addr
PC + 1
Inst (YY + 1)
RETFIE
Dummy
1997 Microchip Technology Inc.
PIC17C75X
EXAMPLE 6-1:
SAVING STATUS AND WREG IN RAM (SIMPLE)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
;
UNBANK1
EQU
0x01A
; Address for 1st location to save
UNBANK2
EQU
0x01B
; Address for 2nd location to save
UNBANK3
EQU
0x01C
; Address for 3rd location to save
UNBANK4
EQU
0x01D
; Address for 4th location to save
UNBANK5
EQU
0x01E
; Address for 5th location to save
;
(Label Not used in program)
UNBANK6
EQU
0x01F
; Address for 6th location to save
;
(Label Not used in program)
;
:
; At Interrupt Vector Address
PUSH
MOVFP
ALUSTA, UNBANK1
; Push ALUSTA value
MOVFP
BSR, UNBANK2
; Push BSR value
MOVFP
WREG, UNBANK3
; Push WREG value
MOVFP
PCLATH, UNBANK4
; Push PCLATH value
;
:
; Interrupt Service Routine (ISR) code
;
POP
MOVFP
UNBANK4, PCLATH
; Restore PCLATH value
MOVFP
UNBANK3, WREG
; Restore WREG value
MOVFP
UNBANK2, BSR
; Restore BSR value
MOVFP
UNBANK1, ALUSTA
; Restore ALUSTA value
;
RETFIE
; Return from interrupt (enable interrupts)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 37
PIC17C75X
EXAMPLE 6-2:
SAVING STATUS AND WREG IN RAM (NESTED)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.
;
Nobank_FSR
EQU
0x40
Bank_FSR
EQU
0x41
ALU_Temp
EQU
0x42
WREG_TEMP
EQU
0x43
BSR_S1
EQU
0x01A
; 1st location to save BSR
BSR_S2
EQU
0x01B
; 2nd location to save BSR (Label Not used in program)
BSR_S3
EQU
0x01C
; 3rd location to save BSR (Label Not used in program)
BSR_S4
EQU
0x01D
; 4th location to save BSR (Label Not used in program)
BSR_S5
EQU
0x01E
; 5th location to save BSR (Label Not used in program)
BSR_S6
EQU
0x01F
; 6th location to save BSR (Label Not used in program)
;
INITIALIZATION
;
CALL
CLEAR_RAM
; Must Clear all Data RAM
;
INIT_POINTERS
; Must Initialize the pointers for POP and PUSH
CLRF
BSR, F
; Set All banks to 0
CLRF
ALUSTA, F
; FSR0 post increment
BSF
ALUSTA, FS1
CLRF
WREG, F
; Clear WREG
MOVLW
BSR_S1
; Load FSR0 with 1st address to save BSR
MOVWF
FSR0
MOVWF
Nobank_FSR
MOVLW
0x20
MOVWF
Bank_FSR
:
:
; Your code
:
:
; At Interrupt Vector Address
PUSH
BSF
ALUSTA, FS0
; FSR0 has auto-increment, does not affect status bits
BCF
ALUSTA, FS1
; does not affect status bits
MOVFP
BSR, INDF0
; No Status bits are affected
CLRF
BSR, F
; Periperal and Data RAM Bank 0 No Status bits are affected
MOVPF
ALUSTA, ALU_Temp
;
MOVPF
FSR0, Nobank_FSR
; Save the FSR for BSR values
MOVPF
WREG, WREG_TEMP
;
MOVFP
Bank_FSR, FSR0
; Restore FSR value for other values
MOVFP
ALU_Temp, INDF0
; Push ALUSTA value
MOVFP
WREG_TEMP, INDF0
; Push WREG value
MOVFP
PCLATH, INDF0
; Push PCLATH value
MOVPF
FSR0, Bank_FSR
; Restore FSR value for other values
MOVFP
Nobank_FSR, FSR0
;
;
:
; Interrupt Service Routine (ISR) code
;
POP
CLRF
ALUSTA, F
; FSR0 has auto-decrement, does not affect status bits
MOVFP
Bank_FSR, FSR0
; Restore FSR value for other values
DECF
FSR0, F
;
MOVFP
INDF0, PCLATH
; Pop PCLATH value
MOVFP
INDF0, WREG
; Pop WREG value
BSF
ALUSTA, FS1
; FSR0 does not change
MOVPF
INDF0, ALU_Temp
; Pop ALUSTA value
MOVPF
FSR0, Bank_FSR
; Restore FSR value for other values
DECF
Nobank_FSR, F
;
MOVFP
Nobank_FSR, FSR0
; Save the FSR for BSR values
MOVFP
ALU_Temp, ALUSTA
;
MOVFP
INDF0, BSR
; No Status bits are affected
;
RETFIE
; Return from interrupt (enable interrupts)
DS30264A-page 38
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
7.0
MEMORY ORGANIZATION
FIGURE 7-1:
There are two memory blocks in the PIC17C75X; program memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
PC<15:0>
16
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into
General Purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to control the peripheral modules are described in the section
discussing each individual peripheral module.
7.1
•
•
•
Stack Level 16
Program Memory Organization
PIC17C75X devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The reset vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 7-1).
PROGRAM MEMORY OPERATION
The PIC17C75X can operate in one of four possible
program memory configurations. The configuration is
selected by configuration bits. The possible modes
are:
•
•
•
•
Reset Vector
0000h
INT Pin Interrupt Vector
0008h
Timer0 Interrupt Vector
0010h
T0CKI Pin Interrupt Vector
0018h
Peripheral Interrupt Vector
0020h
0021h
User Memory
Space (1)
7.1.1
PROGRAM MEMORY MAP
AND STACK
1FFFh
(PIC17C752)
Microprocessor
Microcontroller
Extended Microcontroller
Protected Microcontroller
3FFFh
(PIC17C756)
Configuration Memory
Space
The microcontroller and protected microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data.
The protected microcontroller mode also enables the
code protection feature.
The extended microcontroller mode accesses both the
internal program memory as well as external program
memory. Execution automatically switches between
internal and external memory. The 16-bits of address
allow a program memory range of 64K-words.
The microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program memory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
The different modes allow different access to the configuration bits, test memory, and boot ROM. Table 7-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
1997 Microchip Technology Inc.
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
Reserved
BODEN
PM2
Test EPROM
FDFFh
FE00h
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE08h
FE0Dh
FE0Eh
FE0Fh
FE10h
FF5Fh
FF60h
Boot ROM
FFFFh
Note 1:
Preliminary
User memory space may be internal, external, or
both. The memory configuration depends on the
processor mode.
DS30264A-page 39
PIC17C75X
MODE MEMORY ACCESS
Operating
Mode
Internal
Program
Memory
Configuration Bits,
Test Memory,
Boot ROM
Microprocessor
No Access
No Access
Microcontroller
Access
Access
Extended
Microcontroller
Access
No Access
Protected
Microcontroller
Access
Access
Regardless of the processor mode, data memory is
always on-chip.
MEMORY MAP IN DIFFERENT MODES
Extended
Microcontroller
Mode
Microcontroller
Modes
0000h
0000h
01FFFh
On-chip
Program
Memory
01FFFh
2000h
2000h
External
Program
Memory
External
Program
Memory
PIC17C752
FE00h Config. Bits
Test Memory
FFFFh Boot ROM
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
OFF-CHIP
ON-CHIP
00h
FFh
OFF-CHIP
ON-CHIP
00h
120h
00h
120h
1FFh
FFh
ON-CHIP
120h
1FFh
FFh
ON-CHIP
0000h
On-chip
Program
Memory
3FFFh
4000h
3FFFh
External
Program
Memory
1FFh
ON-CHIP
0000h
0000h
On-chip
Program
Memory
4000h
External
Program
Memory
PIC17C756
FE00h Config. Bits
Test Memory
FFFFh Boot ROM
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
FFh
ON-CHIP
1FFh 2FFh 3FFh
OFF-CHIP
120h 220h 320h
120h 220h 320h
FFh
ON-CHIP
1FFh 2FFh 3FFh
ON-CHIP
Preliminary
ON-CHIP
00h
00h
120h 220h 320h
DS30264A-page 40
On-chip
Program
Memory
PROGRAM SPACE
0000h
DATA SPACE
Microprocessor
Mode
PROGRAM SPACE
FIGURE 7-2:
The PIC17C75X can operate in modes where the program memory is off-chip. They are the microprocessor
and extended microcontroller modes. The microprocessor mode is the default for an unprogrammed
device.
FFh
1FFh 2FFh 3FFh
ON-CHIP
DATA SPACE
TABLE 7-1:
1997 Microchip Technology Inc.
PIC17C75X
7.1.2
EXTERNAL MEMORY INTERFACE
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
When either microprocessor or extended microcontroller mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE<2:0> is
for the control signals. External components are
needed to demultiplex the address and data. This can
be done as shown in Figure 7-4. The waveforms of
address and data are shown in Figure 7-3. For complete timings, please refer to the electrical specification
section.
FIGURE 7-3:
Q1
AD
<15:0>
Q2
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers memory, please refer to the electrical specifications of the
desired PIC17C75X device, as well as the desired
memory device to ensure compatibility.
TABLE 7-2:
EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
Q4
Q3
Address out Data in
Q1
Q2
Q3
Address out
PIC17C75X Instruction
Oscillator
Cycle
Frequency Time (TCY)
Q1
Q4
'1'
WR
Read cycle
Write cycle
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
PIC17C752
PIC17C756
8 MHz
500 ns
-25
16 MHz
250 ns
-15
20 MHz
200 ns
-10
25 MHz
160 ns
-70
33 MHz
121 ns
(1)
Note 1: The access times for this requires the use of
fast SRAMs.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 7-2 lists external memory speed requirements for
a given PIC17C75X device frequency.
FIGURE 7-4:
EPROM Suffix
Data out
ALE
OE
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
Memory
(MSB)
A15-A0
AD7-AD0
373
PIC17CXXX
Memory
(LSB)
Ax-A0
Ax-A0
D7-D0
D7-D0
CE
CE
OE WR (2)
OE
WR(2)
AD15-AD8
373
ALE
138(1)
(1)
I/O
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 41
PIC17C75X
7.2
Data Memory Organization
7.2.1
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, while the
second is the Special Function Registers (SFR) area.
The SFRs control and give the status for the operation
of the device.
Portions of data memory are banked, this occurs in
both areas. The GPR area is banked to allow greater
than 232 bytes of general purpose RAM.
Banking requires the use of control bits for bank selection. These control bits are located in the Bank Select
Register (BSR). If an access is made to the unbanked
region, the BSR bits are ignored. Figure 7-5 shows the
data memory map organization.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any location in the register file (“F”), and vice-versa. The definition of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more locations than peripheral registers which can be used as
General Purpose Registers. This can be useful in some
applications where variables need to be copied to other
locations in the general purpose RAM (such as saving
status information during an interrupt).
The entire data memory can be accessed either
directly or indirectly through file select registers FSR0
and FSR1 (Section 7.4). Indirect addressing uses the
appropriate control bits of the BSR for accesses into
the banked areas of data memory. The BSR is
explained in greater detail in Section 7.8.
DS30264A-page 42
GENERAL PURPOSE REGISTER (GPR)
All devices have some amount of GPR area. The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
All the PIC17C75X devices have banked memory in
the GPR area. To facilitate switching between these
banks, the MOVLR bank instruction has been added to
the instruction set. GPRs are not initialized by a
Power-on Reset and are unchanged on all other resets.
7.2.2
SPECIAL FUNCTION REGISTERS (SFR)
The SFRs are used by the CPU and peripheral functions to control the operation of the device (Figure 7-5).
These registers are static RAM.
The SFRs can be classified into two sets, those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bank instruction has been provided.
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 7-5:
PIC17C75X REGISTER FILE MAP
Addr Unbanked
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Fh
Bank 1 (1)
Bank 2 (1)
Bank 3 (1)
Bank 4 (1)
Bank 5 (1)
Bank 6 (1)
Bank 7 (1)
PORTA
DDRC
TMR1
PW1DCL
PIR2
DDRF
SSPADD
PW3DCL
DDRB
PORTC
TMR2
PW2DCL
PIE2
PORTF
SSPCON1
PW3DCH
PORTB
DDRD
TMR3L
PW1DCH
—
DDRG
SSPCON2
CA3L
RCSTA1
PORTD
TMR3H
PW2DCH
RCSTA2
PORTG
SSPSTAT
CA3H
RCREG1
DDRE
PR1
CA2L
RCREG2
ADCON0
SSPBUF
CA4L
TXSTA1
PORTE
PR2
CA2H
TXSTA2
ADCON1
—
CA4H
TXREG1
PIR1
PR3L/CA1L
TCON1
TXREG2
ADRESL
—
TCON3
SPBRG1
PIE1
PR3H/CA1H
TCON2
SPBRG2
ADRESH
—
—
Unbanked
PRODL
PRODH
General
Purpose
RAM
Bank 0 (2)
Bank 1 (2) Bank 2 (2, 3) Bank 3 (2, 3)
20h
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
‘0’s
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 43
PIC17C75X
TABLE 7-3:
Address
Name
SPECIAL FUNCTION REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets (3)
Unbanked
00h
INDF0
Uses contents of FSR0 to address data memory (not a physical register)
---- ---- ---- ----
01h
FSR0
Indirect data memory address pointer 0
xxxx xxxx uuuu uuuu
02h
PCL
Low order 8-bits of PC
0000 0000 0000 0000
03h(1)
PCLATH
Holding register for upper 8-bits of PC
04h
ALUSTA
05h
T0STA
(2)
0000 0000 uuuu uuuu
FS3
FS2
FS1
FS0
OV
Z
DC
C
1111 xxxx 1111 uuuu
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
0000 000- 0000 000-
06h
CPUSTA
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 1100 --11 qquu
07h
INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000 0000 0000
08h
INDF1
Uses contents of FSR1 to address data memory (not a physical register)
---- ---- ---- ----
09h
FSR1
Indirect data memory address pointer 1
xxxx xxxx uuuu uuuu
0Ah
WREG
Working register
xxxx xxxx uuuu uuuu
0Bh
TMR0L
TMR0 register; low byte
xxxx xxxx uuuu uuuu
0Ch
TMR0H
TMR0 register; high byte
xxxx xxxx uuuu uuuu
0Dh
TBLPTRL
Low byte of program memory table pointer
0000 0000 0000 0000
0Eh
TBLPTRH
High byte of program memory table pointer
0000 0000 0000 0000
0Fh
BSR
Bank select register
0000 0000 0000 0000
Bank 0
10h
PORTA
11h
DDRB
RBPU
—
RA5/TX1/
CK1
RA4/RX1/ RA3/SDI/
DT1
SDA
RA2/SS/
SCL
RA1/T0CKI
RA0/INT
Data direction register for PORTB
0-xx xxxx 0-uu uuuu
1111 1111 1111 1111
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
xxxx xxxx uuuu uuuu
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00u
SYNC
—
—
TRMT
TX9D
0000 --1x 0000 --1u
12h
PORTB
13h
RCSTA1
14h
RCREG1
15h
TXSTA1
16h
TXREG1
Serial Port Transmit Register (for USART1)
xxxx xxxx uuuu uuuu
17h
SPBRG1
Baud Rate Generator Register (for USART1)
xxxx xxxx uuuu uuuu
DDRC
Data direction register for PORTC
Serial port receive register
CSRC
TX9
TXEN
xxxx xxxx uuuu uuuu
Bank 1
10h
11h
PORTC
12h
DDRD
13h
PORTD
14h
DDRE
RC7/
AD7
RC6/
AD6
RC5/
AD5
1111 1111 1111 1111
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
—
RE3/
CAP4
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Data direction register for PORTE
xxxx xxxx uuuu uuuu
---- 1111 ---- 1111
15h
PORTE
16h
PIR1
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
x000 0010 u000 0010
17h
PIE1
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000 0000 0000
Legend:
Note 1:
2:
3:
—
—
—
RE2/WR
RE1/OE
RE0/ALE ---- xxxx ---- uuuu
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 44
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 7-3:
Address
SPECIAL FUNCTION REGISTERS (Cont.’d)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets (3)
Bank 2
10h
TMR1
Timer1’s register
xxxx xxxx uuuu uuuu
11h
TMR2
Timer2’s register
xxxx xxxx uuuu uuuu
12h
TMR3L
Timer3’s register; low byte
xxxx xxxx uuuu uuuu
13h
TMR3H
Timer3’s register; high byte
xxxx xxxx uuuu uuuu
14h
PR1
Timer1’s period register
xxxx xxxx uuuu uuuu
15h
PR2
Timer2’s period register
xxxx xxxx uuuu uuuu
16h
PR3L/CA1L
Timer3’s period register - low byte/capture1 register; low byte
xxxx xxxx uuuu uuuu
17h
PR3H/CA1H
Timer3’s period register - high byte/capture1 register; high byte
xxxx xxxx uuuu uuuu
Bank 3
10h
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ---- uu-- ----
11h
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ---- uu0- ----
12h
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
13h
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
14h
CA2L
Capture2 low byte
15h
CA2H
Capture2 high byte
16h
TCON1
CA2ED1 CA2ED0
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS
TMR1CS 0000 0000 0000 0000
TMR3ON
TMR2ON
TMR1ON 0000 0000 0000 0000
Bank 4:
10h
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010 000- 0010
11h
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000 000- 0000
12h
Unimplemented
13h
RCSTA2
14h
RCREG2
15h
TXSTA2
16h
TXREG2
Serial Port Transmit Register for USART2
xxxx xxxx uuuu uuuu
17h
SPBRG2
Baud Rate Generator for USART2
xxxx xxxx uuuu uuuu
10h
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
11h
PORTF
12h
DDRG
Data Direction Register for PORTG
13h
PORTG
RG7/
RG6/
TX2/CK2 RX2/DT2
14h
ADCON0
—
—
—
—
—
—
—
—
---- ---- ---- ----
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00u
—
—
TRMT
TX9D
0000 --1x 0000 --1u
Serial Port Receive Register for USART2
CSRC
TX9
TXEN
SYNC
xxxx xxxx uuuu uuuu
Bank 5:
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
0000 0000 0000 0000
1111 1111 1111 1111
RG5/
PWM3
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
xxxx 0000 uuuu 0000
CHS3
CHS2
CHS1
CHS0
—
GO/DONE
—
ADON
0000 -0-0 0000 -0-0
ADCS1
ADCS0
ADFM
—
PCFG3
PCFG2
PCFG1
PCFG0
000- 0000 000- 0000
15h
ADCON1
16h
ADRESL
A/D Result Register low byte
xxxx xxxx uuuu uuuu
17h
ADRESH
A/D Result Register high byte
xxxx xxxx uuuu uuuu
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2:
3:
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 45
PIC17C75X
TABLE 7-3:
Address
SPECIAL FUNCTION REGISTERS (Cont.’d)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets (3)
Bank 6:
SSP Address register in I2C slave mode. SSP baud rate reload register in I2C master mode.
10h
SSPADD
11h
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
12h
SSPCON2
GCEN
AKSTAT
AKDT
AKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
0000 0000 0000 0000
13h
SSPSTAT
14h
SSPBUF
15h
Unimplemented
—
—
—
—
—
—
—
—
---- ---- ---- ----
16h
Unimplemented
—
—
—
—
—
—
—
—
---- ---- ---- ----
17h
Unimplemented
—
—
—
—
—
—
—
—
---- ---- ---- ----
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
Bank 7:
10h
PW3DCL
DC1
DC0
TM2PW3
-
-
-
-
-
xx0- ---- uu0- ----
11h
PW3DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
12h
CA3L
Capture3 low byte
xxxx xxxx uuuu uuuu
13h
CA3H
Capture3 high byte
xxxx xxxx uuuu uuuu
14h
CA4L
Capture4 low byte
xxxx xxxx uuuu uuuu
15h
CA4H
Capture4 high byte
xxxx xxxx uuuu uuuu
16h
TCON3
—
CA4OVF
CA3OVF
CA4ED1
CA4ED0
CA3ED1
CA3ED0
17h
Unimplemented
—
—
—
—
—
—
—
PWM3ON -000 0000 -000 0000
—
---- ---- ---- ----
Unbanked
18h (5)
PRODL
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx uuuu uuuu
(5)
PRODH
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx uuuu uuuu
19h
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 46
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
7.2.2.1
ALU STATUS REGISTER (ALUSTA)
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Therefore, the result of an instruction with
the ALUSTA register as destination may be different
than intended.
For example, CLRF ALUSTA will clear the upper four
bits and set the Z bit. This leaves the ALUSTA register
as 0000u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions be used to alter the
ALUSTA register because these instructions do not
FIGURE 7-6:
affect any status bit. To see how other instructions
affect the status bits, see the “Instruction Set Summary.”
Note 3: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
Note 4: The overflow bit will be set if the 2’s complement result exceeds +127 or is less
than -128.
The Arithmetic and Logic Unit (ALU) is capable of carrying out arithmetic or logical operations on two operands or a single operand. All single operand
instructions operate either on the WREG register or the
given file register. For two operand instructions, one of
the operands is the WREG register and the other one
is either a file register or an 8-bit immediate constant.
ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1
FS3
FS2
FS1
FS0
bit7
R/W - x
OV
R/W - x
Z
R/W - x
DC
R/W - x
C
bit0
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
bit 2:
bit 1:
bit 0:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
C: carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the most significant bit of the result occurred
Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate
(RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source register.
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 47
PIC17C75X
7.2.2.2
The POR bit allows the differentiation between a
Power-on Reset, external MCLR reset, or a WDT
Reset. The BOR bit indicates if a Brown-out Reset
occured.
CPU STATUS REGISTER (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register has a bit that is used to
globally enable/disable interrupts. If only a specific
interrupt is desired to be enabled/disabled, please refer
to the INTerrupt STAtus (INTSTA) register and the
Peripheral Interrupt Enable (PIE) registers. The
CPUSTA register also indicates if the stack is available
and contains the Power-down (PD) and Time-out (TO)
bits. The TO, PD, and STKAV bits are not writable.
These bits are set and cleared according to device
logic. Therefore, the result of an instruction with the
CPUSTA register as destination may be different than
intended.
FIGURE 7-7:
U-0
—
bit7
Note 1: The BOR status bit is a don’t care and is
not necessarily predictable if the
brown-out circuit is disabled (when the
BODEN bit in the Configuration word is
programmed).
CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U-0
—
R-1
R/W - 1
STKAV GLINTD
R-1
TO
R-1
PD
R/W - 0
POR
bit 7-6: Unimplemented: Read as '0'
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n = Value at POR reset
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDT instruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software after a Brown-out Reset occurs)
DS30264A-page 48
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
7.2.2.3
TMR0 STATUS/CONTROL REGISTER
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a signal on the RA0/INT pin will set the RA0/INT interrupt
flag. The other bits configure the Timer0 prescaler and
clock source.
FIGURE 7-8:
R/W - 0
INTEDG
bit7
bit 7:
bit 6:
bit 5:
T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0
T0SE
R/W - 0
T0CS
R/W - 0
T0PS3
R/W - 0
T0PS2
R/W - 0
T0PS1
R/W - 0
T0PS0
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
-n = Value at POR reset
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1 (Internal Clock)
Don’t care
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
bit 0:
Prescale Value
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Unimplemented: Read as '0'
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 49
PIC17C75X
7.3
Stack Operation
7.4
PIC17C75X devices have a 16 x 16-bit hardware stack
(Figure 7-1). The stack is not part of either the program
or data memory space, and the stack pointer is neither
readable nor writable. The PC (Program Counter) is
“PUSHed” onto the stack when a CALL or LCALL
instruction is executed or an interrupt is acknowledged.
The stack is “POPed” in the event of a RETURN, RETLW,
or a RETFIE instruction execution. PCLATH is not
affected by a “PUSH” or a “POP” operation.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all resets. There is a stack
available bit (STKAV) to allow software to ensure that
the stack has not overflowed. The STKAV bit is set
after a device reset. When the stack pointer equals Fh,
STKAV is cleared. When the stack pointer rolls over
from Fh to 0h, the STKAV bit will be held clear until a
device reset.
Note 1: There is not a status bit for stack underflow. The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the top of stack.
Note 2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt vector.
Note 3: After a reset, if a “POP” operation occurs
before a “PUSH” operation, the STKAV bit
will be cleared. This will appear as if the
stack is full (underflow has occurred). If a
“PUSH” operation occurs next (before
another “POP”), the STKAV bit will be
locked clear. Only a device reset will
cause this bit to set.
Indirect Addressing
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to be
read or written can be modified by the program. This
can be useful for data tables in the data memory.
Figure 7-9 shows the operation of indirect addressing.
This shows the moving of the value to the data memory address specified by the value of the FSR register.
Example 7-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined number of bytes (block) of data to the USART transmit register (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
FIGURE 7-9:
INDIRECT ADDRESSING
RAM
Instruction
Executed
Opcode
Address
File = INDFx
Instruction
Fetched
Opcode
File
FSR
After the device is “PUSHed” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
DS30264A-page 50
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
7.4.1
INDIRECT ADDRESSING REGISTERS
The PIC17C75X has four registers for indirect
addressing. These registers are:
A simple program to clear RAM from 20h - FFh is
shown in Example 7-1.
EXAMPLE 7-1:
• INDF0 and FSR0
• INDF1 and FSR1
Registers INDF0 and INDF1 are not physically implemented. Reading or writing to these registers activates
indirect addressing, with the value in the corresponding FSR register being the address of the data. The
FSR is an 8-bit register and allows addressing anywhere in the 256-byte data memory address range.
For banked memory, the bank of memory accessed is
specified by the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
7.4.2
INDIRECT ADDRESSING OPERATION
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two control bits associated with each FSR register. These two
bits configure the FSR register to:
• Auto-decrement the value (address) in the FSR
after an indirect access
• Auto-increment the value (address) in the FSR
after an indirect access
• No change to the value (address) in the FSR after
an indirect access
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
LP
7.5
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
CLRF
CPFSEQ
GOTO
:
:
INDIRECT ADDRESSING
0x20
FSR0
ALUSTA,
ALUSTA,
ALUSTA,
END_RAM
INDF0
FSR0
LP
FS1
FS0
C
+ 1
;
;
;
;
;
;
;
;
;
;
;
FSR0 = 20h
Increment FSR
after access
C = 0
Addr(FSR) = 0
FSR0 = END_RAM+1?
NO, clear next
YES, All RAM is
cleared
Table Pointer (TBLPTRL and
TBLPTRH)
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWT and
TABLRD.
The TABLRD and the TABLWT instructions allow transfer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
7.6
Table Latch (TBLATH, TBLATL)
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or program memory. The table latch is used as a temporary
holding latch during data transfer between program
and data memory (see TABLRD, TABLWT, TLRD and
TLWT instruction descriptions). For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPF and MOVFP instructions, where
either 'p' or 'f' is specified as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be determined by the value in the BSR.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 51
PIC17C75X
7.7
Program Counter Module
Using Figure 7-10, the operations of the PC and
PCLATH for different instructions are as follows:
The Program Counter (PC) is a 16-bit register. PCL,
the low byte of the PC, is mapped in the data memory.
PCL is readable and writable just as is any other register. PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or program memory, an 8-bit register PCLATH (PC high
latch) is used as a holding latch for the high byte of the
PC. PCLATH is mapped into data memory. The user
can read or write PCH through PCLATH.
The 16-bit wide PC is incremented after each instruction fetch during Q1 unless:
• Modified by a GOTO, CALL, LCALL, RETURN,
RETLW, or RETFIE instruction
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
a)
b)
c)
d)
Figure 7-10 and Figure 7-11 show the operation of the
program counter for various situations.
FIGURE 7-10: PROGRAM COUNTER
OPERATION
e)
Internal data bus <8>
Using Figure 7-11, the operation of the PC and
PCLATH for GOTO and CALL instructions is as follows:
8
PCLATH
CALL, GOTO instructions:
A 13-bit destination address is provided in the
instruction (opcode).
Opcode<12:0> → PC<12:0>
PC<15:13> → PCLATH<7:5>
Opcode<12:8> → PCLATH<4:0>
8
8
PCH
PCL
FIGURE 7-11: PROGRAM COUNTER USING
THE CALL AND GOTO
INSTRUCTIONS
15
13 12
8 7
Opcode
0
5
PC<15:13>
3
7
54
0
PCLATH
8
0
8 7
PCH
DS30264A-page 52
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH.
For example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed
jump, the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
The following PC related operations do not change
PCLATH:
8
15
LCALL instructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH → PCH
Opcode<7:0> → PCL
Read instructions on PCL:
Any instruction that reads PCL.
PCL → data bus → ALU or destination
PCH → PCLATH
Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data → data bus → PCL
PCLATH → PCH
Read-Modify-Write instructions on PCL:
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Read: PCL → data bus → ALU
Write: 8-bit result → data bus → PCL
PCLATH → PCH
RETURN instruction:
Stack<MRU> → PC<15:0>
a)
b)
c)
PCL
Preliminary
LCALL, RETLW, and RETFIE instructions.
Interrupt vector is forced onto the PC.
Read-modify-write instructions on PCL (e.g.
BSF PCL).
1997 Microchip Technology Inc.
PIC17C75X
7.8
Bank Select Register (BSR)
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank instruction has been provided in the instruction
set.
The BSR is used to switch between banks in the data
memory area (Figure 7-12). In the PIC17C752, and
PIC17C756 devices, the entire byte is implemented.
The lower nibble is used to select the peripheral register bank. The upper nibble is used to select the general
purpose memory bank.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank
to bank in order to address all peripherals related to a
single task. To assist this, a MOVLB bank instruction
has been included in the instruction set.
Note:
Registers in Bank 15 in the Special Function Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
FIGURE 7-12: BSR OPERATION
BSR
7
4 3
(2)
Address
Range
0
(1)
0
1
2
4
3
5
6
7
8
10h
15
SFR (Peripheral)
Banks
•••
17h
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8
0
1
2
3
15
4
20h
Bank 15
GPR (RAM)
Banks
•••
FFh
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 15
Note 1:
Only Banks 0 through 7 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: Bank 0 and Bank 1 are implemented for the PIC17C752, and Banks 0 through 3 are implemented for the PIC17C756.
Selection of an unimplemented bank is not recommended.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 53
PIC17C75X
NOTES:
DS30264A-page 54
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
8.0
TABLE READS AND TABLE
WRITES
FIGURE 8-2:
The PIC17C75X has four instructions that allow the
processor to move data from the data memory space
to the program memory space, and vice versa. Since
the program memory space is 16-bits wide and the
data memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data memory.
The TLWT t,f and TABLWT t,i,f instructions are
used to write data from the data memory space to the
program memory space. The TLRD t,f and TABLRD
t,i,f instructions are used to write data from the program memory space to the data memory space.
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in extended microcontroller or
microprocessor mode.
TABLE POINTER
TBLPTRH
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
TABLATL
3
3
TABLWT
1,i,f
TABLWT
DATA
MEMORY
f
Figure 8-1 through Figure 8-4 show the operation of
these four instructions.
FIGURE 8-1:
TABLWT INSTRUCTION
OPERATION
TLWT INSTRUCTION
OPERATION
0,i,f
PROGRAM MEMORY
1
Prog-Mem
(TBLPTR)
2
TABLE POINTER
TBLPTRH
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
DATA
MEMORY
f
TLWT
TABLATL
1,f
TLWT
0,f
PROGRAM MEMORY
Note 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
2: 16-bit TABLAT value written to address
Program Memory (TBLPTR).
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
1
Note 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 55
PIC17C75X
FIGURE 8-3:
TLRD INSTRUCTION
OPERATION
FIGURE 8-4:
TABLE POINTER
TABLE POINTER
TBLPTRH
TBLPTRH
TBLPTRL
TLRD
1,f
TBLPTRL
TABLE LATCH (16-bit)
TABLE LATCH (16-bit)
TABLATH
TABLRD INSTRUCTION
OPERATION
TABLATH
TABLATL
TLRD
TABLATL
0,f
3
3
DATA
MEMORY
TABLRD
PROGRAM MEMORY
TABLRD
1,i,f
DATA
MEMORY
f
0,i,f
PROGRAM MEMORY
1
f
1
Prog-Mem
(TBLPTR)
2
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
DS30264A-page 56
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
2: 16-bit value at Program Memory (TBLPTR)
loaded into TABLAT register.
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
8.1
Table Writes to Internal Memory
8.1.1
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the interrupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execution is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specification #D114). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
Note 1: If an interrupt is pending, the TABLWT is
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
Disable all interrupt sources, except the source
to terminate EPROM program write.
Raise MCLR/VPP pin to the programming voltage.
Clear the WDT.
Do the table write. The interrupt will terminate
the long write.
Verify the memory location (table read).
Note 2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it terminate the long write prematurely.
Note 1: Programming requirements must be
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM
locations that are not fully programmed
and may lose their state over time.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is
terminated. If GLINTD is clear, the program will vector,
if GLINTD is set, the program will not vector to the
interrupt address.
Note 2: If the VPP requirement is not met, the
table write is a 2 cycle write and the program memory is unchanged.
TABLE 8-1:
Interrupt
Source
RA0/INT, TMR0,
T0CKI
Peripheral
TERMINATING LONG WRITES
INTERRUPT - TABLE WRITE INTERACTION
GLINTD
Enable
Bit
Flag
Bit
0
1
1
0
1
1
1
0
1
0
x
1
0
0
1
1
1
1
0
1
1
0
x
1
1997 Microchip Technology Inc.
Action
Terminate long table write (to internal program
memory), branch to interrupt vector (branch clears
flag bit).
None
None
Terminate table write, do not branch to interrupt
vector (flag is automatically cleared).
Terminate table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt
vector (flag remains set).
Preliminary
DS30264A-page 57
PIC17C75X
8.2
Table Writes to External Memory
8.2.2
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
Note:
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is automatically incremented (for the next write). In
Example 8-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 8-1:
If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or
T0CKI interrupt flag is automatically
cleared or the pending peripheral interrupt is acknowledged.
FIGURE 8-5:
TABLE WRITE CODE
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
TABLE WRITE
HIGH (TBL_ADDR)
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
LOW (DATA)
0,0,WREG
;
;
;
;
;
;
;
;
;
;
;
;
Clear WDT
Load the Table
address
Load HI byte
in TABLATH
Load LO byte
in TABLATH
and write to
program memory
(Ext. SRAM)
TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLWT
Instruction
executed
INST (PC-1)
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
TBL
Data out
INST (PC+1)
TABLWT cycle1
Q1 Q2 Q3 Q4
PC+2
INST (PC+2)
TABLWT cycle2
INST (PC+1)
Data write cycle
ALE
OE
'1'
WR
Note:
If external write, and GLINTD = '1', and Enable bit = '1', then when '1' → Flag bit, Do table write.
The highest pending interrupt is cleared.
DS30264A-page 58
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 8-6:
CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLWT1
Instruction
executed
INST (PC-1)
PC+1
TBL1
Data out 1
TABLWT2
PC+2
TBL2
Data out 2
INST (PC+2)
INST (PC+3)
TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2
Data write cycle
PC+3
INST (PC+2)
Data write cycle
ALE
OE
WR
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 59
PIC17C75X
8.3
Table Reads
EXAMPLE 8-2:
The table read allows the program memory to be read.
This allows constants to be stored in the program
memory space, and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at program memory address TBLPTR. After the dummy byte
has been read from the TABLATH, the TABLATH is
loaded with the 16-bit data from program memory
address TBLPTR + 1. The first read loads the data into
the latch, and can be considered a dummy read
(unknown data loaded into 'f'). INDF0 should be configured for either auto-increment or auto-decrement.
FIGURE 8-7:
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
TLRD
TABLRD
TABLE READ
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
;
address
LOW (TBL_ADDR) ;
TBLPTRL
;
0,0,DUMMY
; Dummy read,
; Updates TABLATH
1, INDF0
; Read HI byte
;
of TABLATH
0,1,INDF0
; Read LO byte
;
of TABLATH and
;
Update TABLATH
TABLRD TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLRD
Instruction
executed
INST (PC-1)
PC+1
TBL
Data in
INST (PC+2)
INST (PC+1)
TABLRD cycle1
PC+2
TABLRD cycle2
INST (PC+1)
Data read cycle
ALE
OE
WR
FIGURE 8-8:
'1'
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLRD1
Instruction
executed
INST (PC-1)
PC+1
TBL1 Data in 1
PC+2
TBL2
Data in 2
INST (PC+2)
TABLRD2
INST (PC+3)
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
Data read cycle
PC+3
INST (PC+2)
Data read cycle
ALE
OE
'1'
WR
DS30264A-page 60
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
9.0
HARDWARE MULTIPLIER
All PIC17C75X devices have an 8 x 8 hardware multiplier included in the ALU of the device. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored into the 16-bit
PRODuct register (PRODH:PRODL). The multiplier
does not affect any flags in the ALUSTA register.
Example 9-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 9-1:
MOVFP
MULWF
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply algorithms
EXAMPLE 9-2:
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 9-1 shows a performance comparison between
PIC17CXXX devices using the single cycle hardware
multiply, and performing the same function without the
hardware multiply.
Example 9-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
TABLE 9-1:
Multiply Method
8 x 8 unsigned
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
16 x 16 unsigned
16 x 16 signed
ARG1, WREG
ARG2
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVFP
MULWF
ARG1, WREG
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVFP
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
;
PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
PERFORMANCE COMPARISON
Routine
8 x 8 signed
8 x 8 UNSIGNED MULTIPLY
ROUTINE
1997 Microchip Technology Inc.
Program Memory
Cycles (Max)
(Words)
13
1
—
6
21
24
52
36
Preliminary
69
1
—
6
242
24
254
36
Time
@ 33 MHz
8.364 µs
0.121 µs
—
0.727 µs
29.333 µs
2.91 µs
30.788 µs
4.36 µs
DS30264A-page 61
PIC17C75X
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 9-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 9-1:
RES3:RES0
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 9-3:
MOVFP
MULWF
MOVPF
MOVPF
16 x 16 UNSIGNED
MULTIPLY ROUTINE
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
;
=
ARG1H:ARG1L • ARG2H:ARG2L
=
(ARG1H • ARG2H • 216)
+
8)
(ARG1H • ARG2L • 2
+
(ARG1L • ARG2H • 28)
+
MOVFP
MULWF
MOVPF
MOVPF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
;
MOVFP
MULWF
(ARG1L • ARG2L)
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
;
MOVFP
MULWF
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
DS30264A-page 62
Preliminary
ARG1H, WREG ;
ARG2L
; ARG1H * ARG2L ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
1997 Microchip Technology Inc.
PIC17C75X
Example 9-4 shows the sequence to do an 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the arguments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 9-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 9-4:
MOVFP
MULWF
MOVPF
MOVPF
16 x 16 SIGNED MULTIPLY
ROUTINE
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
;
MOVFP
MULWF
RES3:RES0
MOVPF
MOVPF
= ARG1H:ARG1L • ARG2H:ARG2L
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
;
= (ARG1H • ARG2H • 216)
+
(ARG1H • ARG2L • 28)
+
(ARG1L • ARG2H • 28)
+
(ARG1L • ARG2L)
+
(-1 • ARG2H<7> • ARG1H:ARG1L • 216)
+
MOVFP
MULWF
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
;
MOVFP
MULWF
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
ARG1H, WREG ;
ARG2L
; ARG1H * ARG2L ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG
RES2
ARG1H, WREG
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, WREG
RES2
ARG2H, WREG
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
SIGN_ARG1
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
;
CONT_CODE
:
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 63
PIC17C75X
NOTES:
DS30264A-page 64
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
10.0
I/O PORTS
10.1
PIC17C75X devices have seven I/O ports, PORTA
through PORTG. PORTB through PORTG have a corresponding Data Direction Register (DDR), which is
used to configure the port pins as inputs or outputs.
These seven ports are made up of 50 I/O pins. Some
of these ports pins are multiplexed with alternate functions.
PORTC, PORTD, and PORTE are multiplexed with the
system bus. These pins are configured as the system
bus when the device’s configuration bits are selected to
Microprocessor or Extended Microcontroller modes. In
the two other microcontroller modes, these pins are
general purpose I/O.
PORTA, PORTB, PORTE<3>, PORTF and PORTG
are multiplexed with the peripheral features of the
device. These peripheral features are:
•
•
•
•
•
•
•
Timer modules
Capture modules
PWM modules
USART/SCI modules
SSP Module
A/D Module
External Interrupt pin
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR).
Reading PORTA reads the status of the pins.
The RA1 pin is multiplexed with TMR0 clock input, RA2
and RA3 are multiplexed with the SSP functions, and
RA4 and RA5 are multiplexed with the USART1 functions. The control of RA2, RA3, RA4 and RA5 as outputs are automatically configured by the their
multiplexed peripheral module.
10.1.1
When some of these peripheral modules are turned on,
the port pin will automatically configure to the alternate
function. The modules that do this are:
• PWM module
• SSP module
• USART/SCI module
When using the RA2 or RA3 pin(s) as output(s), read-modify-write instructions (such
as BCF, BSF, BTG) on PORTA are not recommended.
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
To avoid this possibility use a shadow register for PORTA. Do the bit operations on
this shadow register and then move it to
PORTA.
FIGURE 10-1: RA0 AND RA1 BLOCK
DIAGRAM
The other peripheral modules (which require an input)
must have their data direction bit configured appropriately.
Note:
USING RA2, RA3 AS OUTPUTS
The RA2 and RA3 pins are open drain outputs. To use
the RA2 and/or the RA3 pin(s) as output(s), simply
write to the PORTA register the desired value. A '0' will
cause the pin to drive low, while a '1' will cause the pin
to float (hi-impedance). An external pull-up resistor
should be used to pull the pin high. Writes to the RA2
and RA3 pins will not affect the other PORTA pins.
Note:
When a pin is automatically configured as an output by
a peripheral module, the pins data direction (DDR) bit
is unknown. After disabling the peripheral module, the
user should re-initialize the DDR bit to the desired configuration.
PORTA Register
DATA BUS
A pin that is a peripheral input, can be configured as an output (DDRx<y> is cleared).
The peripheral events will be determined
by the action output on the port pin.
RD_PORTA
(Q2)
Note: I/O pins have protection diodes to VDD and VSS.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 65
PIC17C75X
Example 10-1 shows an instruction sequence to initialize PORTA. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
FIGURE 10-3: RA3 BLOCK DIAGRAM
Peripheral data in
D
EXAMPLE 10-1: INITIALIZING PORTA
MOVLB
MOVLW
MOVPF
0
0xF3
PORTA
Data Bus
Q
EN
; Select Bank 0
;
; Initialize PORTA
;
RA<3:2> are output low
;
RA<5:4> and RA<1:0>
;
are inputs
;
(outputs floating)
RD_PORTA
(Q2)
Q
FIGURE 10-2: RA2 BLOCK DIAGRAM
D
Peripheral data in
Q
D
CK
Data Bus
Q
WR_PORTA
(Q4)
SDA out
“1”
EN
SSP Mode
Note: I/O pin has protection diodes to VSS.
RD_PORTA
(Q2)
Q
1
0
Q
FIGURE 10-4: RA4 AND RA5 BLOCK
DIAGRAM
D
CK
Serial port input signal
WR_PORTA
(Q4)
Data Bus
SCL out
I2C Mode enable
Note: I/O pin has protection diodes to VSS.
RD_PORTA
(Q2)
Serial port output signals
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
OE = SPEN (SYNC+SYNC,CSRC) for RA5
Note: I/O pins have protection diodes to VDD and VSS.
DS30264A-page 66
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 10-1:
PORTA FUNCTIONS
Bit0
Buffer
Type
RA0/INT
RA1/T0CKI
bit0
bit1
ST
ST
RA2/SS/SCL
bit2
ST
RA3/SDI/SDA
bit3
ST
RA4/RX1/DT1
bit4
ST
RA5/TX1/CK1
bit5
ST
Name
Input or external interrupt input.
Input or clock input to the TMR0 timer/counter, and/or an external interrupt
input.
Input/Output or slave select input for the SPI or clock input for the I2C bus.
Output is open drain type.
RBPU
bit7
—
Legend: ST = Schmitt Trigger input.
TABLE 10-2:
Function
Input/Output or data input for the SPI or data for the I2C bus.
Output is open drain type.
Input/Output or USART1 Asynchronous Receive or
USART1 Synchronous Data.
Input/Output or USART1 Asynchronous Transmit or
USART1 Synchronous Clock.
Control bit for PORTB weak pull-ups.
REGISTERS/BITS ASSOCIATED WITH PORTA
Value on
POR,
BOR
Value on
all other
resets
(Note1)
RA0/INT
0-xx xxxx
0-uu uuuu
PS0
—
0000 000-
0000 000-
OERR
RC9D
0000 -00x
0000 -00u
TX9D
0000 --1x
0000 --1u
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h, Bank 0
PORTA
RBPU
—
RA5/
TX1/CK1
RA4/
RX1/DT1
RA3/
SDI/SDA
RA2/
SS/SCL
RA1/T0CKI
05h, Unbanked
T0STA
INTEDG
T0SE
T0CS
PS3
PS2
PS1
13h, Bank 0
RCSTA1
SPEN
RC9
SREN
CREN
—
FERR
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
Legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. Shaded cells are not used by PORTA.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 67
PIC17C75X
10.2
PORTB and DDRB Registers
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt by:
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is DDRB. A '1' in
DDRB configures the corresponding port pin as an
input. A '0' in the DDRB register configures the corresponding port pin as an output. Reading PORTB reads
the status of the pins, whereas writing to it will write to
the port latch.
a)
Read-Write PORTB (such as; MOVPF PORTB,
PORTB). This will end mismatch condition.
Then, clear the RBIF bit.
b)
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any reset.
This interrupt on mismatch feature, together with software configurable pull-ups on this port, allows easy
interface to a keypad and make it possible for wake-up
on key-depression. For an example, refer to Application Note AN552, “Implementing Wake-up on Keystroke.”
PORTB also has an interrupt on change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin configured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” outputs
of RB7:RB0 are OR’ed together to set the PORTB
Interrupt Flag bit, RBIF (PIR1<7>).
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operations.
FIGURE 10-5: BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Data
Q
CK
WR_PORTB (Q4)
Note: I/O pins have protection diodes to VDD and VSS.
DS30264A-page 68
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
EXAMPLE 10-2: INITIALIZING PORTB
Example 10-2 shows an instruction sequence to initialize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
MOVLB
CLRF
0
PORTB
MOVLW
0xCF
MOVWF
DDRB
;
;
;
;
;
;
;
;
Select Bank 0
Initialize PORTB by clearing
output data latches
Value used to initialize
data direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Data
Q
CK
R
WR_PORTB (Q4)
Peripheral_output
Peripheral_enable
Note: I/O pins have protection diodes to VDD and Vss.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 69
PIC17C75X
FIGURE 10-7: BLOCK DIAGRAM OF RB6 PORT PIN
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
P
0
Port
Data
1
Q
N
Q
D
WR_PORTB (Q4)
CK
SPI output
SPI output enable
Note: I/O pins have protection diodes to VDD and Vss.
FIGURE 10-8: BLOCK DIAGRAM OF RB7 PORT PIN
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
Q
OE
WR_DDRB (Q4)
CK
P
0
Port
Data
1
Q
N
Q
SS output disable
D
CK
WR_PORTB (Q4)
SPI output
SPI output enable
Note: I/O pins have protection diodes to VDD and Vss.
DS30264A-page 70
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 10-3:
PORTB FUNCTIONS
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
RB1/CAP2
bit1
ST
RB2/PWM1
bit2
ST
RB3/PWM2
bit3
ST
RB4/TCLK12
bit4
ST
RB5/TCLK3
bit5
ST
RB6/SCK
bit6
ST
RB7/SDO
bit7
ST
Input/Output or the Capture1 input pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the Capture2 input pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the PWM1 output pin. Software programmable weak pull-up
and interrupt on change features.
Input/Output or the PWM2 output pin. Software programmable weak pull-up
and interrupt on change features.
Input/Output or the external clock input to Timer1 and Timer2. Software
programmable weak pull-up and interrupt on change features.
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
Input/Output or the master/slave clock for the SPI. Software programmable
weak pull-up and interrupt on change features.
Input/Output or data output for the SPI. Software programmable weak
pull-up and interrupt on change features.
Legend: ST = Schmitt Trigger input.
TABLE 10-4:
Address
12h
11h, Bank 0
10h, Bank 0
REGISTERS/BITS ASSOCIATED WITH PORTB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
—
RA5/
TX1/CK1
RA4/
RX1/DT1
RA3/
SDI/SDA
RA2/
SS/SCL
RA1/T0CKI
DDRB
PORTA
Data direction register for PORTB
RBPU
Value on
POR,
BOR
Value on
all other
resets
(Note1)
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
RA0/INT
0-xx xxxx 0-uu uuuu
--11 1100 --11 qq11
06h, Unbanked
CPUSTA
—
—
STKAV
GLINTD
TO
PD
POR
BOR
07h, Unbanked
INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000 0000 0000
16h, Bank 1
PIR1
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010 0000 0010
RBIE
RC1IE
0000 0000 0000 0000
17h, Bank 1
PIE1
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TX1IE
16h, Bank 3
TCON1
CA2ED1 CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS
TMR1CS 0000 0000 0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON
TMR2ON
TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 71
PIC17C75X
10.3
PORTC and DDRC Registers
Example 10-3 shows an instruction sequence to initialize PORTC. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
PORTC is an 8-bit bi-directional port. The corresponding data direction register is DDRC. A '1' in DDRC configures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTC reads the status of
the pins, whereas writing to it will write to the port latch.
PORTC is multiplexed with the system bus. When
operating as the system bus, PORTC is the low order
byte of the address/data bus (AD7:AD0). The timing for
the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 10-3: INITIALIZING PORTC
This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a general purpose I/O.
MOVLB
CLRF
1
PORTC
MOVLW
0xCF
MOVWF
DDRC
;
;
;
;
;
;
;
;
;
Select Bank 1
Initialize PORTC data
latches before setting
the data direction register
Value used to initialize
data direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
FIGURE 10-9: BLOCK DIAGRAM OF RC7:RC0 PORT PINS
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
0
1
Port
Data
D
Q
WR_PORTC
CK
D
Q
R
CK
S
RD_DDRC
WR_DDRC
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30264A-page 72
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 10-5:
PORTC FUNCTIONS
Name
Bit
Buffer Type
Function
RC0/AD0
bit0
TTL
Input/Output or system bus address/data pin.
RC1/AD1
bit1
TTL
Input/Output or system bus address/data pin.
RC2/AD2
bit2
TTL
Input/Output or system bus address/data pin.
RC3/AD3
bit3
TTL
Input/Output or system bus address/data pin.
RC4/AD4
bit4
TTL
Input/Output or system bus address/data pin.
RC5/AD5
bit5
TTL
Input/Output or system bus address/data pin.
RC6/AD6
bit6
TTL
Input/Output or system bus address/data pin.
RC7/AD7
bit7
TTL
Input/Output or system bus address/data pin.
Legend: TTL = TTL input.
TABLE 10-6:
REGISTERS/BITS ASSOCIATED WITH PORTC
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
11h, Bank 1
PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
xxxx xxxx
uuuu uuuu
10h, Bank 1
DDRC
1111 1111
1111 1111
Data direction register for PORTC
Legend: x = unknown, u = unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 73
PIC17C75X
10.4
PORTD and DDRD Registers
Example 10-4 shows an instruction sequence to initialize PORTD. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
PORTD is an 8-bit bi-directional port. The corresponding data direction register is DDRD. A '1' in DDRD configures the corresponding port pin as an input. A '0' in
the DDRD register configures the corresponding port
pin as an output. Reading PORTD reads the status of
the pins, whereas writing to it will write to the port latch.
PORTD is multiplexed with the system bus. When
operating as the system bus, PORTD is the high order
byte of the address/data bus (AD15:AD8). The timing
for the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 10-4: INITIALIZING PORTD
This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a general purpose I/O.
MOVLB
CLRF
1
PORTD
MOVLW
0xCF
MOVWF
DDRD
;
;
;
;
;
;
;
;
;
Select Bank 1
Initialize PORTD data
latches before setting
the data direction register
Value used to initialize
data direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
0
1
Port
Data
D
Q
WR_PORTD
CK
D
Q
R
CK
S
RD_DDRD
WR_DDRD
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30264A-page 74
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 10-7:
Name
PORTD FUNCTIONS
Bit
Buffer Type
RD0/AD8
bit0
RD1/AD9
bit1
RD2/AD10
bit2
RD3/AD11
bit3
RD4/AD12
bit4
RD5/AD13
bit5
RD6/AD14
bit6
RD7/AD15
bit7
Legend: TTL = TTL input.
TABLE 10-8:
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Function
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
REGISTERS/BITS ASSOCIATED WITH PORTD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
13h, Bank 1
PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
xxxx xxxx
uuuu uuuu
12h, Bank 1
DDRD
1111 1111
1111 1111
Data direction register for PORTD
Legend: x = unknown, u = unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 75
PIC17C75X
10.5
PORTE and DDRE Register
Example 10-5 shows an instruction sequence to initialize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
PORTE is a 4-bit bi-directional port. The corresponding
data direction register is DDRE. A '1' in DDRE configures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to it will write to the port latch.
PORTE is multiplexed with the system bus. When
operating as the system bus, PORTE contains the control signals for the address/data bus (AD15:AD0).
These control signals are Address Latch Enable (ALE),
Output Enable (OE), and Write (WR). The control signals OE and WR are active low signals. The timing for
the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 10-5: INITIALIZING PORTE
MOVLB
CLRF
MOVLW
MOVWF
Three pins of this port are configured as
the system bus when the device’s configuration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other microcontroller modes, RE2:RE0 are general purpose I/O pins.
1
; Select Bank 1
PORTE ; Initialize PORTE data
; latches before setting
; the data direction
; register
0x03 ; Value used to initialize
; data direction
DDRE ; Set RE<1:0> as inputs
; RE<3:2> as outputs
; RE<7:4> are always
; read as '0'
FIGURE 10-11: BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)
Data Bus
TTL
Input
Buffer
RD_PORTE
Port
0
Data
1
D
Q
WR_PORTE
CK
D
Q
R
CK
S
RD_DDRE
WR_DDRE
EX_EN
CNTL
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30264A-page 76
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN
Peripheral In
D
Data Bus
Q
EN
EN
VDD
RD_PORTE
P
Q
Port
Data
Q
N
D
RD_DDRE
D
Q
Q
WR_PORTE
CK
WR_DDRE
CK
S
Note: I/O pin has protection diodes to VDD and Vss.
TABLE 10-9:
PORTE FUNCTIONS
Name
Bit
Buffer Type
RE0/ALE
bit0
RE1/OE
bit1
RE2/WR
bit2
RE3/CAP4
bit3
Legend: TTL = TTL input.
Function
TTL
Input/Output or system bus Address Latch Enable (ALE) control pin.
TTL
Input/Output or system bus Output Enable (OE) control pin.
TTL
Input/Output or system bus Write (WR) control pin.
ST
Input/Output or Capture4 input pin
ST = Schmitt Trigger input
TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on,
POR,
BOR
Value on all
other resets
(Note1)
—
—
—
—
RE3/CAP4
RE2/WR
RE1/OE
RE0/ALE
15h, Bank 1
PORTE
---- xxxx
---- uuuu
14h, Bank 1
DDRE
Data direction register for PORTE
---- 1111
---- 1111
14h, Bank 7
CA4L
Capture4 low byte
xxxx xxxx
uuuu uuuu
15h, Bank 7
CA4H
Capture4 high byte
16h, Bank 7
TCON3
—
CA4OVF
CA3OVF
CA4ED1
CA4ED0
CA3ED1
CA3ED0 PWM3ON
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 77
PIC17C75X
10.6
PORTF and DDRF Registers
Example 10-6 shows an instruction sequence to initialize PORTF. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
PORTF is an 8-bit wide bi-directional port. The corresponding data direction register is DDRF. A '1' in DDRF
configures the corresponding port pin as an input. A '0'
in the DDRF register configures the corresponding port
pin as an output. Reading PORTF reads the status of
the pins, whereas writing to them will write to the
respective port latch.
EXAMPLE 10-6: INITIALIZING PORTF
All eight bits of PORTF are multiplexed with 8 of the 12
channels of the 10-bit A/D converter.
MOVLB
MOVLW
MOVPF
CLRF
5
0x0E
ADCON1
PORTF
Upon reset the entire Port is automatically configured
as analog inputs, and must be configured in software to
be a digital I/O.
MOVLW
0x03
MOVWF
DDRF
;
;
;
;
;
;
;
;
;
;
;
Select Bank 5
Configure PORTF as
Digital
Initialize PORTF data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RF<1:0> as inputs
RF<7:2> as outputs
FIGURE 10-13: BLOCK DIAGRAM OF RF7:RF0
Data bus
D
Q
VDD
WR PORTF
Q
CK
P
Data Latch
I/O pin
D
Q
CK
Q
N
WR DDRF
VSS
DDRF Latch
ST
input
buffer
RD DDRF
Q
D
EN
EN
RD PORT
PCFG3:PCFG0
To other pads
VAN
CHS3:CHS0
DS30264A-page 78
To other pads
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 10-11: PORTF FUNCTIONS
Name
Bit
Buffer Type
Function
RF0/AN4
ST
Input/Output or analog input 4
RF1/AN5
bit0
bit1
ST
Input/Output or analog input 5
RF2/AN6
bit2
ST
Input/Output or analog input 6
RF3/AN7
bit3
ST
Input/Output or analog input 7
RF4/AN8
bit4
ST
Input/Output or analog input 8
RF5/AN9
bit5
ST
Input/Output or analog input 9
RF6/AN10
bit6
ST
Input/Output or analog input 10
RF7/AN11
bit7
ST
Input/Output or analog input 11
Legend: ST = Schmitt Trigger input.
TABLE 10-12: REGISTERS/BITS ASSOCIATED WITH PORTF
Address
Name
10h, Bank 5
DDRF
11h, Bank 5
PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Direction Register for PORTF
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
Value on,
POR,
BOR
Value on all
other resets
(Note1)
1111 1111
1111 1111
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTF.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 79
PIC17C75X
10.7
PORTG and DDRG Registers
Example 10-7 shows the instruction sequence to initialize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the
BSR register for bank selection.
PORTG is an 8-bit wide bi-directional port. The corresponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corresponding port pin as an output. Reading PORTG
reads the status of the pins, whereas writing to them
will write to the respective port latch.
EXAMPLE 10-7: INITIALIZING PORTG
The lower four bits of PORTG are multiplexed with four
of the 12 channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
MOVLB
MOVLW
MOVPF
CLRF
5
0x0E
ADCON1
PORTG
MOVLW
0x03
MOVWF
DDRG
Upon reset the entire Port is automatically configured
as analog inputs, and must be configured in software
to be a digital I/O.
;
;
;
;
;
;
;
;
;
;
;
Select Bank 5
Configure PORTG as
digital
Initialize PORTG data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RG<1:0> as inputs
RG<7:2> as outputs
FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0
Data bus
D
Q
VDD
WR PORTG
Q
CK
P
Data Latch
I/O pin
D
Q
CK
Q
N
WR DDRG
VSS
DDRG Latch
ST
input
buffer
RD DDRG
Q
D
EN
EN
RD PORT
PCFG3:PCFG0
To other pads
VAN
CHS3:CHS0
DS30264A-page 80
To other pads
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 10-15: RG4 BLOCK DIAGRAM
Peripheral Data In
Data Bus
Q
D
EN
EN
RD_PORTG
D
VDD
P
D
Q
N
WR_PORTG
CK
Q
Q
RD_DDRG
WR_DDRG
CK
Note: I/O pin has protection diodes to VDD and Vss.
FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM
Peripheral Data In
D
Data Bus
Q
NEN
RD_PORTG
VDD
1
P
Port
Data
D
Q
Q
WR_PORTG
CK
0
D
Q
N
Q
CK
R
RD_DDRG
WR_DDRG
OUTPUT
OUTPUT ENABLE
Note: I/O pins have protection diodes to VDD and Vss.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 81
PIC17C75X
TABLE 10-13: PORTG FUNCTIONS
Name
Bit
Buffer Type
Function
RG0/AN3
ST
Input/Output or analog input 3.
RG1/AN2
bit0
bit1
ST
Input/Output or analog input 2.
RG2/AN1/VREF-
bit2
ST
Input/Output or analog input 1 or the ground reference voltage
RG3/AN0/VREF+
bit3
ST
Input/Output or analog input 0 or the positive reference voltage
RG4/CAP3
bit4
ST
RG4 can also be the Capture3 input pin.
RG5/PWM3
bit5
ST
RG5 can also be the PWM3 output pin.
RG6/RX2/DT2
bit6
ST
RG6 can also be selected as the USART2 (SCI) Asynchronous
Receive or USART2 (SCI) Synchronous Data.
RG7/TX2/CK2
bit7
ST
RG7 can also be selected as the USART2 (SCI) Asynchronous Transmit or USART2 (SCI) Synchronous Clock.
Legend: ST = Schmitt Trigger input.
TABLE 10-14: REGISTERS/BITS ASSOCIATED WITH PORTG
Address
Name
Bit 7
Bit 6
Bit 5
12h, Bank 5
DDRG
Data Direction Register for PORTG
13h, Bank 5
PORTG
RG7/
RG6/
TX2/CK2 RX2/DT2
RG5/
PWM3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
Value on,
POR,
BOR
Value on all
other resets
(Note1)
1111 1111
1111 1111
xxxx 0000
uuuu 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTG.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30264A-page 82
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
10.8
I/O Programming Considerations
10.8.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 10-8: READ MODIFY WRITE
INSTRUCTIONS ON AN
I/O PORT
Any instruction which writes, operates internally as a
read followed by a write operation. For example, the
BCF and BSF instructions read the register into the
CPU, execute the bit operation, and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g. bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the
pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the
content of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
; PORTB<7:6> have pull-ups and are
; not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------;
BCF
PORTB, 7
; 01pp pppp
11pp pppp
BCF
PORTB, 6
; 10pp pppp
11pp pppp
BCF
BCF
;
;
;
;
;
Reading a port reads the values of the port pins. Writing
to the port register writes the value to the port latch.
When using read-modify-write instructions (BCF, BSF,
BTG, etc.) on a port, the value of the port pins is read,
the desired operation is performed with this value, and
the value is then written to the port latch.
DDRB, 7
DDRB, 6
11pp pppp
10pp pppp
Note that the user may have expected the
pin values to be 00pp pppp. The 2nd BCF
caused RB7 to be latched as the pin value
(High).
Note:
Example 10-8 shows the effect of two sequential
read-modify-write instructions on an I/O port.
; 10pp pppp
; 10pp pppp
10.8.2
A pin actively outputting a Low or High
should not be driven from external devices
in order to change the level on this pin (i.e.
“wired-or”, “wired-and”). The resulting high
output currents may damage the device.
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 10-17). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load dependent) before executing the instruction that reads the
values on that I/O port. Otherwise, the previous state of
that pin may be read into the CPU rather than the “new”
state. When in doubt, it is better to separate these
instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 10-17: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
This example shows a write to PORTB
followed by a read from PORTB.
NOP
NOP
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
Instruction
executed
1997 Microchip Technology Inc.
Note:
MOVWF PORTB
write to
PORTB
MOVF PORTB,W
Preliminary
NOP
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
DS30264A-page 83
PIC17C75X
NOTES:
DS30264A-page 84
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
11.0
OVERVIEW OF TIMER
RESOURCES
11.3
The PIC17C75X has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
• Timer0 - 16-bit timer with programmable 8-bit
prescaler
• Timer1 - 8-bit timer
• Timer2 - 8-bit timer
• Timer3 - 16-bit timer
For enhanced time-base functionality, four input Captures and three Pulse Width Modulation (PWM) outputs are possible. The PWMs use the Timer1 and
Timer2 resources and the input Captures use the
Timer3 resource.
11.1
Timer0 Overview
The Timer0 module is a simple 16-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
When Timer0 uses an external clock source, it has the
flexibility to allow user selection of the incrementing
edge, rising or falling.
The Timer0 module also has a programmable prescaler. The PS3:PS0 bits (T0STA<4:1>) determine the
prescale value. TMR0 can increment at the following
rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, 1:256.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s frequency. The maximum external frequency, on the
T0CKI pin, is 50 MHz, given the high and low time
requirements of the clock.
11.2
Timer2 Overview
The Timer2 module is an 8-bit timer/counter with an
8-bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
flag is set, and an interrupt will be generated if
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also provide the clock for
the Timer1 module.
TMR2 can be concatenated with TMR1 to form a
16-bit timer. The TMR2 register is the MSB and TMR1
is the LSB. When in the 16-bit timer mode, there is a
corresponding 16-bit period register (PR2:PR1). When
the TMR2:TMR1 value rolls over from the period
match value to 0h, the TMR1IF flag is set, and an
interrupt will be generated if enabled.
11.4
Timer3 Overview
The Timer3 module is a 16-bit timer/counter with a
16-bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated if enabled. In counter mode, the
clock comes from the RB5/TCLK3 pin.
When operating in the four capture mode, the period
registers become the second (of four) 16-bit capture
registers.
11.5
Role of the Timer/Counters
The timer modules are general purpose, but have dedicated resources associated with them. TImer1 and
Timer2 are the time-bases for the three Pulse Width
Modulation (PWM) outputs, while Timer3 is the
time-base for the four input captures.
Timer1 Overview
The Timer1 module is an 8-bit timer/counter with an
8-bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
flag is set, and an interrupt will be generated if
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the Timer2 module.
TMR1 can be concatenated with TMR2 to form a
16-bit timer. The TMR1 register is the LSB and TMR2
is the MSB. When in the 16-bit timer mode, there is a
corresponding 16-bit period register (PR2:PR1). When
the TMR2:TMR1 value rolls over from the period
match value to 0h, the TMR1IF flag is set, and an
interrupt will be generated if enabled.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 85
PIC17C75X
NOTES:
DS30264A-page 86
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
12.0
TIMER0
The Timer0 module consists of a 16-bit timer/counter,
TMR0. The high byte is register TMR0H and the low
byte is register TMR0L. A software programmable 8-bit
prescaler makes Timer0 an effective 24-bit overflow
timer. The clock source is software programmable as
either the internal instruction clock or an external clock
on the RA1/T0CKI pin. The control bits for this module
are in register T0STA (Figure 12-1).
FIGURE 12-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0
INTEDG
bit7
bit 7:
bit 6:
bit 5:
R/W - 0
T0SE
R/W - 0
T0CS
R/W - 0
T0PS3
R/W - 0
T0PS2
R/W - 0
T0PS1
R/W - 0
T0PS0
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
Read as '0'
-n = Value at POR reset
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1 (Internal Clock)
Don’t care
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for TMR0.
1 = Internal instruction clock cycle (TCY)
0 = External Clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for TMR0.
T0PS3:T0PS0 Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
bit 0:
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Unimplemented: Read as '0'
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 87
PIC17C75X
12.1
Timer0 Operation
12.2
When the T0CS (T0STA<5>) bit is set, TMR0 increments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256. The timer increments from 0000h to FFFFh and rolls over to 0000h.
On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the corresponding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
Using Timer0 with External Clock
When an external clock input is used for Timer0, it is
synchronized with the internal phase clocks.
Figure 12-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical specification section.
12.2.1
DELAY FROM EXTERNAL CLOCK EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-3 shows that this delay is
between 3TOSC and 7TOSC. Thus, for example, measuring the interval between two edges (e.g. period) will
be accurate within ±4TOSC (±121 ns @ 33 MHz).
FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM
Interrupt on overflow
sets T0IF
(INTSTA<5>)
0
RA1/T0CKI
Fosc/4
1
Prescaler
(8 stage
async ripple
counter)
T0SE
(T0STA<6>)
Synchronization
TMR0H<8> TMR0L<8>
PSOUT
4
T0CS
(T0STA<5>)
T0PS3:T0PS0
(T0STA<4:1>)
Q2
Q4
FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT)
(note 3)
Sampled
(note 2)
Prescaler
output
(note 1)
Increment
TMR0
TMR0
T0
T0 + 1
T0 + 2
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: ↑ = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30264A-page 88
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
12.3
Read/Write Consideration for TMR0
12.3.2
Since writing to either TMR0L or TMR0H will effectively
inhibit increment of that half of the TMR0 in the next
cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
TMR0H second in two consecutive instructions, as
shown in Example 12-2. The interrupt must be disabled. Any write to either TMR0L or TMR0H clears the
prescaler.
Although TMR0 is a 16-bit timer/counter, only 8-bits at
a time can be read or written during a single instruction
cycle. Care must be taken during any read or write.
12.3.1
READING 16-BIT VALUE
The problem in reading the entire 16-bit value is that
after reading the low (or high) byte, its value may
change from FFh to 00h.
EXAMPLE 12-2: 16-BIT WRITE
Example 12-1 shows a 16-bit read. To ensure a proper
read, interrupts must be disabled during this routine.
BSF
MOVFP
MOVFP
BCF
EXAMPLE 12-1: 16-BIT READ
MOVPF
MOVPF
MOVFP
CPFSLT
RETURN
MOVPF
MOVPF
RETURN
TMR0L, TMPLO
TMR0H, TMPHI
TMPLO, WREG
TMR0L
TMR0L, TMPLO
TMR0H, TMPHI
WRITING A 16-BIT VALUE TO TMR0
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
12.4
CPUSTA, GLINTD
RAM_L, TMR0L
RAM_H, TMR0H
CPUSTA, GLINTD
; Disable interrupts
;
;
; Done, enable
;
interrupts
Prescaler Assignments
Timer0 has an 8-bit prescaler. The prescaler assignment is fully under software control; i.e., it can be
changed “on the fly” during program execution. When
changing the prescaler assignment, clearing the prescaler is recommended before changing assignment.
The value of the prescaler is “unknown,” and assigning
a value that is less then the present value makes it difficult to take this unknown time into account.
FIGURE 12-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC+2
PC+3
PC+4
ALE
TMR0L
T0
T0+1
New T0 (NT0)
New T0+1
Fetch
Instruction
executed
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Write to TMR0L
Read TMR0L
Read TMR0L
Read TMR0L
(Value = NT0)
(Value = NT0)
(Value = NT0 +1)
TMR0H
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 89
PIC17C75X
FIGURE 12-5: TMR0 READ/WRITE IN TIMER MODE
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
TMR0L
Instruction
fetched
Instruction
executed
12
12
TMR0H
FE
56
FF
MOVFP
MOVFP
DATAL,TMR0L DATAH,TMR0H
Write TMR0L Write TMR0H
Previously
Fetched
Instruction
AB
13
57
MOVPF
TMR0L,W
Read TMR0L
MOVFP
MOVFP
DATAL,TMR0L DATAH,TMR0H
Write TMR0L Write TMR0H
MOVPF
TMR0L,W
Read TMR0L
58
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 12-1:
Address
REGISTERS/BITS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
INTEDG
T0SE
—
—
PEIF
T0CKIF
T0IF
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
Bit 4
Bit 3
Bit 2
Bit 1
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
0000 000-
0000 000-
STKAV
GLINTD
TO
PD
POR
BOR
--11 1100
--11 qq11
INTF
PEIE
T0CKIE
T0IE
INTE
05h, Unbanked
T0STA
06h, Unbanked
CPUSTA
07h, Unbanked
INTSTA
0000 0000
0000 0000
0Bh, Unbanked
TMR0L
TMR0 register; low byte
xxxx xxxx
uuuu uuuu
0Ch, Unbanked
TMR0H
TMR0 register; high byte
xxxx xxxx
uuuu uuuu
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, Shaded cells are not used by Timer0.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30264A-page 90
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
13.0
TIMER1, TIMER2, TIMER3,
PWMS AND CAPTURES
Six other registers comprise the Capture2, Capture3,
and Capture4 registers (CA2H:CA2L, CA3H:CA3L,
and CA4H:CA4L).
The PIC17C75X has a wealth of timers and time-based
functions to ease the implementation of control applications. These time-base functions include three PWM
outputs and four Capture inputs.
Timer1 and Timer2 are two 8-bit incrementing timers,
each with an 8-bit period register (PR1 and PR2
respectively) and separate overflow interrupt flags.
Timer1 and Timer2 can operate either as timers (increment on internal Fosc/4 clock) or as counters (increment on falling edge of external clock on pin
RB4/TCLK12). They are also software configurable to
operate as a single 16-bit timer/counter. These timers
are also used as the time-base for the PWM (Pulse
Width Modulation) modules.
Timer3 is a 16-bit timer/counter which uses the TMR3H
and TMR3L registers. Timer3 also has two additional
registers (PR3H/CA1H: PR3L/CA1L) that are configurable as a 16-bit period register or a 16-bit capture
register. TMR3 can be software configured to increment from the internal system clock (FOSC/4) or from
an external signal on the RB5/TCLK3 pin. Timer3 is the
time-base for all of the 16-bit captures.
Figure 13-1, Figure 13-2, and Figure 13-3 are the control registers for the operation of Timer1, Timer2, and
Timer3, as well as PWM1, PWM2, PWM3, Capture1,
Capture2, Capture3, and Capture4.
Table 13-1 shows the Timer resource requirements for
these time-base functions. Each timer is an open
resource so that multiple functions may operate with it.
TABLE 13-1:
TIME-BASE FUNCTION /
RESOURCE
REQUIREMENTS
Time-base Function
PWM1
PWM2
PWM3
Capture1
Capture2
Capture3
Capture4
Timer Resource
Timer1
Timer1 or Timer2
Timer1 or Timer2
Timer3
Timer3
Timer3
Timer3
FIGURE 13-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
bit 2:
bit 1:
bit 0:
T16: Timer2:Timer1 Mode Select bit
1 = Timer2 and Timer1 form a 16-bit timer
0 = Timer2 and Timer1 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 91
PIC17C75X
FIGURE 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R-0
R-0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA1H:PR3L/CA1L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
PWM2ON: PWM2 On bit
1 = PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
PWM1ON: PWM1 On bit
1 = PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without
a period register)
0 = Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer (T16 is
set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit TMR2:TMR1
0 = Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
DS30264A-page 92
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
U-0
bit7
bit 7:
bit 6:
bit 5:
R-0
R-0
CA4OVF CA3OVF
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
bit0
Unimplemented: Read as ‘0’
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
-n = Value at POR reset
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 0:
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 93
PIC17C75X
13.1
Timer1 and Timer2
13.1.1
TIMER1, TIMER2 IN 8-BIT MODE
13.1.1.1
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be independently configured to increment from the internal
instruction cycle clock (TCY) or from an external clock
source on the RB4/TCLK12 pin. The timer clock source
is configured by the TMRxCS bit (x = 1 for Timer1 or =
2 for Timer2). When TMRxCS is clear, the clock source
is internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counters will increment on
every falling edge of the RB4/TCLK12 pin.
EXTERNAL CLOCK INPUT FOR TIMER1
AND TIMER2
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counter will increment on
every falling edge on the RB4/TCLK12 pin. The
TCLK12 input is synchronized with internal phase
clocks. This causes a delay from the time a falling edge
appears on TCLK12 to the time TMR1 or TMR2 is actually incremented. For the external clock input timing
requirements, see the Electrical Specification section.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next increment cycle. The timer interrupt flag is set when the
timer is reset. TMR1 and TMR2 have individual interrupt flag bits. The TMR1 interrupt flag bit is latched into
TMR1IF, and the TMR2 interrupt flag bit is latched into
TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled/disabled by setting/clearing this bit. For peripheral interrupts to be enabled, the Peripheral Interrupt Enable bit
must be set (PEIE = '1') and global interrupt must be
enabled (GLINTD = '0').
The timers can be turned on and off under software
control. When the timer on control bit (TMRxON) is set,
the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 13-4: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
Fosc/4
0
TMR1
Reset
Set TMR1IF
(PIR1<4>)
1
TMR1ON
(TCON2<0>)
Comparator<8>
Comparator x8
TMR1CS
(TCON1<0>)
Equal
PR1
RB4/TCLK12
1
TMR2
Fosc/4
Set TMR2IF
(PIR1<5>)
0
TMR2ON
(TCON2<1>)
Comparator<8>
Comparator x8
TMR2CS
(TCON1<1>)
DS30264A-page 94
Reset
Equal
PR2
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
13.1.2
TIMER1 AND TIMER2 IN 16-BIT MODE
13.1.2.1
To select 16-bit mode, set the T16 bit. In this mode
TMR2 and TMR1 are concatenated to form a 16-bit
timer (TMR2:TMR1). The 16-bit timer increments until
it matches the 16-bit period register (PR2:PR1). On
the following timer clock, the timer value is reset to 0h,
and the TMR1IF bit is set.
When TMR1CS is set, the 16-bit TMR2:TMR1 increments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. This causes a delay from the time a falling
edge appears on RB4/TCLK12 to the time
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
When selecting the clock source for the16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care”, however ensure that
TMR2ON is set (allows TMR2 to increment). When
TMR1CS is clear, the timer increments once every
instruction cycle (Fosc/4). When TMR1CS is set, the
timer increments on every falling edge of the
RB4/TCLK12 pin. For the 16-bit timer to increment,
both TMR1ON and TMR2ON bits must be set
(Table 13-2).
TABLE 13-2:
EXTERNAL CLOCK INPUT FOR
TMR2:TMR1
TURNING ON 16-BIT TIMER
T16 TMR2ON TMR1ON
Result
1
1
1
16-bit timer
(TMR2:TMR1) ON
1
0
1
Only TMR1 increments
1
x
0
16-bit timer OFF
0
1
1
Timers in 8-bit mode
FIGURE 13-5: TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE
1
RB4/TCLK12
Fosc/4
0
TMR1ON
(TCON2<0>)
TMR1CS
(TCON1<0>)
Set Interrupt TMR1IF
(PIR1<4>)
1997 Microchip Technology Inc.
Reset
Equal
MSB
LSB
TMR2 x 8
TMR1 x 8
Comparator<8>
Comparator
x16
PR2 x 8
Preliminary
PR1 x 8
DS30264A-page 95
PIC17C75X
TABLE 13-3:
SUMMARY OF TIMER1 AND TIMER2 REGISTERS
Address
Name
16h, Bank 3
17h, Bank 3
Bit 5
Bit 4
Bit 3
TCON1
CA2ED1
CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS TMR2CS
TMR1CS
0000 0000
0000 0000
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON
TMR1ON
0000 0000
0000 0000
PWM3ON
16h, Bank 7
TCON3
-000 0000
-000 0000
TMR1
Timer1’s register
xxxx xxxx
uuuu uuuu
11h, Bank 2
TMR2
Timer2’s register
xxxx xxxx
uuuu uuuu
16h, Bank 1
PIR1
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
—
—
STKAV
GLINTD
TO
PD
POR
BOR
06h, Unbanked CPUSTA
CA3OVF
CA4ED1
CA4ED0
CA3ED1
CA3ED0
Bit 0
10h, Bank 2
07h, Unbanked INTSTA
CA4OVF
Bit 1
Value on all
other resets
(Note1)
Bit 6
—
Bit 2
Value on
POR,
BOR
Bit 7
--11 1100
--11 qq11
14h, Bank 2
PR1
Timer1 period register
xxxx xxxx
uuuu uuuu
15h, Bank 2
PR2
Timer2 period register
xxxx xxxx
uuuu uuuu
10h, Bank 3
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h, Bank 3
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
10h, Bank 7
PW3DCL
DC1
DC0
TM2PW3
—
—
—
—
—
xx0- ----
uu0- ----
12h, Bank 3
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h, Bank 3
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
11h, Bank 7
PW3DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
DS30264A-page 96
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
13.1.3
USING PULSE WIDTH MODULATION
(PWM) OUTPUTS WITH TIMER1 AND
TIMER2
Three high speed pulse width modulation (PWM) outputs are provided. The PWM1 output uses Timer1 as
its time-base, while PWM2 and PWM3 may independently be software configured to use either Timer1 or
Timer2 as the time-base. The PWM outputs are on the
RB2/PWM1, RB3/PWM2, and RG5/PWM3 pins.
Each PWM output has a maximum resolution of
10-bits. At 10-bit resolution, the PWM output frequency
is 32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the
PWM output frequency is 128.9 kHz. The duty cycle of
the output can vary from 0% to 100%.
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output irrespective of the data direction bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is controlled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configuration of the RB3/PWM2 pin and the PWM3ON
(TCON3<0>) bit controls the configuration of the
RG5/PWM3 pin.
FIGURE 13-6: SIMPLIFIED PWM BLOCK
DIAGRAM
PWxDCH
PWxDCL<7:6>
Write
(Slave)
Read
Duty Cycle registers
Figure 13-6 shows a simplified block diagram of a
PWM module.
The duty cycle registers are double buffered for glitch
free operation. Figure 13-7 shows how a glitch could
occur if the duty cycle registers were not double buffered.
PWMx
Comparator
TMRx
R
(Note 1)
Comparator
PRy
S
Q
PWMxON
Clear Timer,
PWMx pin and
Latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
FIGURE 13-7: PWM OUTPUT
0
10
20
30
40
0
PWM
output
Timer
interrupt
Note
Write new
PWM value
Timer interrupt
new PWM value
transferred to slave
The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 97
PIC17C75X
13.1.3.1
PWM PERIODS
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 and PWM3 outputs can be individually software
configured to use either Timer1 or Timer2 as the
time-base. For PWM2, when TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1, and when TM2PW2 is set, the
time-base is determined by Timer2 and PR2. For
PWM3, when TM2PW3 bit (PW3DCL<5>) is clear, the
time-base is determined by TMR1 and PR1, and when
TM2PW3 is set, the time-base is determined by Timer2
and PR2.
Running two different PWM outputs on two different
timers allows different PWM periods. Running all
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 can not be used as a 16-bit timer if any PWM is
being used.
The PWM periods can be calculated as follows:
period of PWM1 = [(PR1) + 1] x 4TOSC
period of PWM3 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the
maximum PWM frequency (FPWM) given the value in
the period register.
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
Maximum PWM resolution (bits) for a given PWM frequency:
=
The duty cycle registers for both PWM outputs are double buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note:
For PW1DCH, PW1DCL, PW2DCH,
PW2DCL, PW3DCH and PW3DCL registers, a write operation writes to the "master
latches" while a read operation reads the
"slave latches". As a result, the user may
not read back what was just written to the
duty cycle registers.
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:
ADDWF PW1DCH. This may cause duty cycle outputs
that are unpredictable.
TABLE 13-4:
period of PWM2 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
log
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
OSC
)
( FFPWM
bits
log (2)
where: FPWM = 1 / period of PWM
PWM
Frequency
PRx Value
High
Resolution
Standard
Resolution
13.1.3.2
PWM FREQUENCY vs.
RESOLUTION AT 33 MHz
32.2
Frequency (kHz)
64.5
90.66
128.9
515.6
0xFF
10-bit
0x7F 0x5A
9-bit 8.5-bit
0x3F
8-bit
0x0F
6-bit
8-bit
7-bit
6-bit
4-bit
6.5-bit
PWM INTERRUPTS
The PWM modules makes use of the TMR1 and/or
TMR2 interrupts. A timer interrupt is generated when
TMR1 or TMR2 equals its period register and on the
following increment is cleared to zero. This interrupt
also marks the beginning of a PWM cycle. The user
can write new duty cycle values before the timer
roll-over. The TMR1 interrupt is latched into the
TMR1IF bit and the TMR2 interrupt is latched into the
TMR2IF bit. These flags must be cleared in software.
The PWMx duty cycle is as follows:
PWMx Duty Cycle =(DCx) x TOSC
where DCx represents
PWxDCH:PWxDCL.
DS30264A-page 98
the
10-bit
value
from
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
13.1.3.3
13.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
EXTERNAL CLOCK INPUT
EXTERNAL CLOCK SOURCE
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifications that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as 1TCY
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maximum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when internal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, as shown in Table 13-4 (standard
resolution mode).
This jitter will be ±1TCY, unless the external clock is
synchronized with the processor clock. Use of one of
the PWM outputs as the clock source to the TCLK12
input, will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
TABLE 13-5:
Address
REGISTERS/BITS ASSOCIATED WITH PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
16h, Bank 3
TCON1
CA2ED1
CA2ED0
CA1ED1
CA1ED0
17h, Bank 3
TCON2
CA2OVF
CA1OVF
PWM2ON
PWM1ON
—
CA4OVF
CA3OVF
CA4ED1
Bit 3
Bit 2
Bit 1
T16
TMR3CS
Bit 0
Value on
POR,
BOR
Value on all
other
resets
(Note1)
TMR2CS
TMR1CS
0000 0000
0000 0000
CA1/PR3 TMR3ON TMR2ON
TMR1ON
0000 0000
0000 0000
CA4ED0
PWM3ON
16h, Bank 7
TCON3
-000 0000
-000 0000
10h, Bank 2
TMR1
Timer1’s register
CA3ED1
CA3ED0
xxxx xxxx
uuuu uuuu
11h, Bank 2
TMR2
Timer2’s register
xxxx xxxx
uuuu uuuu
16h, Bank 1
PIR1
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
07h, Unbanked INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
06h, Unbanked CPUSTA
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 1100
--11 qq11
14h, Bank 2
PR1
Timer1 period register
xxxx xxxx
uuuu uuuu
15h, Bank 2
PR2
Timer2 period register
xxxx xxxx
uuuu uuuu
10h, Bank 3
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h, Bank 3
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
10h, Bank 7
PW3DCL
DC1
DC0
TM2PW3
—
—
—
—
—
xx0- ----
uu0- ----
12h, Bank 3
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h, Bank 3
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
11h, Bank 7
PW3DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,
shaded cells are not used by PWM Module.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 99
PIC17C75X
13.2
Timer3
(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4),
one for each capture register pair. The capture pins are
multiplexed with the I/O pins. An event can be:
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
another 16-bit capture register.
•
•
•
•
A rising edge
A falling edge
Every 4th rising edge
Every 16th rising edge
Each 16-bit capture register has an interrupt flag associated with it. The flag is set when a capture is made.
The capture modules are truly part of the Timer3 block.
Figure 13-8 and Figure 13-9 show the block diagrams
for the two modes of operation.
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the counter increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer/counter to increment. When TMR3ON is clear, the timer will not increment or set flag bit TMR3IF.
13.2.1
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
THREE CAPTURE AND ONE PERIOD
REGISTER MODE
In this mode registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 13-8. The timer increments until it
equals the period register and then resets to 0000h on
the next timer clock. TMR3 Interrupt Flag bit (TMR3IF)
is set at this point. This interrupt can be disabled by
clearing the TMR3 Interrupt Enable bit (TMR3IE).
TMR3IF must be cleared in software.
• Three capture and one period register mode
• Four capture register mode
The PIC17C75X has up to four 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are four capture pins
FIGURE 13-8: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
(TCON1<2>)
PR3H/CA1H
PR3L/CA1L
Comparator<8>
Comparator x16
0
Fosc/4
TMR3H
1
Set TMR3IF
(PIR1<6>)
Equal
Reset
TMR3L
TMR3ON
(TCON2<2>)
RB5/TCLK3
Edge select,
Prescaler select
RB1/CAP2
2
CA2ED1: CA2ED0
(TCON1<7:6>)
Edge select,
Prescaler select
RG4/CAP3
2
CA3ED1: CA3ED0
(TCON3<2:1>)
Edge select,
Prescaler select
RE3/CAP4
2
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30264A-page 100
Capture2
Enable
CA2H
CA2L
Set CA2IF
(PIR1<3>)
Capture3
Enable
CA3H
CA3L
Set CA3IF
(PIR2<2>)
Capture4
Enable
CA4H
CA4L
Set CA4IF
(PIR2<3>)
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
This mode (3 Capture, 1 Period) is selected if control bit
CA1/PR3 is clear. In this mode, the Capture1 register,
consisting of high byte (PR3H/CA1H) and low byte
(PR3L/CA1L), is configured as the period control register for TMR3. Capture1 is disabled in this mode, and
the corresponding Interrupt bit CA1IF is never set.
TMR3 increments until it equals the value in the period
register and then resets to 0000h on the next timer
clock.
All other Captures are active in this mode.
13.2.1.1
CAPTURE OPERATION
The CAxED1 and CAxED0 bits determine the event on
which capture will occur. The possible events are:
•
•
•
•
Capture on every falling edge
Capture on every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
The input on the capture pin CAPx is synchronized
internally to internal phase clocks. This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
The capture overflow status flag bit is double buffered.
The master bit is set if one captured word is already
residing in the Capture register (CAxH:CAxL) and
another “event” has occurred on the CAPx pin. The
new event will not transfer the TMR3 value to the
capture register, protecting the previous unread
capture value. When the user reads both the high and
the low bytes (in any order) of the Capture register, the
master overflow bit is transferred to the slave overflow
bit (CAxOVF) and then the master bit is reset. The user
can then read TCONx to determine the value of
CAxOVF.
The recommended sequence to read capture registers
and capture overflow flag bits is shown in
Example 13-1.
When a capture takes place, an interrupt flag is latched
into the CAxIF bit. This interrupt can be enabled by setting the corresponding mask bit CAxIE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CAxIF interrupt flag
bit is cleared in software.
When the capture prescale select is changed, the prescaler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip reset.
The capture pin, CAPx, is a multiplexed pin. When
used as a port pin, the capture is not disabled. However, the user can simply disable the Capture interrupt
by clearing CAxIE. If the CAPx pin is used as an output
pin, the user can activate a capture by writing to the
port pin. This may be useful during development phase
to emulate a capture interrupt.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 101
PIC17C75X
13.2.2
All the captures operate in the same manner. Refer to
Section 13.2.1 for the operation of capture.
FOUR CAPTURE MODE
This mode is selected by setting bit CA1/PR3. A block
diagram is shown in Figure 13-9. In this mode, TMR3
runs without a period register and increments from
0000h to FFFFh and rolls over to 0000h. The TMR3
interrupt Flag (TMR3IF) is set on this rollover. The
TMR3IF bit must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set upon detection of the capture event. The
corresponding interrupt mask bit is CA1IE. The
Capture1 Overflow Status bit is CA1OVF.
FIGURE 13-9: TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM
Fosc/4
Set TMR3IF
(PIR1<6>)
0
TMR3H
1
RB5/TCLK3
TMR3CS
(TCON1<2>)
TMR3L
TMR3ON
(TCON2<2>)
Edge Select,
Prescaler Select
RB0/CAP1
2
Capture1 Enable
Set CA1IF
(PIR1<2>)
PR3H/CA1H
PR3L/CA1L
CA1ED1, CA1ED0
(TCON1<5:4>)
Edge Select,
Prescaler Select
RB1/CAP2
2
CA2ED1, CA2ED0
(TCON1<7:6>)
Edge Select,
Prescaler Select
RG4/CAP3
2
Capture2 Enable
Set CA2IF
(PIR1<3>)
CA2H
CA2L
Capture3 Enable
Set CA3IF
(PIR2<2>)
CA3H
CA3L
CA3ED1: CA3ED0
(TCON3<2:1>)
Edge Select,
Prescaler Select
RE3/CAP4
2
Capture4 Enable
Set CA4IF
(PIR2<3>)
CA4H
CA4L
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30264A-page 102
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
13.2.3
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, different registers will need to be read.
READING THE CAPTURE REGISTERS
The Capture overflow status flag bits are double
buffered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and
then the master bit is reset. The user can then read
TCONx to determine the value of CAxOVF.
EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS
MOVLB
MOVPF
MOVPF
MOVPF
3
CA2L, LO_BYTE
CA2H, HI_BYTE
TCON2, STAT_VAL
TABLE 13-6:
Address
;
;
;
;
Select Bank 3
Read Capture2 low byte, store in LO_BYTE
Read Capture2 high byte, store in HI_BYTE
Read TCON2 into file STAT_VAL
REGISTERS ASSOCIATED WITH CAPTURE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CA1ED0
T16
Bit 2
Bit 1
Bit 0
TMR3CS TMR2CS TMR1CS
Value on
POR,
BOR
Value on all
other resets
(Note1)
16h, Bank 3
TCON1
CA2ED1 CA2ED0
CA1ED1
17h, Bank 3
TCON2
CA2OVF CA1OVF
PWM2ON
16h, Bank 7
TCON3
CA3ED0 PWM3ON -000 0000
-000 0000
12h, Bank 2
TMR3L
Holding register for the low byte of the 16-bit TMR3 register
xxxx xxxx
uuuu uuuu
13h, Bank 2
TMR3H
Holding register for the high byte of the 16-bit TMR3 register
xxxx xxxx
uuuu uuuu
16h, Bank 1
PIR1
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
000- 0000
—
CA4OVF
CA3OVF
0000 0000
0000 0000
PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
0000 0000
CA4ED1
CA4ED0
CA3ED1
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
07h, Unbanked INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
06h, Unbanked CPUSTA
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 1100
--11 qq11
16h, Bank 2
PR3L/CA1L
xxxx xxxx
uuuu uuuu
17h, Bank 2
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
xxxx xxxx
uuuu uuuu
14h, Bank 3
CA2L
Capture2 low byte
xxxx xxxx
uuuu uuuu
15h, Bank 3
CA2H
Capture2 high byte
xxxx xxxx
uuuu uuuu
12h, Bank 7
CA3L
Capture3 low byte
xxxx xxxx
uuuu uuuu
13h, Bank 7
CA3H
Capture3 high byte
xxxx xxxx
uuuu uuuu
14h, Bank 7
CA4L
Capture4 low byte
xxxx xxxx
uuuu uuuu
15h, Bank 7
CA4H
Capture4 high byte
xxxx xxxx
uuuu uuuu
Legend:
Note 1:
Timer3 period register, low byte/capture1 register, low byte
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by Capture.
Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 103
PIC17C75X
13.2.4
13.2.5
EXTERNAL CLOCK INPUT FOR TIMER3
READING/WRITING TIMER3
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method is to stop the timer, perform any read or write
operation, and then restart Timer3 (using the TMR3ON
bit). However, if it is necessary to keep Timer3 free-running, care must be taken. For writing to the 16-bit
TMR3, Example 13-2 may be used. For reading the
16-bit TMR3, Example 13-3 may be used. Interrupts
must be disabled during this routine.
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks twice every instruction cycle. This
causes a delay from the time a falling edge appears on
TCLK3 to the time TMR3 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section. Figure 13-10 shows
the timing diagram when operating from an external
clock.
EXAMPLE 13-2: WRITING TO TMR3
BSF
MOVFP
MOVFP
BCF
CPUSTA,
RAM_L,
RAM_H,
CPUSTA,
GLINTD
TMR3L
TMR3H
GLINTD
; Disable interrupts
;
;
; Done, enable interrupts
EXAMPLE 13-3: READING FROM TMR3
MOVPF
MOVPF
MOVFP
CPFSLT
RETURN
MOVPF
MOVPF
RETURN
TMR3L,
TMR3H,
TMPLO,
TMR3L,
TMPLO
TMPHI
WREG
WREG
TMR3L, TMPLO
TMR3H, TMPHI
;
;
;
;
;
;
;
;
read low TMR3
read high TMR3
tmplo −> wreg
TMR3L < wreg?
no then return
read low TMR3
read high TMR3
return
FIGURE 13-10: TIMER1, TIMER2, AND TIMER3 OPERATION (IN COUNTER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TCLK12
or TCLK3
TMR1, TMR2, or TMR3
34h
PR1, PR2, or PR3H:PR3L
'A9h'
35h
A8h
A9h
00h
'A9h'
WR_TMR
RD_TMR
TMRxIF
Instruction
executed
MOVWF
TMRx
MOVFP
TMRx,W
MOVFP
TMRx,W
Write to TMRx
Read TMRx
Read TMRx
Note 1: TCLK12 is sampled in Q2 and Q4.
2: ↓ indicates a sampling point.
3: The latency from TCLK12 ↓ to timer increment is between 2Tosc and 6Tosc.
DS30264A-page 104
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 13-11: TIMER1, TIMER2, AND TIMER3 OPERATION (IN TIMER MODE)
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
AD15:AD0
ALE
Instruction
fetched
TMR1
MOVF
MOVWF
MOVF
TMR1, W
TMR1
TMR1, W
Write TMR1 Read TMR1 Read TMR1
04h
05h
03h
MOVLB 3
04h
BSF
TCON2, 0
Stop TMR1
05h
NOP
06h
BCF
TCON2, 0
Start TMR1
NOP
07h
NOP
NOP
08h
NOP
00h
PR1
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1
reads 03h
1997 Microchip Technology Inc.
TMR1
reads 04h
Preliminary
DS30264A-page 105
PIC17C75X
NOTES:
DS30264A-page 106
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULES
TABLE 14-1:
Generic name
RCSTA
TXSTA
SPBRG
RCREG
TXREG
Each USART module is a serial I/O module. There are
two USART modules that are available on the
PIC17C75X. They are specified as USART1 and
USART2. The description of the operation of these
modules is generic in regard to the register names and
pin names used. Table 14-1 shows the generic names
that are used in the description of operation and the
actual names for both USART1 and USART2. Since
the control bits in each register have the same function,
their names are the same (there is no need to differentiate).
RCIE
RCIF
TXIE
TXIF
The Transmit Status And Control Register (TXSTA) is
shown in Figure 14-1, while the Receive Status And
Control Register (RCSTA) is shown in Figure 14-2.
RX/DT
TX/CK
USART MODULE GENERIC
NAMES
USART1 name USART2 name
Registers
RCSTA1
RCSTA2
TXSTA1
TXSTA2
SPBRG1
SPBRG2
RCREG1
RCREG2
TXREG1
TXREG2
Interrupt Control Bits
RC1IE
RC2IE
RC1IF
RC2IF
TX1IE
TX2IE
TX1IF
TX2IF
Pins
RA4/RX1/DT1
RG6/RX2/DT2
RA5/TX1/CK1
RG7/TX2/CK2
FIGURE 14-1: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC
TX9
TXEN
SYNC
bit7
bit 7:
bit 6:
bit 5:
bit 4:
U-0
—
U-0
—
R-1
TRMT
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
R/W - x
TX9D
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
TX9: 9-bit Transmit Select bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2: Unimplemented: Read as '0'
bit 1:
bit 0:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 107
PIC17C75X
The USART can be configured as a full duplex asynchronous system that can communicate with peripheral
devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral
devices such as A/D or D/A integrated circuits, Serial
EEPROMs etc. The USART can be configured in the
following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The SPEN (RCSTA<7>) bit has to be set in order to
configure the I/O pins as the Serial Communication
Interface.
The USART module will control the direction of the
RX/DT and TX/CK pins, depending on the states of the
USART configuration bits in the RCSTA and TXSTA
registers. The bits that control I/O direction are:
•
•
•
•
•
SPEN
TXEN
SREN
CREN
CSRC
FIGURE 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
RX9
SREN
CREN
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
R- 0
FERR
R-0
OERR
R-x
RX9D
bit 0
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
DS30264A-page 108
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 14-3: USART TRANSMIT
Sync
Master/Slave
÷4
BRG
Sync/Async
Sync/Async
CK/TX
Sync/Async
TSR
÷ 16
Clock
Start 0 1 • • • 7 8 Stop
DT
Load
TXREG
0 1 ••• 7
Data Bus
8
TXEN/
Write to TXREG
Bit Count
Interrupt
TXSTA<0>
TXIE
FIGURE 14-4: USART RECEIVE
OSC
BRG
Interrupt
÷4
Master/Slave
Sync
CK
Buffer
Logic
Sync/Async
Async/Sync
enable
Bit Count
÷ 16
START
Detect
SPEN
RX
Buffer
Logic
RCIE
Majority
Detect
RSR
Clock
Data
SREN/
CREN/
Start_Bit
MSb
LSb
Stop 8 7 • • • 1 0
FIFO
Logic
RX9
Async/Sync
RCREG
FERR
FERR
RX9D
RX9D
7 ••• 1 0
7 ••• 1 0
Clk
FIFO
Data Bus
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 109
PIC17C75X
14.1
USART Baud Rate Generator (BRG)
Example 14-1 shows the calculation of the baud rate
error for the following conditions:
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 14-2 shows
the formula for computation of the baud rate for different USART modes. These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
FOSC = 16 MHz
Desired Baud Rate = 9600
SYNC = 0
EXAMPLE 14-1: CALCULATING BAUD
RATE ERROR
Desired Baud rate=Fosc / (64 (X + 1))
Given the desired baud rate and Fosc, the nearest integer value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
TABLE 14-2:
SYNC
16000000 /(64 (X + 1))
X
25.042 = 25
=
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
BAUD RATE FORMULA
Mode
9600 =
Error =
Baud Rate
0
Asynchronous
FOSC/(64(X+1))
FOSC/(4(X+1))
1
Synchronous
X = value in SPBRG (0 to 255)
9615
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
(9615 - 9600) / 9600
=
0.16%
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
USART2
USART1
TABLE 14-3:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
13h, Bank 0
RCSTA1
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
13h, Bank 4
RCSTA2
15h, Bank 4
TXSTA2
17h, Bank 4
SPBRG2
Baud rate generator register
xxxx xxxx
uuuu uuuu
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the Baud Rate
Generator.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 110
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 14-4:
BAUD
RATE
(K)
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
NA
—
—
9.6
NA
—
—
NA
—
—
NA
—
—
NA
—
—
19.2
NA
—
—
NA
—
—
19.53
+1.73
255
19.23
+0.16
207
76.8
77.10
+0.39
106
77.16
+0.47
80
76.92
+0.16
64
76.92
+0.16
51
96
95.93
-0.07
85
96.15
+0.16
64
96.15
+0.16
51
95.24
-0.79
41
300
294.64
-1.79
27
297.62
-0.79
20
294.1
-1.96
16
307.69
+2.56
12
500
485.29
-2.94
16
480.77
-3.85
12
500
0
9
500
0
7
HIGH
8250
—
0
6250
—
0
5000
—
0
4000
—
0
LOW
32.22
—
255
24.41
—
255
19.53
—
255
15.625
—
255
BAUD
RATE
(K)
FOSC = 10 MHz
FOSC = 7.159 MHz
FOSC = 5.068 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
9.6
9.766
+1.73
255
9.622
+0.23
185
9.6
0
131
19.2
19.23
+0.16
129
19.24
+0.23
92
19.2
0
65
76.8
75.76
-1.36
32
77.82
+1.32
22
79.2
+3.13
15
96
96.15
+0.16
25
94.20
-1.88
18
97.48
+1.54
12
300
312.5
+4.17
7
298.3
-0.57
5
316.8
+5.60
3
500
500
0
4
NA
—
—
NA
—
—
HIGH
2500
—
0
1789.8
—
0
1267
—
0
LOW
9.766
—
255
6.991
—
255
4.950
—
255
BAUD
RATE
(K)
FOSC = 3.579 MHz
FOSC = 1 MHz
FOSC = 32.768 kHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
0.303
+1.14
26
1.2
NA
—
—
1.202
+0.16
207
1.170
-2.48
6
2.4
NA
—
—
2.404
+0.16
103
NA
—
—
—
9.6
9.622
+0.23
92
9.615
+0.16
25
NA
—
19.2
19.04
-0.83
46
19.24
+0.16
12
NA
—
—
76.8
74.57
-2.90
11
83.34
+8.51
2
NA
—
—
—
96
99.43
_3.57
8
NA
—
—
NA
—
300
298.3
-0.57
2
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
894.9
—
0
250
—
0
8.192
—
0
LOW
3.496
—
255
0.976
—
255
0.032
—
255
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 111
PIC17C75X
TABLE 14-5:
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
1.221
+1.73
255
1.202
+0.16
207
2.4
2.398
-0.07
214
2.396
0.14
162
2.404
+0.16
129
2.404
+0.16
103
9.6
9.548
-0.54
53
9.53
-0.76
40
9.469
-1.36
32
9.615
+0.16
25
19.2
19.09
-0.54
26
19.53
+1.73
19
19.53
+1.73
15
19.23
+0.16
12
KBAUD
%ERROR
SPBRG
value
(decimal)
76.8
73.66
-4.09
6
78.13
+1.73
4
78.13
+1.73
3
83.33
+8.51
2
96
103.12
+7.42
4
97.65
+1.73
3
104.2
+8.51
2
NA
—
—
300
257.81
-14.06
1
390.63
+30.21
0
312.5
+4.17
0
NA
—
—
500
515.62
+3.13
0
NA
—
—
NA
—
—
NA
—
—
HIGH
515.62
—
0
—
—
0
312.5
—
0
250
—
0
LOW
2.014
—
255
1.53
—
255
1.221
—
255
0.977
—
255
BAUD
RATE
(K)
FOSC = 10 MHz
FOSC = 7.159 MHz
FOSC = 5.068 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
0.31
+3.13
255
1.2
1.202
+0.16
129
1.203
_0.23
92
1.2
0
65
2.4
2.404
+0.16
64
2.380
-0.83
46
2.4
0
32
9.6
9.766
+1.73
15
9.322
-2.90
11
9.9
-3.13
7
19.2
19.53
+1.73
7
18.64
-2.90
5
19.8
+3.13
3
76.8
78.13
+1.73
1
NA
—
—
79.2
+3.13
0
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
156.3
—
0
111.9
—
0
79.2
—
LOW
0.610
—
255
0.437
—
255
0.309
BAUD
RATE
(K)
FOSC = 3.579 MHz
FOSC = 1 MHz
0
—
255
SPBRG
value
(decimal)
FOSC = 32.768 kHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
0.3
0.301
+0.23
185
0.300
+0.16
51
0.256
-14.67
1
1.2
1.190
-0.83
46
1.202
+0.16
12
NA
—
—
2.4
2.432
+1.32
22
2.232
-6.99
6
NA
—
—
9.6
9.322
-2.90
5
NA
—
—
NA
—
—
19.2
18.64
-2.90
2
NA
—
—
NA
—
—
76.8
NA
—
—
NA
—
—
NA
—
—
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
55.93
—
0
15.63
—
0
0.512
—
0
LOW
0.218
—
255
0.061
—
255
0.002
—
255
DS30264A-page 112
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.2
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmitter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
14.2.1
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 14-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the
TXREG is empty and an interrupt bit, TXIF, is set. This
interrupt can be enabled/disabled by setting/clearing
the TXIE bit. TXIF will be set regardless of TXIE and
cannot be reset in software. It will reset only when new
data is loaded into TXREG. While TXIF indicates the
status of the TXREG, the TRMT (TXSTA<1>) bit shows
the status of the TSR. TRMT is a read only bit which is
set when the TSR is empty. No interrupt logic is tied to
this bit, so the user has to poll this bit in order to determine if the TSR is empty.
Note:
Transmission
is
enabled
by
setting
the
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
1.
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Load data to the TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN (starts
transmission).
2.
3.
4.
5.
6.
7.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the opposite
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
The TSR is not mapped in data memory,
so it is not available to the user.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 113
PIC17C75X
FIGURE 14-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
(TX/CK pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
Word 1
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 14-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
(TX/CK pin)
Start Bit
Bit 0
TXIF bit
Bit 1
Word 1
Bit 7/8
Word 1
Transmit Shift Reg.
TRMT bit
Start Bit
Word 2
Stop Bit
Bit 0
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 14-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
16h, Bank 1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
13h, Bank 0
RCSTA1
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 0
TXREG1
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA1
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
xxxx xxxx
uuuu uuuu
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 4
TXREG2
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
RX9
Bit 5
SREN
Bit 4
CREN
Bit 3
Bit 2
Bit 1
Bit 0
Value on all
other resets
(Note1)
Name
SPEN
Bit 6
Value on
POR,
BOR
Address
Serial port transmit register (USART1)
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
Baud rate generator register (USART1)
Serial port transmit register (USART2)
CSRC
TX9
TXEN
SYNC
—
—
Baud rate generator register (USART2)
TRMT
TX9D
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 114
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.2.2
USART ASYNCHRONOUS RECEIVER
Note:
The receiver block diagram is shown in Figure 14-4.
The data comes in the RX/DT pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the stop bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit,
RCIF, is set. The actual interrupt can be enabled/disabled by setting/clearing the RCIE bit. RCIF is a read
only bit which is cleared by the hardware. It is cleared
when RCREG has been read and is empty. RCREG is
a double buffered register; (i.e. it is a two deep FIFO).
It is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR. On detection of the stop bit of the
third byte, if the RCREG is still full, then the overrun
error bit, OERR (RCSTA<1>) will be set. The word in
the RSR will be lost. RCREG can be read twice to
retrieve the two bytes in the FIFO. The OERR bit has to
be cleared in software which is done by resetting the
receive logic (CREN is set). If the OERR bit is set,
transfers from the RSR to RCREG are inhibited, so it is
essential to clear the OERR bit if it is set. The framing
error bit FERR (RCSTA<2>) is set if a stop bit is not
detected.
14.2.3
The FERR and the 9th receive bit are buffered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with values for the next received Received data.
Therefore, it is essential for the user to
read the RCSTA register before reading
RCREG in order not to lose the old FERR
and RX9D information.
SAMPLING
The data on the RX/DT pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX/DT pin. The sampling is done
on the seventh, eighth and ninth falling edges of a x16
clock (Figure 14-7).
The x16 clock is a free running clock, and the three
sample points occur at a frequency of every 16 falling
edges.
FIGURE 14-7: RX PIN SAMPLING SCHEME
Start bit
RX
(RX/DT pin)
Bit0
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 115
PIC17C75X
7.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF bit will be set when reception completes and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred during reception.
Read RCREG for the 8-bit received data.
If an overrun error occurred, clear the error by
clearing the OERR bit.
8.
9.
Note:
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 14-8: ASYNCHRONOUS RECEPTION
Start
bit
RX
(RX/DT pin)
bit0
bit1
Start
bit
bit7/8 Stop
bit
bit0
bit7/8
Stop
bit
Start
bit
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
Stop
bit
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 14-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
16h, Bank 1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
13h, Bank 0
RCSTA1
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 0
RCREG1
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
10h, Bank 4
PIR2
SSPIF
BCLIF
Baud rate generator register
ADIF
—
CA4IF
CA3IF
xxxx xxxx
uuuu uuuu
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 4
RCREG2
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 116
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchronous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>)
bit is set in order to configure the I/O pins to CK (clock)
and DT (data) lines respectively. The Master mode
indicates that the processor transmits the master clock
on the CK line. The Master mode is entered by setting
the CSRC (TXSTA<7>) bit.
14.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 14-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF bit is set. This interrupt can be
enabled/disabled by setting/clearing the TXIE bit. TXIF
will be set regardless of the state of bit TXIE and cannot
be cleared in software. It will reset only when new data
is loaded into TXREG. While TXIF indicates the status
of TXREG, TRMT (TXSTA<1>) shows the status of the
TSR. TRMT is a read only bit which is set when the
TSR is empty. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
is empty. The TSR is not mapped in data memory, so it
is not available to the user.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the TX/CK pin. Data out is stable around
the falling edge of the synchronous clock
(Figure 14-10). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to the TSR, resulting in an empty TXREG.
Back-to-back transfers are possible.
tion). The TX/CK pin will remain an output if the CSRC
bit is set (internal clock). The transmitter logic is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear the TXEN
bit. If the SREN bit is set (to interrupt an ongoing transmission and receive a single word), then after the single word is received, SREN will be cleared and the
serial port will revert back to transmitting, since the
TXEN bit is still set. The DT line will immediately switch
from hi-impedance receive mode to transmit and start
driving. To avoid this, TXEN should be cleared.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to the
TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
2.
3.
4.
5.
6.
7.
8.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmitter. The RX/DT and TX/CK pins will revert to hi-impedance. If either CREN or SREN are set during a
transmission, the transmission is aborted and the
RX/DT pin reverts to a hi-impedance state (for a recep-
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 117
PIC17C75X
TABLE 14-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Value on
POR,
BOR
Value on all
other resets
(Note1)
TX1IF
RC1IF
0000 0010
0000 0010
TX1IE
RC1IE
0000 0000
0000 0000
RX9D
0000 -00x
0000 -00u
Name
16h, Bank 1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
17h, Bank 1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
13h, Bank 0
RCSTA1
SPEN
RX9
CREN
—
FERR
OERR
16h, Bank 0
TXREG1
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
xxxx xxxx
uuuu uuuu
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 4
TXREG2
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
SREN
Bit 4
Bit 0
Address
Bit 1
Baud rate generator register
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
FIGURE 14-9: SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
DT
(RX/DT pin)
bit0
bit1
bit2
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit7
Word 1
bit0
Word 2
CK
(TX/CK pin)
Write to
TXREG
Write word 1
Write word 2
TXIF
Interrupt flag
TRMT
TXEN
'1'
FIGURE 14-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
(RX/DT pin)
bit0
bit1
bit2
bit6
bit7
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30264A-page 118
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.3.2
Steps to follow when setting up a Synchronous Master
Reception:
USART SYNCHRONOUS MASTER
RECEPTION
1.
Once synchronous mode is selected, reception is
enabled by setting either the SREN (RCSTA<5>) bit or
the CREN (RCSTA<4>) bit. Data is sampled on the
RX/DT pin on the falling edge of the clock. If SREN is
set, then only a single word is received. If CREN is set,
the reception is continuous until CREN is reset. If both
bits are set, then CREN takes precedence. After clocking the last bit, the received data in the Receive Shift
Register (RSR) is transferred to RCREG (if it is empty).
If the transfer is complete, the interrupt bit RCIF is set.
The actual interrupt can be enabled/disabled by setting/clearing the RCIE bit. RCIF is a read only bit which
is RESET by the hardware. In this case it is reset when
RCREG has been read and is empty. RCREG is a double buffered register; i.e., it is a two deep FIFO. It is
possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin
shifting into the RSR. On the clocking of the last bit of
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve
the two bytes in the FIFO. The OERR bit has to be
cleared in software. This is done by clearing the CREN
bit. If OERR is set, transfers from RSR to RCREG are
inhibited, so it is essential to clear the OERR bit if it is
set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
Initialize the SPBRG register for the appropriate
baud rate. See Section 14.1 for details.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
The RCIF bit will be set when reception is complete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
CREN.
2.
3.
4.
5.
6.
7.
8.
9.
Note:
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 14-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT
(RX/DT pin)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
CK
(TX/CK pin)
Write to the
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
Read
RCREG
Note: Timing diagram demonstrates SYNC master mode with SREN = 1.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 119
PIC17C75X
TABLE 14-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
16h, Bank 1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank 1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
13h, Bank 0
RCSTA1
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 0
RCREG1
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
10h, Bank 4
PIR2
SSPIF
BCLIF
Baud rate generator register
ADIF
—
CA4IF
CA3IF
xxxx xxxx
uuuu uuuu
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 4
RCREG2
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 120
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
14.4
USART Synchronous Slave Mode
14.4.2
The synchronous slave mode differs from the master
mode in the fact that the shift clock is supplied externally at the TX/CK pin (instead of being supplied internally in the master mode). This allows the device to
transfer or receive data in the SLEEP mode. The slave
mode is entered by clearing the CSRC (TXSTA<7>)
bit.
14.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the sync master and slave modes are
identical except in the case of the SLEEP mode.
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will transmit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to interrupt vector
(0020h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting the SYNC and SPEN bits and clearing the
CSRC bit.
Clear the CREN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to TXREG.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
USART SYNCHRONOUS SLAVE
RECEPTION
Operation of the synchronous master and slave modes
are identical except in the case of the SLEEP mode.
Also, SREN is a don't care in slave mode.
If receive is enabled (CREN) prior to the SLEEP instruction, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
To enable reception, set the CREN bit.
The RCIF bit will be set when reception is complete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
the CREN bit.
2.
3.
4.
5.
6.
7.
8.
Note:
To abort reception, either clear the SPEN
bit, the SREN bit (when in single receive
mode), or the CREN bit (when in continuous receive mode). This will reset the
receive logic, so that it will be in the proper
state when receive is re-enabled.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 121
PIC17C75X
TABLE 14-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
16h, Bank 1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
17h, Bank 1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
13h, Bank 0
RCSTA1
SPEN
—
FERR
RX9
SREN
CREN
Bit 3
Bit 2
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
TX1IF
RC1IF
0000 0010
0000 0010
TX1IE
RC1IE
0000 0000
0000 0000
OERR
RX9D
0000 -00x
0000 -00u
Bit 1
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
16h, Bank 0
TXREG1
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
17h, Bank 0
SPBRG1
xxxx xxxx
uuuu uuuu
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 4
TXREG2
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
Baud rate generator register
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
TABLE 14-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
16h, Bank1
PIR1
RBIF
TMR3IF TMR2IF TMR1IF
CA2IF
CA1IF
TX1IF
RC1IF
0000 0010
0000 0010
17h, Bank1
PIE1
RBIE
TMR3IE TMR2IE TMR1IE
CA2IE
CA1IE
TX1IE
RC1IE
0000 0000
0000 0000
13h, Bank0
RCSTA1
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank0
RCREG1
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA1
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG1
10h, Bank 4
PIR2
SSPIF
BCLIF
Baud rate generator register
ADIF
—
CA4IF
CA3IF
xxxx xxxx
uuuu uuuu
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
13h, Bank 4
RCSTA2
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 4
RCREG2
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
15h, Bank 4
TXSTA2
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 4
SPBRG2
xxxx xxxx
uuuu uuuu
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 122
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.0
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
FIGURE 15-2: I2C SLAVE MODE BLOCK
DIAGRAM
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
Internal
data bus
Read
Write
SSPBUF reg
SCL
shift
clock
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I 2C)
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment."
SSPSR reg
SDA
MSb
Figure 15-1, Figure 15-2, and Figure 15-3 show the
block diagrams for the three different modes of operation.
Addr Match
Match detect
FIGURE 15-1: SPI MODE BLOCK
DIAGRAM
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
Internal
data bus
Read
LSb
Write
FIGURE 15-3: I2C MASTER MODE BLOCK
DIAGRAM
SSPBUF reg
Internal
data bus
Read
SSPADD<6:0>
7
SSPSR reg
SDI
shift
clock
bit0
Write
Baud Rate Generator
SDO
SSPBUF reg
SCL
shift
clock
SS Control
Enable
SS
SSPSR reg
Edge
Select
SDA
2
Clock Select
SCK
MSb
LSb
Addr Match
Match detect
SSPM3:SSPM0
SMP:CKE 4
TMR2 output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
SSPADD reg
Start and Stop bit
detect / generate
Set/Clear S bit
and
Clear/Set P, bits
(SSPSTAT reg)
and Set SSPIF
Data to TX/RX in SSPSR
Data direction bit
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 123
PIC17C75X
FIGURE 15-4: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
R/W-0 R/W-0
SMP
CKE
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R-0
D/A
R-0
P
R-0
S
R-0
R/W
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 15-8, Figure 15-11, and Figure 15-12)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I2C slave mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress. Or’ing this bit with SAE, RCE, SPE, or AKE will indicate if the SSP is in
IDLE mode.
UA: Update Address (10-bit I2C slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include ACK and stop bits), SSPBUF is empty
DS30264A-page 124
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-5: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER1 (ADDRESS 11h, BANK 6)
R/W-0
WCOL
bit7
bit 7:
bit 6:
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is
not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1 = Reserved
1x1x = Reserved
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 125
PIC17C75X
FIGURE 15-6: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
GCEN
bit7
bit 7:
bit 6:
bit 5:
bit 4:
R-0
ACKSTAT
R/W-0
ACKDT
R/W-0
ACKEN
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n =Value at POR reset
GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address is received in the SSPSR.
0 = General call address disabled.
ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKD data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 3:
RCEN: Receive Enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C
0 = Receive idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 2:
PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 1:
RSEN: Restart Condition Enabled bit (In I2C master mode only)
1 = Initiate Restart condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Restart condition idle.
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled)
bit 0:
SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
DS30264A-page 126
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.1
SPI Mode
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control
bits
in
the
SSPCON1
register
(SSPCON1<5:0>) and SSPSTAT<7:6>. These control
bits allow the following to be specified:
•
•
•
•
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit BF (SSPSTAT<0>) indicates when SSPBUF has
been loaded with the received data (transmission is
complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 15-1 shows the loading of the
SSPBUF (SSPSR) for data transmission. The shaded
instruction is only required if the received data is meaningful.
EXAMPLE 15-1: LOADING THE SSPBUF
(SSPSR) REGISTER
MOVLB 6
LOOP BTFSS SSPSTAT, BF
;
;
;
;
;
GOTO LOOP
;
MOVPF SSPBUF, RXDATA ;
MOVFP TXDATA, SSPBUF ;
Bank 6
Has data been
received
(transmit
complete)?
No
Save in user RAM
New data to xmit
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR2<7>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON1<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSPBUF register completed successfully.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 127
PIC17C75X
The block diagram of the SSP module, when in SPI
mode (Figure 15-7), shows that the SSPSR is not
directly readable or writable, and can only be accessed
by addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 15-7: SSP BLOCK DIAGRAM
(SPI MODE)
•
•
•
•
•
Internal
data bus
Read
Write
SSPBUF reg
SSPSR reg
SDI
SDO
SS Control
Enable
SS
Edge
Select
2
Clock Select
SCK
SSPM3:SSPM0
SMP:CKE 4
TMR2 output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
Data direction bit
DS30264A-page 128
SDI is automatically controlled by the SPI module
SDO must have DDRB<7> cleared
SCK (Master mode) must have DDRB<6> cleared
SCK (Slave mode) must have DDRB<6> set
SS must have PORTA<2> set
Note:
The SS pin must be configured as an input
for the slave select to operate. This is done
by writing a ’1’ to PORTA<2>.
Any serial port function that is not desired may be overridden by programming the corresponding data direction (DDR) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose open drain outputs by writing a ’0’.
shift
clock
bit0
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>) must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
registers, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the DDR register)
appropriately programmed. That is:
Figure 15-9 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite
edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.1.1
MSB is transmitted first. In master mode, the SPI clock
rate (bit rate) is user programmable to be one of the following:
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-9) is to broadcast data by the software protocol.
•
•
•
•
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum bit clock frequency (at 33 MHz)
of 8.25 MHz.
Figure 15-8 Shows the waveforms for master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately programming bit CKP (SSPCON1<4>). This then would give
waveforms for SPI communication as shown in
Figure 15-8, Figure 15-11, and Figure 15-12 where the
FIGURE 15-8: SPI MODE TIMING (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDO
(CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 129
PIC17C75X
15.1.2
15.1.3
SLAVE MODE
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR2<7>)
is set.
While in slave mode the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in sleep mode, the slave can transmit/receive
data and wake the device from sleep.
SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The RA2 Data Latch must be high. When the SS pin
is low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the
middle of a transmitted byte, and becomes a
floating output. External pull-up/ pull-down resistors
may be desirable, depending on the application.
Note:
Note:
When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
In Figure 15-11 the SS pin terminates the transmission/reception. The SSPIF bit is set after the last edge
of the SCK. In Figure 15-12 the SS pin causes the first
bit of the data to be output. The SSPIF bit in set after
the last SCK edge.
FIGURE 15-9: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
Shift Register
(SSPSR)
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
DS30264A-page 130
PROCESSOR 2
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-10: SLAVE SYNCHRONIZATION TIMING
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit7
bit0
bit0
bit7
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 131
PIC17C75X
FIGURE 15-11: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS30264A-page 132
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit7
SDO
SDI
(SMP = 0)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
TABLE 15-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
14h, Bank 6
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
11h, Bank 6
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
13h, Bank 6
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
07h, Unbanked INTSTA
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 133
PIC17C75X
15.2
SSP I 2C Operation
The SSP module in I 2C mode fully implements all master and slave functions (including general call support)
and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function).
The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
Appendix E gives an overview of the I 2C bus specification.
FIGURE 15-13: SSP BLOCK DIAGRAM
(I2C MODE)
Internal
data bus
Read
Write
shift
clock
MSb
LSb
Addr Match
Match detect
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
FIGURE 15-14: I2C MASTER MODE BLOCK
DIAGRAM
Internal
data bus
Read
SSPADD<6:0>
7
Write
Baud Rate Generator
SSPBUF reg
SCL
shift
clock
SSPSR reg
SDA
MSb
LSb
Match detect
•
•
•
•
•
SSP Control Register1 (SSPCON1)
SSP Control Register2 (SSPCON2)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Master mode, clock = OSC/4 (SSPADD +1)
SSPSR reg
SDA
The SSP module has six registers for I2C operation.
These are the:
The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I 2C modes to be selected:
SSPBUF reg
SCL
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. Pins that are on PortA are automatically configured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON1<5>).
Addr Match
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain. These
pins are on PORTA and therefore there is no need to
program to be inputs.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
SSPADD reg
Start and Stop bit
detect / generate
DS30264A-page 134
Set/Clear S bit
and
Clear/Set P, bits
(SSPSTAT reg)
and Set SSPIF
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.2.1
a)
SLAVE MODE
In slave mode, the SCL and SDA pins must be configured as inputs. The SSP module will override the input
state with the output data when required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
b)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON1<6>) was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR2<7>) is set.
Table 15-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmitter:
1.
3.
4.
5.
15.2.1.1
7.
8.
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
TABLE 15-2:
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address, if match occurs releases the
SCL line, this will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
2.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification as well as the requirement of
the SSP module is shown in timing parameter #100
and parameter #101.
ADDRESSING
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR2<7>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
6.
9.
Note:
Following the RESTART condition (step 7)
in 10-bit mode, the user only needs to
match the first 7-bit address. The user
does not update the SSPADD for the second half of the address.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
1997 Microchip Technology Inc.
Preliminary
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Yes
Yes
Yes
Yes
DS30264A-page 135
PIC17C75X
15.2.1.2
SLAVE RECEPTION
15.2.1.3
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCLpin is held low. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then SCL pin
should be enabled by setting bit CKP (SSPCON1<4>).
The master must monitor the SCL pin prior to asserting
another clock pulse. The slave devices may be holding
off the master by stretching the clock. The eight data
bits are shifted out on the falling edge of the SCL input.
This ensures that the SDA signal is valid during the
SCL high time (Figure 15-16).
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR2<7>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
Note:
SLAVE TRANSMISSION
The SSPBUF will be loaded if the SSPOV
bit = 1 and the BF flag = 0. If a read of the
SSPBUF was performed, but the user did
not clear the state of the SSPOV bit before
the next receive occured. The ACK is not
sent and the SSPBUF is updated.
FIGURE 15-15: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
Receiving Data
R/W=0
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
1
S
2
3
4
5
6
7
9
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
8
7
6
9
SSPIF (PIR2<7>)
P
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON1<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
FIGURE 15-16: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30264A-page 136
Preliminary
1997 Microchip Technology Inc.
1997 Microchip Technology Inc.
Preliminary
UA (SSPSTAT<1>)
2
1
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
1
SCL
S
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
8
9
ACK
Receive First Byte of Address R/W = 0
SDA
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address.
6
A6 A5 A4 A3 A2 A1
Dummy read of SSPBUF
to clear BF flag
A7
8
A0
Receive Second Byte of Address
Clock is held low until
update of SSPADD has
taken place
9
ACK
2
3
1
4
1
Cleared in software
1
1
Cleared by hardware when
SSPADD is updated with high
byte of address.
Dummy read of SSPBUF
to clear BF flag
Sr
1
5
0
6
7
A9 A8
Receive First Byte of Address
8
9
R/W=1
ACK
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
Cleared in software
CKP has to be set for clock to be released
2
D6
Write of SSPBUF
initiates transmit
1
D7
Transmitting Data
9
ACK
Bus Master
terminates
transfer
P
Master sends NACK
Transmit is complete
PIC17C75X
FIGURE 15-17: I2C SLAVE-TRANSMITTER (10-BIT ADDRESS)
DS30264A-page 137
DS30264A-page 138
Preliminary
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
1
SCL
S
1
SDA
2
1
3
1
5
0
6
A9
7
A8
UA is set indicating that
the SSPADD needs to be
updated
8
9
ACK
R/W = 0
SSPBUF is written with
contents of SSPSR
4
1
Receive First Byte of Address
1
3
A5
4
A4
Cleared in software
2
A6
5
A3
6
A2
7
A1
8
A0
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address.
Dummy read of SSPBUF
to clear BF flag
A7
Receive Second Byte of Address
Clock is held low until
update of SSPADD has
taken place
9
ACK
2
4
5
6
Cleared in software
3
Dummy read of SSPBUF
to clear BF flag
1
7
ACK
P
Read of SSPBUF
clears BF flag
8
9
R/W=1
D4 D3 D2 D1 D0
Receive Data Byte
D7 D6 D5
Bus Master
terminates
transfer
PIC17C75X
FIGURE 15-18: I2C SLAVE-RECEIVER (10-BIT ADDRESS)
1997 Microchip Technology Inc.
PIC17C75X
15.2.2
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually determines which device will be the slave addressed by the
master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then the SCL pin
should be enabled by setting bit CKP.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7>
= 1). Following a start-bit detect, 8-bits are shifted into
SSPSR and the address is compared against
SSPADD, and is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transfered to the SSPBUF, the BF flag is set (eigth bit),
and on the falling edge of the ninth bit (ACK bit) the
SSPIF interrupt is set.
When the interrupt is serviced. The source for the
interrupt can be checked by reading the contents of
the SSPBUF to determine if the address was device
specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the
UA bit is set (SSPSTAT<1>). If the general call
address is sampled when GCEN = 1 while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
acknowledge (Figure 15-19).
FIGURE 15-19: GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
Receiving data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF (PIR2<7>)
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 139
PIC17C75X
TABLE 15-3:
Address
REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note 1)
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
00-- 0000
00-- 0000
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
10h. Bank 6
SSPADD
Synchronous Serial Port (I2C mode) Address Register
14h, Bank 6
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
11h, Bank 6
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
12h, Bank 6
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
13h, Bank 6
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
07h, Unbanked INTSTA
Legend:
00-- 0000
00-- 0000
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 140
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.2.3
MASTER MODE
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is disabled. Control of the I 2C bus may be taken when the P
bit is set, or the bus is idle with both the S and P bits
clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
In master mode, the SCL and SDA lines are manipulated by the SSP hardware.
FIGURE 15-20: SSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus
Read
SSPM3:SSPM0
SSPADD<6:0>
Write
SSPBUF
shift
clock
SDA
SDA in
SSPSR
SCL in
Bus Collision
1997 Microchip Technology Inc.
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
Preliminary
clock cntl
SCL
Receive Enable
MSb
clock arbitrate/WCOL detect
(hold off clock source)
Baud
rate
generator
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS30264A-page 141
PIC17C75X
15.2.4
MULTI-MASTER MODE
15.2.5.1
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. Control of the I 2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check is performed in hardware, with the
result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Restart Condition
An Acknowledge Condition
15.2.5
I2C MASTER MODE SUPPORT
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting
the SSPEN bit. Once master mode is enabled, the
user has six options.
- Assert a start condition on SDA and SCL.
- Assert a restart condition on SDA and SCL.
- Write to the SSPBUF register initiating transmission of data/address.
- Generate a stop Condition on SDA and SCL.
- Configure the I2C port to receive data.
- Generate an acknowledge condition at the end
of a received byte of data.
Note:
The SSP Module when configured in I2C
Master Mode does not allow queueing of
events. For instance: The user is not
allowed to intitiate a start condition, and
immediately write the SSPBUF register to
initate transmission before the START condition is complete. In this case the SSPBUF will not be written to, and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated
START condition. Since the repeated START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
In Master transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device, (7 bits) and the data direction bit. In
this case the data direction bit (R/W) will be logic '0'.
Serial data is transmitted 8 bits at a time. After each
byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the
beginning and the end of a serial transfer.
In Master receive mode the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic '1'. Thus the first byte
transmitted is a 7-bit slave address followed by a '1' to
indicate receive bit. Serial data is received via SDA
while SCL outputs the serial clock. Serial data is
received 8 bits at a time. After each byte is received,
an acknowledge bit is transmitted. START and STOP
conditions indicate the beginning and end of transmission.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.
transmission of the last data bit is followed by ACK)
the internal clock will automatically stop counting and
the SCL pin will remain in its last state
A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
DS30264A-page 142
I2C MASTER MODE OPERATION
Preliminary
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
start time before any other operation takes
place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The SSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of
data.
DATA is shifted out the SDA pin until all 8 bits
are transmitted.
1997 Microchip Technology Inc.
PIC17C75X
15.2.6
9.
The SSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
10. The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
11. The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
BAUD RATE GENERATOR
In I2C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-21). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. In I2C master mode,
the BRG is not reloaded automatically. If Clock Arbitration is taking place for instance, the BRG will be
reloaded when the SCL pin is sampled high
(Figure 15-22).
FIGURE 15-21: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
Reload
SCL
Control
SSPADD<6:0>
Reload
CLKOUT
BRG Down Counter
Fosc/4
FIGURE 15-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG counts
down
BRG
value
00h
03h
02h
BRG counts
down
01h
BRG counts
down
00h
XX
03h
02h
01h
00h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
Note: There are two baud rate overflows per clock period. Clock period may be of variable time due to clock arbitration.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 143
PIC17C75X
15.2.7
I2C MASTER MODE START CONDITION
TIMING
Note:
To initiate a START condition the user sets the start
condition enable bit or SEN bit (SSPCON2<0>). If the
SDA and SCL pins are sampled high, the baud rate
generator is re-loaded with the contents of
SSPADD<6:0>, and starts its count. If SCL and SDA
are both sampled high when the baud rate generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
START condition, and causes the S bit (SSPSTAT<3>)
to be set. Since the I2C module is configured in master
mode, a '1' in the S bit causes the SSPIF flag to be
set. Following this, the baud rate generator is reloaded
with the contents of SSPADD<6:0> and resumes its
count. When the baud rate generator times out (TBRG)
the SEN bit in the SSPCON2 register will be automatically cleared, the baud rate generator is suspended
leaving the SDA line held low, and the START condition is complete.
15.2.7.1
If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I2C module is reset into its IDLE state.
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 15-23: FIRST START BIT TIMING
Write to SSPCON2<0> occurs here.
SDA = 1,
SCL = 1
TBRG
Set S bit (SSPSTAT<3>)
At completion of start bit,
automatic clear SSPCON2<0>
TBRG
Write to SSPBUF occurs here
1st Bit
SDA
SCL
DS30264A-page 144
2nd Bit
TBRG
S
TBRG
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-24: START CONDITION FLOWCHART
SSPEN = 1,
SSPCON1<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Bus collision detected,
Set BCLIF,
Release SCL,
Clear SEN
No
SDA = 1?
SCL = 1?
Yes
Load BRG with
SSPADD<6:0>
No
No
No
Yes
SCL= 0?
SDA = 0?
BRG
Rollover?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit and SSPIF.
No
SCL = 0?
Yes
No
BRG
rollover?
Yes
Reset BRG
Force SCL = 0,
Start Condition Done,
Clear SEN.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 145
PIC17C75X
15.2.8
I2C MASTER MODE RESTART CONDITION
TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
A RESTART condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the SSP
module is in the idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with
the contents of SSPADD<5:0>, and begins counting.
The SDA pin is released (brought high) for one baud
rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin
will be de-asserted (brought high). When SCL is sampled high the baud rate generator is re-loaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL = 1. Following
this, the RSEN bit in the SSPCON2 register will be
automatically cleared, and the baud rate generator is
not reloaded, leaving the SDA pin held low. As soon
as a start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF
bit will not be set until the baud rate generator has
timed-out.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the
falling edge of the eighth clock the master will
de-assert the SDA pin allowing the slave to respond
with an acknowledge. On the falling edge of the ninth
clock the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is programmed into the AKSTAT status bit
SSPCON2<6>. Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set,
the BF flag is cleared, and the baud rate generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
15.2.8.1
WCOL STATUS FLAG
If the user writes the SSPBUF when a RESTART
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note 1: If the RSEN is programmed while a transmit is in progress, it will not take effect.
Note 2: A bus collision during the RESTART condition occurs if:
Note:
•SDA is sampled low when SCL goes
from low to high.
•SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the RESTART
condition is complete.
FIGURE 15-25: REPEAT START CONDITION TIMING
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
SDA = 1,
SCL = 1
TBRG
At completion of start bit,
automatic clear SSPCON2<1>
TBRG
TBRG
1st Bit
SDA
Falling edge of ninth clock
End of Xmit
Write to SSPBUF occurs here.
TBRG
SCL
TBRG
Sr = Restart
DS30264A-page 146
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-26: RESTART CONDITION FLOWCHART (PAGE 1)
Start
B
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
RSEN = 1(SSPCON2<1>)
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
BRG
rollover?
No
Yes
Release SCL
(Clock Arbitration)
SCL = 1?
No
Yes
Bus Collision,
Set BCLIF,
Release SDA,
Clear RSEN
No
SDA = 1?
Yes
Load BRG with
SSPADD<6:0>
C
1997 Microchip Technology Inc.
A
Preliminary
DS30264A-page 147
PIC17C75X
FIGURE 15-27: RESTART CONDITION FLOWCHART (PAGE 2)
B
C
A
Yes
No
No
SCL = 1?
No
SDA = 0?
Yes
BRG
rollover?
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S,
Set SSPIF
No
BRG
rollover?
Yes
Force SCL = 0,
Restart condition done,
Clear RSEN
DS30264A-page 148
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.2.9
I2C MASTER MODE TRANSMISSION
15.2.9.1
Transmission of a data byte, a 7-bit address, or the
either half of a 10-bit address is accomplished by simply writing a value to SSPBUF register. This action will
set the buffer full flag (BF) and allow the baud rate
generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time spec). SCL is held low
for one baud rate generator roll over count (TBRG).
Data should be valid before SCL is released high (see
Data setup time spec). When the SCL pin is released
high, it is held that way for TBRG, the data on the SDA
pin must remain stable for that duration and some hold
time after the next falling edge of SCL. After the
eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA allowing the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurs or if data was received properly.
The status of ACK is read into the SSPCON2 register
bit6 on the falling edge of the ninth clock. If the master
receives an acknowledge, the acknowledge status bit
(AKSTAT) is cleared. If not, the bit is set. After the
ninth clock the SSPIF is set, and the master clock
(baud rate generator) is suspended until the next data
byte is loaded into the SSPBUF leaving SCL low and
SDA unchanged. (Figure 15-29)
1997 Microchip Technology Inc.
BF STATUS FLAG
In transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
15.2.9.2
WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.2.9.3
AKSTAT STATUS FLAG
In transmit mode, the AKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the slave does not
acknowledge (ACK = 1). A slave sends an acknowledge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Preliminary
DS30264A-page 149
PIC17C75X
FIGURE 15-28: MASTER TRANSMIT FLOWCHART
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Yes
Num_Clocks
= 8?
Release SDA so
slave can drive ACK
No
Load BRG with
SSPADD<6:0>,
start BRG count
Load BRG with
SSPADD<6:0>,
start BRG count,
SDA = Current Data bit
BRG
rollover?
BRG
rollover?
No
No
Yes
Yes
Force SCL = 1,
Stop BRG
Stop BRG,
Force SCL = 1
(Clock Arbitration)
SCL = 1?
(Clock Arbitration)
No
SCL = 1?
No
Yes
Yes
SDA =
Data bit?
No
Bus collision detected
Set BCLIF, hold prescale off
Clear XMIT enable
Load BRG with
SSPADD<6:0>,
count high time
Yes
No
Rollover?
Load BRG with
SSPADD<6:0>,
count SCL high time
Yes
Yes
BRG
rollover?
No
No
SCL = 0?
SDA =
Data bit?
Read SDA and place into
AKSTAT bit (SSPCON2<6>)
Force SCL = 0,
BF = 0,
Set SSPIF
Yes
Yes
No
Reset BRG
Num_Clocks
= Num_Clocks + 1
DS30264A-page 150
Preliminary
1997 Microchip Technology Inc.
1997 Microchip Technology Inc.
S
Preliminary
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
cleared in software
2
6
7
8
9
After start condition SEN cleared by hardware.
SSPBUF written
1
D7
3
D5
4
D4
5
D3
6
D2
7
D1
SSPBUF is written in software
8
D0
cleared in software service routine
From SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave clear AKSTAT bit SSPCON2<6>
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7 bit address and R/W
start transmit
A7
Transmit Address to Slave
SEN = 0
Write SSPCON2<0> SEN = 1
START condition begins
P
Cleared in software
9
ACK
AKSTAT in
SSPCON2 = 1
PIC17C75X
FIGURE 15-29: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS30264A-page 151
PIC17C75X
15.2.10 I2C MASTER MODE RECEPTION
15.2.10.1 BF STATUS FLAG
Master mode reception is enabled by programming
the receive enable bit, RCEN (SSPCON2<3>).
In receive operation, BF is set when an address or
data byte is loaded into SSPBUF from SSPSR. It is
cleared when SSPBUF is read.
Note:
The SSP Module must be in IDLE mode
before the RCE bit is set, or the RCEN bit
will be disreguarded.
The baud rate generator begins counting, and on
each rollover, the state of the SCL pin changes (high
to low/low to high), and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive
enable flag is automatically cleared, the contents of
the SSPSR are loaded into the SSPBUF, the BF flag is
set, the SSPIF is set, and the baud rate generator is
suspended from counting, holding SCL low. The SSP
is now in IDLE state, awaiting the next command.
When the buffer is read by the CPU, the BF flag is
automatically cleared. The user can then send an
acknowledge bit at the end of reception, by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>).
DS30264A-page 152
15.2.10.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already
set from a previous reception.
15.2.10.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e. SSPSR is still shifting in a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 15-30: MASTER RECEIVER FLOWCHART
Idle mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
start count
BRG
rollover?
No
Yes
Release SCL
(Clock Arbitration)
SCL = 1?
No
Yes
Load BRG with
SSPADD<6:0>,
start count.
BRG
rollover?
No
Yes
Sample SDA,
Shift data into SSPSR
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 153
DS30264A-page 154
S
Preliminary
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
(PIR2<7>)
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
Write to SSPBUF occurs here
Start XMIT
SEN = 0
Write to SSPCON2<0> (SEN = 1)
Begin Start Condition
7
A1
8
9
R/W = 1
ACK
ACK from Slave
1
2
3
5
6
7
8
D0
9
ACK
1
3
4
5
Cleared in software
Set SSPIF interrupt
at end of acknowledge
sequence
2
6
7
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of recieve
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 1
Receiving Data from Slave
RCEN = 1 start
next receive
ACK from Master
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of recieve
4
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1)
Write to SSPCON2<4>
to start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC17C75X
FIGURE 15-31: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
1997 Microchip Technology Inc.
PIC17C75X
15.2.11 ACKNOWLEDGE SEQUENCE TIMING
15.2.11.1 WCOL STATUS FLAG
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for TBRG . The SCL
pin is then pulled low for one TBRG. Following this,
the ACKEN bit is automatically cleared, the baud rate
generator is turned off, and the SSP module then goes
into IDLE mode. (Figure 15-32)
If the user writes the SSPBUF when an acknowledege
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-32: ACKNOWLEDGE SEQUENCE TIMING
Acknowledge sequence starts here
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
D0
SCL
ACK
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: TBRG= one baud rate generator period.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 155
PIC17C75X
FIGURE 15-33: ACKNOWLEDGE FLOWCHART
Idle mode
Set ACKEN
Force SCL = 0
BRG
rollover?
Yes
No
No
SCL = 0?
Yes
Yes
Drive ACKDT bit
(SSPCON2<5>)
onto SDA pin,
Load BRG with
SSPADD<6:0>,
start count.
SCL = 0?
Reset BRG
Force SCL = 0,
Clear ACKEN
No
No
ACKDT = 0?
Yes
No
BRG
rollover?
Yes
Yes
Force SCL = 1
SDA = 1?
No
Bus collision detected,
Set BCLIF,
Release SCL,
Clear ACKEN
No
SCL = 1?
(Clock Arbitration)
Yes
Load BRG with
SSPADD <6:0>,
start count.
DS30264A-page 156
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
Whenever the CPU decides to take control of the bus,
it will first determine if the bus is busy by checking the
S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
15.2.12 STOP CONDITION TIMING
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator
times out, the SCL pin will be brought high, and one
TBRG (baud rate generator rollover count) later, the
SDA pin will be de-asserted. When the SDA pin is
sampled high while SCL is high, the PEN bit will be
automatically cleared, and the P bit (SSPSTAT<4>) is
set which in turn will set the SSPIF flag. (Figure 15-34)
15.2.12.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-34: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2
Set PEN
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high, PEN bit (SSPCON2<2>) is
automatically cleared. P bit (SSPSTAT<4>) is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: TBRG = one baud rate generator period.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 157
PIC17C75X
FIGURE 15-35: STOP CONDITION FLOWCHART
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
PEN = 1
Start BRG
Force SDA = 0
SCL doesn’t change
BRG
rollover?
No
SDA = 0?
No
Yes
Release SDA,
Start BRG
Yes
Start BRG
BRG
rollover?
BRG
rollover?
No
No
Yes
No
P bit Set?
Yes
De-assert SCL,
SCL = 1
Yes
(Clock Arbitration)
SCL = 1?
Bus Collision detected,
Set BCLIF,
Clear SPEN
No
SDA going from
0 to 1 while SCL = 1
Sets P bit SSPSTAT<4>,
Set SSPIF,
Stop Condition done
Yes
DS30264A-page 158
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.2.13 CLOCK ARBITRATION
Clock arbitration occurs when the master during any
receive, transmit, or restart/stop condition de-asserts
the SCL pin (SCL allowed to float high). When the
SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the
clock is held low by an external device. (Figure 15-36)
FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (Tosc • 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
1997 Microchip Technology Inc.
TBRG
TBRG
Preliminary
DS30264A-page 159
PIC17C75X
15.2.14 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I2C port to its IDLE state. (Figure 15-37).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services the bus collision interrupt service routine, and if
the I2C bus is free, the user can resume communication by asserting a START condition.
If a START, RESTART, STOP, or Acknowledge condition was in progress when the bus collision occurred,
the condition is aborted, the SDA and SCL lines are
de-asserted, and the respective control bits in the
SSPCON2 register are cleared. When the user services the bus collision interrupt service routine, and if
the I2C bus is free, the user can resume communication by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 15-37: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt.
BCLIF
DS30264A-page 160
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.2.14.1 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-38)
SCL is sampled low before SDA is asserted low.
(Figure 15-39)
b)
During a START condition both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-40). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
is sampled as '0', a bus collision does not occur. At
the end of the BRG count the SCL pin is asserted low.
Note:
If:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 15-38).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the START condition, and if the
address is the same, arbitration must be
allowed to continue into the data portion,
RESTART, or STOP conditions.
FIGURE 15-38: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, enable start
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
BCLIF
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 161
PIC17C75X
FIGURE 15-39: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SEN
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
SSPIF
FIGURE 15-40: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S, SSPIF
TBRG
Less than TBRG
SDA
SCL
SDA goes low early.
Reset BRG and assert SDA
Set SEN, enable start
sequence if SDA = 1, SCL = 1
S
SEN
BCLIF
S
SSPIF
SDA = 0, SCL = 1
Set S, SSPIF
DS30264A-page 162
Preliminary
Interrupts cleared
in software.
1997 Microchip Technology Inc.
PIC17C75X
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
15.2.14.2 BUS COLLISION DURING A RESTART
CONDITION
During a RESTART condition, a bus collision occurs if:
a)
b)
A ’0’ is sampled on SDA when SCL goes from ’0’
to ’1’
SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ’1’.
If, however, SCL goes from high to low before the
BRG times out and SDA has not already been
asserted, then a bus collision occurs. In this case,
another master is attempting to transmit a data ’1’ during the RESTART condition.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0. The SCL pin is then
de-asserted, and when sampled high, the SDA pin is
sampled. If SDA is low, a bus collision has occurred
(i.e. another master is attempting to transmit a data
’0’). If however SDA is sampled high then the BRG is
If at the end of the BRG time out both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the
count, regardless of the status of the SCL pin, the SCL
pin is driven low and the RESTART condition is complete. (Figure 15-41)
FIGURE 15-41: BUS COLLISION DURING A RESTART CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
Cleared in software
S
SSPIF
FIGURE 15-42: BUS COLLISION DURING RESTART CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
Interrupt cleared
in software
RSEN
S
SSPIF
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 163
PIC17C75X
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to
drive a data '0'. (Figure 15-43)
15.2.14.3 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a)
b)
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
FIGURE 15-43: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA sampled
low after TBRG,
Set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 15-44: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
DS30264A-page 164
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
15.3
Connection Considerations for I2C
Bus
For standard-mode I2C bus devices, the values of
resistors Rp Rs in Figure 15-45 depends on the following parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
leakage current).
The supply voltage limits the minimum value of resistor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of Rp is shown in
Figure 15-45. The desired noise margin of 0.1VDD for
the low level, limits the maximum value of Rs. Series
resistors are optional.
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the maximum value of Rp due to the specified rise time
(Figure 15-45).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
This control ensures that the rise and fall times of the
SCL and SDA pins will meet the minimum requirements as specified in the I2C specification for 400 kHz
operation.
FIGURE 15-45: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
Rp
DEVICE
Rp
Rs
Rs
SDA
SCL
2
NOTE: I C devices with input levels related to VDD must have one common supply
line to which the pull up resistor is also connected.
1997 Microchip Technology Inc.
Preliminary
Cb=10 - 400 pF
DS30264A-page 165
PIC17C75X
NOTES:
DS30264A-page 166
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
16.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers. These registers
are:
•
•
•
•
The analog-to-digital (A/D) converter module has
twelve analog inputs for the PIC17C75X devices.
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation.
The analog reference voltages (positive and negative
supply) are software selectable to either the device’s
supply voltages (AVDD, AVss) or the voltage level on
the RG3/AN0/VREF+ and RG2/AN1/VREF- pins.
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Figure 16-1, controls
the operation of the A/D module. The ADCON1 register, shown in Figure 16-2, configures the functions of
the port pins. The port pins can be configured as analog inputs (RG3 and RG2 can also be the voltage references) or as digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in sleep, the A/D clock must be derived from the
A/D’s internal RC oscillator.
FIGURE 16-1: ADCON0 REGISTER (ADDRESS: 14h, BANK 5)
R/W-0
CHS3
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
U-0
—
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
bit 7-4: CHS2:CHS0: Analog Channel Select bits
0000 = channel 0, (AN0)
0001 = channel 1, (AN1)
0010 = channel 2, (AN2)
0011 = channel 3, (AN3)
0100 = channel 4, (AN4)
0101 = channel 5, (AN5)
0110 = channel 6, (AN6)
0111 = channel 7, (AN7)
1000 = channel 8, (AN8)
1001 = channel 9, (AN9)
1010 = channel 10, (AN10)
1011 = channel 11, (AN11)
11xx = RESERVED, do not select
bit 3:
bit 2:
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Unimplemented: Read as '0'
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared
by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 167
PIC17C75X
FIGURE 16-2: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
ADFM
U-0
—
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/8
01 = FOSC/32
10 = FOSC/64
11 = FRC (clock derived from an internal RC oscillator)
bit 5:
bit 4:
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n = Value at POR reset
ADFM: A/D Result format select
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
Unimplemented: Read as '0'
bit 3-0: PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG3:PCFG1 AN11 AN10 AN9
000
001
010
011
100
101
110
111
A
A
A
A
A
D
D
D
A = Analog input
bit 0:
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
AN8
AN7
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
AN6 AN5
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
AN4
A
A
A
A
D
D
D
D
AN3 AN2 AN1 AN0
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
D = Digital I/O
PCFG0: A/D Voltage Reference Select bit
1 = A/D reference is the VREF+ and VREF- pins
0 = A/D reference is AVDD and AVSS
Note:When this bit is set, ensure that the A/D voltage reference specifications are met.
DS30264A-page 168
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
2.
The ADRESH:ADRESL registers contains the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared,
and A/D interrupt flag bit ADIF is set. The block diagrams of the A/D module are shown in Figure 16-3.
3.
4.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding DDR bits selected as inputs.
To determine acquisition time, see Section 16.1. After
this acquisition time has elapsed the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
1.
5.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Clear GLINTD bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
7.
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 16-3: A/D BLOCK DIAGRAM
CHS3:CHS0
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
VIN
0011
(Input voltage)
AN4
AN3
0010
A/D
Converter
AN2
0001
AN1
PCFG0
0000
AN0
VREF(Reference
voltage)
AVSS
VREF+
1997 Microchip Technology Inc.
AVDD
Preliminary
DS30264A-page 169
PIC17C75X
16.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 16-4. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for analog sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
Example 16-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions.
CHOLD = 200 pF
Rs = 10 kΩ
1/2 LSb error
VDD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
VHOLD = 0 @ t = 0
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation calculates
the acquisition time to within 1/2 LSb error (1024 steps
for the A/D). The 1/2 LSb error is the maximum error
allowed for the A/D to meet its specified accuracy.
EQUATION 16-1:
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specification.
A/D MINIMUM CHARGING
TIME (FOR CHOLD)
Note 4: After a conversion has completed, a
2.0TAD delay must complete before acquisition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
VHOLD = (VREF - (VREF/2048)) • (1 - e(-Tcap/CHOLD(RIC + RSS + RS)))
given
VHOLD = (VREF/2048), for 1/2 LSb resolution
VREF = VREF+ - VREF-
or
Tcap = -(200 pF)(1 kΩ + RSS + RS) ln(1/2047)
FIGURE 16-4: ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS RSS
CHOLD
= DAC capacitance
= 200 pF
I leakage
± 500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS30264A-page 170
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Preliminary
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
1997 Microchip Technology Inc.
PIC17C75X
EXAMPLE 16-1: CALCULATING THE
MINIMUM REQUIRED
ACQUISITION TIME
16.2
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient †
† Only required for temperatures ≠ 25°C
•
•
•
•
TACQ = 10 µs + Tcap + [(Temp - 25°C)(0.05 µs/°C)]
TCAP = -CHOLD (RIC + RSS + RS) ln(1/2047)
-200 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0004885)
-200 pF (18 kΩ) ln(0.0004885)
-3.6 µs (-7.6241)
27.447 µs
TACQ = 10 µs + 27.447 µs + [(50°C - 25°C)(0.05 µs/°C)]
37.447 µs + 1.25 µs
38.697 µs
TABLE 16-1:
ADCS1:ADCS0
8TOSC
00
32TOSC
01
64TOSC
10
RC
TABLE 16-2:
Operation
ADCS1:ADCS0
8TOSC
00
32TOSC
01
RC
Legend:
Note 1:
2:
3:
4:
Table 16-1 and Table 16-2 show the resultant TAD
times derived from the device operating frequencies
and the A/D clock source selected. These times are for
standard voltage range devices.
33 MHz
20 MHz
242 ns(2)
Device Frequency
400 ns(2)
1.6 µs
970 ns(2)
1.94 µs
3.2 µs
(1, 4)
µs(1, 4)
5 MHz
1.25 MHz
333.33 kHz
1.6 µs
6.4 µs
24 µs
6.4 µs
25.6 µs(3)
96 µs(3)
12.8 µs(3)
µs(1, 4)
51.2 µs(3)
µs(1, 4)
192 µs(3)
TAD vs. DEVICE OPERATING FREQUENCIES (EXTENDED VOLTAGE DEVICES (LC))
AD Clock Source (TAD)
64TOSC
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
2-6
2-6
2-6
2 - 6 µs(1)
2 - 6 µs
Shaded cells are are outside of recommended ranges.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequencies is greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep operation.
11
Legend:
Note 1:
2:
3:
4:
8TOSC
32TOSC
64TOSC
Internal RC oscillator
TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Operation
Selecting the A/D Conversion Clock
10
8 MHz
1.0 µs(2)
4.0 µs
8.0 µs
4 MHz
2.0 µs(2)
8 µs
16 µs
Device Frequency
2 MHz
1 MHz
333.33 kHz
4 µs
8 µs
24 µs
16 µs
32 µs(3)
96 µs(3)
32
µs(3)
64
µs(3)
192 µs(3)
3 - 9 µs(1, 4)
3 - 9 µs(1, 4)
3 - 9 µs(1)
3 - 9 µs(1)
3 - 9 µs(1, 4)
Shaded cells are are outside of recommended ranges.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequencies is greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep operation.
11
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 171
PIC17C75X
16.3
Configuring Analog Port Pins
16.4
The ADCON1, and DDR registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding DDR bits
set (input). If the DDR bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the DDR bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN11:AN0
pins), may cause the input buffer to consume current that is out of the devices
specification.
A/D Conversions
Example 16-2 shows how to perform an A/D conversion. The PORTF and lower four PORTG pins are configured as analog inputs. The analog references
(VREF+ and VREF-) are the device AVDD and AVSS. The
A/D interrupt is enabled, and the A/D conversion clock
is FRC. The conversion is performed on the RG3/AN0
pin (channel 0).
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
That
is,
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers). After
the A/D conversion is aborted, a 2TAD wait is required
before the next acquisition is started. After this 2TAD
wait, acquisition on the selected channel is automatically started.
EXAMPLE 16-2: A/D CONVERSION
MOVLB
CLRF
MOVLW
MOVWF
MOVLB
BCF
BSF
BSF
BCF
;
;
;
;
5
ADCON1, F
0xC1
ADCON0
4
PIR2, ADIF
PIE2, ADIE
INTSTA, PEIE
CPUSTA, GLINTD
;
;
;
;
;
;
;
;
;
Bank 5
Configure A/D inputs
RC Clock, A/D is on, Channel 0 is selected
Bank 4
Clear A/D interrupt flag bit
Enable A/D interrupts
Enable peripheral interrupts
Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
MOVLB
BSF
:
:
5
ADCON0, GO
DS30264A-page 172
; Bank 5
; Start A/D Conversion
;
The ADIF bit will be set and the GO/DONE bit
;
is cleared upon completion of the A/D Conversion
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
16.4.1
16.5
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 16-5 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the conversion to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
FIGURE 16-5: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 1
2107
7
0000 00
ADRESH
ADFM = 0
0
7
RESULT
RESULT
ADRESH
ADRESL
0
0000 00
ADRESL
10-bits
10-bits
Left Justified
Right Justified
1997 Microchip Technology Inc.
0765
Preliminary
DS30264A-page 173
PIC17C75X
A/D Accuracy/Error
16.7
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from of an actual transition versus an
ideal transition for any code. The absolute error of the
A/D converter is specified at < + 1 LSb for VDD = VREF
(over the device’s specified operating range). However, the accuracy of the A/D converter will degrade as
VDD diverges from VREF.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization
of the analog input to a digital code. Quantization error
is typically + 1/2 LSb and is inherent in the analog to
digital conversion process. The only way to reduce
quantization error is to increase the resolution of the
A/D converter.
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a system through the interaction of the total leakage current
and source impedance at the analog input.
Gain error measures the maximum deviation of the last
actual transition and the last ideal transition adjusted
for offset error. This error appears as a change in slope
of the transfer function. The difference is gain error to
full scale error is that full scale doe not take offset error
into account. Gain error can be calibrated out in software.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition
adjusted by the gain error for each code.
Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
16.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.3V, then the accuracy of the conversion is out of specification.
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
16.9
Transfer Function
The transfer function of the A/D converter is as follows:
the first transition occurs when the analog input voltage
(VAIN) equals Analog VREF / 1024 (Figure 16-6).
FIGURE 16-6: A/D TRANSFER FUNCTION
3FFh
3FEh
Digital code output
16.6
Differential non-linearity measures the maximum actual
code width versus the ideal code width. This measure
is unadjusted.
003h
002h
001h
The maximum pin leakage current is ± 1 µA.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
DS30264A-page 174
1023 LSb
1022.5 LSb
1022 LSb
1021.5 LSb
3 LSb
2.5 LSb
2 LSb
1 LSb
1.5 LSb
0.5 LSb
000h
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions. This reduces, to a large extent,
the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due
to digital switching noise can be significant if many I/O
pins are active.
Analog input voltage
16.10
References
A good reference for the undestanding A/D converter is
the "Analog-Digital Conversion Handbook" third edition,
published
by
Prentice
Hall
(ISBN
0-13-03-2848-0).
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 16-7: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
A/D Clock
= RC?
Yes
SLEEP
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
GO = 0,
ADIF = 1
No
No
Yes
Device in
SLEEP?
Abort Conversion
GO = 0,
ADIF = 0
Wake-up Yes
From Sleep?
Finish Conversion
GO = 0,
ADIF = 1
Wait 2TAD
No
No
Finish Conversion
GO = 0,
ADIF = 1
SLEEP
Power-down A/D
Wait 2TAD
Stay in Sleep
Power-down A/D
Wait 2TAD
TABLE 16-3:
Address
REGISTERS/BITS ASSOCIATED WITH A/D
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
(Note 1)
06h, unbanked CPUSTA
—
—
STAKAV
GLINTD
TO
PD
POR
BOR
--11 1100
--11 qq11
07h, unbanked INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
10h, Bank 4
PIR2
SSPIF
BCLIF
ADIF
—
CA4IF
CA3IF
TX2IF
RC2IF
000- 0010
000- 0010
11h, Bank 4
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
000- 0000
10h, Bank 5
DDRF
1111 1111
1111 1111
0000 0000
Data Direction register for PORTF
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
0000 0000
1111 1111
1111 1111
RG5/
PWM3
RG4/
CAP3
RG3/
AN0/VREF+
RG2/
AN1/VREF
-
RG1/
AN2
RG0/
AN3
xxxx 0000
uuuu 0000
CHS2
CHS1
CHS0
—
GO/DONE
—
ADON
0000 -0-0
0000 -0-0
ADCS0
ADFM
—
PCFG3
PCFG2
PCFG1
PCFG0
000- 0000
000- 0000
A/D Result Low Register
xxxx xxxx
uuuu uuuu
A/D Result High Register
xxxx xxxx
uuuu uuuu
11h, Bank 5
PORTF
12h, Bank 5
DDRG
Data Direction register for PORTG
13h, Bank 5
PORTG
RG7/
RG6/
TX2/CK2 RX2/DT2
14h, Bank 5
ADCON0
CHS3
15h, Bank 5
ADCON1
ADCS1
16h, Bank 5
ADRESL
17h, Bank 5
ADRESH
Legend:
Note 1:
RF7/
AN11
RF6/
AN10
RF5/
AN9
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 175
PIC17C75X
NOTES:
DS30264A-page 176
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
17.0
SPECIAL FEATURES OF THE
CPU
The PIC17CXXX has a Watchdog Timer which can be
shutoff only through EPROM bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay of 96 ms (nominal) on power-up only, designed to
keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications
need no external reset circuitry.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of
real-time applications. The PIC17CXXX family has a
host of such features intended to maximize system reliability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
• Oscillator selection (Section 4.0)
• Reset (Section 5.0)
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts (Section 6.0)
• Watchdog Timer (WDT)
• SLEEP mode
• Code protection
The SLEEP mode is designed to offer a very low current power-down mode. The user can wake from
SLEEP through external reset, Watchdog Timer Reset
or through an interrupt. Several oscillator options are
also made available to allow the part to fit the application. The RC oscillator option saves system cost while
the LF crystal option saves power. Configuration bits
are used to select various options. This configuration
word has the format shown in Figure 17-1.
FIGURE 17-1: CONFIGURATION WORDS
U-x
R/P - 1 R/P - 1 U - x
—
PM2 BODEN —
bit15
bit 8 bit 7
U-x
U-x
—
—
bit15
bit 8 bit 7
bit 6H
R/P - 1
PM1
U-x
—
U-x
—
U-x
—
U-x
—
U - x R/P - 1 R/P - 1
R/P - 1
R/P - 1
—
PM0 WDTPS1 WDTPS0 FOSC1
U-x
High (H) Table Read Addr.
—
FE0Fh - FE08h
bit 0
R/P - 1 Low (L) Table Read Addr.
FOSC0 FE07h - FE00h
bit 0
BODEN: Brown-out Detect Enable
1=
Brown-out Detect circuitry is enabled
0=
Brown-out Detect circuitry is disabled
bits 7H:6L:4L PM2, PM1, PM0, Processor Mode Select bits
111 = Microprocessor Mode
110 = Microcontroller mode
101 = Extended microcontroller mode
000 = Code protected microcontroller mode
bits 2L:3L
bits 1L:0L
—
WDTPS1:WDTPS0, WDT Postscaler Select bits
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
FOSC1:FOSC0, Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator
Reserved
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 177
PIC17C75X
17.1
Configuration Bits
The PIC17CXXX has eight configuration locations
(Table 17-1). These locations can be programmed
(read as '0') or left unprogrammed (read as '1') to select
various device configurations. Any write to a configuration location, regardless of the data, will program that
configuration bit. A TABLWT instruction is required to
write to program memory locations. The configuration
bits can be read by using the TABLRD instructions.
Reading any configuration location between FE00h
and FE07h will read the low byte of the configuration
word (Figure 17-1) into the TABLATL register. The TABLATH register will be FFh. Reading a configuration
location between FE08h and FE0Fh will read the high
byte of the configuration word into the TABLATL register. The TABLATH register will be FFh.
17.2
Oscillator Configurations
17.2.1
OSCILLATOR TYPES
The PIC17CXXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
•
•
•
•
LF
XT
EC
RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
For information on the different oscillator types and
how to use them, please refer to Section 4.0.
Addresses FE00h thorough FE0Fh are only in the program memory space for microcontroller and code protected microcontroller modes. A device programmer
will be able to read the configuration word in any processor mode. See programming specifications for
more detail.
TABLE 17-1:
Note:
CONFIGURATION
LOCATIONS
Bit
Address
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
PM1
BODEN
PM2
FE00h
FE01h
FE02h
FE03h
FE04h
FE06h
FE0Eh
FE0Fh
When programming the desired configuration locations, they must be programmed
in ascending order. Starting with address
FE00h.
DS30264A-page 178
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
17.3
Watchdog Timer (WDT)
17.3.2
The WDT and postscaler are cleared when:
The Watchdog Timer’s function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out
generates a device RESET. The WDT can be
permanently disabled by programming the configuration bits WDTPS1:WDTPS0 as '00' (Section 17.1).
•
•
•
•
The device is in the reset state
A SLEEP instruction is executed
A CLRWDT instruction is executed
Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
17.3.3
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
17.3.1
CLEARING THE WDT AND POSTSCALER
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
17.3.4
WDT PERIOD
WDT AS NORMAL TIMER
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The overflow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. The simple timer does not
increment when in sleep.
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and prevent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator(1)
WDT
Postscaler
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 17-2:
REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
—
Config
06h, Unbanked
WDT Overflow
CPUSTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
—
—
STKAV
GLINTD
TO
PD
POR
BOR
Value on
POR,
BOR
Value on all
other resets
(Note1)
(Note 2)
(Note 2)
--11 1100
--11 qq11
Legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 179
PIC17C75X
17.4
Power-down Mode (SLEEP)
be used to determine the cause of device reset. The
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
The Power-down mode is entered by executing a
SLEEP instruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high, low, or hi-impedance).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP instruction.
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
17.4.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
•
•
•
•
•
POR
External reset input on MCLR/VPP pin
WDT Reset (if WDT was enabled)
BOR
Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some peripheral Interrupts
Note:
If the global interrupt is disabled (GLINTD
is set), but any interrupt source has both its
interrupt enable bit and the corresponding
interrupt flag bit set, the device will immediately wake-up from sleep. The TO bit is
set, and the PD bit is cleared.
The following peripheral interrupts can wake the device
from SLEEP:
•
•
•
•
•
•
The WDT is cleared when the device wakes from
SLEEP, regardless of the source of wake-up.
Capture interrupts
USART synchronous slave transmit interrupts
USART synchronous slave receive interrupts
A/D conversion complete
SPI slave transmit / receive complete
I2C slave receive
17.4.1.1
WAKE-UP DELAY
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024TOSC. This needs to be taken into account when
considering the interrupt response time when coming
out of SLEEP.
Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execution. The TO and PD bits in the CPUSTA register can
FIGURE 17-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Tost(2)
CLKOUT(4)
INT
(RA0/INT pin)
INTF flag
Interrupt Latency (2)
GLINTD bit
Processor
in SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Instruction
executed
Inst (PC) = SLEEP
Inst (PC-1)
PC+2
PC+1
0004h
Inst (PC+1)
Inst (PC+2)
SLEEP
Inst (PC+1)
0005h
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30264A-page 180
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
17.4.2
MINIMIZING CURRENT CONSUMPTION
To minimize current consumption, all I/O pins should be
either at VDD, or VSS, with no external circuitry drawing
current from the I/O pin. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should be at VDD or VSS. The contributions
from on-chip pull-ups on PORTB should also be considered, and disabled when possible.
17.5
Code Protection
The code in the program memory can be protected by
selecting the microcontroller in code protected mode
(PM2:PM0 = '000').
In this mode, instructions that are in the on-chip program memory space, can continue to read or write the
program memory. An instruction that is executed outside of the internal program memory range will be
inhibited from writing to or reading from program memory.
Note:
Microchip does not recommend code protecting windowed devices.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 181
PIC17C75X
17.6
In-Circuit Serial Programming
The PIC17C75X group of the high end family
(PIC17CXXX) has an added feature that allows serial
programming while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
For complete details of serial programming, please
refer to the PIC17C75X Programming Specification.
(Contact your local Microchip Technology Sales Office
for availability.)
FIGURE 17-4: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
Devices may be serialized to make the product unique,
“special” variants of the product may be offered, and
code updates are possible. This allows for increased
design flexibility.
To place the device into the serial programming test
mode, two pins will need to be placed at VIHH. These
are the TEST pin and the MCLR/VPP pin. Also a
sequence of events must occur as follows:
1.
2.
To Normal
Connections
PIC17C75X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
TEST CNTL
TEST
RA1/T0CKI
Dev. CLK
The TEST pin is placed at VIHH.
The MCLR/VPP pin is placed at VIHH.
Data I/O
RA4/RX1/DT1
Data CLK
RA5/TX1/CK1
There is a setup time between step 1 and step 2 that
must be met.
After this sequence the Program Counter is pointing to
program memory address 0xFF60. This location is in
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this, the device must
be clocked. The device clock source in this mode is the
RA1/T0CKI pin. After delaying to allow the USART/SCI
to initialize, commands can be received. The flow is
shown in these 3 steps:
1.
2.
3.
VDD
To Normal
Connections
The device clock source starts.
Wait 80 device clocks for Boot ROM code to
configure the USART/SCI.
Commands may now be sent.
TABLE 17-3:
ISP INTERFACE PINS
Name
RA4/RX1/DT1
RA5/TX1/CK1
RA1/T0CKI
TEST
MCLR/VPP
VDD
VSS
DS30264A-page 182
Function
DT
CK
OSCI
TEST
MCLR/VPP
VDD
VSS
Type
I/O
I
I
I
P
P
P
During Programming
Description
Serial Data
Serial Clock
Device Clock Source
Test mode selection control input. Force to VIHH,
Master Clear reset and Device Programming Voltage
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
18.0
INSTRUCTION SET SUMMARY
The PIC17CXXX instruction set consists of 58 instructions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
specifies the instruction type, while the operand(s) further specify the operation of the instruction. The
PIC17CXXX instruction set can be grouped into three
types:
• byte-oriented
• bit-oriented
• literal and control operations.
These formats are shown in Figure 18-1.
Table 18-1 shows the field descriptions for the
opcodes. These descriptions are useful for understanding the opcodes in Table 18-2 and in each specific
instruction descriptions.
byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the file register specified by the instruction.
bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by
the operation, while 'f' represents the number of the file
in which the bit is located.
literal and control operations, 'k' represents an 8- or
13-bit constant or literal value.
The instruction set is highly orthogonal and is grouped
into:
• byte-oriented operations
• bit-oriented operations
• literal and control operations
All instructions are executed within one single instruction cycle, unless:
• a conditional test is true
• the program counter is changed as a result of an
instruction
• a table read or a table write instruction is executed (in this case, the execution takes two
instruction cycles with the second cycle executed
as a NOP)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
TABLE 18-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (00h to FFh)
p
Peripheral register file address (00h to 1Fh)
i
Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t
Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal field,
constant data)
WREG Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
d
Destination select
0 = store result in WREG
1 = store result in file register f
Default is d = '1'
u
Unused, encoded as '0'
s
Destination select
0 = store result in file register f and in the WREG
1 = store result in file register f
Default is s = '1'
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow
Z,OV
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
TBLATL Table Latch low byte
TBLATH Table Latch high byte
TOS
PC
Top of Stack
Program Counter
BSR
Bank Select Register
WDT
Watchdog Timer Counter
TO
Time-out bit
PD
Power-down bit
dest Destination either the WREG register or the specified register file location
[ ]
Options
( )
Contents
→
Assigned to
<>
Register bit field
∈
In the set of
italics User defined term (font is courier)
1997 Microchip Technology Inc.
DS30264A-page 183
PIC17C75X
Table 18-2 lists the instructions recognized by the
MPASM assembler.
Note 1: Any unused opcode is Reserved. Use of
any reserved opcode may cause unexpected operation.
All instruction examples use the following format to represent a hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
To represent a binary number:
0000 0100b
where b signifies a binary string.
FIGURE 18-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
15
9
8
d
OPCODE
7
0
f (FILE #)
d = 0 for destination WREG
d = 1 for destination f
f = 8-bit file register address
Byte to Byte move operations
15
13 12
8 7
OPCODE
p (FILE #)
11 10
8 7
b (BIT #)
0
f (FILE #)
Literal and control operations
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO operations
15
13 12
OPCODE
ALUSTA AS DESTINATION
If an instruction writes to ALUSTA, the Z, C, DC and OV
bits may be set or cleared as a result of the instruction
and overwrite the original data bits written. For example, executing CLRF
ALUSTA will clear register
ALUSTA, and then set the Z bit leaving 0000 0100b
in the register.
18.1.2
PCL AS SOURCE OR DESTINATION
Read, write or read-modify-write on PCL may have the
following results:
Read PC:
PCH → PCLATH; PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
Read-Modify-Write:
PCL→ ALU operand
PCLATH → PCH;
8-bit result → PCL
18.1.3
b = 3-bit address
f = 8-bit file register address
15
18.1.1
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
Bit-oriented file register operations
OPCODE
Special Function Registers as
Source/Destination
The PIC17C75X’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
0
f (FILE #)
p = peripheral register file address
f = 8-bit file register address
15
18.1
BIT MANIPULATION
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and
writing the result back (read-modify-write (R-M-W)).
The user should keep this in mind when operating on
some special function registers, such as ports.
Note:
Status bits that are manipulated by the
device (including the Interrupt flag bits) are
set or cleared in the Q1 cycle. So there is
no issue on doing R-M-W instructions on
registers which contain these bits
0
k (literal)
k = 13-bit immediate value
DS30264A-page 184
1997 Microchip Technology Inc.
PIC17C75X
18.2
Q Cycle Activity
The four Q cycles that make up an instruction cycle
(Tcy) can be generalized as:
Each instruction cycle (Tcy) is comprised of four Q
cycles (Q1-Q4). The Q cycle is the same as the device
oscillator cycle (TOSC). The Q cycles provide the timing/designation for the Decode, Read, Process Data,
Write etc., of each instruction cycle. The following diagram shows the relationship of the Q cycles to the
instruction cycle.
Q1: Instruction Decode Cycle or forced No
operation
Q2: Instruction Read Cycle or No operation
Q3: Process the Data
Q4: Instruction Write Cycle or No operation
Each instruction will show the detailed Q cycle operation for the instruction.
FIGURE 18-2: Q CYCLE ACTIVITY
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Tosc
Tcy1
1997 Microchip Technology Inc.
Tcy2
Tcy3
DS30264A-page 185
PIC17C75X
TABLE 18-2:
PIC17CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f,d
ADD WREG to f
Cycles
MSb
16-bit Opcode
LSb
Status
Affected
Notes
1
0000 111d ffff ffff
OV,C,DC,Z
ADDWFC
f,d
ADD WREG and Carry bit to f
1
0001 000d ffff ffff
OV,C,DC,Z
AND WREG with f
1
0000 101d ffff ffff
Z
CLRF
f,s
Clear f, or Clear f and Clear WREG
1
0010 100s ffff ffff
None
1
0001 001d ffff ffff
Z
f
Compare f with WREG, skip if f = WREG
1 (2)
0011 0001 ffff ffff
None
6,8
Compare f with WREG, skip if f > WREG
1 (2)
0011 0010 ffff ffff
None
2,6,8
Compare f with WREG, skip if f < WREG
1 (2)
0011 0000 ffff ffff
None
2,6,8
Decimal Adjust WREG Register
1
0010 111s ffff ffff
C
Decrement f
1
0000 011d ffff ffff
OV,C,DC,Z
Decrement f, skip if 0
1 (2)
0001 011d ffff ffff
None
6,8
Decrement f, skip if not 0
1 (2)
0010 011d ffff ffff
None
6,8
ANDWF
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
f,d
f,d
f
f
f,s
DECF
f,d
DCFSNZ
f,d
INCFSZ
f,d
DECFSZ
INCF
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBWF
SUBWFB
SWAPF
TABLRD
TABLWT
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
f,d
f,d
f,d
Complement f
Increment f
3
3
1
0001 010d ffff ffff
OV,C,DC,Z
Increment f, skip if 0
1 (2)
0001 111d ffff ffff
None
6,8
Increment f, skip if not 0
1 (2)
0010 010d ffff ffff
None
6,8
1
0000 100d ffff ffff
Z
f,d
Inclusive OR WREG with f
Move f to p
1
011p pppp ffff ffff
None
p,f
Move p to f
1
010p pppp ffff ffff
Z
Move WREG to f
1
0000 0001 ffff ffff
None
f
Multiply WREG with f
1
0011 0100 ffff ffff
None
Negate WREG
1
0010 110s ffff ffff
OV,C,DC,Z
No Operation
1
0000 0000 0000 0000
None
Rotate left f through Carry
1
0001 101d ffff ffff
C
Rotate left f (no carry)
1
0010 001d ffff ffff
None
Rotate right f through Carry
1
0001 100d ffff ffff
C
Rotate right f (no carry)
1
0010 000d ffff ffff
None
Set f
1
0010 101s ffff ffff
None
3
Subtract WREG from f
1
0000 010d ffff ffff
OV,C,DC,Z
1
Subtract WREG from f with Borrow
1
0000 001d ffff ffff
OV,C,DC,Z
1
Swap f
1
0001 110d ffff ffff
None
Table Read
2 (3)
1010 10ti ffff ffff
None
7
Table Write
2
1010 11ti ffff ffff
None
5
f,p
f
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
f,d
t,i,f
t,i,f
1,3
Refer to Table 18-1 for opcode field descriptions.
2’s Complement method.
Unsigned arithmetic.
If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register (WREG) is required to be affected, then f = WREG must be specified.
During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
Two-cycle instruction when condition is true, else single cycle instruction.
Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
DS30264A-page 186
1997 Microchip Technology Inc.
PIC17C75X
TABLE 18-2:
Mnemonic,
Operands
TLRD
TLWT
TSTFSZ
XORWF
PIC17CXXX INSTRUCTION SET (Cont.’d)
Description
t,f
t,f
f
Cycles
MSb
16-bit Opcode
LSb
Status
Affected
Notes
Table Latch Read
1
1010 00tx ffff ffff
None
Table Latch Write
1
1010 01tx ffff ffff
None
1 (2)
0011 0011 ffff ffff
None
1
0000 110d ffff ffff
Z
1
1000 1bbb ffff ffff
None
Test f, skip if 0
f,d
Exclusive OR WREG with f
BCF
f,b
Bit Clear f
BTFSC
f,b
6,8
BIT-ORIENTED FILE REGISTER OPERATIONS
BSF
BTFSS
BTG
f,b
f,b
Bit Set f
1
1000 0bbb ffff ffff
None
Bit test, skip if clear
1 (2)
1001 1bbb ffff ffff
None
6,8
Bit test, skip if set
1 (2)
1001 0bbb ffff ffff
None
6,8
1
0011 1bbb ffff ffff
None
1
1011 0001 kkkk kkkk
OV,C,DC,Z
f,b
Bit Toggle f
ADDLW
k
ADD literal to WREG
AND literal with WREG
1
1011 0101 kkkk kkkk
Z
CALL
k
Subroutine Call
2
111k kkkk kkkk kkkk
None
Clear Watchdog Timer
1
0000 0000 0000 0100
TO,PD
GOTO
k
Unconditional Branch
2
110k kkkk kkkk kkkk
None
Inclusive OR literal with WREG
1
1011 0011 kkkk kkkk
Z
k
Long Call
2
1011 0111 kkkk kkkk
None
Move literal to low nibble in BSR
1
1011 1000 uuuu kkkk
None
Move literal to high nibble in BSR
1
1011 101x kkkk uuuu
None
Move literal to WREG
1
1011 0000 kkkk kkkk
None
Multiply literal with WREG
1
1011 1100 kkkk kkkk
None
Return from interrupt (and enable interrupts)
2
0000 0000 0000 0101
GLINTD
7
Return literal to WREG
2
1011 0110 kkkk kkkk
None
7
Return from subroutine
2
0000 0000 0000 0010
None
7
Enter SLEEP Mode
1
0000 0000 0000 0011
TO, PD
Subtract WREG from literal
1
1011 0010 kkkk kkkk
OV,C,DC,Z
Exclusive OR literal with WREG
1
1011 0100 kkkk kkkk
Z
LITERAL AND CONTROL OPERATIONS
ANDLW
CLRWDT
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
k
—
k
k
k
k
k
—
k
—
—
k
k
7
7
4,7
Refer to Table 18-1 for opcode field descriptions.
2’s Complement method.
Unsigned arithmetic.
If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register (WREG) is required to be affected, then f = WREG must be specified.
During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
Two-cycle instruction when condition is true, else single cycle instruction.
Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
1997 Microchip Technology Inc.
DS30264A-page 187
PIC17C75X
ADDLW
ADD Literal to WREG
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) + (f) → (dest)
Status Affected:
OV, C, DC, Z
Syntax:
[ label ] ADDLW
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) + k → (WREG)
Status Affected:
OV, C, DC, Z
Encoding:
Description:
1011
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
kkkk
kkkk
The contents of WREG are added to
the 8-bit literal 'k' and the result is
placed in WREG.
Words:
Decode
0001
k
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
ADDLW
Before Instruction
WREG = 0x10
After Instruction
WREG = 0x25
Encoding:
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
0x15
ffff
ffff
Add WREG to register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Decode
111d
f,d
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
ADDWF
REG, 0
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG
REG
DS30264A-page 188
=
=
0xD9
0xC2
1997 Microchip Technology Inc.
PIC17C75X
ADDWFC
ADD WREG and Carry bit to f
ANDLW
And Literal with WREG
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) + (f) + C → (dest)
(WREG) .AND. (k) → (WREG)
Operation:
Status Affected:
Z
Status Affected:
OV, C, DC, Z
Encoding:
0001
Description:
f,d
Encoding:
000d
ffff
ffff
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in data memory location 'f'.
Words:
1
Cycles:
Decode
Q2
Q3
Q4
Process
Data
Write to
destination
ADDWFC
REG
Example:
Before Instruction
Carry bit =
REG
=
WREG =
1
0x02
0x4D
0
kkkk
kkkk
The contents of WREG are AND’ed with
the 8-bit literal 'k'. The result is placed in
WREG.
Words:
1
Cycles:
1
Decode
Read
register 'f'
0101
Description:
Q Cycle Activity:
Q1
1
Q Cycle Activity:
Q1
1011
k
Q2
Q3
Q4
Read literal
'k'
Process
Data
Write to
WREG
Example:
ANDLW
0x5F
Before Instruction
WREG
=
0xA3
After Instruction
WREG
=
0x03
After Instruction
Carry bit =
REG
=
WREG =
0
0x02
0x50
1997 Microchip Technology Inc.
DS30264A-page 189
PIC17C75X
ANDWF
AND WREG with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) .AND. (f) → (dest)
Status Affected:
Z
Encoding:
0000
Description:
101d
f,d
ffff
ffff
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operation:
0 → (f<b>)
Status Affected:
None
Encoding:
1000
f,b
1bbb
ffff
ffff
The contents of WREG are AND’ed with
register 'f'. If 'd' is 0 the result is stored
in WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
BCF
FLAG_REG,
7
Before Instruction
Example:
ANDWF
=
=
FLAG_REG = 0xC7
After Instruction
Before Instruction
WREG
REG
REG, 1
0x17
0xC2
FLAG_REG = 0x47
After Instruction
WREG
REG
=
=
DS30264A-page 190
0x17
0x02
1997 Microchip Technology Inc.
PIC17C75X
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
1000
f,b
0bbb
ffff
Description:
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
ffff
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
BSF
FLAG_REG, 7
Before Instruction
BTFSC
Bit Test, skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Encoding:
FLAG_REG= 0x8A
1bbb
ffff
ffff
Description:
If bit 'b' in register ’f' is 0 then the next
instruction is skipped.
If bit 'b' is 0 then the next instruction
fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle
instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
FLAG_REG= 0x0A
After Instruction
1001
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG,1
Before Instruction
PC
=
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
1997 Microchip Technology Inc.
DS30264A-page 191
PIC17C75X
BTFSS
Bit Test, skip if Set
BTG
Bit Toggle f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BTG f,b
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 255
0≤b<7
Operation:
skip if (f<b>) = 1
Operation:
(f<b>) → (f<b>)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
1001
0bbb
ffff
ffff
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a two-cycle
instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q3
Q4
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
0011
1bbb
ffff
ffff
Description:
Bit 'b' in data memory location 'f' is
inverted.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Decode
Encoding:
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
Example:
BTG
PORTC,
4
Before Instruction:
PORTC
=
0111 0101 [0x75]
After Instruction:
Example:
HERE
FALSE
TRUE
BTFSS
:
:
PORTC
=
0110 0101 [0x65]
FLAG,1
Before Instruction
PC
=
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
DS30264A-page 192
1997 Microchip Technology Inc.
PIC17C75X
CALL
Subroutine Call
CLRF
Clear f
Syntax:
Operands:
[ label ] CALL k
Syntax:
[label] CLRF
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
Operation:
PC+ 1→ TOS, k → PC<12:0>,
k<12:8> → PCLATH<4:0>;
PC<15:13> → PCLATH<7:5>
Operation:
00h → f, s ∈ [0,1]
00h → dest
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
Description:
Words:
111k
kkkk
kkkk
kkkk
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack. The 13-bit value is loaded
into PC bits<12:0>. Then the
upper-eight bits of the PC are copied
into PCLATH. CALL is a two-cycle
instruction.
See LCALL for calls outside 8K memory
space.
1
Cycles:
Decode
No
operation
Q2
Q3
Q4
Read literal
'k'<7:0>,
Push PC to
stack
No
operation
Process
Data
Write to PC
No
operation
ffff
ffff
Clears the contents of the specified register(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
No
operation
100s
Description:
Decode
2
Q Cycle Activity:
Q1
0010
f,s
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
and if
specified
WREG
CLRF
FLAG_REG
Before Instruction
FLAG_REG
=
0x5A
=
0x00
After Instruction
Example:
HERE
CALL
THERE
FLAG_REG
Before Instruction
PC =
Address(HERE)
After Instruction
PC =
TOS =
Address(THERE)
Address (HERE + 1)
1997 Microchip Technology Inc.
DS30264A-page 193
PIC17C75X
CLRWDT
Clear Watchdog Timer
COMF
Complement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT postscaler,
1 → TO
1 → PD
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
( f ) → (dest)
Status Affected:
Z
Status Affected:
TO, PD
Encoding:
Description:
0000
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
0000
Q2
Q3
Q4
No
operation
Process
Data
No
operation
ffff
ffff
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Words:
1
Cycles:
1
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
COMF
REG1,0
Before Instruction
CLRWDT
REG1
=
?
=
=
=
=
0x00
0
1
1
After Instruction
WDT counter
WDT Postscaler
001d
Description:
Decode
WDT counter
DS30264A-page 194
0100
0001
Q Cycle Activity:
Q1
Before Instruction
TO
PD
0000
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words:
Decode
Encoding:
f,d
=
0x13
After Instruction
REG1
WREG
=
=
0x13
0xEC
1997 Microchip Technology Inc.
PIC17C75X
CPFSEQ
Compare f with WREG,
skip if f = WREG
CPFSGT
Compare f with WREG,
skip if f > WREG
Syntax:
[ label ] CPFSEQ
Syntax:
[ label ] CPFSGT
Operands:
0 ≤ f ≤ 255
Operands:
0 ≤ f ≤ 255
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Operation:
(f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0011
0001
f
ffff
ffff
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If 'f' = WREG then the fetched instruction is discarded and an NOP is executed instead making this a two-cycle
instruction.
Words:
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Before Instruction
PC Address
WREG
REG
=
=
=
HERE
?
?
=
=
≠
=
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
0011
0010
ffff
ffff
Description:
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
If the contents of 'f' are greater than the
contents of WREG then the fetched
instruction is discarded and an NOP is
executed instead making this a
two-cycle instruction.
Words:
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
HERE
NGREATER
GREATER
CPFSGT REG
:
:
If skip:
Example:
Before Instruction
PC
WREG
=
=
Address (HERE)
?
>
=
≤
=
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
After Instruction
After Instruction
If REG
PC
If REG
PC
Encoding:
f
1997 Microchip Technology Inc.
If REG
PC
If REG
PC
DS30264A-page 195
PIC17C75X
CPFSLT
Compare f with WREG,
skip if f < WREG
Syntax:
[ label ] CPFSLT
Operands:
Operation:
Status Affected:
Syntax:
[label] DAW
0 ≤ f ≤ 255
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
0 ≤ f ≤ 255
s ∈ [0,1]
Operation:
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
WREG<3:0> → f<3:0>, s<3:0>;
f
None
0011
0000
ffff
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
HERE
NLESS
LESS
CPFSLT REG
:
:
f,s
ffff
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and an NOP is
executed instead making this a
two-cycle instruction.
Words:
Example:
Decimal Adjust WREG Register
Operands:
Encoding:
Description:
DAW
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
WREG<7:4> → f<7:4>, s<7:4>
Status Affected:
C
Encoding:
0010
111s
=
=
DAW adjusts the eight bit value in
WREG resulting from the earlier addition of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0: Result is placed in Data
memory location 'f' and
WREG.
s = 1: Result is placed in Data
memory location 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Address (HERE)
?
Example1:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
Address (NLESS)
ffff
Description:
Before Instruction
PC
W
ffff
DAW
REG1, 0
Before Instruction
WREG
REG1
C
DC
=
=
=
=
0xA5
??
0
0
After Instruction
WREG
REG1
C
DC
=
=
=
=
0x05
0x05
1
0
Example 2:
Before Instruction
WREG
REG1
C
DC
=
=
=
=
0xCE
??
0
0
After Instruction
WREG
REG1
C
DC
DS30264A-page 196
=
=
=
=
0x24
0x24
1
0
1997 Microchip Technology Inc.
PIC17C75X
DECF
Decrement f
DECFSZ
Decrement f, skip if 0
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) – 1 → (dest)
Operation:
Status Affected:
OV, C, DC, Z
(f) – 1 → (dest);
skip if result = 0
Status Affected:
None
Encoding:
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Process
Data
Write to
destination
DECF
CNT,
Before Instruction
=
=
=
=
1
Encoding:
0001
011d
ffff
ffff
Description:
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
HERE
DECFSZ
GOTO
0x01
0
After Instruction
CNT
Z
ffff
Read
register 'f'
Example:
CNT
Z
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Decode
011d
If skip:
0x00
1
Example:
CNT, 1
LOOP
CONTINUE
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
1997 Microchip Technology Inc.
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+1)
DS30264A-page 197
PIC17C75X
DCFSNZ
Decrement f, skip if not 0
GOTO
Unconditional Branch
Syntax:
[label] DCFSNZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ k ≤ 8191
Operation:
Operation:
(f) – 1 → (dest);
skip if not 0
k → PC<12:0>;
k<12:8> → PCLATH<4:0>,
PC<15:13> → PCLATH<7:5>
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0010
011d
ffff
ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is not 0, the next instruction, which is already fetched, is discarded, and an NOP is executed
instead making it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Encoding:
110k
Q2
Q3
Q4
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
kkkk
kkkk
GOTO allows an unconditional branch
anywhere within an 8K page boundary. The thirteen bit immediate value is
loaded into PC bits <12:0>. Then the
upper eight bits of PC are loaded into
PCLATH. GOTO is always a two-cycle
instruction.
Words:
1
Cycles:
2
Decode
Read
register 'f'
kkkk
Description:
Q Cycle Activity:
Q1
Decode
GOTO k
No
operation
Q2
Q3
Q4
Read literal
'k'
No
operation
Process
Data
No
operation
Write to PC
No
operation
If skip:
Example:
HERE
ZERO
NZERO
DCFSNZ
:
:
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
TEMP, 1
Before Instruction
TEMP_VALUE
=
?
=
=
=
≠
=
TEMP_VALUE - 1,
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
TEMP_VALUE
If TEMP_VALUE
PC
If TEMP_VALUE
PC
DS30264A-page 198
1997 Microchip Technology Inc.
PIC17C75X
INCF
Increment f
INCFSZ
Increment f, skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) + 1 → (dest)
Operation:
Status Affected:
OV, C, DC, Z
(f) + 1 → (dest)
skip if result = 0
Status Affected:
None
Encoding:
0001
Description:
010d
ffff
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
INCF f,d
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
INCF
CNT, 1
Encoding:
=
=
=
0xFF
0
?
After Instruction
CNT
Z
C
=
=
=
0x00
1
1
111d
ffff
ffff
Description:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Before Instruction
CNT
Z
C
0001
INCFSZ f,d
If skip:
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
1997 Microchip Technology Inc.
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
DS30264A-page 199
PIC17C75X
INFSNZ
Increment f, skip if not 0
IORLW
Inclusive OR Literal with WREG
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .OR. (k) → (WREG)
Status Affected:
Z
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) + 1 → (dest),
skip if not 0
Status Affected:
None
Encoding:
0010
Description:
INFSNZ f,d
Encoding:
010d
ffff
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
1011
IORLW k
0011
kkkk
kkkk
Description:
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
IORLW
0x35
Before Instruction
Q2
Q3
Q4
WREG
Read
register 'f'
Process
Data
Write to
destination
After Instruction
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
WREG
=
=
0x9A
0xBF
If skip:
Example:
HERE
ZERO
NZERO
INFSNZ
REG, 1
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
DS30264A-page 200
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
1997 Microchip Technology Inc.
PIC17C75X
IORWF
Inclusive OR WREG with f
LCALL
Long Call
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
Operation:
(WREG) .OR. (f) → (dest)
PC + 1 → TOS;
k → PCL, (PCLATH) → PCH
Status Affected:
Z
Status Affected:
None
Encoding:
0000
IORWF
100d
f,d
ffff
ffff
Description:
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
IORWF
RESULT, 0
Before Instruction
RESULT =
WREG =
0x13
0x91
Encoding:
0x13
0x93
1011
0111
k
kkkk
kkkk
Description:
LCALL allows an unconditional subroutine call to anywhere within the 64K program memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit destination address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
After Instruction
RESULT =
WREG =
LCALL
No
operation
Example:
Q2
Q3
Q4
Read
literal 'k'
No
operation
Process
Data
No
operation
Write
register PCL
No
operation
MOVLW
MOVPF
LCALL
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
Before Instruction
SUBROUTINE =
PC
=
16-bit Address
?
After Instruction
PC
1997 Microchip Technology Inc.
=
Address (SUBROUTINE)
DS30264A-page 201
PIC17C75X
MOVFP
Move f to p
MOVLB
Move Literal to low nibble in BSR
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 15
Operation:
k → (BSR<3:0>)
Status Affected:
None
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operation:
(f) → (p)
Status Affected:
None
Encoding:
Description:
Encoding:
011p
pppp
ffff
ffff
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 word data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either ’p' or 'f' can be WREG (a useful
special situation).
MOVFP is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
Words:
1
Cycles:
1
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'p'
1011
MOVFP
1000
uuuu
kkkk
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write literal
'k' to
BSR<3:0>
MOVLB
5
Before Instruction
BSR register
=
0x22
=
0x25 (Bank 5)
After Instruction
BSR register
Example:
MOVLB k
Description:
Example:
Q Cycle Activity:
Q1
Decode
MOVFP f,p
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33,
0x11
=
=
0x33,
0x33
After Instruction
REG1
REG2
DS30264A-page 202
1997 Microchip Technology Inc.
PIC17C75X
MOVLR
Move Literal to high nibble in
BSR
MOVLW
Move Literal to WREG
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
Operands:
0 ≤ k ≤ 15
0 ≤ k ≤ 255
Operation:
k → (BSR<7:4>)
k → (WREG)
Operation:
Status Affected:
None
Status Affected:
None
Encoding:
Description:
101x
kkkk
uuuu
The 4-bit literal 'k' is loaded into the
most significant 4-bits of the Bank
Select Register (BSR). Only the high
4-bits of the Bank Select Register
are affected. The lower half of the
BSR is unchanged. The assembler
will encode the “u” fields as 0.
1
Cycles:
1
1011
0000
kkkk
kkkk
The eight bit literal 'k' is loaded into
WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
MOVLW
Q2
Q3
Q4
After Instruction
Read literal
'k'
Process
Data
Write
literal 'k' to
BSR<7:4>
WREG
MOVLR
MOVLW k
Description:
Example:
Q Cycle Activity:
Q1
Example:
Encoding:
1011
Words:
Decode
MOVLR k
=
0x5A
0x5A
5
Before Instruction
BSR register
=
0x22
=
0x52
After Instruction
BSR register
1997 Microchip Technology Inc.
DS30264A-page 203
PIC17C75X
MOVPF
Move p to f
MOVWF
Move WREG to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
Operation:
(WREG) → (f)
Status Affected:
None
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operation:
(p) → (f)
Status Affected:
Z
Encoding:
Encoding:
010p
Description:
pppp
ffff
ffff
Move data from data memory location
'p' to data memory location 'f'. Location
'f' can be anywhere in the 256 byte data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either 'p' or 'f' can be WREG (a useful
special situation).
MOVPF is particularly useful for transferring a peripheral register (e.g. the timer
or an I/O port) to a data memory location. Both 'f' and 'p' can be indirectly
addressed.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
MOVPF p,f
0001
f
ffff
ffff
Description:
Move data from WREG to register 'f'.
Location 'f' can be anywhere in the 256
word data space.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
Example:
MOVWF
REG
Before Instruction
WREG
REG
Q2
Q3
Q4
Read
register 'p'
Process
Data
Write
register 'f'
Example:
0000
MOVWF
MOVPF
=
=
0x4F
0xFF
After Instruction
WREG
REG
=
=
0x4F
0x4F
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x11
0x33
=
=
0x11
0x11
After Instruction
REG1
REG2
DS30264A-page 204
1997 Microchip Technology Inc.
PIC17C75X
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
Operation:
(k x WREG) → PRODH:PRODL
Operation:
(WREG x f) → PRODH:PRODL
Status Affected:
None
Status Affected:
None
Encoding:
MULLW
1011
1100
k
kkkk
kkkk
Encoding:
0011
MULWF
0100
f
ffff
ffff
Description:
An unsigned multiplication is carried
out between the contents of WREG
and the 8-bit literal 'k'. The 16-bit
result is placed in PRODH:PRODL
register pair. PRODH contains the
high byte.
WREG is unchanged.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Description:
An unsigned multiplication is carried
out between the contents of WREG
and the register file location 'f'. The
16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
Both WREG and 'f' are unchanged.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write
registers
PRODH:
PRODL
MULLW
0xC4
Before Instruction
WREG
PRODH
PRODL
Decode
Example:
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
registers
PRODH:
PRODL
MULWF
REG
Before Instruction
=
=
=
0xE2
?
?
WREG
REG
PRODH
PRODL
=
=
=
0xC4
0xAD
0x08
After Instruction
After Instruction
WREG
PRODH
PRODL
Q Cycle Activity:
Q1
1997 Microchip Technology Inc.
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
DS30264A-page 205
PIC17C75X
NEGW
Negate W
Syntax:
[label]
Operands:
0 ≤ F ≤ 255
s ∈ [0,1]
Operation:
WREG + 1 → (f);
WREG + 1 → s
Status Affected:
OV, C, DC, Z
Encoding:
0010
Description:
NEGW
110s
f,s
1
Cycles:
1
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Encoding:
ffff
ffff
WREG is negated using two’s complement. If 's' is 0 the result is placed in
WREG and data memory location 'f'. If
's' is 1 the result is placed only in data
memory location 'f'.
Words:
NOP
0000
NOP
0000
Description:
No operation.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
0000
0000
Q2
Q3
Q4
No
operation
No
operation
No
operation
Example:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Example:
NEGW
None.
REG,0
Before Instruction
WREG
REG
=
=
0011 1010 [0x3A],
1010 1011 [0xAB]
After Instruction
WREG
REG
=
=
DS30264A-page 206
1100 0111 [0xC6]
1100 0111 [0xC6]
1997 Microchip Technology Inc.
PIC17C75X
RETFIE
Return from Interrupt
RETLW
Return Literal to WREG
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
TOS → (PC);
0 → GLINTD;
PCLATH is unchanged.
Operation:
k → (WREG); TOS → (PC);
PCLATH is unchanged
Status Affected:
None
Status Affected:
GLINTD
Encoding:
Encoding:
0000
RETFIE
0000
0000
0101
1011
Description:
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
Words:
1
Words:
1
Cycles:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
Q3
Q4
No
operation
No
operation
Clear
GLINTD
No
operation
POP PC
from stack
No
operation
Example:
kkkk
kkkk
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
No
operation
No
operation
No
operation
POP PC
from stack,
Write to
WREG
No
operation
RETFIE
Example:
After Interrupt
PC
=
GLINTD =
0110
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Description:
Q Cycle Activity:
Q1
RETLW k
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PC
;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
TOS
0
WREG contains table
offset value
WREG now has
table value
WREG = offset
Begin table
End of table
Before Instruction
WREG
=
0x07
After Instruction
WREG
1997 Microchip Technology Inc.
=
value of k7
DS30264A-page 207
PIC17C75X
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ] RLCF
Operands:
None
Operands:
Operation:
TOS → PC;
0 ≤ f ≤ 255
d ∈ [0,1]
Status Affected:
None
Operation:
f<n> → d<n+1>;
f<7> → C;
C → d<0>
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter.
Status Affected:
C
Words:
1
Description:
Cycles:
2
Encoding:
0000
Description:
Q Cycle Activity:
Q1
Decode
No
operation
RETURN
0000
0000
0010
Q2
Q3
Q4
No
operation
No
operation
Process
Data
No
operation
POP PC
from stack
No
operation
Example:
RETURN
Encoding:
0001
101d
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
After Interrupt
ffff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
register f
C
Decode
f,d
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
PC = TOS
Example:
RLCF
REG,0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
WREG
C
DS30264A-page 208
=
=
=
1110 0110
1100 1100
1
1997 Microchip Technology Inc.
PIC17C75X
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
f<n> → d<n+1>;
f<7> → d<0>
Operation:
Status Affected:
None
f<n> → d<n-1>;
f<0> → C;
C → d<7>
Status Affected:
C
Encoding:
0010
Description:
001d
f,d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Encoding:
0001
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
RLNCF
Before Instruction
C
REG
=
=
0
1110 1011
=
=
1101 0111
Q2
Q3
Q4
Process
Data
Write to
destination
RRCF
REG1,0
Before Instruction
=
=
1110 0110
0
After Instruction
REG1
WREG
C
1997 Microchip Technology Inc.
ffff
Read
register 'f'
Example:
REG1
C
After Instruction
C
REG
REG, 1
ffff
register f
C
Q2
Example:
100d
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
register f
Words:
RRCF f,d
=
=
=
1110 0110
0111 0011
0
DS30264A-page 209
PIC17C75X
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
s ∈ [0,1]
Operation:
f<n> → d<n-1>;
f<0> → d<7>
Operation:
FFh → f;
FFh → d
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
RRNCF f,d
000d
ffff
ffff
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed back in register 'f'.
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Process
Data
Write to
destination
RRNCF
REG, 1
Before Instruction
=
=
?
1101 0111
After Instruction
WREG
REG
=
=
Example 2:
0
1110 1011
RRNCF
REG, 0
=
=
?
1101 0111
After Instruction
WREG
REG
=
=
DS30264A-page 210
ffff
ffff
Words:
1
Cycles:
1
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Example1:
SETF
REG, 0
Before Instruction
REG
WREG
=
=
0xDA
0x05
After Instruction
REG
WREG
Example2:
=
0xFF
=
0xFF
SETF
REG, 1
Before Instruction
Before Instruction
WREG
REG
101s
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1
only the data memory location 'f' is set
to FFh.
Q Cycle Activity:
Q1
Read
register 'f'
Example 1:
0010
Description:
Decode
Decode
WREG
REG
Encoding:
SETF f,s
1110 1011
1101 0111
REG
WREG
=
=
0xDA
0x05
After Instruction
REG
WREG
=
=
0xFF
0x05
1997 Microchip Technology Inc.
PIC17C75X
SLEEP
Enter SLEEP mode
SUBLW
Subtract WREG from Literal
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
00h → WDT;
0 → WDT postscaler;
1 → TO;
0 → PD
Operation:
k – (WREG) → (WREG)
Status Affected:
OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Description:
0000
0000
1
Cycles:
1
Q Cycle Activity:
Q1
0010
kkkk
kkkk
Description:
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1:
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
SUBLW
0x02
Before Instruction
Q2
Q3
Q4
No
operation
Process
Data
Go to
sleep
Example:
SLEEP
Before Instruction
TO =
PD =
1011
WREG is subtracted from the eight bit
literal 'k'. The result is placed in
WREG.
0011
The power-down status bit (PD) is
cleared. The time-out status bit (TO)
is set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Decode
Encoding:
?
?
WREG
C
=
=
After Instruction
WREG
C
Z
=
=
=
; result is positive
Before Instruction
WREG
C
TO =
PD =
After Instruction
† If WDT causes wake-up, this bit is cleared
1
1
0
Example 2:
After Instruction
1†
0
1
?
WREG
C
Z
=
=
=
=
=
2
?
0
1
1
; result is zero
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
1997 Microchip Technology Inc.
=
=
=
FF ; (2’s complement)
0
; result is negative
1
DS30264A-page 211
PIC17C75X
Subtract WREG from f
SUBWF
SUBWFB
Subtract WREG from f with
Borrow
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] SUBWFB f,d
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) – (W) → (dest)
Operation:
(f) – (W) – C → (dest)
Status Affected:
OV, C, DC, Z
Status Affected:
OV, C, DC, Z
Encoding:
0000
010d
ffff
ffff
Description:
Subtract WREG from register 'f' (2’s
complement method). If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example 1:
SUBWF
=
=
=
=
=
=
=
=
=
=
=
; result is positive
=
=
=
=
DS30264A-page 212
REG1
WREG
C
Z
Example2:
ffff
Q2
Q3
Q4
Process
Data
Write to
destination
SUBWFB
=
=
=
=
=
=
=
Before Instruction
0
2
1
1
After Instruction
REG1
WREG
C
; result is zero
REG1
WREG
C
Z
Example3:
=
=
=
=
=
=
=
Before Instruction
FF
2
0
0
After Instruction
REG1
WREG
C
; result is negative
REG1
WREG
C
Z
(0001 1001)
(0000 1101)
0x0C
0x0D
1
0
(0000 1011)
(0000 1101)
; result is positive
=
=
=
=
=
=
=
REG1,0
0x1B
0x1A
0
(0001 1011)
(0001 1010)
0x1B
0x00
1
1
(0001 1011)
SUBWFB
1
2
?
REG1, 1
0x19
0x0D
1
SUBWFB
2
2
?
After Instruction
REG1
WREG
C
Z
ffff
Read
register 'f'
After Instruction
Before Instruction
=
=
=
Q Cycle Activity:
Q1
1
2
1
0
Example 3:
REG1
WREG
C
1
REG1
WREG
C
After Instruction
REG1
WREG
C
Z
1
Cycles:
Before Instruction
Before Instruction
=
=
=
Words:
Decode
001d
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s complement method). If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in register 'f'.
3
2
?
Example 2:
REG1
WREG
C
Description:
Example 1:
After Instruction
REG1
WREG
C
Z
0000
REG1, 1
Before Instruction
REG1
WREG
C
Encoding:
; result is zero
REG1,1
0x03
0x0E
1
(0000 0011)
(0000 1101)
0xF5
0x0E
0
0
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
1997 Microchip Technology Inc.
PIC17C75X
SWAPF
Swap f
TABLRD
Table Read
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] TABLRD t,i,f
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
Operation:
f<3:0> → dest<7:4>;
f<7:4> → dest<3:0>
0 ≤ f ≤ 255
i ∈ [0,1]
t ∈ [0,1]
Operation:
Status Affected:
None
If t = 1,
TBLATH → f;
If t = 0,
TBLATL → f;
Prog Mem (TBLPTR) → TBLAT;
If i = 1,
TBLPTR + 1 → TBLPTR
Status Affected:
None
Encoding:
0001
110d
ffff
ffff
Description:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Encoding:
Description:
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
1010
SWAPF
REG,
1.
2.
0
Before Instruction
REG
=
3.
0x53
After Instruction
REG
=
0x35
ffff
1
Cycles:
2 (3 cycle if f = PCL)
Decode
No
operation
ffff
A byte of the table latch (TBLAT)
is moved to register file 'f'.
If t = 0: the high byte is moved;
If t = 1: the low byte is moved
Then the contents of the program
memory location pointed to by
the
16-bit
Table
Pointer
(TBLPTR) is loaded into the
16-bit Table Latch (TBLAT).
If i = 1: TBLPTR is incremented;
If i = 0: TBLPTR is not
incremented
Words:
Q Cycle Activity:
Q1
1997 Microchip Technology Inc.
10ti
Q2
Q3
Q4
Read
register
TBLATH or
TBLATL
No
operation
(Table Pointer
on Address
bus)
Process
Data
Write
register 'f'
No
operation
No
operation
(OE goes low)
DS30264A-page 213
PIC17C75X
TABLRD
Table Read
TABLWT
Table Write
Example1:
TABLRD
Syntax:
[ label ] TABLWT t,i,f
Operands:
0 ≤ f ≤ 255
i ∈ [0,1]
t ∈ [0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem
(TBLPTR);
If i = 1,
TBLPTR + 1 → TBLPTR
Status Affected:
None
1, 1, REG ;
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Example2:
TABLRD
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
0, 0, REG ;
Encoding:
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
1010
Description:
1.
2.
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x55
0x12
0x34
0xA356
0x1234
Note:
ffff
ffff
Load value in ’f’ into 16-bit table
latch (TBLAT)
If t = 0: load into low byte;
If t = 1: load into high byte
The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be interrupted. A short write will occur (2 TCY).
The internal memory location will not be affected.
3.
The TBLPTR can be automatically incremented
If i = 0; TBLPTR is not
incremented
If i = 1; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Decode
No
operation
DS30264A-page 214
11ti
Q2
Q3
Read
register 'f'
Process
Data
Q4
Write
register
TBLATH or
TBLATL
No
No
No
operation
operation
operation
(Table Pointer
(Table Latch on
on Address
Address bus,
bus)
WR goes low)
1997 Microchip Technology Inc.
PIC17C75X
TABLWT
Table Write
TLRD
Table Latch Read
Example1:
TABLWT
Syntax:
[ label ] TLRD t,f
Operands:
0 ≤ f ≤ 255
t ∈ [0,1]
Operation:
If t = 0,
TBLATL → f;
If t = 1,
TBLATH → f
Status Affected:
None
1, 1, REG
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR - 1)
Example 2:
TABLWT
=
=
=
=
=
0x53
0x53
0x55
0xA357
0x5355
Encoding:
1010
0x53
0xAA
0x55
0xA356
0xFFFF
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Program
Memory
=
=
=
=
=
15
0x53
0xAA
0x53
0xA356
0xAA53
0
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Data
Memory
16 bits
8
7
TBLAT
Q2
Q3
Q4
Read
register
TBLATH or
TBLATL
Process
Data
Write
register 'f'
Example:
TLRD
t, RAM
Before Instruction
TBLPTR
15
ffff
Read data from 16-bit table latch
(TBLAT) into file register 'f'. Table Latch
is unaffected.
If t = 1; high byte is read
If t = 0; low byte is read
This instruction is used in conjunction
with TABLRD to transfer data from program memory to data memory.
Before Instruction
=
=
=
=
=
ffff
Description:
0, 0, REG
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
00tx
t
RAM
TBLAT
0
=
=
=
0
?
0x00AF
8 bits
(TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
TBLAT
=
=
0xAF
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t
RAM
TBLAT
=
=
=
1
?
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
TBLAT
Program
Memory
=
=
0x00
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
15
0
Data
Memory
TBLPTR
15
16 bits
1997 Microchip Technology Inc.
8
7
TBLAT
0
8 bits
DS30264A-page 215
PIC17C75X
TLWT
Table Latch Write
TSTFSZ
Test f, skip if 0
Syntax:
[ label ] TLWT t,f
Syntax:
[ label ] TSTFSZ f
Operands:
0 ≤ f ≤ 255
t ∈ [0,1]
Operands:
0 ≤ f ≤ 255
Operation:
skip if f = 0
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH
Status Affected:
None
Encoding:
0011
0011
ffff
ffff
Description:
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
If t = 1; high byte is written
If t = 0; low byte is written
This instruction is used in conjunction
with TABLWT to transfer data from data
memory to program memory.
Words:
1
Cycles:
1 (2)
Words:
1
If skip:
Cycles:
1
Status Affected:
None
Encoding:
1010
Description:
Q Cycle Activity:
Q1
Decode
01tx
ffff
ffff
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register
TBLATH or
TBLATL
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
TSTFSZ
:
CNT
:
Before Instruction
PC = Address(HERE)
Example:
TLWT
t, RAM
Before Instruction
t
RAM
TBLAT
Q Cycle Activity:
Q1
=
=
=
0
0xB7
0x0000
(TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
After Instruction
RAM
TBLAT
=
=
0xB7
0x00B7
(TBLATH = 0x00)
(TBLATL = 0xB7)
Before Instruction
t
RAM
TBLAT
=
=
=
1
0xB7
0x0000
(TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
TBLAT
=
=
DS30264A-page 216
0xB7
0xB700
(TBLATH = 0xB7)
(TBLATL = 0x00)
1997 Microchip Technology Inc.
PIC17C75X
XORLW
Exclusive OR Literal with
WREG
XORWF
Exclusive OR WREG with f
Syntax:
[ label ] XORWF
Syntax:
[ label ] XORLW k
Operands:
Operands:
0 ≤ k ≤ 255
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) .XOR. k → (WREG)
Operation:
(WREG) .XOR. (f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
1011
0100
kkkk
kkkk
Description:
The contents of WREG are XOR’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
XORLW
0xAF
Before Instruction
WREG
=
0xB5
After Instruction
WREG
=
0x1A
Encoding:
110d
ffff
ffff
Description:
Exclusive OR the contents of WREG
with register 'f'. If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in the register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
XORWF
REG, 1
Before Instruction
REG
WREG
=
=
0xAF
0xB5
After Instruction
REG
WREG
1997 Microchip Technology Inc.
0000
f,d
=
=
0x1A
0xB5
DS30264A-page 217
PIC17C75X
NOTES:
DS30264A-page 218
1997 Microchip Technology Inc.
PIC17C75X
19.0
DEVELOPMENT SUPPORT
19.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH−MP)
19.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
19.3
ICEPIC: Low-cost PIC16CXXX
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
19.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
19.5
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1997 Microchip Technology Inc.
DS30264A-page 219
PIC17C75X
19.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
19.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
19.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30264A-page 220
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. PICDEM-3 will
be available in the 3rd quarter of 1996.
19.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
19.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
1997 Microchip Technology Inc.
PIC17C75X
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator
System.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in developing software for specific use applications.
19.14
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
19.11
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
19.13
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
19.15
SEEVAL Evaluation and
Programming System
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
19.12
MP-DriveWay – Application Code
Generator
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
19.16
TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
19.17
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
1997 Microchip Technology Inc.
DS30264A-page 221
Emulator Products
Software Tools
DS30264A-page 222
Programmers
✔
KEELOQ
Evaluation Kit
PICDEM-3
PICDEM-2
PICDEM-1
SEEVAL
Designers Kit
KEELOQ
Programmer
PRO MATE II
Universal
Programmer
PICSTART
Plus Low-Cost
Universal Dev. Kit
PICSTART
Lite Ultra Low-Cost
Dev. Kit
Total Endurance
Software Model
✔
✔
✔
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
✔
MPLAB C
Compiler
✔
✔
MPLAB
Integrated
Development
Environment
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
✔
✔
✔
✔
✔
✔
PIC14000
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C5X
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16CXXX
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
✔
✔
✔
✔
Available
3Q97
PIC17C75X
✔
✔
✔
24CXX
25CXX
93CXX
✔
✔
✔
HCS200
HCS300
HCS301
TABLE 19-1:
Demo Boards
PIC12C5XX
PIC17C75X
DEVELOPMENT TOOLS FROM MICROCHIP
1997 Microchip Technology Inc.
PIC17C75X
20.0
PIC17C752/756 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................. -55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... -0.3V to +14V
Voltage on RA2 and RA3 with respect to VSS ............................................................................................. -0.3V to +14V
Voltage on all other pins with respect to VSS .................................................................................... -0.3V to VDD + 0.3V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin(s) - total (@ 70˚C) ............................................................................................500 mA
Maximum current into VDD pin(s) - total (@ 70˚C) ...............................................................................................500 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3).....................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins ................................................................................................60 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined) .................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined) ..................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined).............................................................100 mA
Maximum current sunk by PORTF and PORTG (combined) ................................................................................150 mA
Maximum current sourced by PORTF and PORTG (combined) ...........................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 223
PIC17C75X
TABLE 20-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC17LC752-08
PIC17LC756-08
PIC17C752-25
PIC17C756-25
PIC17C752-33
PIC17C756-33
JW Devices
(Ceramic Windowed
Devices)
RC
VDD: 3.0V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD †: 6 mA max.
IDD †: 6 mA max.
IDD †: 6 mA max.
IDD †: 6 mA max.
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
XT VDD: 3.0V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD †: 12 mA max.
IDD †: 38 mA max.
IDD †: 50 mA max.
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
Freq: 8 MHz max.
Freq: 25 MHz max.
Freq: 33 MHz max.
Freq: 33 MHz max.
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
EC VDD: 3.0V to 6.0V
IDD †: 12 mA max.
IDD †: 38 mA max.
IDD †: 50 mA max.
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
IPD †: 5 µA max. at 5.5V
Freq: 8 MHz max.
Freq: 25 MHz max.
Freq: 33 MHz max.
Freq: 33 MHz max.
LF VDD: 3.0V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 3.0V to 6.0V
IDD †: 115 µA max. at 32 kHz IDD †: 85 µA typ. at 32 kHz
IDD †: 85 µA typ. at 32 kHz
IDD †: 115 µA max. at 32 kHz
IPD †: 5 µA max. at 5.5V
IPD †: < 1 µA typ. at 5.5V
IPD †: < 1 µA typ. at 5.5V
IPD †: 5 µA max. at 5.5V
Freq: 2 MHz max.
Freq: 2 MHz max.
Freq: 2 MHz max.
Freq: 2 MHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
†
The WDT, BOR,and A/D circuitry are disabled.
DS30264A-page 224
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
20.1
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param.
No.
D001
D002
PIC17C752/756-25 (Commercial, Industrial)
PIC17C752/756-33 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Characteristic
Min
Typ† Max Units
Conditions
VDD
Supply Voltage
4.5
–
6.0
V
VDR
RAM Data Retention
1.5 *
–
–
V
Device in SLEEP mode
Voltage (Note 1)
VDD start voltage to
–
VSS
–
V
See section on Power-on Reset for
D003
VPOR
ensure internal
details
Power-on Reset signal
VDD rise rate to
0.085 *
–
–
V/ms See section on Power-on Reset for
D004
SVDD
ensure proper
details
operation
Brown-out Reset
3.6
–
4.3
V
D005
VBOR
voltage trip point
–
1.8
–
V
VDD = VPORTP
D006
VPORTP Power-on reset trip
point
FOSC = 4 MHz (Note 4)
mA
TBD 6 *
IDD
Supply Current
–
D010
mA
12
TBD
(Note 2)
–
FOSC = 8 MHz
D011
mA
TBD 24 *
–
FOSC = 16 MHz
D012
mA
38
TBD
–
D013
FOSC = 25 MHz
mA
50
TBD
–
D015
FOSC = 33 MHz
D021
IPD
Power-down Current
–
<1
5
µA
VDD = 5.5V, WDT disabled
(Note 3)
Module Differential
Current
D023
∆IBOR
BOR circuitry
–
300 500
µA
VDD = 4.5V, BODEN enabled
D024
∆IWDT
Watchdog Timer
–
10
35
µA
VDD = 5.5V
D026
∆IAD
A/D converter
–
1
–
µA
VDD = 5.5V, A/D not converting
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (C L • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 225
PIC17C75X
20.2
DC CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Param.
No.
D001
D002
D003
D004
D005
D006
D010
D011
D014
Sym
VDD
VDR
PIC17LC752/756 (Commercial, Industrial)
PIC17LC752/756 (Commercial, Industrial)
Characteristic
Min
Supply Voltage
3.0
RAM Data Retention
1.5 *
Voltage (Note 1)
VDD start voltage to
–
VPOR
ensure internal
Power-on Reset signal
VDD rise rate to
0.010 *
SVDD
ensure proper
operation
Brown-out Reset
3.6
VBOR
voltage trip point
–
VPORTP Power-on reset trip
point
Supply Current
–
IDD
(Note 2)
–
–
Typ† Max
Units
Conditions
–
–
6.0
–
V
V
VSS
–
V
See section on Power-on Reset for
details
–
–
V/ms
See section on Power-on Reset for
details
–
4.3
V
1.8
–
V
3
6
85
6 *
12
150
mA
mA
µA
Device in SLEEP mode
VDD = VPORTP
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 32 kHz,
(EC osc configuration)
VDD = 5.5V, WDT disabled
Power-down Current
–
<1
5
µA
(Note 3)
Module Differential
Current
D023
∆IBOR
BOR circuitry
–
300 500
µA
VDD = 4.5V, BODEN enabled
D024
∆IWDT
Watchdog Timer
–
10
35
µA
VDD = 5.5V
D026
∆IAD
A/D converter
–
1
–
µA
VDD = 5.5V, A/D not converting
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR
= VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (C L • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
D021
IPD
DS30264A-page 226
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
20.3
DC CHARACTERISTICS:
PIC17C752/756-25
(Commercial, Industrial)
PIC17C752/756-33 (Commercial, Industrial)
PIC17LC752/756-08 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 20.1
DC CHARACTERISTICS
Param.
No.
Sym
VIL
D030
D031
Characteristic
Input Low Voltage
I/O ports
with TTL buffer (Note 6)
with Schmitt Trigger buffer
D032
D033
VIH
D040
D041
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
Input High Voltage
I/O ports
with TTL buffer (Note 6)
with Schmitt Trigger buffer
D042
D043
D050
MCLR
OSC1 (XT, and LF mode)
VHYS Hysteresis of
Schmitt Trigger inputs
Input Leakage Current
(Notes 2, 3)
IIL
I/O ports (except RA2, RA3)
D060
Min
Typ†
Max
Units
VSS
VSS
–
–
0.8
0.2VDD
V
V
VSS
–
0.2VDD
V
Vss
–
0.2VDD
V
–
0.5VDD
–
V
2.0
1 + 0.2VDD
–
–
VDD
VDD
V
V
0.8VDD
–
VDD
V
VDD
–
–
V
V
V
0.8VDD
–
–
0.5VDD
0.15VDD *
–
–
–
±1
Conditions
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V, and
5.5V ≤ VDD ≤ 6.0V
Note1
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V, and
5.5V ≤ VDD ≤ 6.0V
Note1
µA Vss ≤ VPIN ≤ VDD,
I/O Pin (in digital mode) at
hi-impedance PORTB weak
pull-ups disabled
D061
D062
D063
D063B
MCLR, TEST
RA2, RA3
OSC1 (EC, RC modes)
OSC1 (XT, LF modes)
–
–
–
–
–
–
±2
±2
±1
VPIN
D064
MCLR, TEST
–
–
25
µA VMCLR = VPP = 12V
(when not programming)
60
200
400
µA
IPURB PORTB weak pull-up current
D070
*
†
‡
Note 1:
2:
3:
4:
5:
6:
µA
µA
µA
µA
VPIN = Vss or VPIN = VDD
Vss ≤ VRA2, VRA3 ≤ 12V
Vss ≤ VPIN ≤ VDD
RF ≥ 1 MΩ, see Figure 4-2
VPIN = VSS, RBPU = 0
4.5V ≤ VDD ≤ 6.0V
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C75X Programming
Specifications (Literature number DS TBD).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 227
PIC17C75X
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 20.1
DC CHARACTERISTICS
Param.
No.
D080
Sym
VOL
D081
Characteristic
Output Low Voltage
I/O ports
with TTL buffer
D082
RA2 and RA3
D083
D084
OSC2/CLKOUT
(RC and EC osc modes)
D090
VOH
D091
Typ†
Max
Units
–
–
–
–
–
–
0.1VDD
0.1VDD *
0.4
V
V
V
–
–
–
–
–
–
–
–
–
–
3.0
0.4
0.6
0.4
0.1VDD *
V
V
V
V
V
0.9VDD
0.9VDD *
2.4
–
–
–
–
–
–
V
V
V
2.4
0.9VDD *
–
–
–
–
V
V
V
Output High Voltage (Note 3)
I/O ports (except RA2 and RA3)
with TTL buffer
D093
D094
Min
OSC2/CLKOUT
(RC and EC osc modes)
VOD
Open Drain High Voltage
–
–
12
D100
COSC2
Capacitive Loading Specs
on Output Pins
OSC2/CLKOUT pin
–
–
25 ‡
D101
CIO
–
–
50 ‡
D102
CAD
–
–
50 ‡
D150
*
†
‡
Note 1:
2:
3:
4:
5:
6:
All I/O pins and OSC2
(in RC mode)
System Interface Bus
(PORTC, PORTD and PORTE)
Conditions
IOL = VDD/1.250 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 3.0V
IOL = 6 mA, VDD = 4.5V
Note 6
IOL = 60.0 mA, VDD = 6.0V
IOL = 60.0 mA, VDD = 2.5V
IOL = 60.0 mA, VDD = 4.5V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
(PIC17LC75X only)
IOH = -VDD/2.500 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 3.0V
IOH = -6.0 mA, VDD = 4.5V
Note 6
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
(PIC17LC75X only)
RA2 and RA3 pins only
Pulled-up to externally
applied voltage
pF In EC or RC osc modes
when OSC2 pin is outputting
CLKOUT.
external clock is used to
drive OSC1.
pF
pF In Microprocessor or
Extended Microcontroller
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C75X Programming
Specifications (Literature number DS TBD).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
DS30264A-page 228
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 20.1
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Internal Program Memory
Programming Specs (Note 4)
VPP Voltage on MCLR/VPP pin
VDDP Supply voltage during
programming
Current into MCLR/VPP pin
IPP
IDDP Supply current during
programming
TPROG Programming pulse width
D110
D111
D112
D113
D114
*
†
‡
Note 1:
2:
3:
4:
5:
6:
Min
Typ†
Max
Units
Conditions
12.75
4.75
–
5.0
13.25
5.25
V
V
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
100
–
1000
µs Terminated via internal/external interrupt or a
reset
Note 5
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
Note 1: When using the Table Write for internal programming, the device temperature must be less than 40˚C.
Note 2: For In-circuit Serial Programming (ISP), refer to the device programming specification.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 229
PIC17C75X
20.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
al
ALE
cc
Capture1 and Capture2
ck
CLKOUT or clock
dt
Data in
in
INT pin
io
I/O port
mc
MCLR
oe
OE
os
OSC1
Uppercase symbols and their meanings:
S
D
Driven
E
Edge
F
Fall
H
High
I
Invalid (Hi-impedance)
DS30264A-page 230
T
Time
ost
pwrt
rb
rd
rw
t0
t123
wdt
wr
Oscillator Start-Up Timer
Power-Up Timer
PORTB
RD
RD or WR
T0CKI
TCLK12 and TCLK3
Watchdog Timer
WR
L
P
R
V
Z
Low
Period
Rise
Valid
Hi-impedance
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D, E, F, and G pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
0.25V
Data out valid
Output
driven
Output
hi-impedance
Data out invalid
0.9 VDD
0.1 VDD
Rise Time
Fall Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 231
PIC17C75X
20.5
Timing Diagrams and Specifications
FIGURE 20-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
3
1
2
3
4
4
OSC2 †
† In EC and RC modes only.
TABLE 20-2:
Param.
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Fosc
External CLKIN Frequency
(Note 1)
DC
DC
DC
DC
1
1
1
DC
125
40
30.3
250
125
40
30.3
500
121.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4/Fosc
8
25
33
4
8
25
33
2
—
—
—
—
1,000
1,000
1,000
—
DC
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
(Note 1)
1
Tosc
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
2
3
4
†
‡
Note 1:
Conditions
EC osc mode - 08 devices (8 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
RC osc mode
XT osc mode - 08 devices (8 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
LF osc mode
EC osc mode - 08 devices (8 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
RC osc mode
XT osc mode - 08 devices (8 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
LF osc mode
Instruction Cycle Time
(Note 1)
TosL, Clock in (OSC1)
10 ‡
—
—
ns
EC oscillator
TosH high or low time
TosR, Clock in (OSC1)
—
—
5‡
ns
EC oscillator
TosF rise or fall time
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
TCY
DS30264A-page 232
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
OSC2 †
13
12
18
14
16
19
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
† In EC and RC modes only.
TABLE 20-3:
Param.
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
10
TosL2ckL
11
TosL2ckH
12
OSC1↓ to CLKOUT↓
—
15 ‡
30 ‡
ns
Note 1
OSC1↓ to CLKOUT↑
—
15 ‡
30 ‡
ns
Note 1
TckR
CLKOUT rise time
—
5‡
15 ‡
ns
Note 1
13
TckF
CLKOUT fall time
—
5‡
15 ‡
ns
Note 1
14
TckH2ioV
CLKOUT ↑ to Port PIC17CXXX
out valid
PIC17LCXXX
—
—
0.5TCY + 20 ‡
ns
Note 1
—
—
0.5TCY + 50 ‡
ns
Note 1
0.25TCY + 25 ‡
—
—
ns
Note 1
0.25TCY + 50 ‡
—
—
ns
Note 1
Note 1
15
TioV2ckH
Port in valid before PIC17CXXX
CLKOUT↑
PIC17LCXXX
Units Conditions
16
TckH2ioI
Port in hold after CLKOUT↑
0‡
—
—
ns
17
TosL2ioV
OSC1↓ (Q1 cycle) to Port out valid
—
—
100 ‡
ns
18
TosL2ioI
OSC1↓ (Q2 cycle) to Port input invalid
(I/O in hold time)
0‡
—
—
ns
19
TioV2osL
Port input valid to OSC1↓
(I/O in setup time)
30 ‡
—
—
ns
20
TioR
Port output rise time
—
10 ‡
35 ‡
ns
21
TioF
Port output fall time
—
10 ‡
35 ‡
ns
22
TinHL
INT pin high or low time
25 *
—
—
ns
23
TrbHL
RB7:RB0 change INT high or low time
25 *
—
—
ns
*
†
‡
Note 1:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 233
PIC17C75X
FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET TIMING
VDD
MCLR
30
Internal
POR / BOR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 20-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
31
TWDT
Watchdog Timer Time-out Period
(Prescale = 1)
Oscillation Start-up Timer Period
32
TOST
33
TPWRT
34
TIOZ
35
36
*
†
‡
§
Typ†
Max
Units
Conditions
100 *
—
—
ns
VDD = 5V
5*
12
25 *
ms
VDD = 5V
—
1024TOSC§
—
ms
TOSC = OSC1 period
40 *
96
200 *
ms
VDD = 5V
100 ‡
—
—
ns
Depends on pin load
PIC17CXXX
—
—
100 *
ns
PIC17LCXXX
—
—
120 *
ns
100 *
—
—
ns
Power-up Timer Period
MCLR to I/O hi-impedance
TmcL2adI MCLR to System Interface bus (AD15:AD0>)
invalid
TBOR
Min
Brown-out Reset Pulse Width (low)
3.8V ≤ VDD ≤ 4.2V
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
DS30264A-page 234
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 20-5:
Param.
No.
40
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Sym Characteristic
Min
Tt0H T0CKI High Pulse Width
No Prescaler
41
Tt0L T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
42
Tt0P T0CKI Period
*
†
Typ† Max Units Conditions
0.5TCY + 20 §
10*
0.5TCY + 20 §
10*
Greater of:
20 ns or Tcy + 40 §
N
—
—
ns
—
—
—
—
—
—
—
—
ns
ns
ns
ns
N = prescale value
(1, 2, 4, ..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
§
FIGURE 20-6: TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 20-6:
TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Sym
45
46
47
Tt123H
Tt123L
Tt123P
48
*
†
§
Characteristic
Min
TCLK12 and TCLK3 high time
TCLK12 and TCLK3 low time
TCLK12 and TCLK3 input period
0.5TCY + 20 §
0.5TCY + 20 §
TCY + 40 §
N
2TOSC §
Typ
†
Max
—
—
—
—
—
—
Units Conditions
ns
ns
ns
N = prescale value
(1, 2, 4, 8)
TckE2tmrI Delay from selected External Clock Edge to
— 6Tosc §
—
Timer increment
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 235
PIC17C75X
FIGURE 20-7: CAPTURE TIMINGS
CAP pin
(Capture Mode)
50
51
52
TABLE 20-7:
Param.
No.
50
51
52
*
†
CAPTURE REQUIREMENTS
Sym Characteristic
Min
Typ† Max Units Conditions
TccL Capture pin input low time
TccH Capture pin input high time
TccP Capture pin input period
10 *
10 *
—
—
—
—
ns
ns
2TCY §
N
—
—
ns
N = prescale value
(4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
§
FIGURE 20-8: PWM TIMINGS
PWM pin
(PWM Mode)
53
TABLE 20-8:
Param.
No.
53
54
*
†
§
54
PWM REQUIREMENTS
Sym Characteristic
Min
Typ† Max Units Conditions
TccR PWM pin output rise time
—
10 * 35 *
ns
TccF PWM pin output fall time
—
10 * 35 *
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
DS30264A-page 236
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSB
SDO
LSB
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
73
Refer to Figure 20-1 for load conditions.
TABLE 20-9:
Param.
No.
70
*
†
SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
TssL2scH,
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
TssL2scL
71
TscH
SCK input high time (slave mode)
TCY + 20 *
—
—
ns
72
TscL
SCK input low time (slave mode)
TCY + 20 *
—
—
ns
73
TdiV2scH,
Setup time of SDI data input to SCK
100 *
—
—
ns
TdiV2scL
edge
74
TscH2diL,
Hold time of SDI data input to SCK
100 *
—
—
ns
TscL2diL
edge
75
TdoR
SDO data output rise time
—
10
25 *
ns
76
TdoF
SDO data output fall time
—
10
25 *
ns
78
TscR
SCK output rise time (master mode)
—
10
25 *
ns
79
TscF
SCK output fall time (master mode)
—
10
25 *
ns
80
TscH2doV,
SDO data output valid after SCK
—
—
50 *
ns
TscL2doV
edge
Characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are no
tested.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 237
PIC17C75X
FIGURE 20-10: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
BIT6 - - - - - -1
MSB
SDO
LSB
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
Refer to Figure 20-1 for load conditions.
TABLE 20-10: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
71
72
73
*
†
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
TscH
SCK input high time (slave mode)
TCY + 20 *
—
—
ns
TscL
SCK input low time (slave mode)
TCY + 20 *
—
—
ns
TdiV2scH,
Setup time of SDI data input to SCK
100 *
—
—
ns
TdiV2scL
edge
74
TscH2diL,
Hold time of SDI data input to SCK
100 *
—
—
ns
TscL2diL
edge
75
TdoR
SDO data output rise time
—
10
25 *
ns
76
TdoF
SDO data output fall time
—
10
25 *
ns
78
TscR
SCK output rise time (master mode)
—
10
25 *
ns
79
TscF
SCK output fall time (master mode)
—
10
25 *
ns
80
TscH2doV,
SDO data output valid after SCK
—
—
50 *
ns
TscL2doV
edge
—
—
ns
81
TdoV2scH,
SDO data output setup to SCK
TCY *
TdoV2scL
edge
Characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30264A-page 238
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSB
SDO
BIT6 - - - - - -1
LSB
77
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
73
Refer to Figure 20-1 for load conditions.
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No.
70
*
†
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
TssL2scH,
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
TssL2scL
71
TscH
SCK input high time (slave mode)
TCY + 20 *
—
—
ns
72
TscL
SCK input low time (slave mode)
TCY + 20 *
—
—
ns
73
TdiV2scH,
Setup time of SDI data input to SCK
100 *
—
—
ns
TdiV2scL
edge
74
TscH2diL,
Hold time of SDI data input to SCK
100 *
—
—
ns
TscL2diL
edge
75
TdoR
SDO data output rise time
—
10
25 *
ns
76
TdoF
SDO data output fall time
—
10
25 *
ns
77
TssH2doZ
SS↑ to SDO output hi-impedance
10 *
—
50 *
ns
78
TscR
SCK output rise time (master mode)
—
10
25 *
ns
79
TscF
SCK output fall time (master mode)
—
10
25 *
ns
80
TscH2doV,
SDO data output valid after SCK
—
—
50 *
ns
TscL2doV
edge
83
TscH2ssH,
SS ↑ after SCK edge
1.5TCY
—
—
ns
TscL2ssH
+ 40 *
Characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 239
PIC17C75X
FIGURE 20-12: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSB
SDO
BIT6 - - - - - -1
LSB
75, 76
SDI
MSB IN
77
BIT6 - - - -1
LSB IN
74
Refer to Figure 20-1 for load conditions.
TABLE 20-12: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Param.
No.
70
71
72
74
75
76
77
80
82
Sym
TssL2scH,
TssL2scL
TscH
TscL
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscH2doV,
TscL2doV
TssL2doV
83
*
†
Characteristic
SS↓ to SCK↓ or SCK↑ input
SCK input high time (slave mode)
SCK input low time (slave mode)
Hold time of SDI data input to SCK
edge
SDO data output rise time
SDO data output fall time
SS↑ to SDO output hi-impedance
SDO data output valid after SCK
edge
SDO data output valid after SS↓
edge
SS ↑ after SCK edge
Min
Typ†
Max
Units
TCY *
—
—
ns
TCY + 20 *
TCY + 20 *
100 *
—
—
—
—
—
—
ns
ns
ns
—
—
10 *
—
10
10
—
—
25 *
25 *
50 *
50 *
ns
ns
ns
ns
—
—
50 *
ns
Conditions
TscH2ssH,
1.5TCY
—
—
ns
TscL2ssH
+ 40 *
Characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30264A-page 240
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-13: I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 20-1 for load conditions
TABLE 20-13: I2C BUS START/STOP BITS REQUIREMENTS
Param.
No.
Sym
90
TSU:STA
91
92
93
Characteristic
START condition
Setup time
Min
100 kHz mode
400 kHz mode
Units
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
—
—
—
—
—
—
ns
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
—
—
—
—
—
—
ns
—
—
—
—
—
—
ns
(1)
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
—
—
—
—
—
—
ns
1 MHz mode (1)
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
THD:STA START condition
Hold time
1 MHz mode (1)
100 kHz mode
400 kHz mode
TSU:STO STOP condition
Setup time
1 MHz mode (1)
100 kHz mode
400 kHz mode
THD:STO STOP condition
Hold time
Typ Max
1 MHz mode
100 kHz mode
400 kHz mode
Conditions
Only relevant for
repeated START condition
After this period the first
clock pulse is generated
§ This specification ensured by design. For the value required by the I2C specification, please refer to Figure E-11.
Note 1:
Maximum pin capacitance = 10 pF for all I2C pins.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 241
PIC17C75X
FIGURE 20-14: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note: Refer to Figure 20-1 for load conditions
DS30264A-page 242
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 20-14: I2C BUS DATA REQUIREMENTS
Param.
No.
Sym
Characteristic
100
THIGH
Clock high time
101
TLOW
Clock low time
102
TR
SDA and SCL
rise time
100 kHz mode
400 kHz mode
SDA and SCL
fall time
1 MHz mode (1)
100 kHz mode
400 kHz mode
103
TF
Min
Max
Units
—
—
—
µs
µs
µs
—
—
—
µs
µs
µs
—
20 + 0.1Cb *
—
1000 *
300 *
300 *
ns
ns
ns
Cb is specified to be from
10 to 400 pF
—
20 + 0.1Cb *
—
300 *
300 *
100 *
ns
ns
ns
Cb is specified to be from
10 to 400 pF
—
—
—
µs
µs
µs
Only relevant for repeated
START condition
—
—
—
µs
µs
µs
After this period the first
clock pulse is generated
—
0.9 *
—
ns
µs
ns
—
—
—
ns
ns
ns
—
—
—
µs
µs
µs
—
—
—
3500 *
1000 *
—
ns
ns
ns
4.7 ‡
1.3 ‡
TBD *
—
—
—
µs
µs
µs
—
400 *
pF
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
1 MHz mode (1) 2(TOSC)(BRG + 1) §
100 kHz mode 2(TOSC)(BRG + 1) §
400 kHz mode 2(TOSC)(BRG + 1) §
1 MHz mode (1) 2(TOSC)(BRG + 1) §
90
TSU:STA
START condition
setup time
1 MHz mode (1)
100 kHz mode 2(TOSC)(BRG + 1) §
400 kHz mode 2(TOSC)(BRG + 1) §
1 MHz mode (1) 2(TOSC)(BRG + 1) §
91
THD:STA
START condition
hold time
100 kHz mode
400 kHz mode
106
THD:DAT
Data input
hold time
107
TSU:DAT
Data input
setup time
100 kHz mode
400 kHz mode
92
TSU:STO
STOP condition
setup time
1 MHz mode (1)
100 kHz mode 2(TOSC)(BRG + 1) §
400 kHz mode 2(TOSC)(BRG + 1) §
1 MHz mode (1) 2(TOSC)(BRG + 1) §
109
TAA
Output valid
from clock
100 kHz mode
400 kHz mode
110
TBUF
Bus free time
1 MHz mode (1)
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
1 MHz mode (1) 2(TOSC)(BRG + 1) §
100 kHz mode
0
400 kHz mode
0
(1)
TBD
*
1 MHz mode
1 MHz mode (1)
D102 ‡
Cb
Bus capacitive loading
* Characterized but not tested.
§
‡
250 *
100 *
TBD *
Conditions
Note 2
Time the bus must be free
before a new transmission
can start
This specification ensured by design. For the value required by the I2C specification, please refer to Figure E-11.
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the parameter # 107 ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter # 102.+ # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 243
PIC17C75X
FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
122
120
TABLE 20-15: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
No.
Sym
120
Characteristic
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Min
Typ†
Max
Units Conditions
PIC17CXXX
—
—
50
PIC17LCXXX
—
—
75 *
ns
ns
ns
121
TckRF
Clock out rise time and fall time PIC17CXXX
(Master Mode)
PIC17LCXXX
—
—
25
—
—
40 *
ns
122
TdtRF
Data out rise time and fall time PIC17CXXX
—
—
25
ns
—
—
40 *
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
PIC17LCXXX
FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
pin
125
RX/DT
pin
126
TABLE 20-16: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
†
Sym
Characteristic
Min
Typ†
Max
125
TdtV2ckL
126
TckL2dtl
Units Conditions
SYNC RCV (MASTER & SLAVE)
Data hold before CK↓ (DT hold time)
15
—
—
ns
Data hold after CK↓ (DT hold time)
15
—
—
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30264A-page 244
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
TABLE 20-17: A/D CONVERTER CHARACTERISTICS:
PIC17LC752/756-08 (COMMERCIAL, INDUSTRIAL)
PIC17C752/756-25 (COMMERCIAL, INDUSTRIAL)
PIC17C752/756-33 (COMMERCIAL, INDUSTRIAL)
Param.
No.
A01
Sym
NR
A02
Characteristic
Resolution
EABS Absolute error
Min
Typ†
—
—
—
—
Max
Units
Conditions
10
bit
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
< ±1
LSb
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
A03
EIL
Integral linearity error
—
—
< ±1
LSb
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
< ±1
LSb
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
A05
EFS
Full scale error
A06
EOFF Offset error
A10
—
Monotonicity
—
—
< ±1
LSb
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
—
—
< ±1
LSb
VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF
—
guaranteed
—
—
0V
—
—
V
A20
VREF Reference voltage
(VREFH - VREFL)
A21
VREFH Reference voltage High
VSS +
3.0V
—
AVDD +
0.3V
V
A22
VREFL Reference voltage Low
AVSS 0.3V
—
AVDD 3.0V
V
VSS 0.3V
—
VREF +
0.3V
V
—
—
10.0
kΩ
A25
VAIN
Analog input voltage
A30
ZAIN
Recommended impedance
of analog voltage source
A40
IAD
A/D conversion 17CXXX
current (VDD)
17LCXXX
—
180
—
µA
—
90
—
µA
VREF input current (Note 2)
10
—
1000
µA
—
—
10
µA
A50
IREF
VSS ≤ VAIN ≤ VREF
Average current consumption when
A/D is on. (Note 1)
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 16.1.
During A/D conversion cycle
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 245
PIC17C75X
FIGURE 20-17: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2) (1)
131
Q4
130
A/D CLK
132
9
A/D DATA
8
...
7
...
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 20-18: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym
Characteristic
130
TAD
A/D clock period
PIC17CXXX
Units
1.6
—
—
µs
Conditions
TOSC based, VREF ≥ 3.0V
3.0
—
—
µs
TOSC based, VREF full range
2.0 *
4.0
6.0 *
µs
A/D RC Mode
PIC17LCXXX
3.0 *
6.0
9.0 *
µs
A/D RC Mode
12 §
—
13 §
TAD
(Note 2)
40
—
µs
10 *
—
—
µs
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
—
Tosc/2 §
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
sleep instruction to be executed.
Conversion time
(not including acquisition time) (Note 1)
132
TACQ
Acquisition time
Q4 to ADCLK start
Max
PIC17LCXXX
TCNV
TGO
Typ†
PIC17CXXX
131
134
Min
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.1 for minimum conditions when input voltage has changed more then 1 LSb.
DS30264A-page 246
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 20-18: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
AD<15:0>
154
data out
addr out
addr out
152
153
TABLE 20-19: MEMORY INTERFACE WRITE REQUIREMENTS
Param.
No.
150
Sym
Characteristic
TadV2alL
AD<15:0> (address) valid to
ALE↓ (address setup time)
Min
Typ†
Max
PIC17CXXX
0.25Tcy - 10
—
—
PIC17LCXXX
TBD
—
—
Units Conditions
ns
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
152
TadV2wrL
Data out valid to WR↓
PIC17CXXX
0
—
—
PIC17LCXXX
TBD
—
—
PIC17CXXX
0.25Tcy - 40
—
—
PIC17LCXXX
TBD
—
—
ns
ns
(data setup time)
153
TwrH2adI
PIC17CXXX
—
0.25TCY §
—
(data hold time)
WR↑ to data out invalid
PIC17LCXXX
—
TBD
—
WR pulse width
PIC17CXXX
—
0.25TCY §
—
PIC17LCXXX
—
TBD
—
ns
154
TwrL
ns
*
†
§
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 247
PIC17C75X
FIGURE 20-19: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
164
168
160
OE
165
AD<15:0>
Addr out
162
150
WR
161
Data in
Addr out
151
163
167
'1'
'1'
TABLE 20-20: MEMORY INTERFACE READ REQUIREMENTS
Param.
No.
Sym
150
TadV2alL
Characteristic
Min
Typ†
Max
AD15:AD0 (address) valid to
PIC17CXXX
0.25Tcy - 10
—
—
ALE↓ (address setup time)
PIC17LCXXX
TBD
—
—
Units Conditions
ns
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
160
TadZ2oeL AD15:AD0 hi-impedance to
PIC17CXXX
5*
—
—
PIC17LCXXX
TBD
—
—
PIC17CXXX
0*
—
—
PIC17LCXXX
TBD
—
—
ns
ns
OE↓
161
ToeH2adD OE↑ to AD15:AD0 driven
PIC17CXXX
0.25Tcy - 15
—
—
PIC17LCXXX
TBD
—
—
PIC17CXXX
35
—
—
PIC17LCXXX
TBD
—
—
PIC17CXXX
0
—
—
PIC17LCXXX
TBD
—
—
ns
162
TadV2oeH Data in valid before OE↑
ns
(data setup time)
163
ToeH2adI
OE↑to data in invalid
ns
(data hold time)
164
165
TalH
ToeL
ALE pulse width
OE pulse width
PIC17CXXX
—
0.25TCY §
—
PIC17LCXXX
—
TBD
—
PIC17CXXX
0.5Tcy - 35 §
—
—
PIC17LCXXX
TBD
—
—
PIC17CXXX
—
TCY §
—
PIC17LCXXX
—
TBD
—
ns
ns
166
167
168
TalH2alH
Tacc
Toe
ALE↑ to ALE↑(cycle time)
Address access time
Output enable access time
PIC17CXXX
—
—
0.75TCY - 30
PIC17LCXXX
—
—
TBD
PIC17CXXX
—
—
0.5TCY - 45
PIC17LCXXX
—
—
TBD
ns
ns
ns
(OE low to Data Valid)
*
†
§
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
DS30264A-page 248
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
21.0
PIC17C752/756 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some
graphs or tables the data presented is outside specified operating range (e.g. outside specified VDD range). This is for
information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 21-1:
PIN CAPACITANCE PER PACKAGE TYPE
Pin Name
64-pin DIP
All pins, except MCLR, VDD, and VSS
MCLR pin
Typical Capacitance (pF)
68-pin PLCC
64-pin TQFP
10
20
10
20
10
20
FIGURE 21-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25°C)
Frequency normalized to +25°C
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 249
PIC17C75X
FIGURE 21-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
FOSC (MHz)
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
6.0
6.5
VDD (Volts)
FIGURE 21-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
FOSC (MHz)
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
VDD (Volts)
DS30264A-page 250
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 21-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
R = 3.3k
FOSC (MHz)
1.2
R = 5.1k
1.0
0.8
R = 10k
0.6
0.4
Cext = 300 pF, T = 25°C
0.2
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 21-2:
RC OSCILLATOR FREQUENCIES
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
160k
100 pF
300 pF
1997 Microchip Technology Inc.
Average
Fosc @ 5V, 25°C
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
Preliminary
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
DS30264A-page 251
PIC17C75X
FIGURE 21-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
gm(µA/V)
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.5
5.0
6.0
VDD (Volts)
FIGURE 21-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
Typ @ 25°C
gm(mA/V)
12
10
8
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30264A-page 252
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 21-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
IDD (µA)
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
100
4.0V
10
10k
100k
1M
External Clock Frequency (Hz)
10M
100M
FIGURE 21-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
IDD (µA)
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
100
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 253
PIC17C75X
FIGURE 21-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
IPD(nA)
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
IPD(nA)
FIGURE 21-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
4.0
4.5
5.0
5.5
6.0
Temp. = -40°C
6.5
7.0
VDD (Volts)
DS30264A-page 254
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 21-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
IPD(µA)
20
15
10
5
0
4.0
4.5
5.0
5.5
6.5
6.0
7.0
VDD (Volts)
FIGURE 21-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
-40°C
70°C
IPD(µA)
40
0°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 255
PIC17C75X
FIGURE 21-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
WDT Period (ms)
20
Max. 70°C
Min. 0°C
15
Typ. 25°C
10
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.5
3.0
VDD (Volts)
FIGURE 21-14: IOH vs. VOH, VDD = 3V
0
-2
IOH(mA)
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
VOH (Volts)
DS30264A-page 256
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 21-15: IOH vs. VOH, VDD = 5V
0
-5
-10
IOH(mA)
Min @ 85°C
-15
-20
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
FIGURE 21-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
Typ. 25°C
IOL(mA)
20
15
Min. +85°C
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 257
PIC17C75X
FIGURE 21-17: IOL vs. VOL, VDD = 5V
90
80
70
IOL(mA)
Max @ -40°C
Typ @ 25°C
60
50
Min @ +85°C
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
FIGURE 21-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
VTH(Volts)
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30264A-page 258
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE 21-19: VIH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
VIH, max (-40°C to +85°C)
4.5
VIH, typ (25°C)
4.0
VIH, min (-40°C to +85°C)
VIH, VIL(Volts)
3.5
3.0
VIL, max (-40°C to +85°C)
2.5
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 21-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
VTH,(Volts)
2.8
2.6
2.4
2.2
2.0
Min (-40°C to +85°C)
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 259
PIC17C75X
NOTES:
DS30264A-page 260
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
22.0
PACKAGING INFORMATION
22.1
64-Lead Plastic Surface Mount (TQFP 10x10x1 mm Body 1.0/0.10 mm Lead Form)
D1
D
D/2
e/2
A
E1
E
A
DETAIL A
e
E/2
See Detail A
8 Places
11/13°
0° min.
A
See Detail B
A2
Datum Plane
0.25
b
with Lead Finish
0.09/0.20
0.08
R min.
A1
0-7°
Gauge Plane
0.20 min.
0.09/0.16
L
1.00 ref.
b1
Base Metal
DETAIL B
Package Group: Plastic TQFP
Millimeters
Inches
Symbol
Min
Nominal
Max
Min
α
A
A1
A2
b
b1
D
D1
E
E1
e
L
N
0°
0.05
0.95
0.17
0.17
0.45
-
0.10
1.00
0.22
0.20
12.00
10.00
12.00
10.00
0.50
0.60
64
7°
1.20
0.15
1.05
0.27
0.23
0.75
-
0°
1997 Microchip Technology Inc.
Nominal
Max
7°
64
DS30264A-page 261
PIC17C75X
22.2
64-Lead Plastic Dual In-line (750 mil)
N
α
E1 E
C
eA
eB
Pin No. 1
Indicator Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
α
0°
15°
0°
15°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.51
3.38
0.38
.076
0.20
57.40
55.12
19.05
16.76
1.73
19.05
19.05
3.05
64
1.19
0.686
5.08
–
4.27
0.56
1.27
0.30
57.91
55.12
19.69
17.27
1.83
19.05
21.08
3.43
64
–
–
–
0.020
0.133
0.015
0.030
0.008
2.260
2.170
0.750
0.660
0.068
0.750
0.750
0.120
64
0.047
0.027
0.200
–
0.168
0.022
0.050
0.012
2.280
2.170
0.775
0.680
0.072
0.750
0.830
0.135
64
–
–
DS30264A-page 262
Max
Inches
Notes
Typical
Typical
Reference
Typical
Reference
Min
Max
Notes
Typical
Typical
Reference
Typical
Reference
1997 Microchip Technology Inc.
PIC17C75X
22.3
68-Lead Plastic Leaded Chip Carrier (Square)
D
-A-
D1
-D-
3
-F-
0.812/0.661 N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007 S B D-E S
-HA
A1
3
D3/E3
D2
0.38
.015
3
-G-
8
F-G S
0.177
.007 S B A S
2 Sides
9
0.101 Seating
.004 Plane
D
-C-
4
E2
E1
E
0.38
.015
F-G S
4
-B-
3
-E-
0.177
.007 S A F-G S
10
0.254
.010 Max
2
0.254
.010 Max
11
-H-
11
0.508
.020
0.508
.020
-H-
2
0.812/0.661
3
.032/.026
1.524
.060 Min
6
6
-C1.651
.065
1.651
.065
R 1.14/0.64
.045/.025
R 1.14/0.64
.045/.025
5
0.533/0.331
.021/.013
0.64 Min
.025
0.177
, D-E S
.007 M A F-G S
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol
Min
Max
A
4.191
A1
D
D1
D2
D3
E
E1
E2
E3
N
CP
LT
2.286
25.019
24.130
22.860
20.320
25.019
24.130
22.860
20.320
68
0.203
1997 Microchip Technology Inc.
Inches
Notes
Min
Max
4.699
0.165
0.185
2.794
25.273
24.334
23.622
25.273
24.334
23.622
0.102
0.254
0.090
0.985
0.950
0.900
0.800
0.985
0.950
0.900
0.800
68
0.008
0.110
0.995
0.958
0.930
0.995
0.958
0.930
0.004
0.010
Reference
Reference
Notes
Reference
Reference
DS30264A-page 263
PIC17C75X
22.4
Package Marking Information
68-Lead CERQUAD Windowed
MMMMMMMMMMMMMMMMM
Example
PIC17C756-04/CL
9750CAE
AABBCDE
64-Lead TQFP
Example
MMMMMMMMMM
MMMMMMM
PIC17C752
-08I/PT
AABBCDE
9717CAE
68-Lead PLCC
Example
MMMMMMMMMM
MMMMMMM
PIC17C756
-08/L
AABBCDE
9748CAE
64-Lead SDIP (Shrink DIP)
Example
MMMMMMMMMMMMMMMMM
PIC17C752-04I/SP
AABBCDE
9736CAE
Legend:
MM...M
XX...X
AA
BB
C
D1
E
Note:
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30264A-page 264
1997 Microchip Technology Inc.
PIC17C75X
APPENDIX A: MODIFICATIONS
APPENDIX B: COMPATIBILITY
The following is the list of modifications over the
PIC16CXX microcontroller family:
To convert code written for PIC16CXXX to
PIC17CXXX, the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
Instruction word length is increased to 16-bit.
This allows larger page sizes both in program
memory (8 Kwords verses 2 Kwords) and register file (256 bytes versus 128 bytes).
Four modes of operation: microcontroller, protected microcontroller, extended microcontroller,
and microprocessor.
22 new instructions.
The MOVF, TRIS and OPTION instructions have
been removed.
Four new instructions (TLRD, TLWT, TABLRD,
TABLWT) for transferring data between data
memory and program memory. They can be
used to “self program” the EPROM program
memory.
Single cycle data memory to data memory transfers possible (MOVPF and MOVFP instructions).
These instructions do not affect the Working
register (WREG).
W register (WREG) is now directly addressable.
A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
Data memory paging is redefined slightly.
DDR registers replaces function of TRIS registers.
Multiple Interrupt vectors added. This can
decrease the latency for servicing interrupts.
Stack size is increased to 16 deep.
BSR register for data memory paging.
Wake up from SLEEP operates slightly differently.
The Oscillator Start-Up Timer (OST) and
Power-Up Timer (PWRT) operate in parallel and
not in series.
PORTB interrupt on change feature works on all
eight port pins.
TMR0 is 16-bit plus 8-bit prescaler.
Second indirect addressing register added
(FSR1 and FSR2). Configuration bits can select
the FSR registers to auto-increment, auto-decrement, remain unchanged after an indirect
address.
Hardware multiplier added (8 x 8 → 16-bit)
Peripheral modules operate slightly differently.
A/D has both a VREF+ and VREF-.
USARTs do not implement BRGH feature.
Oscillator modes slightly redefined.
Control/Status bits and registers have been
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
In-circuit serial programming is implemented differently.
1997 Microchip Technology Inc.
Remove any TRIS and OPTION instructions, and
implement the equivalent code.
Separate the interrupt service routine into its
four vectors.
Replace:
MOVF
REG1, W
with:
MOVFP
REG1, WREG
Replace:
MOVF
REG1, W
MOVWF
REG2
with:
MOVPF
REG1, REG2 ; Addr(REG1)<20h
or
MOVFP
REG1, REG2 ; Addr(REG2)<20h
2.
3.
4.
Note:
5.
6.
7.
8.
9.
If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
MOVFP
REG1, WREG ;
MOVPF
WREG, REG2 ;
Ensure that all bit names and register names
are updated to new data memory map locations.
Verify data memory banking.
Verify mode of operation for indirect addressing.
Verify peripheral routines for compatibility.
Weak pull-ups are enabled on reset.
To convert code from the PIC17C42 to all the other
PIC17CXXX devices, the user should take the following
steps.
1.
2.
3.
Preliminary
If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
The disabling of global interrupts has been
enhanced so there is no additional testing of the
GLINTD bit after a BSF CPUSTA, GLINTD
instruction.
DS30264A-page 265
PIC17C75X
APPENDIX C: WHAT’S NEW
This is the first revision of the Data Sheet .
Nothing new at this time.
DS30264A-page 266
APPENDIX D: WHAT’S CHANGED
This is the first revision of the Data Sheet .
Nothing new at this time.
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
APPENDIX E: I 2C OVERVIEW
This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 15.2 discussing
the operation of the SSP module in I 2C mode.
The I 2C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. This device will communicate with fast mode
devices if attached to the same bus.
The I 2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hardware, including general call support. Table E-1 defines
some of the I 2C bus terminology. For additional information on the I 2C interface specification, refer to the
Philips document “The I 2C bus and how to use it.”
#939839340011, which can be obtained from the Philips Corporation.
In the I 2C interface protocol each device has an
address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in either
of these two relations:
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The number of devices that may be attached to the I 2C bus is
limited only by the maximum bus loading specification
of 400 pF.
E.1
Initiating and Terminating Data
Transfer
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure E-1 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data transfer. Due to the definition of the START and STOP conditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE E-1:
START AND STOP
CONDITIONS
SDA
SCL
S
Start
Condition
P
Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
TABLE E-1:
I2C BUS TERMINOLOGY
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 267
PIC17C75X
ADDRESSING I 2C DEVICES
E.2
FIGURE E-4:
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure E-2). The
more complex is the 10-bit address with a R/W bit
(Figure E-3). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
FIGURE E-2:
Data
Output by
Receiver
9
8
S
Start
Condition
Clock Pulse for
Acknowledgment
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
Sent by
Slave
Start Condition
Read/Write pulse
Acknowledge
I2C 10-BIT ADDRESS
FORMAT
FIGURE E-3:
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state technique can also be implemented at the bit level,
Figure E-5. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the CKP bit to enable clock
stretching when it is a receiver.
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
E.3
acknowledge
2
1
R/W ACK
slave address
S
R/W
ACK
not acknowledge
SCL from
Master
LSb
S
S
R/W
ACK
Data
Output by
Transmitter
7-BIT ADDRESS FORMAT
MSb
SLAVE-RECEIVER
ACKNOWLEDGE
- Start Condition
- Read/Write Pulse
- Acknowledge
Transfer Acknowledge
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowledge bit (ACK) (Figure E-4). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure E-1).
FIGURE E-5:
DATA TRANSFER WAIT STATE
SDA
MSB
acknowledgment
signal from receiver
byte complete
interrupt with receiver
acknowledgment
signal from receiver
clock line held low while
interrupts are serviced
SCL
S
Start
Condition
DS30264A-page 268
1
2
Address
7
8
9
R/W
ACK
1
Wait
State
Preliminary
2
Data
3•8
9
ACK
P
Stop
Condition
1997 Microchip Technology Inc.
PIC17C75X
SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure E-8.
Figure E-6 and Figure E-7 show Master-transmitter
and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while
FIGURE E-6:
MASTER-TRANSMITTER SEQUENCE
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
Second byte
First 7 bits
For 7-bit address:
S Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
FIGURE E-7:
(write)
Data A
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A master transmitter addresses a slave receiver
with a 10-bit address.
MASTER-RECEIVER SEQUENCE
For 10-bit address:
For 7-bit address:
S Slave Address R/W A1 Slave Address A2
Second byte
First 7 bits
S Slave Address R/W A Data A Data A P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
From master to slave
From slave to master
FIGURE E-8:
Data A/A P
(write)
Sr Slave Address R/W A3 Data A
First 7 bits
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Data A P
(read)
A master transmitter addresses a slave receiver
with a 10-bit address.
COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
(read)
Sr = repeated
Start Condition
(write)
Direction of transfer
may change at this point
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
Sr Slave Address R/W A Slave Address A Data A
First 7 bits
Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
From master to slave
From slave to master
1997 Microchip Technology Inc.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Preliminary
DS30264A-page 269
PIC17C75X
E.4
Multi-master
E.5
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
E.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure E-9), and turns off its data output stage. A master which lost arbitration can generate clock pulses until
the end of the data byte where it lost arbitration. When
the master devices are addressing the same device,
arbitration continues into the data.
FIGURE E-9:
MULTI-MASTER
ARBITRATION
(TWO MASTERS)
Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait-state, until the SCL line comes high. When
the SCL line comes high, all devices start counting off
their high periods. The first device to complete its high
period will pull the SCL line low. The SCL line high time
is determined by the device with the shortest high
period, Figure E-10.
FIGURE E-10: CLOCK SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1 SDA
wait
state
DATA 1
DATA 2
start counting
HIGH period
CLK
1
SDA
CLK
2
SCL
counter
reset
SCL
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning master-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
E.6
I2C Timing Specifications
Table E-2 (Figure E-11) and Table E-3 (Figure E-12)
show the timing specifications as required by the Philips specification for I2C. For additional information
please refer to to Section 15.2 and Section 20.5.
Care needs to be taken to ensure that these conditions
do not occur.
DS30264A-page 270
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE E-11: I2C BUS START/STOP BITS TIMING SPECIFICATION
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
TABLE E-2:
I2C BUS START/STOP BITS TIMING SPECIFICATION
Microchip
Parameter
No.
Sym
90
TSU:STA
91
THD:STA
92
TSU:STO
93
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
1997 Microchip Technology Inc.
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000 ‡
600 ‡
Preliminary
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated
START condition
ns
After this period the first clock
pulse is generated
ns
ns
DS30264A-page 271
PIC17C75X
FIGURE E-12: I2C BUS DATA TIMING SPECIFICATION
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
TABLE E-3:
I2C BUS DATA TIMING SPECIFICATION
Microchip
Parameter
No.
Sym
Characteristic
100
THIGH
Clock high time
101
TLOW
Clock low time
102
TR
103
TF
Min
Max
Units
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.0
0.6
4.7
1.3
—
20 + 0.1Cb
—
—
—
—
1000
300
µs
µs
µs
µs
ns
ns
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
1000
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
SDA and SCL rise
time
90
TSU:STA
START condition
setup time
91
THD:STA
START condition hold
time
106
THD:DAT
Data input hold time
107
TSU:DAT
Data input setup time
92
TSU:STO
STOP condition setup
time
109
TAA
Output valid from
clock
110
TBUF
Bus free time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Conditions
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission
can start
D102
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
DS30264A-page 272
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
APPENDIX F: STATUS AND CONTROL REGISTERS
FIGURE F-1:
PIC17C75X REGISTER FILE MAP
Addr Unbanked
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Fh
Bank 1 (1)
Bank 2 (1)
Bank 3 (1)
Bank 4 (1)
Bank 5 (1)
Bank 6 (1)
Bank 7 (1)
PORTA
DDRC
TMR1
PW1DCL
PIR2
DDRF
SSPADD
PW3DCL
DDRB
PORTC
TMR2
PW2DCL
PIE2
PORTF
SSPCON1
PW3DCH
PORTB
DDRD
TMR3L
PW1DCH
—
DDRG
SSPCON2
CA3L
RCSTA1
PORTD
TMR3H
PW2DCH
RCSTA2
PORTG
SSPSTAT
CA3H
RCREG1
DDRE
PR1
CA2L
RCREG2
ADCON0
SSPBUF
CA4L
TXSTA1
PORTE
PR2
CA2H
TXSTA2
ADCON1
—
CA4H
TXREG1
PIR1
PR3L/CA1L
TCON1
TXREG2
ADRESL
—
TCON3
SPBRG1
PIE1
PR3H/CA1H
TCON2
SPBRG2
ADRESH
—
—
Unbanked
PRODL
PRODH
General
Purpose
RAM
Bank 0 (2)
Bank 1 (2) Bank 2 (2, 3) Bank 3 (2, 3)
20h
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
‘0’s.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 273
PIC17C75X
FIGURE F-2:
ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1
FS3
FS2
FS1
FS0
bit7
R/W - x
OV
R/W - x
Z
R/W - x
DC
R/W - x
C
bit0
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
bit 2:
bit 1:
bit 0:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
C: carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the most significant bit of the result occurred
Note that a subtraction is executed by adding the two’s complement of the second operand. For
rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source
register.
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
DS30264A-page 274
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-3:
R/W - 0
INTEDG
bit7
bit 7:
bit 6:
bit 5:
T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0
T0SE
R/W - 0
T0CS
R/W - 0
PS3
R/W - 0
T0PS2
R/W - 0
T0PS1
R/W - 0
T0PS0
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
-n = Value at POR reset
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1 (Internal Clock)
Don’t care
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
bit 0:
Prescale Value
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Unimplemented: Read as '0'
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 275
PIC17C75X
FIGURE F-4:
U-0
—
bit7
CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U-0
—
R-1
R/W - 1
STKAV GLINTD
R-1
TO
R-1
PD
R/W - 0
POR
bit 7-6: Unimplemented: Read as '0'
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n = Value at POR reset
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDT instruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software after a Brown-out Reset occurs)
DS30264A-page 276
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-5:
R-0
PEIF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 277
PIC17C75X
FIGURE F-6:
PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
bit7
bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
R = Readable bit
W = Writable bit
-n = Value at POR reset
TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
DS30264A-page 278
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-7:
PIE2 REGISTER (ADDRESS: 11h, BANK 4)
R/W - 0 R/W - 0
SSPIE BCLIE
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
ADIE
U-0
—
R/W - 0
CA4IE
R/W - 0
CA3IE
R/W - 0
TX2IE
SSPIE: Synchronous Serial Port Interrupt Enable
1 = Enable SSP Interrupt
0 = Disable SSP Interrupt
R/W - 0
RC2IE
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
ADIE: A/D Module Interrupt Enable
1 = Enable A/D Module Interrupt
0 = Disable A/D Module Interrupt
Unimplemented: Read as ‘0’
CA4IE: Capture4 Interrupt Enable
1 = Enable Capture4 Interrupt
0 = Disable Capture4 Interrupt
CA3IE: Capture3 Interrupt Enable
1 = Enable Capture3 Interrupt
0 = Disable Capture3 Interrupt
TX2IE: USART2 Transmit Interrupt Enable
1 = Enable USART2 Transmit Interrupt
0 = Disable USART2 Transmit Interrupt
RC2IE: USART2 Receive Interrupt Enable
1 = Enable USART2 Receive Interrupt
0 = Disable USART2 Receive Interrupt
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 279
PIC17C75X
FIGURE F-8:
PIR1 REGISTER (ADDRESS: 16h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF TX1IF RC1IF
bit7
bit0
bit 7:
bit 6:
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (software must end the mismatch condition)
0 = None of the PORTB inputs have changed
TMR3IF: TMR3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = TMR3 overflowed
0 = TMR3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
bit 4:
TMR2IF: TMR2 Interrupt Flag bit
1 = TMR2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: TMR1 Interrupt Flag bit
If TMR1 is in 8-bit mode (T16 = 0)
1 = TMR1 value has rolled over to 0000h from equalling the period register (PR1) value
0 = TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1) value
0 = TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1) value
bit 3:
bit 2:
bit 1:
bit 0:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
TX1IF: USART1 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART1 Transmit buffer is empty
0 = USART1 Transmit buffer is full
RC1IF: USART1 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART1 Receive buffer is full
0 = USART1 Receive buffer is empty
DS30264A-page 280
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-9:
PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W - 0 R/W - 0
SSPIF BCLIF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W - 0
ADIF
U-0
—
R/W - 0
CA4IF
R/W - 0
CA3IF
R/W - 1
TX2IF
R/W - 0
RC2IF
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occured, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave / Master
A transmission/reception has taken place.
I2C Master
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = An SSP interrupt condition has occurred.
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I2C master mode
0 = No bus collision has occurred
ADIF: A/D Module Interrupt Flag
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
CA3IF: Capture3 Interrupt Flag
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 281
PIC17C75X
FIGURE F-10: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC
TX9
TXEN
SYNC
bit7
bit 7:
bit 6:
bit 5:
bit 4:
U-0
—
U-0
—
R-1
TRMT
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
R/W - x
TX9D
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
TX9: 9-bit Transmit Select bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2: Unimplemented: Read as '0'
bit 1:
bit 0:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
DS30264A-page 282
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-11: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
RX9
SREN
CREN
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
R- 0
FERR
R-0
OERR
R-x
RX9D
bit 0
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 283
PIC17C75X
FIGURE F-12: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
bit 2:
bit 1:
bit 0:
T16: Timer2:Timer1 Mode Select bit
1 = Timer2 and Timer1 form a 16-bit timer
0 = Timer2 and Timer1 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
DS30264A-page 284
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-13: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R-0
R-0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA1H:PR3L/CA1L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
PWM2ON: PWM2 On bit
1 = PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
PWM1ON: PWM1 On bit
1 = PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without
a period register)
0 = Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer (T16 is
set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit TMR2:TMR1
0 = Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 285
PIC17C75X
FIGURE F-14: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
U-0
bit7
bit 7:
bit 6:
bit 5:
R-0
R-0
CA4OVF CA3OVF
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
bit0
Unimplemented: Read as ‘0’
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
-n = Value at POR reset
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 0:
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
DS30264A-page 286
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-15: ADCON0 REGISTER (ADDRESS: 14h, BANK 5)
R/W-0
CHS3
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
U-0
—
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
bit 7-4: CHS2:CHS0: Analog Channel Select bits
0000 = channel 0, (AN0)
0001 = channel 1, (AN1)
0010 = channel 2, (AN2)
0011 = channel 3, (AN3)
0100 = channel 4, (AN4)
0101 = channel 5, (AN5)
0110 = channel 6, (AN6)
0111 = channel 7, (AN7)
1000 = channel 8, (AN8)
1001 = channel 9, (AN9)
1010 = channel 10, (AN10)
1011 = channel 11, (AN11)
11xx = RESERVED, do not select
bit 3:
bit 2:
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Unimplemented: Read as '0'
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared
by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 287
PIC17C75X
FIGURE F-16: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
ADFM
U-0
—
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/8
01 = FOSC/32
10 = FOSC/64
11 = FRC (clock derived from an internal RC oscillation)
bit 5:
bit 4:
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n = Value at POR reset
ADFM: A/D Result format select
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
Unimplemented: Read as '0'
bit 3-0: PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG3:PCFG1 AN11 AN10 AN9
000
001
010
011
100
101
110
111
A
A
A
A
A
D
D
D
A = Analog input
bit 0:
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
AN8
AN7
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
AN6 AN5
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
AN4
A
A
A
A
D
D
D
D
AN3 AN2 AN1 AN0
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
D = Digital I/O
PCFG0: A/D Voltage Reference Select bit
1 = A/D reference is the VREF+ and VREF- pins
0 = A/D reference is AVDD and AVSS
Note:When this bit is set, ensure that the A/D voltage reference specifications are met.
DS30264A-page 288
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-17: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
R/W-0 R/W-0
SMP
CKE
R-0
R-0
R-0
R-0
R-0
R-0
D/A
P
S
R/W
UA
BF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 15-8, Figure 15-11, and Figure 15-12)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I2C slave mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress. Or’ing this bit with SAE, RCE, SPE, or AKE will indicate if the SSP is in
IDLE mode.
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include ACK and stop bits), SSPBUF is empty
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 289
PIC17C75X
FIGURE F-18: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 11h, BANK 6)
R/W-0
WCOL
bit7
bit 7:
bit 6:
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is
not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1 = Reserved
1x1x = Reserved
DS30264A-page 290
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
FIGURE F-19: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
GCEN
R-0
R/W-0
ACKSTAT ACKDT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACKEN
RCEN
PEN
RSEN
SEN
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n =Value at POR reset
GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address is received in the SSPSR.
0 = General call address disabled.
ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKD data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 3:
RCEN: Receive enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C
0 = Receive idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 2:
PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled).
bit 1:
RSEN: Restart Condition Enabled bit (In I2C master mode only)
1 = Initiate Restart condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Restart condition idle.
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled)
bit 0:
SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF
may not be written (or writes to the SSPBUF are disabled)
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 291
PIC17C75X
NOTES:
DS30264A-page 292
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
APPENDIX G: PIC16/17 MICROCONTROLLERS
G.1
PIC12CXXX Family of Devices
PIC12C509
PIC12C508
Clock
Memory
Peripherals
Features
4
PIC12C671
4
PIC12C672
Maximum Frequency
of Operation (MHz)
4
4
EPROM Program Memory
512 x 12
1024 x 12
1024 x 14
2048 x 14
Data Memory (bytes)
25
41
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
A/D Converter (8-bit) Channels
—
—
4
4
Wake-up from SLEEP on
pin change
Yes
Yes
Yes
Yes
I/O Pins
5
5
5
5
Input Pins
1
1
1
1
Internal Pull-ups
Yes
Yes
Yes
Yes
Voltage Range (Volts)
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Number of Instructions
33
33
35
35
Packages
8-pin DIP, SOIC
8-pin DIP, SOIC
8-pin DIP, SOIC
8-pin DIP, SOIC
All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0.
G.2
PIC14C000 Family of Devices
PIC14C000
Clock
Memory
Peripherals
Features
Maximum Frequency of Operation (MHz)
20
EPROM Program Memory (x14 words)
4K
Data Memory (bytes)
192
Timer Module(s)
TMR0
ADTMR
Serial Port(s)
(SPI/I2C, USART)
I2C with SMBus
Support
Slope A/D Converter Channels
8 External; 6 Internal
Interrupt Sources
11
I/O Pins
22
Voltage Range (Volts)
2.7-6.0
In-Circuit Serial Programming
Yes
Additional On-chip Features
Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor,
Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE,
Comparators with Programmable References (2)
Packages
28-pin DIP (.300 mil), SOIC, SSOP
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 293
PIC17C75X
G.3
PIC16C15X Family of Devices
PIC16C154
Clock
Memory
PIC16C156
PIC16CR156
PIC16C158
PIC16CR158
20
20
20
20
20
20
EPROM Program Memory
(x12 words)
512
—
1K
—
2K
—
ROM Program Memory
(x12 words)
—
512
—
1K
—
2K
73
RAM Data Memory (bytes) 25
25
25
25
73
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
12
12
12
12
Voltage Range (Volts)
3.0-5.5
2.5-5.5
3.0-5.5
2.5-5.5
3.0-5.5
2.5-5.5
Number of Instructions
33
33
33
33
33
33
Packages
18-pin DIP, 18-pin DIP,
18-pin DIP, 18-pin DIP,
18-pin DIP,
18-pin DIP,
SOIC;
SOIC;
SOIC;
SOIC;
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
Peripherals Timer Module(s)
Features
PIC16CR154
Maximum Frequency
of Operation (MHz)
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability.
DS30264A-page 294
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
G.4
PIC16C5X Family of Devices
PIC16C52
Clock
Memory
PIC16C54A
Memory
PIC16C56
20
20
20
20
EPROM Program Memory
(x12 words)
384
512
512
—
512
1K
ROM Program Memory
(x12 words)
—
—
—
512
—
—
RAM Data Memory (bytes)
25
25
25
25
24
25
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
12
12
20
12
Voltage Range (Volts)
2.5-6.25
2.5-6.25
2.0-6.25
2.0-6.25
2.5-6.25
2.5-6.25
Number of Instructions
33
33
33
33
33
33
Packages
18-pin DIP, 18-pin DIP,
18-pin DIP,
18-pin DIP,
SOIC
SOIC;
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP 20-pin SSOP
28-pin DIP,
SOIC,
SSOP
18-pin DIP,
SOIC;
20-pin SSOP
PIC16CR57B
PIC16C58A
PIC16CR58A
Maximum Frequency
of Operation (MHz)
20
20
20
20
EPROM Program Memory
(x12 words)
2K
—
2K
—
ROM Program Memory
(x12 words)
—
2K
—
2K
RAM Data Memory (bytes)
72
72
73
73
Peripherals Timer Module(s)
I/O Pins
Features
PIC16C55
20
PIC16C57
Clock
PIC16CR54A
4
Peripherals Timer Module(s)
Features
PIC16C54
Maximum Frequency
of Operation (MHz)
TMR0
TMR0
TMR0
TMR0
20
20
12
12
Voltage Range (Volts)
2.5-6.25
2.5-6.25
2.0-6.25
2.5-6.25
Number of Instructions
33
33
33
33
Packages
28-pin DIP,
SOIC,
SSOP
28-pin DIP, SOIC,
SSOP
18-pin DIP, SOIC; 18-pin DIP, SOIC;
20-pin SSOP
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and
high I/O current capability.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 295
PIC17C75X
G.5
PIC16C55X Family of Devices
PIC16C556(1)
PIC16C554
Clock
Memory
20
20
20
EPROM Program Memory (x14 words)
512
1K
2K
Data Memory (bytes)
80
80
128
Timer Module(s)
TMR0
TMR0
TMR0
—
—
—
—
—
—
Interrupt Sources
3
3
3
I/O Pins
13
13
13
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
Peripherals Comparators(s)
Internal Reference Voltage
Features
PIC16C558
Maximum Frequency of Operation (MHz)
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
G.6
PIC16C62X and PIC16C64X Family of Devices
PIC16C621
PIC16C620
Clock
Memory
PIC16C642
PIC16C662
20
20
20
20
20
EPROM Program Memory
(x14 words)
512
1K
2K
4K
4K
Data Memory (bytes)
80
80
128
176
176
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
2
2
2
2
2
Peripherals Comparators(s)
Features
PIC16C622
Maximum Frequency
of Operation (MHz)
Internal Reference Voltage
Yes
Yes
Yes
Yes
Yes
Interrupt Sources
4
4
4
4
5
I/O Pins
13
13
13
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
3.0-6.0
3.0-6.0
Brown-out Reset
Yes
Yes
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin PDIP,
SOIC,
Windowed
CDIP
40-pin PDIP,
Windowed
CDIP;
44-pin PLCC,
MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30264A-page 296
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
G.7
PIC16C6X Family of Devices
PIC16C62A
PIC16C61
PIC16CR62
PIC16C63
PIC16CR63
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
EPROM Program Memory
(x14 words)
1K
2K
—
4K
—
ROM Program Memory
(x14 words)
—
—
2K
—
4K
Data Memory (bytes)
36
128
128
192
192
Timer Module(s)
TMR0
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
Peripherals PWM Module(s)
—
1
1
2
2
Serial Port(s)
(SPI/I2C, USART)
—
SPI/I2C
SPI/I2C
SPI/I2C,
USART
SPI/I2C
USART
Parallel Slave Port
—
—
—
—
—
Clock
Memory
Features
Interrupt Sources
3
7
7
10
10
I/O Pins
13
22
22
22
22
Voltage Range (Volts)
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
—
Yes
Packages
18-pin DIP, SO 28-pin SDIP,
SOIC, SSOP
Memory
Yes
28-pin SDIP,
SOIC
PIC16C65A
PIC16CR65
Maximum Frequency
of Operation (MHz)
20
20
20
20
EPROM Program Memory
(x14 words)
2K
—
4K
—
ROM Program Memory (x14 words)
—
2K
—
4K
Data Memory (bytes)
128
128
192
192
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Peripherals Capture/Compare/PWM Module(s)
Features
Yes
28-pin SDIP,
SOIC
PIC16CR64
PIC16C64A
Clock
Yes
28-pin SDIP,
SOIC, SSOP
1
1
2
2
Serial Port(s) (SPI/I2C, USART)
SPI/I2C
SPI/I2C
SPI/I2C, USART
SPI/I2C, USART
Parallel Slave Port
Yes
Yes
Yes
Yes
Interrupt Sources
8
8
11
11
I/O Pins
33
33
33
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
Yes
Yes
Yes
Packages
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 297
PIC17C75X
G.8
PIC16C7XX Family of Devces
PIC16C710
Clock
Memory
PIC16C71
PIC16C711
PIC16C715
PIC16C72
PIC16CR72(1)
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
20
EPROM Program Memory
(x14 words)
512
1K
1K
2K
2K
—
ROM Program Memory
(14K words)
2K
Data Memory (bytes)
36
36
68
128
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
Peripherals PWM Module(s)
—
—
—
—
1
1
Serial Port(s)
(SPI/I2C, USART)
—
—
—
—
SPI/I2C
SPI/I2C
Parallel Slave Port
—
—
—
—
—
—
Features
A/D Converter (8-bit) Channels 4
4
4
4
5
5
Interrupt Sources
4
4
4
4
8
8
I/O Pins
13
13
13
13
22
22
Voltage Range (Volts)
3.0-6.0
3.0-6.0
3.0-6.0
3.0-5.5
2.5-6.0
3.0-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
—
Yes
Yes
Yes
Yes
Packages
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC;
SOIC
SOIC;
SOIC;
SOIC, SSOP SOIC, SSOP
20-pin SSOP
20-pin SSOP 20-pin SSOP
PIC16C74A
PIC16C73A
Clock
Memory
Maximum Frequency of Operation (MHz)
20
20
EPROM Program Memory (x14 words)
4K
4K
Data Memory (bytes)
192
192
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Peripherals Capture/Compare/PWM Module(s)
Features
2
2
Serial Port(s) (SPI/I2C, USART)
SPI/I2C, USART
SPI/I2C, USART
Parallel Slave Port
—
Yes
A/D Converter (8-bit) Channels
5
8
Interrupt Sources
11
12
I/O Pins
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Brown-out Reset
Yes
Yes
Packages
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP,
TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
DS30264A-page 298
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
G.9
PIC16C8X Family of Devices
PIC16CR83
PIC16F83
Clock
Memory
Peripherals
Features
Maximum Frequency
of Operation (MHz)
PIC16F84
PIC16CR84
10
10
10
10
—
Flash Program Memory
512
—
1K
EEPROM Program Memory
—
—
—
—
ROM Program Memory
—
512
—
1K
Data Memory (bytes)
36
36
68
68
Data EEPROM (bytes)
64
64
64
64
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
Interrupt Sources
4
4
4
4
I/O Pins
13
13
13
13
Voltage Range (Volts)
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 299
PIC17C75X
G.10
PIC16C9XX Family Of Devices
PIC16C924
PIC16C923
Clock
Memory
Maximum Frequency of Operation (MHz)
8
EPROM Program Memory
4K
4K
Data Memory (bytes)
176
176
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/PWM Module(s)
1
1
Serial Port(s)
Peripherals (SPI/I2C, USART)
Parallel Slave Port
Features
8
2
SPI/I C
SPI/I2C
—
—
A/D Converter (8-bit) Channels
—
5
LCD Module
4 Com,
32 Seg
4 Com,
32 Seg
Interrupt Sources
8
9
I/O Pins
25
25
Input Pins
27
27
Voltage Range (Volts)
3.0-6.0
3.0-6.0
In-Circuit Serial Programming
Yes
Yes
Brown-out Reset
—
—
Packages
64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30264A-page 300
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
G.11
PIC17CXX Family of Devices
PIC17CR42
PIC17C42A
Clock
Memory
PIC17CR43
PIC17C44
33
33
33
33
33
EPROM Program Memory
(words)
2K
—
4K
—
8K
ROM Program Memory
(words)
—
2K
—
4K
—
RAM Data Memory (bytes)
232
232
454
454
454
Timer Module(s)
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
Captures/PWM Module(s)
2
2
2
2
2
Serial Port(s) (USART)
Yes
Yes
Yes
Yes
Yes
Hardware Multiply
Yes
Yes
Yes
Yes
Yes
External Interrupts
Yes
Yes
Yes
Yes
Yes
Interrupt Sources
11
11
11
11
11
I/O Pins
33
33
33
33
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Number of Instructions
58
58
58
58
58
Packages
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
Peripherals
Features
PIC17C43
Maximum Frequency
of Operation (MHz)
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 301
PIC17C75X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE G-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509, PIC12C671, PIC12C672
8-pin
PIC16C154, PIC16CR154, PIC16C156,
PIC16CR156, PIC16C158, PIC16CR158,
PIC16C52, PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622
PIC16C641, PIC16C642, PIC16C661, PIC16C662
PIC16C710, PIC16C71, PIC16C711, PIC16C715
PIC16F83, PIC16CR83,
PIC16F84A, PIC16CR84
18-pin,
20-pin
PIC16C55, PIC16C57, PIC16CR57B
28-pin
PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73A
28-pin
PIC16CR64, PIC16C64A, PIC16C65A,
PIC16C74A
40-pin
PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44
40-pin
PIC16C923, PIC16C924
64/68-pin
PIC17C756, PIC17C752
64/68-pin
DS30264A-page 302
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
Index
A
A/D
Accuracy/Error .......................................................... 174
ADCON0 Register..................................................... 167
ADCON1 Register..................................................... 168
ADIF bit ..................................................................... 169
Analog Input Model Block Diagram........................... 170
Analog-to-Digital Converter....................................... 167
Block Diagram........................................................... 169
Configuring Analog Port Pins.................................... 172
Configuring the Interrupt ........................................... 169
Configuring the Module............................................. 169
Connection Considerations....................................... 174
Conversion Clock...................................................... 171
Conversions .............................................................. 172
Converter Characteristics ......................................... 245
Delays ....................................................................... 170
Effects of a Reset...................................................... 174
Equations .................................................................. 170
Flowchart of A/D Operation....................................... 175
GO/DONE bit ............................................................ 169
Internal Sampling Switch (Rss) Impedence .............. 170
Operation During Sleep ............................................ 173
Sampling Requirements............................................ 170
Sampling Time .......................................................... 170
Source Impedence.................................................... 170
Time Delays .............................................................. 170
Transfer Function...................................................... 174
A/D Interrupt........................................................................ 34
A/D Interrupt Flag bit, ADIF................................................. 34
A/D Module Interrupt Enable, ADIE .................................... 32
ACK........................................................................... 135, 268
Acknowledge Data bitr, AKD............................................. 126
Acknowledge Pulse........................................................... 135
Acknowledge Sequence Enable bit, AKE ......................... 126
Acknowledge Status bit, AKS ........................................... 126
ADCON0 ............................................................................. 45
ADCON1 ............................................................................. 45
ADDLW ............................................................................. 188
ADDWF ............................................................................. 188
ADDWFC .......................................................................... 189
ADIE.................................................................................... 32
ADIF.................................................................................... 34
ADRES Register ............................................................... 167
ADRESH ............................................................................. 45
ADRESL.............................................................................. 45
AKD................................................................................... 126
AKE................................................................................... 126
AKS........................................................................... 126, 149
ALU ....................................................................................... 9
ALUSTA ...................................................................... 44, 184
ALUSTA Register................................................................ 47
ANDLW ............................................................................. 189
ANDWF ............................................................................. 190
Application Note AN552,"Implementing Wake-up
on Keystroke"...................................................................... 68
Application Note AN578, "Use of the SSP Module in
the I2C Multi-Master Environment."................................... 123
Assembler ......................................................................... 220
Asynchronous Master Transmission ................................. 114
Asynchronous Transmitter ................................................ 113
B
Bank Select Register (BSR)................................................ 53
Banking ......................................................................... 42, 53
1997 Microchip Technology Inc.
Baud Rate Formula .......................................................... 110
Baud Rate Generator ....................................................... 143
Baud Rate Generator (BRG) ............................................ 110
Baud Rates
Asynchronous Mode................................................. 112
Synchronous Mode................................................... 111
BCF .................................................................................. 190
BCLIE ..................................................................................32
BCLIF ..................................................................................34
BF ............................................................. 124, 135, 149, 152
Bit Manipulation ................................................................ 184
Block Diagrams
A/D............................................................................ 169
Analog Input Model................................................... 170
Baud Rate Generator ............................................... 143
BSR Operation ............................................................53
External Brown-out Protection Circuit (Case1)............28
External Power-on Reset Circuit .................................22
External Program Memory Connection .......................41
I2C Master Mode ...................................................... 141
I2C Module................................................................ 134
Indirect Addressing......................................................50
On-chip Reset Circuit ..................................................21
PORTD ........................................................................74
PORTE ........................................................................76
Program Counter Operation ........................................52
PWM............................................................................97
RA0 and RA1...............................................................65
RA2..............................................................................66
RA3..............................................................................66
RA4 and RA5...............................................................66
RB3:RB2 Port Pins ......................................................69
RB7:RB4 and RB1:RB0 Port Pins ...............................68
RC7:RC0 Port Pins......................................................72
SSP (I2C Mode)........................................................ 134
SSP (SPI Mode) ....................................................... 128
SSP Module (I2C Master Mode) ............................... 123
SSP Module (I2C Slave Mode) ................................. 123
SSP Module (SPI Mode) .......................................... 123
Timer3 with One Capture and One Period Register. 100
TMR1 and TMR2 in 16-bit Timer/Counter Mode .........95
TMR1 and TMR2 in Two 8-bit Timer/Counter Mode ...94
TMR3 with Two Capture Registers........................... 102
Using CALL, GOTO.....................................................52
WDT ......................................................................... 179
BODEN ................................................................................28
Borrow ...................................................................................9
BRG .......................................................................... 110, 143
Brown-out Protection ...........................................................28
Brown-out Reset (BOR).......................................................28
BSF................................................................................... 191
BSR .............................................................................. 44, 53
BSR Operation ....................................................................53
BTFSC .............................................................................. 191
BTFSS .............................................................................. 192
BTG .................................................................................. 192
Buffer Full bit, BF .............................................................. 135
Buffer Full Status bit, BF................................................... 124
Bus Arbitration .................................................................. 160
Bus Collision
Section...................................................................... 160
Bus Collision During a RESTART Condition .................... 163
Bus Collision During a Start Condition ............................. 161
Bus Collision During a Stop Condition.............................. 164
Bus Collision Interrupt Enable, BCLIE .................................32
Bus Collision Interrupt Flag bit, BCLIF ................................34
Preliminary
DS30264A-page 303
PIC17C75X
C
C.............................................................................. 9, 47, 274
C Compiler (MP-C)............................................................ 221
CA1/PR3 ............................................................................. 92
CA1ED0 .............................................................................. 91
CA1ED1 .............................................................................. 91
CA1IE.................................................................................. 31
CA1IF .......................................................................... 33, 280
CA1OVF.............................................................................. 92
CA2ED0 .............................................................................. 91
CA2ED1 .............................................................................. 91
CA2H............................................................................. 26, 45
CA2IE.......................................................................... 31, 101
CA2IF .................................................................. 33, 101, 280
CA2L ............................................................................. 26, 45
CA2OVF.............................................................................. 92
CA3H................................................................................... 46
CA3IE.................................................................................. 32
CA3IF .................................................................................. 34
CA3L ................................................................................... 46
CA4H................................................................................... 46
CA4IE.................................................................................. 32
CA4IF .................................................................................. 34
Calculating Baud Rate Error ............................................. 110
CALL ........................................................................... 50, 193
Capacitor Selection
Ceramic Resonators ................................................... 16
Crystal Oscillator ......................................................... 16
Capture ....................................................................... 91, 100
Capture Sequence to Read Example................................ 103
Capture1
Mode ........................................................................... 91
Overflow................................................ 92, 93, 285, 286
Capture1 Interrupt ....................................................... 33, 280
Capture2
Mode ........................................................................... 91
Overflow................................................ 92, 93, 285, 286
Capture2 Interrupt ....................................................... 33, 280
Capture3 Interrupt Enable, CA3IE ...................................... 32
Capture3 Interrupt Flag bit, CA3IF ...................................... 34
Capture4 Interrupt Enable, CA4IE ...................................... 32
Capture4 Interrupt Flag bit, CA4IF ...................................... 34
Carry (C) ............................................................................... 9
Ceramic Resonators ........................................................... 15
Circular Buffer ..................................................................... 50
CKE................................................................................... 124
CKP........................................................................... 125, 290
Clearing the Prescaler....................................................... 179
Clock Polarity Select bit, CKP ................................... 125, 290
Clock/Instruction Cycle (Figure) .......................................... 19
Clocking Scheme/Instruction Cycle..................................... 19
CLRF................................................................................. 193
CLRWDT........................................................................... 194
Code Examples
Indirect Addressing ..................................................... 51
Loading the SSPBUF register................................... 127
Saving Status and WREG in RAM .............................. 38
Table Read ................................................................. 60
Table Write.................................................................. 58
Code Protection ................................................................ 181
COMF................................................................................ 194
Configuration
Bits ............................................................................ 178
Locations................................................................... 178
Oscillator ............................................................. 15, 178
Word ......................................................................... 177
DS30264A-page 304
CPFSEQ ........................................................................... 195
CPFSGT ........................................................................... 195
CPFSLT ............................................................................ 196
CPUSTA ............................................................... 44, 48, 180
Crystal Operation, Overtone Crystals ................................. 16
Crystal or Ceramic Resonator Operation............................ 16
Crystal Oscillator................................................................. 15
D
D/A.................................................................................... 124
Data Memory
GPR ...................................................................... 39, 42
Indirect Addressing ..................................................... 50
Organization ............................................................... 42
SFR ............................................................................ 39
Data Memory Banking ........................................................ 42
Data/Address bit, D/A ....................................................... 124
DAW ................................................................................. 196
DC........................................................................... 9, 47, 274
DDRB...................................................................... 25, 44, 68
DDRC ..................................................................... 25, 44, 72
DDRD ..................................................................... 25, 44, 74
DDRE...................................................................... 25, 44, 76
DDRF.................................................................................. 45
DDRG ................................................................................. 45
DECF ................................................................................ 197
DECFSNZ......................................................................... 198
DECFSZ ........................................................................... 197
Delay From External Clock Edge........................................ 88
Development Support ....................................................... 219
Development Tools........................................................... 219
Digit Borrow .......................................................................... 9
Digit Carry (DC) .................................................................... 9
Duty Cycle .......................................................................... 97
E
Electrical Characteristics
PIC17C752/756
Absolute Maximum Ratings.............................. 223
Capture Timing ................................................. 236
CLKOUT and I/O Timing .................................. 233
DC Characteristics............................................ 225
External Clock Timing....................................... 232
Memory Interface Read Timing ........................ 248
Memory Interface Write Timing ........................ 247
Parameter Measurement Information............... 231
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing ................... 234
Timer0 Clock Timing......................................... 235
Timer1, Timer2 and Timer3 Clock Timing ........ 235
Timing Parameter Symbology .......................... 230
USART Module Synchronous Receive
Timing.................................................................. 244
USART Module Synchronous Transmission
Timing............................................................... 244
EPROM Memory Access Time Order Suffix....................... 41
Extended Microcontroller .................................................... 39
Extended Microcontroller Mode .......................................... 41
External Memory Interface.................................................. 41
External Program Memory Waveforms............................... 41
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
F
Family of Devices
PIC12CXXX .............................................................. 293
PIC14C000 ............................................................... 293
PIC16C15X ............................................................... 294
PIC16C55X ............................................................... 296
PIC16C5X ................................................................. 295
PIC16C62X and PIC16C64X .................................... 296
PIC16C6X ................................................................. 297
PIC16C7XX............................................................... 298
PIC16C8X ................................................................. 299
PIC16C9XX............................................................... 300
PIC17C75X ................................................................... 6
PIC17CXX................................................................. 301
FERR ................................................................................ 115
Flowcharts
Acknowledge............................................................. 156
Master Receiver........................................................ 153
Master Transmit ........................................................ 150
Restart Condition ...................................................... 147
Start Condition .......................................................... 145
Stop Condition .......................................................... 158
FOSC0 .............................................................................. 177
FOSC1 .............................................................................. 177
FS0 ............................................................................. 47, 274
FS1 ............................................................................. 47, 274
FS2 ............................................................................. 47, 274
FS3 ............................................................................. 47, 274
FSR0............................................................................. 44, 51
FSR1............................................................................. 44, 51
Fuzzy Logic Dev. System (fuzzyTECH-MP) .......... 219, 221
G
GCE .................................................................................. 126
General Call Address Sequence....................................... 139
General Call Address Support .......................................... 139
General Call Enable bit, GCE ........................................... 126
General Format for Instructions ........................................ 184
General Purpose RAM ........................................................ 39
General Purpose RAM Bank............................................... 53
General Purpose Register (GPR) ....................................... 42
GLINTD......................................................... 35, 48, 101, 180
Global Interrupt Disable bit, GLINTD .................................. 35
GOTO ............................................................................... 198
GPR (General Purpose Register) ....................................... 42
GPR Banks ......................................................................... 53
Graphs
IOH vs. VOH, VDD = 3V .............................................. 256
IOH vs. VOH, VDD = 5V .............................................. 257
IOL vs. VOL, VDD = 3V ............................................... 257
IOL vs. VOL, VDD = 5V ............................................... 258
Maximum IDD vs. Frequency (External Clock
125°C to -40°C) ........................................................ 253
Maximum IPD vs. VDD Watchdog Disabled ............... 254
Maximum IPD vs. VDD Watchdog Enabled................ 255
RC Oscillator Frequency vs. VDD (Cext = 100 pF).... 250
RC Oscillator Frequency vs. VDD (Cext = 22 pF)...... 250
RC Oscillator Frequency vs. VDD (Cext = 300 pF).... 251
Transconductance of LF Oscillator vs.VDD ............... 252
Transconductance of XT Oscillator vs. VDD.............. 252
Typical IDD vs. Frequency (External Clock 25°C) ..... 253
Typical IPD vs. VDD Watchdog Disabled 25°C .......... 254
Typical IPD vs. VDD Watchdog Enabled 25°C ........... 255
Typical RC Oscillator vs. Temperature ..................... 249
VIH, VIL of MCLR, T0CKI and OSC1 (In RC Mode)
vs. VDD ...................................................................... 259
VTH (Input Threshold Voltage) of I/O Pins vs. VDD ... 258
1997 Microchip Technology Inc.
H
VTH (Input Threshold Voltage) of OSC1
Input (In XT, HS, and LP Modes) vs. VDD ................ 259
WDT Timer Time-Out Period vs. VDD ....................... 256
Hardware Multiplier..............................................................61
I
I/O Ports
Bi-directional................................................................83
I/O Ports ......................................................................65
Programming Considerations ......................................83
Read-Modify-Write Instructions ...................................83
Successive Operations................................................83
I2C .................................................................................... 134
Addressing I2C Devices............................................ 268
Arbitration ................................................................. 270
Combined Format..................................................... 269
I2C Overview ............................................................ 267
Initiating and Terminating Data Transfer .................. 267
Master-Receiver Sequence ...................................... 269
Master-Transmitter Sequence .................................. 269
Multi-master.............................................................. 270
START...................................................................... 267
STOP................................................................ 267, 268
Transfer Acknowledge.............................................. 268
I2C Master Mode Receiver Flowchart............................... 153
I2C Master Mode Reception ............................................. 152
I2C Master Mode Restart Condition.................................. 146
I2C Mode Selection........................................................... 134
I2C Module
Acknowledge Flowchart............................................ 156
Acknowledge Sequence timing ................................ 155
Addressing................................................................ 135
Baud Rate Generator ............................................... 143
Block Diagram .......................................................... 141
BRG Block Diagram ................................................. 143
BRG Reset due to SDA Collision ............................. 162
BRG Timing .............................................................. 143
Bus Arbitration .......................................................... 160
Bus Collision............................................................. 160
Acknowledge .................................................... 160
Restart Condition.............................................. 163
Restart Condition Timing (Case1) .................... 163
Restart Condition Timing (Case2) .................... 163
Start Condition.................................................. 161
Start Condition Timing .............................. 161, 162
Stop Condition .................................................. 164
Stop Condition Timing (Case1) ........................ 164
Stop Condition Timing (Case2) ........................ 164
Transmit Timing................................................ 160
Bus Collision timing .................................................. 160
Clock Arbitration ....................................................... 159
Clock Arbitration Timing (Master Transmit) .............. 159
Conditions to not give ACK Pulse............................. 135
General Call Address Support.................................. 139
Master Mode............................................................. 141
Master Mode 7-bit Reception timing......................... 154
Master Mode Operation............................................ 142
Master Mode Start Condition.................................... 144
Master Mode Transmission ...................................... 149
Master Mode Transmit Sequence ............................ 142
Master Transmit Flowchart ....................................... 150
Multi-Master Communication.................................... 160
Multi-master Mode.................................................... 142
Operation.................................................................. 134
Repeat Start Condition timing................................... 146
Restart Condition Flowchart ..................................... 147
Slave Mode............................................................... 135
Preliminary
DS30264A-page 305
PIC17C75X
Slave Reception........................................................ 136
Slave Transmission................................................... 136
SSPBUF.................................................................... 134
Start Condition Flowchart.......................................... 145
Stop Condition Flowchart .......................................... 158
Stop Condition Receive or Transmit timing............... 157
Stop Condition timing................................................ 157
Waveforms for 7-bit Reception ................................. 136
Waveforms for 7-bit Transmission ............................ 136
I2C Module Address Register, SSPADD........................... 134
I2C Slave Mode ................................................................. 135
INCF.................................................................................. 199
INCFSNZ........................................................................... 200
INCFSZ ............................................................................. 199
In-Circuit Serial Programming ........................................... 182
INDF0............................................................................ 44, 51
INDF1............................................................................ 44, 51
Indirect Addressing
Indirect Addressing ..................................................... 50
Operation .................................................................... 51
Registers..................................................................... 51
Initialization Conditions for Special Function Registers ...... 25
Initializing PORTB ............................................................... 69
Initializing PORTC............................................................... 72
Initializing PORTD............................................................... 74
Initializing PORTE ................................................... 76, 78, 80
INSTA.................................................................................. 44
Instruction Flow/Pipelining .................................................. 19
Instruction Set ................................................................... 186
ADDLW ..................................................................... 188
ADDWF ..................................................................... 188
ADDWFC .................................................................. 189
ANDLW ..................................................................... 189
ANDWF ..................................................................... 190
BCF........................................................................... 190
BSF ........................................................................... 191
BTFSC ...................................................................... 191
BTFSS ...................................................................... 192
BTG........................................................................... 192
CALL ......................................................................... 193
CLRF......................................................................... 193
CLRWDT................................................................... 194
COMF ....................................................................... 194
CPFSEQ ................................................................... 195
CPFSGT ................................................................... 195
CPFSLT .................................................................... 196
DAW.......................................................................... 196
DECF ........................................................................ 197
DECFSNZ ................................................................. 198
DECFSZ.................................................................... 197
GOTO ....................................................................... 198
INCF.......................................................................... 199
INCFSNZ .................................................................. 200
INCFSZ ..................................................................... 199
IORLW ...................................................................... 200
IORWF ...................................................................... 201
LCALL ....................................................................... 201
MOVFP ..................................................................... 202
MOVLB ..................................................................... 202
MOVLR ..................................................................... 203
MOVLW .................................................................... 203
MOVPF ..................................................................... 204
MOVWF .................................................................... 204
MULLW ..................................................................... 205
MULWF ..................................................................... 205
NEGW....................................................................... 206
NOP .......................................................................... 206
DS30264A-page 306
RETFIE ..................................................................... 207
RETLW ..................................................................... 207
RETURN................................................................... 208
RLCF ........................................................................ 208
RLNCF...................................................................... 209
RRCF........................................................................ 209
RRNCF ..................................................................... 210
SETF ........................................................................ 210
SLEEP ...................................................................... 211
SUBLW ..................................................................... 211
SUBWF..................................................................... 212
SUBWFB .................................................................. 212
SWAPF ..................................................................... 213
TABLRD ........................................................... 213, 214
TABLWT ........................................................... 214, 215
TLRD ........................................................................ 215
TLWT ........................................................................ 216
TSTFSZ .................................................................... 216
XORLW .................................................................... 217
XORWF .................................................................... 217
Instruction Set Summary .................................................. 183
Instructions
TABLRD ..................................................................... 60
TLRD .......................................................................... 60
INT Pin................................................................................ 36
INTE.................................................................................... 30
INTEDG ........................................................................ 49, 87
Inter-Integrated Circuit (I2C) ............................................. 123
Internal Sampling Switch (Rss) Impedence...................... 170
Interrupt on Change Feature .............................................. 68
Interrupt Status Register (INTSTA)..................................... 30
Interrupts
A/D Interrupt ............................................................... 34
Bus Collision Interrupt ................................................ 34
Capture1 Interrupt .............................................. 33, 280
Capture2 Interrupt .............................................. 33, 280
Capture3 Interrupt ...................................................... 34
Capture4 Interrupt ...................................................... 34
Context Saving ........................................................... 35
Flag bits
TMR1IE .............................................................. 29
TMR1IF............................................................... 29
TMR2IE .............................................................. 29
TMR2IF............................................................... 29
TMR3IE .............................................................. 29
TMR3IF............................................................... 29
Global Interrupt Disable .............................................. 35
Interrupts .................................................................... 29
Logic ........................................................................... 29
Operation .................................................................... 35
Peripheral Interrupt Enable......................................... 31
Peripheral Interrupt Request ...................................... 33
PIE2 Register ............................................................. 32
PIR1 Register ............................................................. 33
PIR2 Register ............................................................. 34
PORTB Interrupt on Change .............................. 33, 280
PWM ........................................................................... 98
RA0/INT ...................................................................... 35
Status Register ........................................................... 30
Synchronous Serial Port Interrupt .............................. 34
T0CKI Interrupt ........................................................... 35
Timing ......................................................................... 36
TMR1 Overflow Interrupt .................................... 33, 280
TMR2 Overflow Interrupt .................................... 33, 280
TMR3 Overflow Interrupt .................................... 33, 280
USART1 Receive Interrupt ................................. 33, 280
USART1 Transmit Interrupt ................................ 33, 280
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
USART2 Receive Interrupt ......................................... 34
Vectors
Peripheral Interrupt ............................................. 35
Program Memory Locations................................ 39
RA0/INT Interrupt................................................ 35
T0CKI Interrupt ................................................... 35
Vectors/Priorities......................................................... 35
Wake-up from SLEEP............................................... 180
INTF .................................................................................... 30
INTSTA ............................................................................... 44
INTSTA Register ................................................................. 30
IORLW .............................................................................. 200
IORWF .............................................................................. 201
L
LCALL ......................................................................... 50, 201
M
Maps
Register File Map................................................ 43, 273
Memory
External Interface........................................................ 41
External Memory Waveforms...................................... 41
Memory Map (Different Modes) .................................. 40
Mode Memory Access ................................................ 40
Organization................................................................ 39
Program Memory ........................................................ 39
Program Memory Map ................................................ 39
Microcontroller .................................................................... 39
Microprocessor ................................................................... 39
Minimizing Current Consumption ...................................... 181
MOVFP ....................................................................... 42, 202
Moving Data Between Data and Program Memories.......... 42
MOVLB ....................................................................... 42, 202
MOVLR ............................................................................. 203
MOVLW ............................................................................ 203
MOVPF ....................................................................... 42, 204
MOVWF ............................................................................ 204
MPASM Assembler ................................................... 219, 220
MP-C C Compiler .............................................................. 221
MPSIM Software Simulator ....................................... 219, 221
MULLW ............................................................................. 205
Multi-Master Communication ............................................ 160
Multi-Master Mode ............................................................ 142
Multiply Examples
16 x 16 Routine........................................................... 62
16 x 16 Signed Routine............................................... 63
8 x 8 Routine............................................................... 61
8 x 8 Signed Routine................................................... 61
MULWF ............................................................................. 205
N
NEGW............................................................................... 206
NOP .................................................................................. 206
O
Opcode Field Descriptions ................................................ 183
Opcodes.............................................................................. 52
Oscillator
Configuration....................................................... 15, 178
Crystal......................................................................... 15
External Clock............................................................. 17
External Crystal Circuit ............................................... 17
External Parallel Resonant Crystal Circuit .................. 17
External Series Resonant Crystal Circuit.................... 17
RC............................................................................... 18
1997 Microchip Technology Inc.
RC Frequencies........................................................ 251
Oscillator Start-up Time (Figure) .........................................22
Oscillator Start-up Timer (OST) ...........................................22
OST .....................................................................................22
OV .......................................................................... 9, 47, 274
Overflow (OV) ........................................................................9
P
P ....................................................................................... 124
Packaging Information ...................................................... 261
PC (Program Counter).........................................................52
PCFG0 bit ................................................................. 168, 288
PCFG1 bit ................................................................. 168, 288
PCFG2 bit ................................................................. 168, 288
PCH .....................................................................................52
PCL....................................................................... 44, 52, 184
PCLATH ....................................................................... 44, 52
PD............................................................................... 48, 180
PEIE ........................................................................... 30, 101
PEIF.....................................................................................30
Peripheral Bank ...................................................................53
Peripheral Banks .................................................................53
Peripheral Interrupt Enable..................................................31
Peripheral Interrupt Request (PIR1) ....................................33
Peripheral Register Banks ...................................................42
PICDEM-1 Low-Cost PIC16/17 Demo Board ........... 219, 220
PICDEM-2 Low-Cost PIC16CXX Demo Board......... 219, 220
PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............ 220
PICMASTER In-Circuit Emulator ...................................... 219
PICSTART Low-Cost Development System .................... 219
PICSTART Low-Cost Development System .................... 219
PIE .................................................................... 116, 120, 122
PIE1 .............................................................................. 25, 44
PIE2 ........................................................................ 25, 32, 45
Pin Compatible Devices ................................................... 302
PIR.................................................................... 116, 120, 122
PIR1.............................................................................. 25, 44
PIR2.............................................................................. 25, 45
PM0 .......................................................................... 177, 181
PM1 .......................................................................... 177, 181
POP .............................................................................. 35, 50
POR .....................................................................................22
PORTA ................................................................... 25, 44, 65
PORTB ................................................................... 25, 44, 68
PORTB Interrupt on Change ...................................... 33, 280
PORTC ................................................................... 25, 44, 72
PORTD ................................................................... 25, 44, 74
PORTE ................................................................... 25, 44, 76
PORTF ................................................................................45
PORTG ................................................................................45
Power-down Mode............................................................ 180
Power-on Reset (POR)........................................................22
Power-up Timer (PWRT) .....................................................22
PR1............................................................................... 26, 45
PR2............................................................................... 26, 45
PR3/CA1H ...........................................................................26
PR3/CA1L............................................................................26
PR3H/CA1H ........................................................................45
PR3L/CA1L..........................................................................45
Prescaler Assignments ........................................................89
PRO MATE Universal Programmer .................................. 219
PRODH......................................................................... 27, 46
PRODL ......................................................................... 27, 46
Program Counter (PC).........................................................52
Program Memory
External Access Waveforms........................................41
Preliminary
DS30264A-page 307
PIC17C75X
External Connection Diagram ..................................... 41
Map ............................................................................. 39
Modes
Extended Microcontroller .................................... 39
Microcontroller .................................................... 39
Microprocessor ................................................... 39
Protected Microcontroller .................................... 39
Operation .................................................................... 39
Organization................................................................ 39
Protected Microcontroller .................................................... 39
PS0 ............................................................................... 49, 87
PS1 ............................................................................... 49, 87
PS2 ............................................................................... 49, 87
PS3 ............................................................................... 49, 87
PUSH ............................................................................ 35, 50
PW1DCH....................................................................... 26, 45
PW1DCL ....................................................................... 26, 45
PW2DCH....................................................................... 26, 45
PW2DCL ....................................................................... 26, 45
PW3DCH....................................................................... 27, 46
PW3DCL ....................................................................... 27, 46
PWM ............................................................................. 91, 97
Duty Cycle................................................................... 98
External Clock Source ................................................ 99
Frequency vs. Resolution ........................................... 98
Interrupts..................................................................... 98
Max Resolution/Frequency for External Clock Input ... 99
Output ......................................................................... 97
Periods........................................................................ 98
PWM1 ........................................................... 92, 93, 285, 286
PWM1ON ...................................................................... 92, 97
PWM2 ........................................................... 92, 93, 285, 286
PWM2ON ...................................................................... 92, 97
PWM3ON ............................................................................ 93
PWRT.................................................................................. 22
R
R/W ................................................................................... 124
R/W bit ...................................................................... 135, 268
R/W bit .............................................................................. 136
RA1/T0CKI pin .................................................................... 87
RBIE.................................................................................... 31
RBIF .................................................................................... 33
RBPU .................................................................................. 68
RC Oscillator ....................................................................... 18
RC Oscillator Frequencies ................................................ 251
RC1IE.................................................................................. 31
RC1IF.......................................................................... 33, 280
RC2IE.................................................................................. 32
RC2IF.................................................................................. 34
RCE,Receive Enable bit, RCE .......................................... 126
RCREG ..................................................... 115, 116, 120, 121
RCREG1 ....................................................................... 25, 44
RCREG2 ....................................................................... 25, 45
RCSTA .............................................................. 116, 120, 122
RCSTA1 ........................................................................ 25, 44
RCSTA2 ........................................................................ 25, 45
Read/Write bit, R/W .......................................................... 124
Reading 16-bit Value........................................................... 89
Receive Overflow Indicator bit, SSPOV .................... 125, 290
Receive Status and Control Register ................................ 107
Register File Map ........................................................ 43, 273
Registers
ADCON0 ..................................................................... 45
ADCON1 ..................................................................... 45
ADRESH ..................................................................... 45
DS30264A-page 308
Preliminary
ADRESL ..................................................................... 45
ALUSTA.......................................................... 35, 44, 47
BRG .......................................................................... 110
BSR ...................................................................... 35, 44
CA2H .......................................................................... 45
CA2L........................................................................... 45
CA3H .......................................................................... 46
CA3L........................................................................... 46
CA4H .......................................................................... 46
CA4L........................................................................... 46
CPUSTA ............................................................... 44, 48
DDRB ......................................................................... 44
DDRC ......................................................................... 44
DDRD ......................................................................... 44
DDRE ......................................................................... 44
DDRF.......................................................................... 45
DDRG ......................................................................... 45
FSR0 .................................................................... 44, 51
FSR1 .................................................................... 44, 51
INDF0 ................................................................... 44, 51
INDF1 ................................................................... 44, 51
INSTA ......................................................................... 44
INTSTA ....................................................................... 30
PCL............................................................................. 44
PCLATH ..................................................................... 44
PIE1 ...................................................................... 31, 44
PIE2 ...................................................................... 32, 45
PIR1...................................................................... 33, 44
PIR2...................................................................... 34, 45
PORTA ....................................................................... 44
PORTB ....................................................................... 44
PORTC ....................................................................... 44
PORTD ....................................................................... 44
PORTE ....................................................................... 44
PORTF ....................................................................... 45
PORTG ....................................................................... 45
PR1............................................................................. 45
PR2............................................................................. 45
PR3H/CA1H ............................................................... 45
PR3L/CA1L................................................................. 45
PRODH....................................................................... 46
PRODL ....................................................................... 46
PW1DCH .................................................................... 45
PW1DCL..................................................................... 45
PW2/DCL.................................................................... 45
PW2DCH .................................................................... 45
PW3DCH .................................................................... 46
PW3DCL..................................................................... 46
RCREG1..................................................................... 44
RCREG2..................................................................... 45
RCSTA1 ..................................................................... 44
RCSTA2 ..................................................................... 45
SPBRG1 ..................................................................... 44
SPBRG2 ..................................................................... 45
Special Function Table ............................................... 44
SSPADD ..................................................................... 46
SSPBUF ..................................................................... 46
SSPCON1 .................................................................. 46
SSPCON2 .................................................................. 46
SSPSTAT ........................................................... 46, 124
T0STA ............................................................ 44, 49, 87
TBLPTRH ................................................................... 44
TBLPTRL .................................................................... 44
TCON1 ................................................................. 45, 91
TCON2 ................................................................. 45, 92
TCON3 ................................................................. 46, 93
TMR0H ....................................................................... 44
1997 Microchip Technology Inc.
PIC17C75X
TMR1 .......................................................................... 45
TMR2 .......................................................................... 45
TMR3H........................................................................ 45
TMR3L ........................................................................ 45
TXREG1...................................................................... 44
TXREG2...................................................................... 45
TXSTA1 ...................................................................... 44
TXSTA2 ...................................................................... 45
WREG................................................................... 35, 44
Regsters
TMR0L ........................................................................ 44
Reset
Section ........................................................................ 21
Status Bits and Their Significance .............................. 23
Time-Out in Various Situations ................................... 23
Time-Out Sequence.................................................... 23
Restart Condition Enabled bit, RSE.................................. 126
RETFIE ............................................................................. 207
RETLW ............................................................................. 207
RETURN ........................................................................... 208
RLCF................................................................................. 208
RLNCF .............................................................................. 209
RRCF ................................................................................ 209
RRNCF ............................................................................. 210
RSE................................................................................... 126
RX Pin Sampling Scheme................................................. 115
S
S........................................................................................ 124
SAE................................................................................... 126
Sampling ........................................................................... 115
Saving STATUS and WREG in RAM .................................. 38
SCK................................................................................... 127
SCL ................................................................................... 135
SDA................................................................................... 135
SDI .................................................................................... 127
SDO .................................................................................. 127
Serial Clock, SCK ............................................................. 127
Serial Clock, SCL .............................................................. 135
Serial Data Address, SDA................................................. 135
Serial Data In, SDI ............................................................ 127
Serial Data Out, SDO........................................................ 127
SETF................................................................................. 210
SFR................................................................................... 184
SFR (Special Function Registers)....................................... 39
SFR As Source/Destination .............................................. 184
Signed Math.......................................................................... 9
Slave Select Synchronization ........................................... 130
Slave Select, SS ............................................................... 127
SLEEP ...................................................................... 180, 211
SMP .................................................................................. 124
Software Simulator (MPSIM) ............................................ 221
SPBRG ............................................................. 116, 120, 122
SPBRG1 ....................................................................... 25, 44
SPBRG2 ....................................................................... 25, 45
SPE................................................................................... 126
Special Features of the CPU ............................................ 177
Special Function Registers ................................... 39, 44, 184
Summary..................................................................... 44
Special Function Registers, File Map ......................... 43, 273
SPI
Master Mode ............................................................. 129
Serial Clock............................................................... 127
Serial Data In ............................................................ 127
Serial Data Out ......................................................... 127
Serial Peripheral Interface (SPI) ............................... 123
1997 Microchip Technology Inc.
Slave Select.............................................................. 127
SPI clock................................................................... 129
SPI Mode.................................................................. 127
SPI Clock Edge Select, CKE ............................................ 124
SPI Data Input Sample Phase Select, SMP ..................... 124
SPI Master/Slave Connection........................................... 130
SPI Module
Master/Slave Connection ......................................... 130
Slave Mode............................................................... 130
Slave Select Synchronization ................................... 130
Slave Synch Timnig.................................................. 131
Slave Timing with CKE = 0 ....................................... 132
Slave Timing with CKE = 1 ....................................... 133
SS ..................................................................................... 127
SSP .................................................................................. 123
Block Diagram (SPI Mode) ....................................... 128
SPI Mode.................................................................. 127
SSPADD........................................................... 134, 135
SSPBUF ........................................................... 129, 134
SSPCON1 ................................................................ 125
SSPCON2 ................................................................ 126
SSPSR ............................................................. 129, 135
SSPSTAT ......................................................... 124, 134
SSP I2C
SSP I2C Operation ................................................... 134
SSP Module
SPI Master Mode...................................................... 129
SPI Master./Slave Connection.................................. 130
SPI Slave Mode........................................................ 130
SSPCON1 Register .................................................. 134
SSP Overflow Detect bit, SSPOV..................................... 135
SSPADD ..............................................................................46
SSPBUF ............................................................. 46, 134, 135
SSPCON1 .......................................................... 46, 125, 134
SSPCON2 .................................................................. 46, 126
SSPEN ..................................................................... 125, 290
SSPIE ..................................................................................32
SSPIF ......................................................................... 34, 136
SSPM3:SSPM0 ........................................................ 125, 290
SSPOV ..................................................... 125, 135, 152, 290
SSPSTAT ........................................................... 46, 124, 134
Stack
Operation.....................................................................50
Pointer .........................................................................50
Stack............................................................................39
Start bit (S) ....................................................................... 124
Start Condition Enabled bit, SAE...................................... 126
STKAV .......................................................................... 48, 50
Stop bit (P)........................................................................ 124
Stop Condition Enable bit ................................................. 126
SUBLW ............................................................................. 211
SUBWF............................................................................. 212
SUBWFB .......................................................................... 212
SWAPF ............................................................................. 213
Synchronous Master Mode............................................... 117
Synchronous Master Reception ....................................... 119
Synchronous Master Transmission .................................. 117
Synchronous Serial Port ................................................... 123
Synchronous Serial Port Enable bit, SSPEN............ 125, 290
Synchronous Serial Port Interrupt .......................................34
Synchronous Serial Port Interrupt Enable, SSPIE...............32
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ........................................................ 125, 290
Synchronous Slave Mode................................................. 121
T
T0CKI ..................................................................................35
Preliminary
DS30264A-page 309
PIC17C75X
T0CKI Pin............................................................................ 36
T0CKIE................................................................................ 30
T0CKIF................................................................................ 30
T0CS ............................................................................. 49, 87
T0IE..................................................................................... 30
T0IF..................................................................................... 30
T0SE ............................................................................. 49, 87
T0STA ........................................................................... 44, 49
T16 ...................................................................................... 91
Table Latch ......................................................................... 51
Table Pointer....................................................................... 51
Table Read
Example ...................................................................... 60
Table Reads Section................................................... 60
TLRD........................................................................... 60
Table Write
Code ........................................................................... 58
Timing ......................................................................... 58
To External Memory.................................................... 58
TABLRD .................................................................... 213, 214
TABLWT.................................................................... 214, 215
TAD .................................................................................... 171
TBLATH .............................................................................. 51
TBLATL ............................................................................... 51
TBLPTRH...................................................................... 44, 51
TBLPTRL ...................................................................... 44, 51
TCLK12 ....................................................................... 91, 284
TCLK3 ......................................................................... 91, 284
TCON1 .......................................................................... 26, 45
TCON2 ................................................................................ 45
TCON2,TCON3................................................................... 26
TCON3 .......................................................................... 46, 93
Time-Out Sequence ............................................................ 23
Timer Resources................................................................. 85
Timer0 ................................................................................. 87
Timer1
16-bit Mode ................................................................. 95
Clock Source Select.................................................... 91
On bit .................................................... 92, 93, 285, 286
Section .................................................................. 91, 94
Timer2
16-bit Mode ................................................................. 95
Clock Source Select.................................................... 91
On bit .................................................... 92, 93, 285, 286
Section .................................................................. 91, 94
Timer3
Clock Source Select.................................................... 91
On bit .................................................... 92, 93, 285, 286
Section ................................................................ 91, 100
Timers
TCON3........................................................................ 93
Timing Diagrams
A/D Conversion ......................................................... 246
Acknowledge Sequence Timing................................ 155
Asynchronous Master Transmission ......................... 114
Asynchronous Reception .......................................... 116
Back to Back Asynchronous Master Transmission ... 114
Baud Rate Generator with Clock Arbitration ............. 143
BRG Reset Due to SDA Collision ............................. 162
Bus Collision
Start Condition Timing ...................................... 161
Bus Collision During a Restart Condition (Case 1) ... 163
Bus Collision During a Restart Condition (Case2) .... 163
Bus Collision During a Start Condition (SCL = 0) ..... 162
Bus Collision During a Stop Condition ...................... 164
Bus Collision for Transmit and Acknowledge............ 160
DS30264A-page 310
External Parallel Resonant Crystal Oscillator
Circuit ......................................................................... 17
External Program Memory Access ............................. 41
I2C Bus Data............................................................. 242
I2C Bus Start/Stop bits.............................................. 241
I2C Master Mode First Start bit timing ...................... 144
I2C Master Mode Reception timing........................... 154
I2C Master Mode Transmission timing ..................... 151
Interrupt (INT, TMR0 Pins) ......................................... 36
Master Mode Transmit Clock Arbitration .................. 159
Oscillator Start-up Time .............................................. 22
PIC17C752/756 Capture Timing .............................. 236
PIC17C752/756 CLKOUT and I/O............................ 233
PIC17C752/756 External Clock ................................ 232
PIC17C752/756 Memory Interface Read ................. 248
PIC17C752/756 Memory Interface Write.................. 247
PIC17C752/756 PWM Timing .................................. 236
PIC17C752/756 Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer ......................... 234
PIC17C752/756 Timer0 Clock .................................. 235
PIC17C752/756 Timer1, Timer2 and Timer3 Clock . 235
PIC17C752/756 USART Module Synchronous
Receive..................................................................... 244
PIC17C752/756 USART Module Synchronous
Transmission ............................................................ 244
Repeat Start Condition ............................................. 146
Slave Synchronization .............................................. 131
SPI Mode Timing (Master Mode)SPI Mode
Master Mode Timing Diagram .......................... 129
SPI Mode Timing (Slave Mode with CKE = 0).......... 132
SPI Mode Timing (Slave Mode with CKE = 1).......... 133
Stop Condition Receive or Transmit ......................... 157
Synchronous Reception ........................................... 119
Synchronous Transmission ...................................... 118
Table Write ................................................................. 58
TMR0 .................................................................... 88, 89
TMR0 Read/Write in Timer Mode ............................... 90
TMR1, TMR2, and TMR3 in Timer Mode ................. 105
Wake-Up from SLEEP .............................................. 180
TLRD ................................................................................ 215
TLWT ................................................................................ 216
TMR0
16-bit Read ................................................................. 89
16-bit Write ................................................................. 89
Module ........................................................................ 88
Operation .................................................................... 88
Overview..................................................................... 85
Prescaler Assignments ............................................... 89
Read/Write Considerations......................................... 89
Read/Write in Timer Mode.......................................... 90
Timing ................................................................... 88, 89
TMR0 Status/Control Register (T0STA) ............................. 49
TMR0H ............................................................................... 44
TMR0L ................................................................................ 44
TMR1 ............................................................................ 26, 45
8-bit Mode................................................................... 94
External Clock Input ................................................... 94
Overview..................................................................... 85
Timer Mode .............................................................. 105
Two 8-bit Timer/Counter Mode ................................... 94
Using with PWM ......................................................... 97
TMR1 Overflow Interrupt ............................................ 33, 280
TMR1CS ............................................................................. 91
TMR1IE............................................................................... 31
TMR1IF....................................................................... 33, 280
TMR1ON............................................................................. 92
TMR2 ............................................................................ 26, 45
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
8-bit Mode ................................................................... 94
External Clock Input.................................................... 94
In Timer Mode........................................................... 105
Two 8-bit Timer/Counter Mode ................................... 94
Using with PWM.......................................................... 97
TMR2 Overflow Interrupt............................................. 33, 280
TMR2CS ............................................................................. 91
TMR2IE............................................................................... 31
TMR2IF ....................................................................... 33, 280
TMR2ON ............................................................................. 92
TMR3
Example, Reading From ........................................... 104
Example, Writing To.................................................. 104
External Clock Input.................................................. 104
In Timer Mode........................................................... 105
One Capture and One Period Register Mode........... 100
Overview ..................................................................... 85
Reading/Writing ........................................................ 104
TMR3 Interrupt Flag bit, TMR3IF ................................ 33, 280
TMR3CS ..................................................................... 91, 100
TMR3H.......................................................................... 26, 45
TMR3IE............................................................................... 31
TMR3IF ....................................................................... 33, 100
TMR3L .......................................................................... 26, 45
TMR3ON ..................................................................... 92, 100
TO ....................................................................... 48, 179, 180
Transmit Status and Control Register ............................... 107
TSTFSZ ............................................................................ 216
Turning on 16-bit Timer....................................................... 95
TX1IE .................................................................................. 31
TX1IF .......................................................................... 33, 280
TX2IE .................................................................................. 32
TX2IF .................................................................................. 34
TXREG...................................................... 113, 117, 121, 122
TXREG1........................................................................ 25, 44
TXREG2........................................................................ 25, 45
TXSTA .............................................................. 116, 120, 122
TXSTA1 ........................................................................ 25, 44
TXSTA2 ........................................................................ 25, 45
Wake-up from SLEEP Through Interrupt.......................... 180
Watchdog Timer ............................................................... 179
Waveform for General Call Address Sequence................ 139
Waveforms
External Program Memory Access ..............................41
WCOL ............................... 125, 144, 149, 152, 155, 157, 290
WCOL Status Flag............................................................ 144
WDT ................................................................................. 179
Clearing the WDT ..................................................... 179
Normal Timer............................................................ 179
Period ....................................................................... 179
Programming Considerations ................................... 179
WDTPS0........................................................................... 177
WDTPS1........................................................................... 177
WREG .................................................................................44
Write Collision Detect bit, WCOL.............................. 125, 290
X
XORLW ............................................................................ 217
XORWF ............................................................................ 217
Z
Z ............................................................................. 9, 47, 274
Zero (Z)..................................................................................9
U
UA ..................................................................................... 124
Update Address, UA ......................................................... 124
Upward Compatibility ............................................................ 5
USART
Asynchronous Master Transmission......................... 114
Asynchronous Mode ................................................. 113
Asynchronous Receive ............................................. 115
Asynchronous Transmitter ........................................ 113
Baud Rate Generator................................................ 110
Synchronous Master Mode ....................................... 117
Synchronous Master Reception................................ 119
Synchronous Master Transmission........................... 117
Synchronous Slave Mode ......................................... 121
Synchronous Slave Transmit .................................... 121
USART1 Receive Interrupt ......................................... 33, 280
USART1 Transmit Interrupt ........................................ 33, 280
USART2 Receive Interrupt Enable, RC2IE......................... 32
USART2 Receive Interrupt Flag bit, RC2IF ........................ 34
USART2 Receive Interrupt Flag bit, TX2IF ......................... 34
USART2 Transmit Interrupt Enable, TX2IE ........................ 32
V
VDD ........................................................................... 225, 226
W
Wake-up from SLEEP ....................................................... 180
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 311
PIC17C75X
List of Equations and Examples
List of Figures
Example 3-1: Signed Math.................................................. 9
Example 4-1: Instruction Pipeline Flow ............................. 19
Example 6-1: Saving STATUS and WREG in RAM
(Simple) ...................................................... 37
Example 6-2: Saving STATUS and WREG in RAM
(Nested) ...................................................... 38
Example 7-1: Indirect Addressing ..................................... 51
Example 8-1: Table Write ................................................. 58
Example 8-2: Table Read ................................................. 60
Example 9-1: 8 x 8 Unsigned Multiply Routine ................. 61
Example 9-2: 8 x 8 Signed Multiply Routine ..................... 61
Equation 9-1: 16 x 16 Unsigned Multiplication Algorithm .. 62
Example 9-3: 16 x 16 Unsigned Multiply Routine ............. 62
Equation 9-2: 16 x 16 Signed Multiplication Algorithm ...... 63
Example 9-4: 16 x 16 Signed Multiply Routine ................. 63
Example 10-1: Initializing PORTA....................................... 66
Example 10-2: Initializing PORTB....................................... 69
Example 10-3: Initializing PORTC ...................................... 72
Example 10-4: Initializing PORTD ...................................... 74
Example 10-5: Initializing PORTE....................................... 76
Example 10-6: Initializing PORTF ....................................... 78
Example 10-7: Initializing PORTG ...................................... 80
Example 10-8: Read Modify Write Instructions on an
I/O Port ....................................................... 83
Example 12-1: 16-Bit Read ................................................. 89
Example 12-2: 16-Bit Write ................................................. 89
Example 13-1: Sequence to Read Capture Registers ...... 103
Example 13-2: Writing to TMR3 ........................................ 104
Example 13-3: Reading from TMR3 ................................. 104
Example 14-1: Calculating Baud Rate Error ..................... 110
Example 15-1: Loading the SSPBUF (SSPSR) Register.. 127
Equation 16-1: A/D Minimum Charging Time
(For CHOLD) .............................................. 170
Example 16-1: Calculating the Minimum Required
Acquisition Time ....................................... 171
Example 16-2: A/D Conversion......................................... 172
Figure 3-1:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 7-9:
Figure 7-10:
Figure 7-11:
Figure 7-12:
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 8-4:
Figure 8-5:
Figure 8-6:
Figure 8-7:
Figure 8-8:
DS30264A-page 312
Preliminary
PIC17C75X Block Diagram ........................ 10
Oscillator / Resonator Start-up
Characteristics............................................ 15
Crystal or Ceramic Resonator Operation
(XT or LF OSC Configuration) .................... 16
Crystal Operation, Overtone Crystals
(XT OSC Configuration) ............................. 16
External Clock Input Operation (EC OSC
Configuration) ............................................. 17
External Parallel Resonant Crystal
Oscillator Circuit ......................................... 17
External Series Resonant Crystal
Oscillator Circuit ......................................... 17
RC Oscillator Mode .................................... 18
Clock/Instruction Cycle ............................... 19
Simplified Block Diagram of On-chip
Reset Circuit ............................................... 21
Using On-Chip POR ................................... 22
External Power-On Reset Circuit
(For Slow VDD Power-Up) .......................... 22
Oscillator Start-Up Time ............................. 22
Time-Out Sequence on Power-Up
(MCLR Tied to VDD) ................................... 24
Time-Out Sequence on Power-Up
(MCLR NOT Tied to VDD)........................... 24
Slow Rise Time (MCLR Tied to VDD) ......... 24
External Brown-out Protection Circuit 1 ..... 28
External Brown-out Protection Circuit 2 ..... 28
Brown-out Situations .................................. 28
Interrupt Logic ............................................ 29
INTSTA Register (Address: 07h,
Unbanked) .................................................. 30
PIE1 Register (Address: 17h, Bank 1) ....... 31
PIE2 Register (Address: 11h, Bank 4) ....... 32
PIR1 Register (Address: 16h, Bank 1) ....... 33
PIR2 Register (Address: 10h, Bank 4) ....... 34
INT Pin / T0CKI Pin Interrupt Timing .......... 36
Program Memory Map and Stack............... 39
Memory Map in Different Modes ................ 40
External Program Memory Access
Waveforms ................................................. 41
Typical External Program Memory
Connection Diagram................................... 41
PIC17C75X Register File Map ................... 43
ALUSTA Register (Address: 04h,
Unbanked) .................................................. 47
CPUSTA Register (Address: 06h,
Unbanked) .................................................. 48
T0STA Register (Address: 05h,
Unbanked) .................................................. 49
Indirect Addressing..................................... 50
Program Counter Operation ....................... 52
Program Counter using The CALL and
GOTO Instructions ....................................... 52
BSR Operation ........................................... 53
TLWT Instruction Operation ........................ 55
TABLWT Instruction Operation .................... 55
TLRD Instruction Operation ........................ 56
TABLRD Instruction Operation .................... 56
TABLWT Write Timing (External Memory)... 58
Consecutive TABLWT Write Timing
(External Memory) ...................................... 59
TABLRD Timing........................................... 60
TABLRD Timing (Consecutive TABLRD
Instructions) ................................................ 60
1997 Microchip Technology Inc.
PIC17C75X
Figure 10-1:
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 10-5:
Figure 10-6:
Figure 10-7:
Figure 10-8:
Figure 10-9:
Figure 10-10:
Figure 10-11:
Figure 10-12:
Figure 10-13:
Figure 10-14:
Figure 10-15:
Figure 10-16:
Figure 10-17:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
Figure 13-7:
Figure 13-8:
Figure 13-9:
Figure 13-10:
Figure 13-11:
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Figure 14-5:
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 14-10:
Figure 14-11:
Figure 15-1:
Figure 15-2:
Figure 15-3:
Figure 15-4:
RA0 and RA1 Block Diagram ..................... 65
RA2 Block Diagram .................................... 66
RA3 Block Diagram .................................... 66
RA4 and RA5 Block Diagram ..................... 66
Block Diagram of RB5:RB4 and RB1:RB0
Port Pins ..................................................... 68
Block Diagram of RB3:RB2 Port Pins......... 69
Block Diagram of RB6 Port Pin................... 70
Block Diagram of RB7 Port Pin................... 70
Block Diagram of RC7:RC0 Port Pins ........ 72
Block Diagram of RD7:RD0 Port Pins
(in I/O Port Mode) ....................................... 74
Block Diagram of RE2:RE0 (in I/O Port
Mode).......................................................... 76
Block Diagram of RE3/CAP4 Port Pin ........ 77
Block Diagram of RF7:RF0......................... 78
Block Diagram of RG3:RG0........................ 80
RG4 Block Diagram .................................... 81
RG7:RG5 Block Diagram............................ 81
Successive I/O Operation ........................... 83
T0STA Register (Address: 05h,
Unbanked) .................................................. 87
Timer0 Module Block Diagram ................... 88
TMR0 Timing with External Clock
(Increment on Falling Edge) ....................... 88
TMR0 Timing: Write High or Low Byte ....... 89
TMR0 Read/Write in Timer Mode ............... 90
TCON1 Register (Address: 16h, Bank 3) ... 91
TCON2 Register (Address: 17h, Bank 3) ... 92
TCON3 Register (Address: 16h, Bank 7) ... 93
Timer1 and Timer2 in Two 8-bit Timer/
Counter Mode ............................................. 94
TMR2 and TMR1 in 16-bit Timer/Counter
Mode........................................................... 95
Simplified PWM Block Diagram .................. 97
PWM Output ............................................... 97
Timer3 with three Capture and One
Period Register Block Diagram................. 100
Timer3 with Four Captures Block
Diagram .................................................... 102
Timer1, Timer2, and Timer3 Operation
(in Counter Mode)..................................... 104
Timer1, Timer2, and Timer3 Operation
(in Timer Mode) ........................................ 105
TXSTA1 Register (Address: 15h, Bank 0)
TXSTA2 Register (Address: 15h, Bank 4) 107
RCSTA1 Register (Address: 13h, Bank 0)
RCSTA2 Register (Address: 13h, Bank 4) 108
USART Transmit....................................... 109
USART Receive........................................ 109
Asynchronous Master Transmission......... 114
Asynchronous Master Transmission
(Back to Back) .......................................... 114
RX Pin Sampling Scheme ........................ 115
Asynchronous Reception.......................... 116
Synchronous Transmission ...................... 118
Synchronous Transmission
(Through TXEN) ....................................... 118
Synchronous Reception (Master Mode,
SREN)....................................................... 119
SPI Mode Block Diagram.......................... 123
I2C Slave Mode Block Diagram ................ 123
I2C Master Mode Block Diagram .............. 123
SSPSTAT: Sync Serial Port Status
Register (Address: 13h, BANK 6) ............. 124
1997 Microchip Technology Inc.
Figure 15-5:
Figure 15-6:
Figure 15-7:
Figure 15-8:
Figure 15-9:
Figure 15-10:
Figure 15-11:
Figure 15-12:
Figure 15-13:
Figure 15-14:
Figure 15-15:
Figure 15-16:
Figure 15-17:
Figure 15-18:
Figure 15-19:
Figure 15-20:
Figure 15-21:
Figure 15-22:
Figure 15-23:
Figure 15-24:
Figure 15-25:
Figure 15-26:
Figure 15-27:
Figure 15-28:
Figure 15-29:
Figure 15-30:
Figure 15-31:
Figure 15-32:
Figure 15-33:
Figure 15-34:
Figure 15-35:
Figure 15-36:
Figure 15-37:
Figure 15-38:
Figure 15-39:
Figure 15-40:
Figure 15-41:
Figure 15-42:
Figure 15-43:
Figure 15-44:
Figure 15-45:
Figure 16-1:
Figure 16-2:
Preliminary
SSPCON1: Sync Serial Port Control
Register1 (Address 11h, BANK 6)............ 125
SSPCON2: Sync Serial Port Control
Register2 (Address 12h, BANK 6)........... 126
SSP Block Diagram (SPI Mode)............... 128
SPI Mode Timing (Master Mode) ............. 129
SPI Master/Slave Connection .................. 130
Slave Synchronization Timing .................. 131
SPI Mode Timing (Slave Mode with
CKE = 0)................................................... 132
SPI Mode Timing (Slave Mode with
CKE = 1)................................................... 133
SSP Block Diagram
(I2C Mode)................................................ 134
I2C Master Mode Block Diagram.............. 134
I2C Waveforms for Reception
(7-bit Address).......................................... 136
I2C Waveforms for Transmission
(7-bit Address).......................................... 136
I2C Slave-Transmitter (10-bit Address).... 137
I2C Slave-Receiver (10-bit Address)........ 138
General Call Address Sequence
(7 or 10-bit Mode)..................................... 139
SSP Block Diagram (I2C Master Mode) ... 141
Baud Rate Generator Block Diagram....... 143
Baud Rate Generator Timing With
Clock Arbitration ....................................... 143
First Start Bit Timing................................. 144
Start Condition FlowChart ........................ 145
Repeat Start Condition Timing ................. 146
Restart Condition FlowChart (page 1)...... 147
Restart Condition FlowChart (page 2)...... 148
Master Transmit FlowChart ...................... 150
I2C Master Mode Timing (Transmission,
7 or 10-bit Address).................................. 151
Master Receiver FlowChart...................... 153
I2C Master Mode Timing (Reception
7-Bit Address)........................................... 154
Acknowledge Sequence Timing ............... 155
Acknowledge FlowChart........................... 156
Stop Condition Receive or Transmit
Mode ........................................................ 157
Stop Condition FlowChart ........................ 158
Clock Arbitration Timing in Master
Transmit Mode ......................................... 159
Bus Collision Timing for Transmit and
Acknowledge ............................................ 160
Bus Collision During Start Condition
(SDA only) ................................................ 161
Bus Collision During Start Condition
(SCL = 0) .................................................. 162
BRG Reset Due to SDA Collision During
Start Condition.......................................... 162
Bus Collision During a Restart Condition
(Case 1).................................................... 163
Bus Collision During Restart Condition
(Case 2).................................................... 163
Bus Collision During a Stop Condition
(Case 1).................................................... 164
Bus Collision During a Stop Condition
(Case 2).................................................... 164
Sample device configuration for I2C bus .. 165
ADCON0 Register (Address: 14h,
Bank 5) ..................................................... 167
ADCON1 Register (Address 15h,
Bank 5) ..................................................... 168
DS30264A-page 313
PIC17C75X
Figure 16-3:
Figure 16-4:
Figure 16-5:
Figure 16-6:
Figure 16-7:
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
Figure 18-1:
Figure 18-2:
Figure 20-1:
Figure 20-2:
Figure 20-3:
Figure 20-4:
Figure 20-5:
Figure 20-6:
Figure 20-7:
Figure 20-8:
Figure 20-9:
Figure 20-10:
Figure 20-11:
Figure 20-12:
Figure 20-13:
Figure 20-14:
Figure 20-15:
Figure 20-16:
Figure 20-17:
Figure 20-18:
Figure 20-19:
Figure 21-1:
Figure 21-2:
Figure 21-3:
Figure 21-4:
Figure 21-5:
Figure 21-6:
Figure 21-7:
Figure 21-8:
Figure 21-9:
Figure 21-10:
Figure 21-11:
Figure 21-12:
Figure 21-13:
Figure 21-14:
Figure 21-15:
Figure 21-16:
Figure 21-17:
Figure 21-18:
Figure 21-19:
A/D Block Diagram ................................... 169
Analog Input Model................................... 170
A/D Result Justification ............................. 173
A/D Transfer Function............................... 174
Flowchart of A/D Operation ...................... 175
Configuration Words ................................. 177
Watchdog Timer Block Diagram ............... 179
Wake-up From Sleep Through Interrupt ... 180
Typical In-Circuit Serial Programming
Connection................................................ 182
General Format for Instructions ................ 184
Q Cycle Activity......................................... 185
Parameter Measurement Information ....... 231
External Clock Timing ............................... 232
CLKOUT and I/O Timing........................... 233
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer, and Brown-out
Reset Timing............................................. 234
Timer0 External Clock Timings ................. 235
Timer1, Timer2, and Timer3 External
Clock Timings ........................................... 235
Capture Timings ....................................... 236
PWM Timings ........................................... 236
SPI Master Mode Timing (CKE = 0) ......... 237
SPI Master Mode Timing (CKE = 1) ......... 238
SPI Slave Mode Timing (CKE = 0) ........... 239
SPI Slave Mode Timing (CKE = 1) ........... 240
I2C Bus Start/Stop Bits Timing.................. 241
I2C Bus Data Timing ................................. 242
USART Synchronous Transmission
(Master/Slave) Timing............................... 244
USART Synchronous Receive
(Master/Slave) Timing............................... 244
A/D Conversion Timing ............................. 246
Memory Interface Write Timing................. 247
Memory Interface Read Timing ................ 248
Typical RC Oscillator Frequency vs.
Temperature ............................................. 249
Typical RC Oscillator Frequency vs. VDD . 250
Typical RC Oscillator Frequency vs. VDD . 250
Typical RC Oscillator Frequency vs. VDD . 251
Transconductance (gm) of LF Oscillator
vs. VDD ...................................................... 252
Transconductance (gm) of XT Oscillator
vs. VDD ...................................................... 252
Typical IDD vs. Frequency (External
Clock 25°C)............................................... 253
Maximum IDD vs. Frequency (External Clock
125°C to -40°C) ........................................ 253
Typical IPD vs. VDD Watchdog Disabled
25°C.......................................................... 254
Maximum IPD vs. VDD Watchdog
Disabled .................................................... 254
Typical IPD vs. VDD Watchdog Enabled
25°C.......................................................... 255
Maximum IPD vs. VDD Watchdog
Enabled..................................................... 255
WDT Timer Time-Out Period vs. VDD ....... 256
IOH vs. VOH, VDD = 3V .............................. 256
IOH vs. VOH, VDD = 5V .............................. 257
IOL vs. VOL, VDD = 3V ............................... 257
IOL vs. VOL, VDD = 5V ............................... 258
VTH (Input Threshold Voltage) of I/O Pins
(TTL) VS. VDD ............................................ 258
VIH, VIL of I/O Pins (Schmitt Trigger) VS.
VDD ........................................................... 259
DS30264A-page 314
Figure 21-20: VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD ....... 259
Figure E-1:
Start and Stop Conditions ........................ 267
Figure E-2:
7-bit Address Format ................................ 268
Figure E-3:
I2C 10-bit Address Format........................ 268
Figure E-4:
Slave-receiver Acknowledge .................... 268
Figure E-5:
Data Transfer Wait State .......................... 268
Figure E-6:
Master-transmitter Sequence ................... 269
Figure E-7:
Master-receiver Sequence ....................... 269
Figure E-8:
Combined Format..................................... 269
Figure E-9:
Multi-master Arbitration
(Two Masters) .......................................... 270
Figure E-10: Clock Synchronization .............................. 270
Figure E-11: I2C Bus Start/Stop Bits Timing
Specification ............................................. 271
Figure E-12: I2C Bus Data Timing Specification .......... 272
Figure F-1:
PIC17C75X Register File Map ................. 273
Figure F-2:
ALUSTA Register (Address: 04h,
Unbanked) ................................................ 274
Figure F-3:
T0STA Register (Address: 05h,
Unbanked) ................................................ 275
Figure F-4:
CPUSTA Register (Address: 06h,
Unbanked) ................................................ 276
Figure F-5:
INTSTA Register (Address: 07h,
Unbanked) ................................................ 277
Figure F-6:
PIE1 Register (Address: 17h, Bank 1) ..... 278
Figure F-7:
PIE2 Register (Address: 11h, Bank 4) ..... 279
Figure F-8:
PIR1 Register (Address: 16h, Bank 1) ..... 280
Figure F-9:
PIR2 Register (Address: 10h, Bank 4) ..... 281
Figure F-10: TXSTA1 Register (Address: 15h, Bank 0)
TXSTA2 Register (Address: 15h,
Bank 4) ..................................................... 282
Figure F-11: RCSTA1 Register (Address: 13h,
Bank 0)
RCSTA2 Register (Address: 13h,
Bank 4) ..................................................... 283
Figure F-12: TCON1 Register (Address: 16h,
Bank 3) ..................................................... 284
Figure F-13: TCON2 Register (Address: 17h,
Bank 3) ..................................................... 285
Figure F-14: TCON3 Register (Address: 16h,
Bank 7) ..................................................... 286
Figure F-15: ADCON0 Register (Address: 14h,
Bank 5) ..................................................... 287
Figure F-16: ADCON1 Register (Address 15h,
Bank 5) ..................................................... 288
Figure F-17: SSPSTAT: Sync Serial Port Status
Register (Address: 13h, BANK 6)............. 289
Figure F-18: SSPCON1: Sync Serial Port Control
Register (Address 11h, BANK 6).............. 290
Figure F-19: SSPCON2: Sync Serial Port Control
Register2 (Address 12h, BANK 6)........... 291
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
List of Tables
Table 1-1:
Table 2-1:
Table 3-1:
Table 4-1:
Table 4-2:
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 6-1:
Table 7-1:
Table 7-2:
Table 7-3:
Table 8-1:
Table 9-1:
Table 10-1:
Table 10-2:
Table 10-3:
Table 10-4:
Table 10-5:
Table 10-6:
Table 10-7:
Table 10-8:
Table 10-9:
Table 10-10:
Table 10-11:
Table 10-12:
Table 10-13:
Table 10-14:
Table 12-1:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 14-1:
Table 14-2:
Table 14-3:
Table 14-4:
Table 14-5:
Table 14-6:
Table 14-7:
Table 14-8:
Table 14-9:
Table 14-10:
Table 14-11:
Table 15-1:
Table 15-2:
Table 15-3:
Table 16-1:
PIC17CXXX Family of Devices..................... 6
Device Memory Varieties.............................. 7
Pinout Descriptions..................................... 11
Capacitor Selection for Ceramic
Resonators ................................................. 16
Capacitor Selection for Crystal Oscillator ... 16
Time-Out in Various Situations ................... 23
STATUS Bits and Their Significance .......... 23
Reset Condition for the Program Counter
and the CPUSTA Register.......................... 23
Initialization Conditions For Special
Function Registers...................................... 25
Interrupt Vectors/Priorities .......................... 35
Mode Memory Access ................................ 40
EPROM Memory Access Time Ordering
Suffix........................................................... 41
Special Function Registers ......................... 44
Interrupt - Table Write Interaction ............... 57
Performance Comparison........................... 61
PORTA Functions....................................... 67
Registers/Bits Associated with PORTA ...... 67
PORTB Functions....................................... 71
Registers/Bits Associated with PORTB ...... 71
PORTC Functions....................................... 73
Registers/Bits Associated with PORTC ...... 73
PORTD Functions....................................... 75
Registers/Bits Associated with PORTD ...... 75
PORTE Functions....................................... 77
Registers/Bits Associated with PORTE ...... 77
PORTF Functions ....................................... 79
Registers/bits Associated With PORTF ...... 79
PORTG Functions ...................................... 82
Registers/bits Associated With PORTG ..... 82
Registers/Bits Associated with Timer0 ....... 90
Time-base Function / Resource
Requirements ............................................. 91
Turning On 16-bit Timer.............................. 95
Summary of Timer1 and Timer2
Registers..................................................... 96
PWM Frequency vs. Resolution
at 33 MHz ................................................... 98
Registers/Bits Associated with PWM.......... 99
Registers Associated with Capture........... 103
USART Module Generic Names............... 107
Baud Rate Formula................................... 110
Registers Associated with Baud Rate
Generator.................................................. 110
Baud Rates for Synchronous Mode.......... 111
Baud Rates for Asynchronous Mode ........ 112
Registers Associated with
Asynchronous Transmission..................... 114
Registers Associated with
Asynchronous Reception.......................... 116
Registers Associated with Synchronous
Master Transmission ................................ 118
Registers Associated with Synchronous
Master Reception...................................... 120
Registers Associated with Synchronous
Slave Transmission .................................. 122
Registers Associated with Synchronous
Slave Reception........................................ 122
Registers Associated with SPI
Operation .................................................. 133
Data Transfer Received Byte Actions....... 135
Registers Associated with I2C Operation.. 140
1997 Microchip Technology Inc.
Table 16-2:
Table 16-3:
Table 17-1:
Table 17-2:
Table 17-3:
Table 18-1:
Table 18-2:
Table 19-1:
Table 20-1:
Table 20-2:
Table 20-3:
Table 20-4:
Table 20-5:
Table 20-6:
Table 20-7:
Table 20-8:
Table 20-9:
Table 20-10:
Table 20-11:
Table 20-12:
Table 20-13:
Table 20-14:
Table 20-15:
Table 20-16:
Table 20-17:
Table 20-18:
Table 20-19:
Table 20-20:
Table 21-1:
Table 21-2:
Table E-1:
Table E-2:
Table E-3:
TABLE G-1:
Preliminary
TAD vs. Device Operating Frequencies
(Standard devices (C)) ............................. 171
TAD vs. Device Operating Frequencies
(Extended Voltage devices (LC)) ............. 171
Registers/bits Associated with A/D........... 175
Configuration Locations............................ 178
Registers/Bits Associated with the
Watchdog Timer ....................................... 179
ISP Interface Pins..................................... 182
Opcode Field Descriptions ....................... 183
PIC17CXXX Instruction Set...................... 186
development tools from microchip............ 222
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices) ......... 224
External Clock Timing Requirements ....... 232
CLKOUT and I/O Timing Requirements... 233
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer, and
Brown-out Reset Requirements ............... 234
Timer0 External Clock Requirements....... 235
Timer1, Timer2, and Timer3 External
Clock Requirements ................................. 235
Capture Requirements ............................. 236
PWM Requirements ................................. 236
SPI Mode Requirements (Master Mode,
CKE = 0)................................................... 237
SPI Mode Requirements (Master Mode,
CKE = 1)................................................... 238
SPI Mode Requirements (Slave Mode
Timing (CKE = 0)...................................... 239
SPI Mode Requirements (Slave Mode,
CKE = 1)................................................... 240
I2C Bus Start/Stop Bits Requirements...... 241
I2C Bus Data Requirements ..................... 243
USART Synchronous Transmission
Requirements ........................................... 244
USART Synchronous Receive
Requirements ........................................... 244
A/D Converter Characteristics:
PIC17LC752/756-08 (Commercial, Industrial)
PIC17C752/756-25 (Commercial, Industrial)
PIC17C752/756-33 (Commercial,
Industrial).................................................. 245
A/D Conversion Requirements................. 246
Memory Interface Write Requirements..... 247
Memory Interface read Requirements...... 248
Pin Capacitance per Package Type ......... 249
RC Oscillator Frequencies ....................... 251
I2C Bus Terminology ................................ 267
I2C Bus Start/Stop Bits Timing Specification...
271
I2C Bus Data Timing Specification .......... 272
Pin Compatible Devices ........................... 302
DS30264A-page 315
PIC17C75X
NOTES:
DS30264A-page 316
Preliminary
1997 Microchip Technology Inc.
PIC17C75X
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
errata sheets, bug reports, and interim patches for
Microchip systems software products. For each SIG, a
moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files
are accepted from the user community in general to
limit the spread of computer viruses.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the
address: mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense. The
Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
1997 Microchip Technology Inc.
Systems Information and Upgrade Hot Line
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
970301
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. FlexROM, MPLAB and fuzzyLAB, are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
DS30264A-page 317
PIC17C75X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC17C75X
Y
N
Literature Number: DS30264A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30264A-page 318
1997 Microchip Technology Inc.
PIC17C75X
PIC17C75X Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO. – XX X /XX XXX
Pattern:
Package:
Temperature
Range:
Frequency
Range:
Device:
Examples
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices
P
= PDIP
JW
= Windowed CERDIP
P
= PDIP (600 mil)
PQ
= MQFP
PT
= TQFP
L
= PLCC
–
= 0˚C to +70˚C
I
= –40˚C to +85˚C
08
= 8 MHz
25
= 25 MHz
33
= 33 MHz
PIC17C756
PIC17C756T
PIC17LC756
: Standard VDD range
: (Tape and Reel)
: Extended VDD range
a)
PIC17C756 – 25/P
Commercial Temp.,
PDIP package,
25 MHz,
normal VDD limits
b)
PIC17LC756–08/PT
Commercial Temp.,
TQFP package,
8MHz,
extended VDD limits
c)
PIC17C756–33I/P
Industrial Temp.,
PDIP package,
33 MHz,
normal VDD limits
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. The Microchip Website at www.microchip.com
2. Your local Microchip sales office (see following page)
3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
4. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 319
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
India
Denmark
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Korea
Germany
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.