MICROCHIP PIC16F87X_98

M
PIC16F87X
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Microcontroller Core Features:
Pin Diagram
 1998 Microchip Technology Inc.
PDIP
MCLR/VPP/THV
RA0/AN0
1
40
2
39
RB7/PGD
RB6/PGC
RA1/AN1
RA2/AN2/VREF-
3
38
RB5
4
37
RA3/AN3/VREF+
5
36
RB4
RB3/PGM
RA4/T0CKI
6
35
RB2
RA5/AN4/SS
7
34
RB1
RE0/RD/AN5
8
33
RB0/INT
RE1/WR/AN6
9
10
32
31
VDD
30
RD7/PSP7
29
28
RD6/PSP6
RD5/PSP5
RE2/CS/AN7
VDD
11
VSS
12
OSC1/CLKIN
13
PIC16F877/874
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM data memory
★ • Pinout compatible to the PIC16C73/74/76/77
• Interrupt capability (up to 14 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming via two pins
★ • Only single 5V source needed for programming
★ • In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
VSS
OSC2/CLKOUT
14
27
RD4/PSP4
RC0/T1OSO/T1CKI
15
26
RC7/RX/DT
RC1/T1OSI/CCP2
16
25
RC6/TX/CK
RC2/CCP1
17
24
RC5/SDO
RC3/SCK/SCL
RD0/PSP0
18
23
19
20
22
21
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit
★ • 10-bit multi-channel Analog-to-Digital converter
★ • Synchronous Serial Port (SSP) with SPI (Master
Mode) and I2C (Master/Slave)
★ • Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Preliminary
DS30292A-page 1
PIC16F87X
Pin Diagrams
PLCC
PIC16F877
PIC16F874
39
38
37
36
35
34
33
32
31
30
9
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
44
43
42
41
40
39
38
37
36
35
34
QFP
7
8
9
10
11
12
13
14
15
16
17
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP/THV
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
6
5
4
3
2
1
44
43
42
41
40
28
27
26
25
24
23
22
21
20
19
18
17
16
15
18
19
20
21
22
23
24
25
26
27
282
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
PIC16F876/873
DIP, SOIC
PIC16F877
PIC16F874
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4
RA4/T0CKI
NC
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
DS30292A-page 2
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
Key Features
PICmicro™ Mid-Range Reference
Manual (DS33023)
PIC16F873
PIC16F874
PIC16F876
PIC16F877
Operating Frequency
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
Resets (and Delays)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
FLASH Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
368
368
EEPROM Data Memory
128
128
256
256
Interrupts
13
14
13
14
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM modules
2
2
2
2
Serial Communications
MSSP, USART
MSSP, USART
MSSP, USART
MSSP, USART
Parallel Communications
—
PSP
—
PSP
10-bit Analog-to-Digital Module
5 input channels
8 input channels
5 input channels
8 input channels
Instruction Set
35 Instructions
35 Instructions
35 Instructions
35 Instructions
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 3
PIC16F87X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................. 11
3.0 I/O Ports ..................................................................................................................................................................................... 29
4.0 Data EEPROM and FLASH Program Memory .......................................................................................................................... 41
5.0 Timer0 Module ........................................................................................................................................................................... 47
6.0 Timer1 Module ........................................................................................................................................................................... 49
7.0 Timer2 Module .......................................................................................................................................................................... 53
8.0 Capture/Compare/PWM (CCP) Module(s) ................................................................................................................................. 55
9.0 Master Synchronous Serial Port (MSSP) Module ...................................................................................................................... 61
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................................... 105
11.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 121
12.0 Special Features of the CPU.................................................................................................................................................... 133
13.0 Instruction Set Summary .......................................................................................................................................................... 151
14.0 Development Support............................................................................................................................................................... 153
15.0 Electrical Characteristics .......................................................................................................................................................... 157
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 177
17.0 Packaging Information.............................................................................................................................................................. 179
Appendix A: Revision History......................................................................................................................................................... 187
Appendix B: Device Differences..................................................................................................................................................... 187
Appendix C: Conversion Considerations........................................................................................................................................ 187
Index .................................................................................................................................................................................................. 191
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS30292A-page 4
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
1.0
DEVICE OVERVIEW
There a four devices (PIC16F873, PIC16F874,
PIC16F876, and PIC16F877) covered by this data
sheet. The PIC16F876/873 devices come in 28-pin
packages and the PIC16F877/874 devices come in 40pin packages. The 28-pin devices do not have a Parallel Slave Port implemented.
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
FIGURE 1-1:
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data EEPROM
PIC16F873
4K
192 Bytes
128 Bytes
PIC16F876
8K
368 Bytes
256 Bytes
13
Program
Memory
PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
FLASH
14
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
MUX
ALU
Power-on
Reset
PORTC
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
W reg
Low-Voltage
Programming
MCLR
Timer0
Data EEPROM
VDD, VSS
Timer1
Timer2
10-bit A/D
CCP1,2
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 5
PIC16F87X
FIGURE 1-2:
PIC16F874 AND PIC16F877 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data EEPROM
PIC16F874
4K
192 Bytes
128 Bytes
PIC16F877
8K
368 Bytes
256 Bytes
13
Program
Memory
14
PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
FLASH
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Brown-out
Reset
OSC1/CLKIN
OSC2/CLKOUT
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MUX
ALU
Power-on
Reset
8
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
PORTD
W reg
RD7/PSP7:RD0/PSP0
In-Circuit
Debugger
Low-Voltage
Programming
Parallel Slave Port
PORTE
RE0/AN5/RD
RE1/AN6/WR
MCLR
Timer0
Data EEPROM
VDD, VSS
RE2/AN7/CS
Timer1
Timer2
10-bit A/D
CCP1,2
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30292A-page 6
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 1-1
PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
OSC1/CLKIN
9
9
I
OSC2/CLKOUT
10
10
O
MCLR/VPP/THV
1
1
I/P
RA0/AN0
2
2
I/O
RA1/AN1
RA2/AN2/VREF-
3
3
I/O
TTL
RA1 can also be analog input1
4
4
I/O
TTL
RA3/AN3/VREF+
5
5
I/O
TTL
RA4/T0CKI
6
6
I/O
ST
RA2 can also be analog input2 or negative analog reference voltage
RA3 can also be analog input3 or positive analog reference voltage
RA4 can also be the clock input to the Timer0 module. Output is open drain type.
RA5/SS/AN4
7
7
I/O
TTL
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
21
22
23
24
25
26
27
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST(1)
TTL
TTL
TTL
TTL
TTL
TTL/ST(2)
Pin Name
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
TTL
RA0 can also be analog input0
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD
28
28
I/O
TTL/ST(2)
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
11
11
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2
12
12
I/O
ST
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1
13
13
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
14
14
I/O
ST
RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA
15
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
17
17
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
20
P
—
Positive supply for logic and I/O pins.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 7
PIC16F87X
TABLE 1-2
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
OSC1/CLKIN
13
14
30
I
OSC2/CLKOUT
14
15
31
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP/THV
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input or
high voltage test mode control. This pin is an active low
reset to the device.
Pin Name
Buffer
Type
Description
ST/CMOS(4) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA0/AN0
2
3
19
I/O
TTL
RA0 can also be analog input0
RA1/AN1
3
4
20
I/O
TTL
RA1 can also be analog input1
RA2/AN2/VREF-
4
5
21
I/O
TTL
RA2 can also be analog input2 or negative analog reference voltage
RA3/AN3/VREF+
5
6
22
I/O
TTL
RA3 can also be analog input3 or positive analog reference voltage
RA4/T0CKI
6
7
23
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4
7
8
24
I/O
TTL
RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
33
36
8
I/O
TTL/ST(1)
RB1
34
37
9
I/O
TTL
RB2
35
38
10
I/O
TTL
RB3/PGM
36
39
11
I/O
TTL
RB3 can also be the low voltage programming input
RB4
37
41
14
I/O
TTL
Interrupt on change pin.
RB5
38
42
15
I/O
TTL
Interrupt on change pin.
(2)
RB6/PGC
39
43
16
I/O
TTL/ST
RB7/PGD
40
44
17
I/O
TTL/ST(2)
Legend:
Note 1:
2:
3:
4:
RB0 can also be the external interrupt pin.
Interrupt on change pin or In-Circuit Debugger pin.
Serial programming clock.
Interrupt on change pin or In-Circuit Debugger pin.
Serial programming data.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30292A-page 8
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 1-2
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (Cont.’d)
Pin Name
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
15
16
32
I/O
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2
16
18
35
I/O
ST
RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1
17
19
36
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
18
20
37
I/O
ST
RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA
23
25
42
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
24
26
43
I/O
ST
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
25
27
44
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
19
21
38
I/O
ST/TTL(3)
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
20
21
22
27
28
29
30
22
23
24
30
31
32
33
39
40
41
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
RE0/RD/AN5
8
9
25
I/O
ST/TTL(3)
RE0 can also be read control for the parallel slave port,
or analog input5.
RE1/WR/AN6
9
10
26
I/O
ST/TTL(3)
RE1 can also be write control for the parallel slave port,
or analog input6.
RE2/CS/AN7
10
11
27
I/O
ST/TTL(3)
12,31
11,32
—
13,34
12,35
1,17,28,
40
6,29
7,28
12,13,
33,34
P
P
—
—
—
RE2 can also be select control for the parallel slave
port, or analog input7.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
These pins are not internally connected. These pins should
be left unconnected.
PORTE is a bi-directional I/O port.
VSS
VDD
NC
Legend: I = input
Note 1:
2:
3:
4:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 9
PIC16F87X
NOTES:
DS30292A-page 10
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.0
MEMORY ORGANIZATION
FIGURE 2-2:
There are three memory blocks in each of these PICmicros. The Program Memory and Data Memory have
separate buses so that concurrent access can occur
and is detailed in this section. The EEPROM data
memory block is detailed in Section 4.0.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1
PIC16F874/873 PROGRAM
MEMORY MAP AND STACK
Stack Level 1
Stack Level 2
Program Memory Organization
The PIC16F87X PICmicros have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F877/876 devices have 8K
x 14 words of FLASH program memory and the
PIC16F873/874 devices have 4K x 14. Accessing a
location above the physically implemented address will
cause a wraparound.
Stack Level 8
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PIC16F877/876 PROGRAM
MEMORY MAP AND STACK
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip
Program
Memory
Page 0
07FFh
0800h
Page 1
0FFFh
PC<12:0>
1000h
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
1FFFh
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
On-chip
Program
Memory
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 11
PIC16F87X
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1
RP0
= 00 →
= 01 →
= 10 →
= 11 →
Bank0
Bank1
Bank2
Bank3
(STATUS<6:5>)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
Note:
2.2.1
EEPROM Data Memory description can
be found in Section 7.0 of this Data Sheet
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR.
DS30292A-page 12
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 2-3:
PIC16F877/876 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD (1)
PORTE (1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
Indirect addr.(*)
80h
OPTION_REG 81h
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
86h
TRISB
87h
TRISC
TRISD (1)
88h
TRISE (1)
89h
8Ah
PCLATH
8Bh
INTCON
8Ch
PIE1
8Dh
PIE2
8Eh
PCON
8Fh
90h
91h
SSPCON2
92h
PR2
93h
SSPADD
94h
SSPSTAT
95h
96h
97h
98h
TXSTA
99h
SPBRG
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
A0h
General
Purpose
Register
80 Bytes
96 Bytes
accesses
70h-7Fh
7Fh
Bank 0
EFh
F0h
FFh
Bank 1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
10Dh
EEADR
10Eh
EEDATH
10Fh
EEADRH
110h
111h
112h
113h
114h
115h
116h
General
117h
Purpose
118h
Register
119h
16 Bytes
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
Bank 2
16Fh
170h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
General
Purpose
Register
16 Bytes
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
80 Bytes
accesses
70h - 7Fh
17Fh
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2: These registers are reserved, maintain these registers clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 13
PIC16F87X
FIGURE 2-4:
PIC16F874/873 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD (1)
PORTE (1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
80h
OPTION_REG 81h
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
86h
TRISB
87h
TRISC
TRISD (1)
88h
TRISE (1)
89h
8Ah
PCLATH
8Bh
INTCON
8Ch
PIE1
PIE2
8Dh
8Eh
PCON
8Fh
90h
SSPCON2
91h
92h
PR2
93h
SSPADD
94h
SSPSTAT
95h
96h
97h
98h
TXSTA
99h
SPBRG
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
96 Bytes
96 Bytes
7Fh
Bank 0
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
accesses
20h-7Fh
1EFh
1F0h
16Fh
170h
17Fh
FFh
Bank 1
accesses
A0h - FFh
Bank 2
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2: These registers are reserved, maintain these registers clear.
DS30292A-page 14
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 15
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h(4)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h(5)
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
09h(5)
PORTE
—
—
—
0Ah(1,4)
PCLATH
—
—
—
0Bh(4)
INTCON
0Ch
PIR1
Indirect data memory address pointer
—
—
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
—
—
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PSPIF(3)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
—
(6)
—
EEIF
BCLIF
—
—
CCP2IF
-r-0 0--0 -r-0 0--0
0Dh
PIR2
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
—
—
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN T1SYNC
TMR1CS TMR1ON --00 0000 --uu uuuu
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 module’s register
—
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
SSPM0
0000 0000 0000 0000
CCP1M0 --00 0000 --00 0000
RX9D
0000 000x 0000 000x
1Bh
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
1Eh
ADRESH
1Fh
ADCON0
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0 --00 0000 --00 0000
A/D Result Register High Byte
ADCS1
ADCS0
CHS2
xxxx xxxx uuuu uuuu
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the
PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
3:
4:
5:
6:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
PIR2<6> and PIE2<6> are reserved on these devices, always maintain these bits clear.
DS30292A-page 16
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 1
80h(4)
INDF
81h
OPTION_RE
G
82h(4)
83h
PCL
(4)
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
STATUS
84h(4)
FSR
85h
TRISA
86h
TRISB
IRP
RP1
RP0
—
1111 1111 1111 1111
0000 0000 0000 0000
TO
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
89h(5)
TRISE
IBF
OBF
IBOV
8Ah(1,4)
PCLATH
—
—
—
8Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
(6)
—
EEIE
BCLIE
—
—
CCP2IE
-r-0 0--0 -r-0 0--0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
SSPCON2
92h
PR2
GCEN
ACKSTAT
ACKDT
PSPMODE
—
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
ACKEN
RCEN
PEN
RSEN
SEN
Timer2 Period Register
93h
SSPADD
94h
SSPSTAT
Synchronous Serial Port (I C mode) Address Register
CKE
0000 0000 0000 0000
1111 1111 1111 1111
2
SMP
0000 -111 0000 -111
---0 0000 ---0 0000
D/A
P
0000 0000 0000 0000
S
R/W
UA
BF
0000 0000 0000 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
Unimplemented
—
—
97h
—
98h
TXSTA
99h
SPBRG
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 -010 0000 -010
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
—
—
9Dh
—
9Eh
ADRESL
9Fh
ADCON1
Unimplemented
A/D Result Register Low Byte
ADFM
—
—
xxxx xxxx uuuu uuuu
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- 0000
--0- 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the
PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
3:
4:
5:
6:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
PIR2<6> and PIE2<6> are reserved on these devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 17
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
101h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
102h(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
103h(4)
STATUS
104h(4)
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
105h
—
106h
PORTB
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
—
Unimplemented
—
—
109h
(1,4)
Unimplemented
—
PORTB Data Latch when written: PORTB pins when read
PCLATH
—
—
—
10Bh(4)
INTCON
GIE
PEIE
T0IE
10Ch
EEDATA
EEPROM data register
10Dh
EEADR
EEPROM address register
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
10Ah
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
—
xxxx xxxx uuuu uuuu
T0IF
INTF
RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM data register high byte
—
xxxx xxxx uuuu uuuu
EEPROM address register high byte
xxxx xxxx uuuu uuuu
Bank 3
180h(4)
INDF
181h
OPTION_RE
G
182h(4)
PCL
183h(4)
STATUS
184h(4)
FSR
185h
Addressing this location uses contents of FSR to address data memory (not a physical register)
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
TRISB
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
186h
RBPU
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
Unimplemented
—
PORTB Data Direction Register
—
1111 1111 1111 1111
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
Write Buffer for the upper 5 bits of the Program
Counter
---0 0000 ---0 0000
18Ah(1,4)
PCLATH
—
—
—
18Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
18Ch
EECON1
EEPGD
—
—
—
WRERR
WREN
WR
RD
x--- x000 x--- u000
18Dh
EECON2
EEPROM control register2 (not a physical register)
---- ---- ---- ----
18Eh
—
Reserved maintain clear
0000 0000 0000 0000
18Fh
—
Reserved maintain clear
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the
PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
3:
4:
5:
6:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
PIR2<6> and PIE2<6> are reserved on these devices, always maintain these bits clear.
DS30292A-page 18
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.2.2.1
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
STATUS REGISTER
The STATUS register, shown in Figure 2-5, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
FIGURE 2-5:
R/W-0
IRP
bit7
bit 7:
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 19
PIC16F87X
2.2.2.2
OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-6:
R/W-1
RBPU
bit7
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R/W-1
PS0
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30292A-page 20
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.2.2.3
INTCON REGISTER
The INTCON Register is a readable and writable register which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 2-7:
R/W-0
GIE
bit7
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 21
PIC16F87X
2.2.2.4
PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-8:
R/W-0
PSPIE
bit7
(1)
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
Note 1: PSPIE is reserved on 28-pin devices, always maintain this bit clear.
DS30292A-page 22
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 2-9:
R/W-0
PSPIF(1)
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
ADIF
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
R= Readable bit
W= Writable bit
- n= Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 7:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave
A transmission/reception has taken place.
I2C Master
A transmission/reception has taken place.
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = No SSP interrupt condition has occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is reserved on 28-pin devices, always maintain this bit clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 23
PIC16F87X
2.2.2.6
PIE2 REGISTER
This register contains the individual enable bits for the
CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
FIGURE 2-10: PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
bit7
R/W-0
(1)
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
U-0
—
bit 7:
Unimplemented: Read as '0'
bit 6:
Reserved: Always maintain this bit clear
bit 5:
Unimplemented: Read as '0'
bit 4:
EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3:
BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
U-0
—
R/W-0
CCP2IE
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-1: Unimplemented: Read as '0'
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note 1: PIE2<6> is reserved, always maintain this bit clear.
DS30292A-page 24
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.2.2.7
PIR2 REGISTER
.
This register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM
write operation interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
U-0
—
R/W-0
CCP2IF
bit0
FIGURE 2-11: PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
bit7
R/W-0
(1)
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
U-0
—
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
Reserved: Always maintain this bit clear
bit 5:
Unimplemented: Read as '0'
bit 4:
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3:
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I2C master mode
0 = No bus collision has occurred
bit 2-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
Note 1: PIR2<6> is reserved, always maintain this bit clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 25
PIC16F87X
2.2.2.8
PCON REGISTER
Note:
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
BOR is unknown on Power-on Reset if the
BOR circuit is disabled by clearing the
BODEN bit in Configuration Word. The
BOR status bit is a don't care and is not
necessarily predictable if the brown-out circuit is disabled.
FIGURE 2-12: PCON REGISTER (ADDRESS 8Eh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-1
BOR
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30292A-page 26
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
2.3
PCL and PCLATH
2.4
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
2.3.1
STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Program Memory Paging
PIC16F87X devices are capable of addressing a continuous 8K word block of program memory. The CALL
and GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper 2 bits
of the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is pushed onto the stack. Therefore,
manipulation of the PCLATH<4:3> bits are not required
for the return instructions (which POPs the address
from the stack).
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 27
PIC16F87X
EXAMPLE 2-2:
movlw
movwf
clrf
incf
btfss
goto
NEXT
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-13.
FIGURE 2-13: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
RP1: RP0
6
bank select
location select
0
IRP
7
bank select
00
01
10
FSR register
0
location select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-3.
DS30292A-page 28
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
3.0
I/O PORTS
FIGURE 3-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™
Mid-Range
Reference
Manual,
(DS33023).
Data
bus
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
D
Q
VDD
WR
Port
Q
CK
P
Data Latch
3.1
PORTA and the TRISA Register
D
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
WR
TRIS
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note:
TRIS Latch
Q
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 3-2:
INITIALIZING PORTA
STATUS, RP0
PORTA
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
D
EN
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
BCF
CLRF
TTL
input
buffer
RD TRIS
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
EXAMPLE 3-1:
I/O pin(1)
VSS
Analog
input
mode
Q
CK
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
N
Q
Data
bus
WR
PORT
D
Q
CK
Q
N
I/O pin(1)
Data Latch
WR
TRIS
Initialize PORTA by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as '0'.
BLOCK DIAGRAM OF RA4/
T0CKI PIN
D
Q
CK
Q
Vss
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 29
PIC16F87X
TABLE 3-1
PORTA FUNCTIONS
Name
Bit#
Buffer
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Function
Input/output or analog input
Input/output or analog input
Input/output or analog input
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
Bit 7
Bit 6
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1
ADFM
—
Bit 5
RA5
Bit 4
Bit 3
RA4
RA3
Bit 2
RA2
Bit 1
RA1
Value on:
POR,
BOR
Bit 0
RA0
PORTA Data Direction Register
—
—
PCFG3
PCFG2
PCFG1
PCFG0
Value on all
other resets
--0x 0000
--0u 0000
--11 1111
--11 1111
--0- 0000
--0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS30292A-page 30
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
Three pins of PORTB are multiplexed with the Low Voltage Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Special Features Section.
EXAMPLE 3-1:
INITIALIZING PORTB
BCF
CLRF
STATUS, RP0
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
;
;
;
;
;
;
;
;
;
;
;
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
b)
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3:
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
BLOCK DIAGRAM OF
RB3:RB0 PINS
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-4:
VDD
RBPU(2)
Data bus
WR Port
Data bus
WR Port
weak
P pull-up
I/O
pin(1)
TRIS Latch
D
Q
WR TRIS
WR TRIS
Data Latch
D
Q
CK
weak
P pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
VDD
RBPU(2)
BLOCK DIAGRAM OF
RB7:RB4 PINS
TTL
Input
Buffer
CK
RD TRIS
Q
TTL
Input
Buffer
CK
Q1
Set RBIF
From other
RB7:RB4 pins
RD TRIS
Q
Latch
D
EN
RD Port
ST
Buffer
Q
D
RD Port
EN
D
Q3
RB7:RB6 in serial programming mode
RD Port
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
RB0/INT
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 31
PIC16F87X
TABLE 3-3
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3/PGM
bit3
TTL
Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6/PGC
bit6
Input/output pin (with interrupt on change) or In-Circuit Debugger pin. InterTTL/ST(2)
nal software programmable weak pull-up. Serial programming clock.
RB7/PGD
bit7
Input/output pin (with interrupt on change) or In-Circuit Debugger pin. InterTTL/ST(2)
nal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
RB0/INT
bit0
TTL/ST(1)
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h
PORTB
86h, 186h
TRISB
81h, 181h
OPTION_
REG
Bit 7
RB7
Bit 6
RB6
Bit 5
Bit 4
RB5
RB4
Value on:
Bit 3 Bit 2 Bit 1 Bit 0 POR,
BOR
RB3
RB2
RB1
RB0
PORTB Data Direction Register
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Value on all
other resets
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
1111 1111
1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30292A-page 32
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
3.3
PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC (3:4) pins
can be configured with normal I2C levels or with
SMBUS levels by using the CKE bit (SSPSTAT <6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-1:
INITIALIZING PORTC
BCF
CLRF
STATUS, RP0
PORTC
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISC
;
;
;
;
;
;
;
;
;
;
;
Select Bank 0
Initialize PORTC by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<0:2> RC<5:7>
PORT/PERIPHERAL Select(2)
Peripheral Data Out
Data bus
WR
PORT
VDD
0
D
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
Q
OE(3)
D
EN
RD
PORT
Peripheral input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
FIGURE 3-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<3:4>
PORT/PERIPHERAL Select(2)
Peripheral Data Out
Data bus
WR
PORT
D
VDD
0
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
Q
OE(3)
RD
PORT
D
EN
0
Schmitt
Trigger
with
SMBus
levels
SSPl input
1
CKE
SSPSTAT<6>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 33
PIC16F87X
TABLE 3-5
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2
bit1
ST
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK
bit6
ST
Input/output port pin or USART Asynchronous Transmit or Synchronous Clock
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or Synchronous Data
Legend: ST = Schmitt Trigger input
TABLE 3-6
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name
07h
PORTC
87h
TRISC
Value on
all
other
resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS30292A-page 34
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
3.4
PORTD and TRISD Registers
FIGURE 3-7:
PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the 28-pin devices.
Data
bus
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
D
WR
PORT
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 3-7
Name
RD0/PSP0
RD1/PSP1
PORTD FUNCTIONS
Bit#
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Buffer Type
Function
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1
bit2
ST/TTL(1)
Input/output port pin or parallel slave port bit2
bit3
ST/TTL(1)
Input/output port pin or parallel slave port bit3
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
bit5
ST/TTL(1)
Input/output port pin or parallel slave port bit5
bit6
ST/TTL(1)
Input/output port pin or parallel slave port bit6
bit7
ST/TTL(1)
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Address Name
08h
PORTD
88h
TRISD
89h
TRISE
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
RD7
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
RD6
RD5
PORTD Data Direction Register
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
Value on all
other
resets
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 35
PIC16F87X
3.5
PORTE and TRISE Register
FIGURE 3-8:
This section is not applicable to the 28-pin devices.
Data
bus
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
D
WR
PORT
Q
I/O pin(1)
CK
Data Latch
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode the input buffers are TTL.
D
WR
TRIS
Q
TRIS Latch
Figure 3-9 shows the TRISE register, which also controls the parallel slave port operation.
RD TRIS
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
Q
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset these pins are configured as analog inputs.
FIGURE 3-9:
R-0
IBF
bit7
Schmitt
Trigger
input
buffer
CK
TRISE REGISTER (ADDRESS 89h)
R-0
OBF
R/W-0
IBOV
R/W-0
U-0
PSPMODE —
R/W-1
bit2
R/W-1
bit1
R/W-1
bit0
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7 :
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2:
Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1:
Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0:
Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
DS30292A-page 36
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 3-9
Name
PORTE FUNCTIONS
Bit#
Buffer Type
bit0
ST/TTL(1)
Function
Input/output port pin or read control input in parallel slave port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
(1)
RE1/WR/AN6
bit1
Input/output port pin or write control input in parallel slave port mode or
ST/TTL
analog input:
WR
1 =Not a write operation
0 =Write operation. Writes PORTD register (if chip selected)
(1)
RE2/CS/AN7
bit2
Input/output port pin or chip select control input in parallel slave port
ST/TTL
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
RE0/RD/AN5
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 3-10
Addr Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1
ADFM
—
—
—
PCFG3
Bit 2
RE2
Bit 1
RE1
Bit 0
RE0
PORTE Data Direction Bits
PCFG2
PCFG1
PCFG0
Value on:
POR,
BOR
Value on all
other resets
---- -xxx
---- -uuu
0000 -111
0000 -111
--0- 0000
--0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 37
PIC16F87X
3.6
Parallel Slave Port
FIGURE 3-10: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL
SLAVE PORT)
The Parallel Slave Port is not implemented on the 28pin devices.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data bus
D
WR
PORT
Q
RDx
pin
CK
TTL
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). And the A/D port
configuration bits PCFG3:PCFG0 (ADCON1<3:0>)
must be set to configure pins RE2:RE0 as digital I/O.
Q
RD
PORT
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
Read
RD
TTL
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 3-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS30292A-page 38
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 3-12: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
PORTD
Port data latch when written: Port pins when read
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0Ch
PIR1
PSPIF ADIF
RCIF
TXIF
SSPIF
8Ch
PIE1
PSPIE ADIE
RCIE
TXIE
9Fh
ADCON1
—
—
ADFM
—
Value on:
POR,
BOR
Value on
all
other
resets
xxxx xxxx
uuuu uuuu
---- -xxx
---- -uuu
0000 -111
0000 -111
CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
SSPIE
CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
PCFG3
PCFG2
--0- 0000
--0- 0000
RE2
RE1
PCFG1
RE0
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel
Slave Port.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 39
PIC16F87X
NOTES:
DS30292A-page 40
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
4.1
The Data EEPROM and FLASH Program memory are
readable and writable during normal operation over the
entire VDD range. The data memory is not directly
mapped in the register file space. Instead it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
•
•
•
•
•
•
EEADR
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
On the PIC16F874/873 devices with 128 bytes of
EEPROM, the MSbit of the EEADR must always be
cleared to prevent inadvertent access to the wrong
location. This also applies to the program memory. The
upper MSbits of EEADRH must always be clear.
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds
the address of the EEPROM location being accessed.
The registers EEDATH and EEADRH are not used for
data EEPROM access. These devices have up to 256
bytes of data EEPROM with an address range from 0h
to FFh.
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temperature as well as from chip to chip. Please refer to the
specifications for exact limits.
The program memory allows word reads and writes.
Program memory reads allow checksum calculation for
UL type applications. A byte or word write automatically
erases the location and writes the new data (erase
before write).
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a 2 byte word which
holds the 14-bit data for read/write, and the
EEADRH:EEADR registers form a 2 byte word which
holds the 13-bit address of the EEPROM location being
accessed. These devices can have up to 8K words of
program EEPROM with an address range from 0h to
3FFFh.
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that
forms an invalid instruction results in a NOP.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 41
PIC16F87X
4.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data memory. When set, any subsequent operations will operate
on the program memory.
Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
FIGURE 4-1:
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
Interrupt flag bit EEIF, in the PIR2 register, is set when
write is complete. It must be cleared in software.
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
EEPGD
—
bit7
bit 7:
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
U-0
—
U-0
—
R/W-x
R/W-0
WRERR WREN
R/S-0
WR
R/S-0
RD
bit0
R= Readable bit
W= Writable bit
S= Settable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
EEPGD: Program / Data EEPROM Select bit
1 = Accesses Program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6:4: Unimplemented: Read as '0'
bit 3:
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2:
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1:
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be
set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0:
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be
set (not cleared) in software).
0 = Does not initiate an EEPROM read
DS30292A-page 42
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
4.3
Reading the Data EEPROM Memory
To read a data memory location, the user must write
the address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available, in the very next
EXAMPLE 4-1:
BSF
BCF
MOVLW
MOVWF
BSF
BCF
BSF
BCF
MOVF
4.4
instruction cycle, in the EEDATA register; therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is written to by the user (during a write operation).
DATA EEPROM READ
STATUS, RP1
STATUS, RP0
DATA_EE_ADDR
EEADR
STATUS, RP0
EECON1, EEPGD
EECON1, RD
STATUS, RP0
EEDATA, W
;
;
;
;
;
;
;
;
;
Bank 2
Data Memory Address to read
Bank 3
Point to DATA memory
EEPROM Read
Bank 2
W = EEDATA
Writing to the Data EEPROM Memory
the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
To write an EEPROM data location, the address must
first be written to the EEADR register and the data to
EXAMPLE 4-2:
DATA EEPROM WRITE
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Data Memory Address to write
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BSF
STATUS, RP0
; Bank 3
BCF
EECON1, EEPGD ; Point to DATA memory
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
BSF
INTCON, GIE
; Enable Interrupts
SLEEP
BCF
; Wait for interrupt to signal write complete
EECON1, WREN
; Disable writes
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., lost programs). The WREN bit should be
kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
 1998 Microchip Technology Inc.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruction, both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
Preliminary
DS30292A-page 43
PIC16F87X
4.5
Reading the FLASH Program Memory
A program memory location may be read by writing two
bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>) and
then set control bit RD (EECON1<0>). Once the read
control bit is set, the microcontroller will use the second
instruction cycle to read the data. This causes the second instruction immediately following the “BSF
EECON1,RD” instruction to be ignored. The data is
EXAMPLE 4-3:
available, in the third cycle, in the EEDATA and
EEDATH registers; therefore it can be read as two
bytes in the following instructions. The data can be read
out of EEDATH:EEDATA starting with the third instruction cycle after the BSF EECON1,RD instruction. The
EEDATA and EEDATH registers will hold this value until
another read operation or until it is written to by the user
(during a write operation).
FLASH PROGRAM READ
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
ADDRH
;
MOVWF
EEADRH
; MSByte of Program Address to read
MOVLW
ADDRL
;
MOVWF
EEADR
; LSByte of Program Address to read
BSF
STATUS, RP0
; Bank 3
BSF
EECON1, EEPGD
; Point to PROGRAM memory
BSF
EECON1, RD
; EEPROM Read
NOP
; Any instructions here are ignored as program
NOP
; memory is read in third cycle after BSF EECON1,RD
BCF
STATUS, RP0
; Bank 2
MOVF
EEDATA, W
; W = LSByte of Program EEDATA
MOVF
EEDATH, W
; W = MSByte of Program EEDATA
DS30292A-page 44
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
4.6
Writing to the FLASH Program
Memory
A word of the FLASH program memory may only be
written to if the word is in a non-code protected segment of memory and the WRT configuration bit is set.
To write a FLASH program location, the first two bytes
of the address must be written to the EEADR and
EEADRH registers and two bytes of the data to the
EEDATA and EEDATH registers, set the EEPGD control bit (EECON1<7>), and then set control bit WR
(EECON1<1>). The sequence in Example 4-4 must be
followed to initiate a write to program memory.
EXAMPLE 4-4:
After the “BSF EECON1,WR“ instruction, the microcontroller will execute the next instruction and then ignore
the subsequent instruction. A NOP instruction should
be used in both places. The microcontroller will then
halt internal operations for the TPEW (parameter D133)
in which the write takes place. This is not a SLEEP
mode, as the clocks and peripherals will continue to
run. After the write cycle, the microcontroller will
resume operation with the 3rd instruction after the
EECON1 write instruction.
FLASH PROGRAM WRITE
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
ADDRH
;
MOVWF
EEADRH
; MSByte of Program Address to read
MOVLW
ADDRL
;
MOVWF
EEADR
; LSByte of Program Address to read
MOVLW
DATAH
;
MOVWF
EEDATH
; MS Program Memory Value to write
MOVLW
DATAL
;
MOVWF
EEDATA
; LS Program Memory Value to write
BSF
STATUS, RP0
; Bank 3
BSF
EECON1, EEPGD
; Point to PROGRAM memory
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
;
;
NOP
;
; Instructions here are ignored by the microcontroller
NOP
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
BSF
INTCON,
BCF
EECON1, WREN
 1998 Microchip Technology Inc.
GIE
; Enable Interrupts
; Disable writes
Preliminary
DS30292A-page 45
PIC16F87X
4.7
Write Verify
4.8.2
PROGRAM FLASH MEMORY
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. WRT and the configuration word cannot be programmed by user code,
only through the use of an external programmer.
Generally a write failure will be a bit which was written
as a '1', but reads back as a '0' (due to leakage off the
bit).
4.9
4.8
Protection Against Spurious Write
4.8.1
EEPROM DATA MEMORY
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
TABLE 7-1:
Operation during Code Protect
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write operations are disabled if either of these mechanisms are
enabled.
4.9.3
DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code protect configuration bit.
4.9.4
PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH program memory regardless
of the state of the code protect configuration bits. However the WRT configuration bit and the code protect bits
have different effects on writing to program memory.
Table 7-1 shows the various configurations and status
of reads and writes. To erase the WRT or code protection bits in the configuration word requires that the
device be fully erased.
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Memory Location
CP1
CP0
WRT
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
x
0
0
1
1
0
0
1
1
0
1
DS30292A-page 46
Internal
Read
Internal
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
Yes
All program memory
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
All program memory
All program memory
Preliminary
ICSP Read ICSP Write
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
No
Yes
Yes
 1998 Microchip Technology Inc.
PIC16F87X
5.0
TIMER0 MODULE
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manual, DS33023.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
5.2
8-bit timer/counter
Readable and writable
Internal or external clock select
Edge select for external clock
8-bit software programmable prescaler
Interrupt on overflow from FFh to 00h
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (Figure 5-2). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no
prescaler for the Watchdog Timer, and vice-versa.
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
5.1
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Timer0 Operation
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0, MOVWF
TMR0, BSF TMR0,x....etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will clear
the prescaler along with the WDT.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed below.
Note:
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
FIGURE 5-1:
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TIMER0 BLOCK DIAGRAM
Data bus
Fosc/4
0
PSout
1
1
Programmable
Prescaler
RA4/T0CKI
pin
0
8
Sync with
Internal
clocks
TMR0
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
PSA
T0CS
Set interrupt
flag bit T0IF
on overflow
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 47
PIC16F87X
5.2.1
5.3
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
Note:
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP.
To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Manual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
FIGURE 5-2:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
RA4/T0CKI
pin
8
M
0
1
U
X
M
0
1
SYNC
2
Cycles
U
X
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
8-bit Prescaler
M
U
X
1
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 5-1
Address
01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
0Bh,8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
81h,181h
OPTION_REG
RBPU INTEDG T0CS
85h
TRISA
—
—
T0IE
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
--11 1111
--11 1111
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS30292A-page 48
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
6.0
TIMER1 MODULE
6.1
The Timer1 module timer/counter has the following features:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 has a control register, shown in Figure 6-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 6-3 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
FIGURE 6-1:
Timer1 Operation
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 8.0).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
R/W-0
R/W-0
TMR1CS TMR1ON
bit7
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2:
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 49
PIC16F87X
6.1.1
TIMER1 COUNTER OPERATION
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
In this mode, Timer1 is being incremented via an external source. Increments occur on a rising edge. After
FIGURE 6-2:
TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
FIGURE 6-3:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
0
TMR1
clock input
TMR1L
1
TMR1ON
on/off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI
1
T1OSCEN
Enable
Oscillator(1)
Fosc/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS30292A-page 50
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
6.2
Timer1 Oscillator
6.3
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Osc Type
Freq
LP
C1
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1, and for CCP2
only, start an A/D conversion (if the A/D module is
enabled).
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
Crystals Tested:
32.768 kHz
Epson C-001R32.768K-A
± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
200 kHz
STD XTL 200.000 kHz
± 20 PPM
Note 1: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
Address
6.4
Note:
These values are for design guidance only.
TABLE 6-2
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
C2
32 kHz
Timer1 Interrupt
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
Bit 7
0Bh,8Bh,
INTCON GIE
10Bh,18Bh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
PEIE T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1) ADIF RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1) ADIE RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
uuuu uuuu
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
--uu uuuu
10h
T1CON —
—
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 51
PIC16F87X
NOTES:
DS30292A-page 52
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
7.0
TIMER2 MODULE
7.1
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (Both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to generate clock shift
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 has a control register, shown in Figure 7-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
The prescaler and postscaler counters are cleared
when any of the following occurs:
Figure 7-2 is a simplified block diagram of the Timer2
module.
• a write to the TMR2 register
• a write to the T2CON register
• any device reset
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
FIGURE 7-1:
U-0
—
R/W-0
TMR2 is not cleared when T2CON is written.
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
R/W-0
R/W-0
T2CKPS1 T2CKPS0
bit7
bit 7:
Timer2 Operation
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 53
PIC16F87X
7.2
Timer2 Interrupt
FIGURE 7-2:
Sets flag
bit TMR2IF
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is initialized to FFh upon reset.
7.3
TIMER2 BLOCK DIAGRAM
TMR2
output (1)
Reset
Postscaler
1:1 to 1:16
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
EQ
TMR2 reg
Comparator
4
Prescaler
1:1, 1:4, 1:16
Fosc/4
2
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
TABLE 7-1
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,
18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1) ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
8Ch
PIE1
PSPIE(1) ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
11h
TMR2
Timer2 module’s register
T2CKPS0
-000 0000 -000 0000
12h
T2CON
92h
PR2
—
TOUTPS3
TOUTPS2
0000 0000 0000 0000
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
1111 1111 1111 1111
Timer2 Period Register
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
DS30292A-page 54
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
8.0
CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
CCP2 Module
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 8-1 shows the
timer resources of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, operation of a CCP module in the following sections is
described with respect to CCP1.
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
TABLE 8-1
Table 8-2 shows the interaction of the CCP modules.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 8-2
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be configured for the special event trigger, which clears TMR1.
Compare
Compare
The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM
PWM
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
FIGURE 8-1:
CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx = PWM mode
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 55
PIC16F87X
8.1
Capture Mode
8.1.4
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
FIGURE 8-2:
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
MOVWF
CCP1CON
;Turn CCP module off
;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
∏ 1, 4, 16
Set flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
Pin
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
8.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS30292A-page 56
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
8.2
Compare Mode
8.2.1
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• driven High
• driven Low
• remains Unchanged
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
8.2.2
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-3:
CCP PIN CONFIGURATION
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Comparator
TMR1H
TIMER1 MODE SELECTION
8.2.3
Special event trigger will:
reset Timer1, but not set interrupt flag bit
TMR1IF (PIR1<0>), and set bit GO/DONE
Q S Output
Logic
match
RC2/CCP1
R
Pin
TRISC<2>
Output Enable CCP1CON<3:0>
Mode Select
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
TMR1L
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
Note:
TABLE 8-3
Address
The special event trigger from the CCP2
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
resets
GIE
PEIE T0IE
INTE
RBIE
T0IF
0Ch
PIR1
PSPIF(1) ADIF RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1) ADIE RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
—
—
—
—
RBIF
Value on:
POR,
BOR
INTCON
0Bh,8Bh,
10Bh,18Bh
INTF
Bit 0
0000 000x 0000 000u
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 57
PIC16F87X
8.3
PWM Mode
8.3.1
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-4 shows a simplified block diagram of the CCP
module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty cycle registers
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [(PR2) + 1] ¥ 4 ¥ TOSC ¥
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
CCPR1L
8.3.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
(Note 1)
TMR2
S
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
Clear Timer,
CCP1 pin and
latch D.C.
PR2
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 8-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-5:
PWM OUTPUT
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
TRISC<2>
Comparator
The Timer2 postscaler (see Section 7.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
log
(
Fosc
Fpwm
=
Duty Cycle
)
bits
log (2)
TMR2 = PR2
TMR2 = Duty Cycle
Note:
TMR2 = PR2
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
For an example PWM period and duty cycle calculation, see the Midrange Reference Manual (DS33023).
DS30292A-page 58
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
8.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
TABLE 8-4
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 8-5
Address
16
0xFF
10
4
0xFF
10
1
0xFF
10
1
0x3F
8
1
0x1F
7
1
0x17
5.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
0Bh,8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
92h
PR2
Timer2 module’s period register
1111 1111
1111 1111
12h
T2CON
-000 0000
-000 0000
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
--00 0000
--00 0000
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 59
PIC16F87X
NOTES:
DS30292A-page 60
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I 2C)
Figure 9-1 shows a block diagram for the SPI mode,
while Figure 9-2, and Figure 9-3 shows the block diagrams for the two different I2C modes of operation.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 61
PIC16F87X
FIGURE 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0 R/W-0
SMP
CKE
bit7
R-0
D/A
R-0
P
R-0
S
R-0
R/W
R-0
UA
R-0
BF
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 7:
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6:
CKE: SPI Clock Edge Select (Figure 9-6, Figure 9-8, and Figure 9-9)
SPI Mode:
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
In I2C Master or Slave Mode:
1 = Input levels conform to SMBUS spec
0 = Input levels conform to I2C specs
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next start bit, stop bit, or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
DS30292A-page 62
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 9-2:
R/W-0
WCOL
bit7
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to SSPBUF was attempted while the I2C conditions were not valid
0 = No collision
Slave Mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. . In
slave mode the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In master
mode the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must
be cleared in software).
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in transmit
mode. (Must be cleared in software).
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode, when enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode, when enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C slave mode, SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled.
1001, 1010, 1100, 1101 = reserved
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 63
PIC16F87X
FIGURE 9-3:
R/W-0
GCEN
bit7
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0
ACKSTAT
R/W-0
ACKDT
R/W-0
ACKEN
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit,
Read as ‘0’
- n =Value at POR reset
bit 7:
GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6:
ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5:
ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4:
ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
bit 3:
RCEN: Receive Enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2:
PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1:
RSEN: Repeated Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0:
SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not
be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS30292A-page 64
 1998 Microchip Technology Inc.
PIC16F87X
9.1
SPI Mode
FIGURE 9-4:
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish communication, typically three pins are used:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
data bus
Read
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Write
SSPBUF reg
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
9.1.1
SSPSR reg
SDI
OPERATION
shift
clock
bit0
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
SS Control
Enable
SS
•
•
•
•
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase
(middle or end of data output time)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Edge
Select
2
Clock Select
Figure 9-4 shows the block diagram of the MSSP module when in SPI mode.
SCK
SSPM3:SSPM0
SMP:CKE 4
TMR2 output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
Data direction bit
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR1<3>) are set. This double buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPBUF register during transmission/
reception of data will be ignored, and the write collision
detect bit WCOL (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register
completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 65
PIC16F87X
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 9-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 9-1:
LOADING THE SSPBUF
(SSPSR) REGISTER
BSF
STATUS, RP0
LOOP BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
LOOP
STATUS, RP0
SSPBUF, W
MOVWF RXDATA
MOVF TXDATA, W
MOVWF SSPBUF
;Specify Bank 1
;Has data been
;received
;(transmit
;complete)?
;No
;Specify Bank 0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
9.1.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON registers, and then set bit SSPEN. This configures the SDI,
FIGURE 9-5:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
9.1.2
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, some must have
their data direction bits (in the TRIS register) appropriately programmed. That is:
TYPICAL CONNECTION
Figure 9-5 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite
edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
Shift Register
(SSPSR)
MSb
LSb
Serial Clock
SCK
PROCESSOR 1
DS30292A-page 66
SCK
PROCESSOR 2
 1998 Microchip Technology Inc.
PIC16F87X
9.1.4
Figure 9-6, Figure 9-8, and Figure 9-9 where the MSb
is transmitted first. In master mode, the SPI clock rate
(bit rate) is user programmable to be one of the following:
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broadcast data by the software protocol.
•
•
•
•
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 9-6:
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDO
(CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 67
PIC16F87X
9.1.5
SLAVE MODE
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in slave mode the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in sleep mode, the slave can transmit/receive
data. When a byte is received the device will wake-up
from sleep.
9.1.6
SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISA<5> must be set. When the SS pin is low,
transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
FIGURE 9-7:
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desirable,
depending on the application.
Note:
When the SPI module is in Slave Mode
with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit7
bit0
bit0
bit7
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS30292A-page 68
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 9-8:
SPI SLAVE MODE WAVEFORM (CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit7
SDO
SDI
(SMP = 0)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 9-9:
SPI SLAVE MODE WAVEFORM (CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 69
PIC16F87X
9.1.7
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt flag bit will be set and if enabled will wake the
device from sleep.
SLEEP OPERATION
In master mode all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
9.1.8
EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
TABLE 9-1
REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
8Ch
PIE1
13h
SSPBUF
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
Legend:
Note 1:
PSPIE
Synchronous Serial Port Receive Buffer/Transmit Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
These bits are reserved on the 28-pin devices, always maintain these bits clear.
DS30292A-page 70
 1998 Microchip Technology Inc.
PIC16F87X
9.2
MSSP I 2C Operation
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call support) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit addressing.
FIGURE 9-11: I2C MASTER MODE BLOCK
DIAGRAM
Internal
data bus
Read
SSPADD<6:0>
7
Write
Baud Rate Generator
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment."
SSPBUF reg
SCL
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
shift
clock
SSPSR reg
SDA
MSb
LSb
FIGURE 9-10: I2C SLAVE MODE BLOCK
DIAGRAM
Match detect
Internal
data bus
SSPADD reg
Read
Write
Start and Stop bit
detect / generate
SSPBUF reg
SCL
shift
clock
SSPSR reg
SDA
MSb
LSb
Match detect
Addr Match
Set/Clear S bit
and
Clear/Set P bit
(SSPSTAT reg)
and Set SSPIF
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I2C mode is enabled. The SSP
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I2C operation.
They are the:
SSPADD reg
Start and
Stop bit detect
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
•
•
•
•
•
SSP Control Register (SSPCON)
SSP Control Register2 (SSPCON2)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I 2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropriate TRIS bits. Selecting an I 2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I 2C mode.
The CKE bit (SSPSTAT<67>) sets the levels of the SDA
and SCL pins in either master or slave mode. When
CKE = 1, the levels will conform to the SMBUS specification. When CKE = 0, the levels will conform to the
I2C specification.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 71
PIC16F87X
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write
data transfer.
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
9.2.1
SLAVE MODE
In slave mode, the SCL and SDA pins must be configured as inputs. The MSSP module will override the
input state with the output data when required (slavetransmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
9.2.1.1
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
1.
2.
3.
a)
4.
b)
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times of
the I2C specification as well as the requirement of the
MSSP module is shown in timing parameter #100 and
parameter #101 of the Electrical Specifications.
DS30292A-page 72
The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
The buffer full bit, BF is set on the falling edge of
the 8th SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the 9th SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmitter:
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
ADDRESSING
5.
6.
7.
8.
9.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note:
Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
 1998 Microchip Technology Inc.
PIC16F87X
9.2.1.2
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the received byte.
SLAVE RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
Note:
The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred. The ACK is not sent and the
SSPBUF is updated.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
TABLE 9-2
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPSR → SSPBUF
SSPOV
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Pulse
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
Yes
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
9.2.1.3
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the status of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-13).
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
FIGURE 9-12: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
ACK
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
S
1
2
3
4
5
6
7
8
9
Not
Receiving Data
Receiving Data
ACK
ACK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
8
7
SSPIF
9
P
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 73
PIC16F87X
FIGURE 9-13: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 1
ACK
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
sampled
A5
A4
A3
A2
A1
3
4
5
6
7
D7
8
9
R/W = 0
Not ACK
Transmitting Data
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30292A-page 74
 1998 Microchip Technology Inc.
 1998 Microchip Technology Inc.
Preliminary
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
1
S
SCL
2
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
8
9
ACK
Receive First Byte of Address R/W = 0
1
SDA
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
Clock is held low until
update of SSPADD has
tACKEN place
9
ACK
2
3
1
4
1
Cleared in software
1
1
Cleared by hardware when
SSPADD is updated.
Dummy read of SSPBUF
to clear BF flag
Sr
1
5
0
6
7
A9 A8
Receive First Byte of Address
8
9
R/W=1
ACK
1
3
4
5
6
7
8
9
ACK
P
Write of SSPBUF
initiates transmit
Cleared in software
Bus Master
terminates
transfer
CKP has to be set for clock to be released
2
D4 D3 D2 D1 D0
Transmitting Data Byte
D7 D6 D5
Master sends NACK
Transmit is complete
PIC16F87X
FIGURE 9-14: I2C SLAVE-TRANSMITTER (10-BIT ADDRESS)
DS30292A-page 75
DS30292A-page 76
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
1
SCL
S
1
SDA
2
1
3
1
5
0
6
A9
7
A8
UA is set indicating that
the SSPADD needs to be
updated
8
9
ACK
R/W = 0
SSPBUF is written with
contents of SSPSR
4
1
Receive First Byte of Address
1
3
A5
4
A4
Cleared in software
2
A6
5
A3
6
A2
7
A1
8
A0
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address.
Dummy read of SSPBUF
to clear BF flag
A7
Receive Second Byte of Address
Clock is held low until
update of SSPADD has
tACKEN place
9
ACK
3
D5
4
D4
5
D3
Cleared in software
2
D6
Cleared by hardware when
SSPADD is updated with high
byte of address.
Dummy read of SSPBUF
to clear BF flag
1
D7
Receive Data Byte
6
D2
7
D1
8
D0
9
ACK
R/W = 1
Read of SSPBUF
clears BF flag
P
Bus Master
terminates
transfer
PIC16F87X
FIGURE 9-15: I2C SLAVE-RECEIVER (10-BIT ADDRESS)
 1998 Microchip Technology Inc.
PIC16F87X
9.2.2
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit) the
SSPIF flag is set.
GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually determines which device will be the slave addressed by the
master. The exception is the general call address which
can address all devices. When this address is used, all
devices should, in theory, respond with an acknowledge.
When the interrupt is serviced. The source for the interrupt can be checked by reading the contents of the
SSPBUF to determine if the address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is configured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
acknowledge (Figure 9-16).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD, and is also compared to the general call
address, fixed in hardware.
FIGURE 9-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
R/W = 0
ACK D7
General Call Address
SDA
Receiving data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV
(SSPCON<6>)
'0'
GCEN
(SSPCON2<7>)
'1'
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 77
PIC16F87X
9.2.3
9.2.4
SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
REGISTERS ASSOCIATED WITH I2C OPERATION
TABLE 9-3
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
0Dh
PIR2
—
(2)
—
EEIF
BCLIF
—
—
CCP2IF
-r-0 0--0
-r-0 0--0
8Dh
PIE2
—
(2)
—
EEIE
BCLIE
—
—
CCP2IE
-r-0 0--0
-r-0 0--0
13h
SSPBUF
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
Legend:
Synchronous Serial Port Receive Buffer/Transmit Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
2: These bits are reserved on these devices, always maintain these bits clear.
DS30292A-page 78
 1998 Microchip Technology Inc.
PIC16F87X
9.2.5
MASTER MODE
In master mode, the SCL and SDA lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is disabled. Control of the I 2C bus may be TACKEN when the
P bit is set, or the bus is idle with both the S and P bits
clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
•
•
•
•
•
START condition
STOP condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
FIGURE 9-17: SSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus
Read
SSPM3:SSPM0,
SSPADD<6:0>
Write
SSPBUF
shift
clock
SDA
SDA in
SSPSR
SCL in
Bus Collision
 1998 Microchip Technology Inc.
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
Preliminary
clock cntl
SCL
Receive Enable
MSb
clock arbitrate/WCOL detect
(hold off clock source)
Baud
rate
generator
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS30292A-page 79
PIC16F87X
9.2.6
MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the MSSP module is disabled. Control of the I 2C
bus may be TACKEN when bit P (SSPSTAT<4>) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be monitored, for abitration, to see if the signal level is the
expected output level. This check is performed in hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
9.2.7
I2C MASTER MODE SUPPORT
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once master mode is enabled, the user
has six options.
- Assert a start condition on SDA and SCL.
- Assert a Repeated Start condition on SDA and
SCL.
- Write to the SSPBUF register initiating transmission of data/address.
- Generate a stop condition on SDA and SCL.
- Configure the I2C port to receive data.
- Generate an Acknowledge condition at the end
of a received byte of data.
9.2.7.4
I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
also the beginning of the next serial transfer, the I2C
bus will not be released.
In Master Transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device, (7 bits) and the Read/Write (R/W) bit.
In this case the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master receive mode the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case the R/W bit will be
logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e. transmission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
A typical transmit sequence would go as follows:
Note:
The MSSP Module, when configured in I2C
Master Mode, does not allow queueing of
events. For instance: The user is not
allowed to initiate a start condition, and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
a)
b)
c)
d)
e)
f)
g)
h)
DS30292A-page 80
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
start time before any other operation takes
place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of
data.
DATA is shifted out the SDA pin until all 8 bits
are transmitted.
 1998 Microchip Technology Inc.
PIC16F87X
i)
j)
k)
l)
The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
Interrupt is generated once the STOP condition
is complete.
9.2.8
BAUD RATE GENERATOR
In I2C master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place for instance, the BRG
will be reloaded when the SCL pin is sampled high
(Figure 9-19).
FIGURE 9-18: BAUD RATE GENERATOR
BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
Reload
SCL
Control
In I2C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 9-18). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another
reload has TACKEN place. The BRG count is decremented twice per instruction cycle (TCY), on the Q2 and
Q4 clock.
CLKOUT
Reload
BRG Down Counter
Fosc/4
FIGURE 9-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 81
PIC16F87X
9.2.9
I2C MASTER MODE START CONDITION
TIMING
by hardware, the baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
To initiate a START condition the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0>,
and starts its count. If SCL and SDA are both sampled
high when the baud rate generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG) the
SEN bit (SSPCON2<0>) will be automatically cleared
Note:
9.2.9.5
If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
I2C module is reset into its IDLE state.
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-20: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
SCL = 1
TBRG
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st Bit
SDA
2nd Bit
TBRG
SCL
TBRG
S
DS30292A-page 82
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 9-21: START CONDITION FLOWCHART
SSPEN = 1,
SSPCON<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Bus collision detected,
Set BCLIF,
Release SCL,
Clear SEN
No
SDA = 1?
SCL = 1?
Yes
Load BRG with
SSPADD<6:0>
No
No
No
Yes
SCL= 0?
SDA = 0?
BRG
Rollover?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit.
No
SCL = 0?
Yes
No
BRG
rollover?
Yes
Reset BRG
Force SCL = 0,
Start Condition Done,
Clear SEN
and set SSPIF
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 83
PIC16F87X
9.2.10
I2C MASTER MODE REPEATED START
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C module is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0>, and begins counting. The SDA pin
is released (brought high) for one baud rate generator
count (TBRG). When the baud rate generator times out,
if SDA is sampled high, the SCL pin will be de-asserted
(brought high). When SCL is sampled high the baud
rate generator is re-loaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared, and the baud rate generator is not reloaded,
leaving the SDA pin held low. As soon as a start con-
dition is detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed-out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes from low to
high.
• SCL goes low before SDA is asserted low. This
may indicate that another master is attempting
to transmit a data "1".
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
9.2.10.6
WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 9-22: REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
SDA = 1,
SCL = 1
TBRG
At completion of start bit,
hardware clear RSEN bit
and set SSPIF
TBRG
TBRG
1st Bit
SDA
Falling edge of ninth clock
End of Xmit
SCL
Write to SSPBUF occurs here.
TBRG
TBRG
Sr = Repeated Start
DS30292A-page 84
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 9-23: REPEATED START CONDITION FLOWCHART (PAGE 1)
Start
Idle Mode,
SSPEN = 1,
SSPCON<3:0> = 1000
B
RSEN = 1
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
BRG
rollover?
No
Yes
Release SCL
(Clock Arbitration)
SCL = 1?
No
Yes
Bus Collision,
Set BCLIF,
Release SDA,
Clear RSEN
No
SDA = 1?
Yes
Load BRG with
SSPADD<6:0>
C
 1998 Microchip Technology Inc.
A
Preliminary
DS30292A-page 85
PIC16F87X
FIGURE 9-24: REPEATED START CONDITION FLOWCHART (PAGE 2)
B
C
A
Yes
No
No
No
SDA = 0?
SCL = 1?
Yes
BRG
rollover?
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S
No
SCL = '0'?
Yes
Reset BRG
DS30292A-page 86
No
BRG
rollover?
Yes
Force SCL = 0,
Repeated Start
condition done,
Clear RSEN,
Set SSPIF.
 1998 Microchip Technology Inc.
PIC16F87X
9.2.11
I2C MASTER MODE TRANSMISSION
9.2.11.7
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address is accomplished by simply writing a value to SSPBUF register. This action will set the
buffer full flag (BF) and allow the baud rate generator to
begin counting and start the next transmission. Each
bit of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate generator roll over count (TBRG). Data should be valid before
SCL is released high (see Data setup time spec).
When the SCL pin is released high, it is held that way
for TBRG, the data on the SDA pin must remain stable
for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF flag is cleared
and the master releases SDA allowing the slave device
being addressed to respond with an ACK bit during the
ninth bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge
status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock the SSPIF is set, and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF leaving SCL low
and SDA unchanged (Figure 9-26).
BF STATUS FLAG
In transmit mode, the BF bit (SSPSTAT<0>) is set when
the CPU writes to SSPBUF and is cleared when all 8
bits are shifted out.
9.2.11.8
WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.11.9
ACKSTAT STATUS FLAG
In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the slave does not acknowledge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 87
PIC16F87X
FIGURE 9-25: MASTER TRANSMIT FLOWCHART
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Release SDA so
slave can drive ACK,
Force BF = 0
Yes
Num_Clocks
= 8?
No
Load BRG with
SSPADD<6:0>,
start BRG count
Load BRG with
SSPADD<6:0>,
start BRG count,
SDA = Current Data bit
BRG
rollover?
BRG
rollover?
No
No
Yes
Yes
Force SCL = 1,
Stop BRG
Stop BRG,
Force SCL = 1
(Clock Arbitration)
SCL = 1?
(Clock Arbitration)
No
SCL = 1?
No
Yes
Yes
SDA =
Data bit?
Read SDA and place into
ACKSTAT bit (SSPCON2<6>)
No
Bus collision detected
Set BCLIF, hold prescale off,
Clear XMIT enable
Yes
Load BRG with
SSPADD<6:0>,
count high time
Load BRG with
SSPADD<6:0>,
count SCL high time
No
Rollover?
Yes
BRG
rollover?
No
No
SCL = 0?
Yes
Yes
SDA =
Data bit?
No
Yes
Force SCL = 0,
Set SSPIF
Reset BRG
Num_Clocks
= Num_Clocks + 1
DS30292A-page 88
 1998 Microchip Technology Inc.
 1998 Microchip Technology Inc.
S
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
cleared in software
2
6
7
8
9
After start condition SEN cleared by hardware.
SSPBUF written
1
D7
3
D5
4
D4
5
D3
6
D2
7
D1
SSPBUF is written in software
8
D0
cleared in software service routine
From SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave clear ACKSTAT bit SSPCON2<6>
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7 bit address and R/W
start transmit
A7
Transmit Address to Slave
SEN = 0
Write SSPCON2<0> SEN = 1
START condition begins
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
PIC16F87X
FIGURE 9-26: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS30292A-page 89
PIC16F87X
9.2.12
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note:
The SSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is suspended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automatically cleared. The user can then send an acknowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
9.2.12.10 BF STATUS FLAG
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.11 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
9.2.12.12 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e. SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
DS30292A-page 90
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 9-27: MASTER RECEIVER FLOWCHART
Idle mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
start count
BRG
rollover?
No
Yes
Release SCL
(Clock Arbitration)
SCL = 1?
No
Yes
Sample SDA,
Shift data into SSPSR
Load BRG with
SSPADD<6:0>,
start count.
BRG
rollover?
No
SCL = 0?
Yes
No
Yes
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 91
DS30292A-page 92
S
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2<0> (SEN = 1)
Begin Start Condition
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN start acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1 start
next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1)
Write to SSPCON2<4>
to start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16F87X
FIGURE 9-28: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
 1998 Microchip Technology Inc.
PIC16F87X
9.2.13
ACKNOWLEDGE SEQUENCE TIMING
the baud rate generator counts for TBRG . The SCL pin
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the baud rate generator is
turned off, and the SSP module then goes into IDLE
mode. (Figure 9-29)
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
9.2.13.13 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledege
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-29: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
Tbrg
Tbrg
SDA
ACK
D0
SCL
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: Tbrg= one baud rate generator period.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 93
PIC16F87X
FIGURE 9-30: ACKNOWLEDGE FLOWCHART
Idle mode
Set ACKEN
Force SCL = 0
BRG
rollover?
Yes
No
No
SCL = 0?
Yes
Yes
Drive ACKDT bit
(SSPCON2<5>)
onto SDA pin,
Load BRG with
SSPADD<6:0>,
start count.
SCL = 0?
Reset BRG
Force SCL = 0,
Clear ACKEN,
Set SSPIF
No
No
ACKDT = 1?
Yes
No
BRG
rollover?
Yes
Yes
Force SCL = 1
SDA = 1?
No
Bus collision detected,
Set BCLIF,
Release SCL,
Clear ACKEN
No
SCL = 1?
(Clock Arbitration)
Yes
Load BRG with
SSPADD <6:0>,
start count.
DS30292A-page 94
 1998 Microchip Technology Inc.
PIC16F87X
9.2.14
STOP CONDITION TIMING
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later the PEN bit is cleared and the SSPIF bit is
set (Figure 9-31).
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
9.2.14.14 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: TBRG = one baud rate generator period.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 95
PIC16F87X
FIGURE 9-32: STOP CONDITION FLOWCHART
Idle Mode,
SSPEN = 1,
SSPCON<3:0> = 1000
PEN = 1
Start BRG
Force SDA = 0
SCL doesn’t change
BRG
rollover?
No
SDA = 0?
No
Yes
Release SDA,
Start BRG
Yes
Start BRG
BRG
rollover?
BRG
rollover?
No
No
Yes
No
P bit Set?
Yes
De-assert SCL,
SCL = 1
Yes
(Clock Arbitration)
SCL = 1?
Bus Collision detected,
Set BCLIF,
Clear PEN
No
SDA going from
0 to 1 while SCL = 1
Set SSPIF,
Stop Condition done
PEN cleared.
Yes
DS30292A-page 96
 1998 Microchip Technology Inc.
PIC16F87X
9.2.15
9.2.16
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit, or repeated start/stop condition, deasserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 9-33).
SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep ( if the SSP interrupt is enabled).
9.2.17
EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
FIGURE 9-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (Tosc • 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
 1998 Microchip Technology Inc.
TBRG
TBRG
Preliminary
DS30292A-page 97
PIC16F87X
9.2.18
MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has TACKEN place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I2C port to its IDLE state. (Figure 9-34).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I2C
bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I2C bus is free, the user can resume communication by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be TACKEN when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 9-34: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt.
BCLIF
DS30292A-page 98
 1998 Microchip Technology Inc.
PIC16F87X
9.2.18.15 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-35).
SCL is sampled low before SDA is asserted low.
(Figure 9-36).
b)
During a START condition both the SDA and the SCL
pins are monitored.
If:
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-37). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
is sampled as '0', a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
Note:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-35).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the START condition, and if the
address is the same, arbitration must be
allowed to continue into the data portion,
REPEATED START, or STOP conditions.
FIGURE 9-35: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, enable start
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
BCLIF
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 99
PIC16F87X
FIGURE 9-36: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SEN
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
'0'
'0'
SSPIF
'0'
'0'
FIGURE 9-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA
SCL
S
SCL pulled low after BRG
Timeout
SEN
BCLIF
Set SSPIF
'0'
Set SEN, enable start
sequence if SDA = 1, SCL = 1
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
DS30292A-page 100
Interrupts cleared
in software.
 1998 Microchip Technology Inc.
PIC16F87X
however SDA is sampled high then the BRG is
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
9.2.18.16 BUS COLLISION DURING A REPEATED
START CONDITION
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to
transmit a data ’1’.
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0. The SCL pin is then deasserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e.
another master is attempting to transmit a data ’0’). If
If at the end of the BRG time out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete (Figure 9-38).
FIGURE 9-38: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
S
'0'
Cleared in software
'0'
SSPIF
'0'
'0'
FIGURE 9-39: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
BCLIF
Interrupt cleared
in software
RSEN
S
'0'
'0'
SSPIF
'0'
'0'
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 101
PIC16F87X
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to float.
When the pin is sampled high (clock arbitration), the
baud rate generator is loaded with SSPADD<6:0> and
counts down to 0. After the BRG times out SDA is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to
drive a data '0' (Figure 9-40).
9.2.18.17 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a)
b)
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
FIGURE 9-40: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA sampled
low after TBRG,
Set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
'0'
SSPIF
'0'
'0'
FIGURE 9-41:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high
Set BCLIF
PEN
BCLIF
P
'0'
SSPIF
'0'
DS30292A-page 102
 1998 Microchip Technology Inc.
PIC16F87X
9.3
Connection Considerations for I2C
Bus
For standard-mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-42 depends on the following parameters
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of Rp is shown in Figure 9-42.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of Rs. Series resistors are
optional and used to improve ESD susceptibility.
• Supply voltage
• Bus capacitance
• Number of connected devices
(input current + leakage current).
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the maximum value of Rp due to the specified rise time
(Figure 9-42).
The supply voltage limits the minimum value of resistor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
FIGURE 9-42: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
Rp
DEVICE
Rp
Rs
Rs
SDA
SCL
NOTE: I2C devices with input levels related to VDD must have one common supply
line to which the pull up resistor is also connected.
 1998 Microchip Technology Inc.
Preliminary
Cb=10 - 400 pF
DS30292A-page 103
PIC16F87X
NOTES:
DS30292A-page 104
 1998 Microchip Technology Inc.
PIC16F87X
10.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured
as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
The USART module also has a multi-processor communication capability using 9-bit address detection.
FIGURE 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit7
bit 7:
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
Unimplemented: Read as '0'
bit 2:
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data. Can be parity bit.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 105
PIC16F87X
FIGURE 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADDEN
R-0
FERR
R-0
OERR
R-x
RX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1 = Enables address detection, enable interrupt and load of the receive burffer when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2:
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of received data (Can be parity bit)
DS30292A-page 106
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
10.1
USART Baud Rate Generator (BRG)
EXAMPLE 10-1: CALCULATING BAUD
RATE ERROR
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Desired Baud rate = Fosc / (64 (X + 1))
9600 =
16000000 /(64 (X + 1))
X
25.042 = 25
=
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
Error
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
9615
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
(9615 - 9600) / 9600
=
0.16%
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Example 10-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
Writing a new value to the SPBRG register, causes the
BRG timer to be reset (or cleared), this ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
10.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 10-1
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
X = value in SPBRG (0 to 255)
Baud Rate= FOSC/(16(X+1))
NA
0
1
TABLE 10-2
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 0
Value on:
POR,
BOR
Value on
all
other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
18h
RCSTA
SPEN
RX9
SREN CREN
ADDEN
FERR
OERR RX9D 0000 000x 0000 000x
99h
SPBRG Baud Rate Generator Register
TX9D 0000 -010 0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 107
PIC16F87X
TABLE 10-3
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
KBAUD
NA
NA
NA
NA
19.53
76.92
96.15
294.1
500
5000
19.53
16 MHz
SPBRG
value
%
KBAUD
ERROR (decimal)
+1.73
+0.16
+0.16
-1.96
0
-
255
64
51
16
9
0
255
FOSC = 5.0688 MHz
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
+0.16
+0.16
-0.79
+2.56
0
-
207
51
41
12
7
0
255
4 MHz
NA
NA
NA
9.766
19.23
75.76
96.15
312.5
500
2500
9.766
7.15909 MHz
SPBRG
SPBRG
value
value
%
%
KBAUD
ERROR (decimal)
ERROR (decimal)
+1.73
+0.16
-1.36
+0.16
+4.17
0
-
255
129
32
25
7
4
0
255
3.579545 MHz
NA
NA
NA
9.622
19.24
77.82
94.20
298.3
NA
1789.8
6.991
+0.23
+0.23
+1.32
-1.88
-0.57
-
1 MHz
185
92
22
18
5
0
255
32.768 kHz
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
KBAUD
%
value KBAUD
%
value
KBAUD
%
value KBAUD
%
value KBAUD
%
value
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
NA
NA
NA
9.6
19.2
79.2
97.48
316.8
NA
1267
4.950
TABLE 10-4
BAUD
RATE
(K)
NA
NA
NA
NA
19.23
76.92
95.24
307.69
500
4000
15.625
10 MHz
SPBRG
value
%
KBAUD
ERROR (decimal)
0
0
+3.13
+1.54
+5.60
-
131
65
15
12
3
0
255
NA
NA
NA
9.615
19.231
76.923
1000
NA
NA
100
3.906
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
312.5
1.221
103
51
12
9
0
255
NA
NA
NA
9.622
19.04
74.57
99.43
298.3
NA
894.9
3.496
+0.23
-0.83
-2.90
+3.57
-0.57
-
92
46
11
8
2
0
255
NA
1.202
2.404
9.615
19.24
83.34
NA
NA
NA
250
0.9766
+0.16
+0.16
+0.16
+0.16
+8.51
-
207
103
25
12
2
0
255
0.303
1.170
NA
NA
NA
NA
NA
NA
NA
8.192
0.032
+1.14
-2.48
-
26
6
0
255
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
KBAUD
+0.16
+0.16
+0.16
+4.17
-
16 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
255
129
32
15
3
2
0
0
255
FOSC = 5.0688 MHz
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
10 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
+0.16
+0.16
+8.51
-
207
103
25
12
2
0
255
4 MHz
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
7.15909 MHz
SPBRG
SPBRG
%
value
%
value
ERROR (decimal) KBAUD ERROR (decimal)
+0.16
+0.16
+1.73
+1.73
+1.73
-
3.579545 MHz
129
64
15
7
1
0
255
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
+0.23
-0.83
-2.90
-2.90
-
1 MHz
92
46
11
5
0
255
32.768 kHz
BAUD
RATE
(K)
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
%
value
%
value
%
value
%
value
%
value
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
0.31
1.2
2.4
9.9
19.8
79.2
NA
NA
NA
79.2
0.3094
+3.13
0
0
+3.13
+3.13
+3.13
-
DS30292A-page 108
255
65
32
7
3
0
0
255
0.3005
1.202
2.404
NA
NA
NA
NA
NA
NA
62.500
3.906
-0.17
+1.67
+1.67
-
207
51
25
0
255
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
+0.23
-0.83
+1.32
-2.90
-2.90
-
Preliminary
185
46
22
5
2
0
255
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.63
0.0610
+0.16
+0.16
-6.99
-
51
12
6
0
255
0.256
NA
NA
NA
NA
NA
NA
NA
NA
0.512
0.0020
-14.67
-
1
0
255
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 10-5
BAUD
RATE
(K)
9.6
19.2
38.4
57.6
115.2
250
625
1250
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
KBAUD
9.615
19.230
37.878
56.818
113.636
250
625
1250
16 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
-1.36
-1.36
-1.36
0
0
0
129
64
32
21
10
4
1
0
9.615
19.230
38.461
58.823
111.111
250
NA
NA
10 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
+0.16
+2.12
-3.55
0
-
103
51
25
16
8
3
-
9.615
18.939
39.062
56.818
125
NA
625
NA
7.16 MHz
SPBRG
SPBRG
%
value
%
value
ERROR (decimal) KBAUD ERROR (decimal)
+0.16
-1.36
+1.7
-1.36
+8.51
0
-
64
32
15
10
4
0
-
9.520
19.454
37.286
55.930
111.860
NA
NA
NA
-0.83
+1.32
-2.90
-2.90
-2.90
-
46
22
11
7
3
-
FOSC = 5.068 MHz
4 MHz
3.579 MHz
1 MHz
32.768 kHz
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
%
value
%
value
%
value
%
value
%
value
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
9.6
19.2
9.6
18.645
0
-2.94
32
16
NA
1.202
38.4
57.6
115.2
250
625
1250
39.6
52.8
105.6
NA
NA
NA
+3.12
-8.33
-8.33
-
7
5
2
-
2.403
9.615
19.231
NA
NA
NA
 1998 Microchip Technology Inc.
+0.17
+0.13
+0.16
+0.16
-
207
9.727
18.643
+1.32
-2.90
22
11
8.928
20.833
-6.99
+8.51
6
2
NA
NA
-
-
103
25
12
-
37.286 -2.90
55.930 -2.90
111.860 -2.90
223.721 -10.51
NA
NA
-
5
3
1
0
-
31.25
62.5
NA
NA
NA
NA
-18.61
+8.51
-
1
0
-
NA
NA
NA
NA
NA
NA
-
-
Preliminary
DS30292A-page 109
PIC16F87X
10.2
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR register is empty.
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
Steps to follow when setting up an Asynchronous
Transmission:
•
•
•
•
1.
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
10.2.1
2.
3.
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 10.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
FIGURE 10-3: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
LSb
• • •
(8)
Pin Buffer
and Control
0
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30292A-page 110
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 10-4: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 10-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 2
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Start Bit
Stop Bit
Bit 0
WORD 2
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-6
Address Name
0Ch
PIR1
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RX9D
0000 000x
0000 000x
18h
RCSTA
19h
TXREG USART Transmit Register
SPEN
RX9
SREN
CREN
ADDEN
FERR
PSPIE(1)
OERR
0000 0000
0000 0000
0000 0000
0000 0000
8Ch
PIE1
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
0000 -010 0000 -010
98h
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 111
PIC16F87X
10.2.2
10.2.3
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 10-6.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC.
The USART module has a special provision for multiprocessor communication. When the RX9 bit is set in
the RCSTA register, 9-bits are received and the ninth
bit is placed in the RX9D status bit of the RSTA register.
The port can be programmed such that when the stop
bit is received, the serial port interrupt will only be activated if the RX9D bit = 1. This feature is enabled by
setting the ADDEN bit RCSTA<3> in the RCSTA register. This feature can be used in a multi-processor system as follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for
a data byte). If the ADDEN bit is set in the slave’s
RCSTA register, all data bytes will be ignored. However, if the ninth received bit is equal to a ‘1’, indicating
that the received byte is an address, the slave will be
interrupted and the contents of the RSR register will be
transferred into the receive buffer. This allows the slave
to be interrupted only by addresses, so that the slave
can examine the received byte to see if it is addressed.
The addressed slave will then clear its ADDEN bit and
prepare to receive data bytes from the master.
SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable
bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
When ADDEN is set, all data bytes are ignored. Following the STOP bit, the data will not be loaded into the
receive buffer, and no interrupt will occur. If another
byte is shifted into the RSR register, the previous data
byte will be lost.
The ADDEN bit will only take effect when the receiver
is configured in 9-bit asynchronous mode.
The receiver block diagram is shown in Figure 10-6.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
DS30292A-page 112
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
∏ 64
or
∏ 16
Baud Rate Generator
RSR register
MSb
Stop (8)
7
∑ ∑ ∑
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADDEN
Enable
Load of
RX9
ADDEN
RSR<8>
Receive
Buffer
8
RX9D
RCREG register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
RC7/RX/DT (pin)
Start
bit
bit0
bit1
bit8
Stop
bit
Start
bit
bit0
bit8
Stop
bit
Load RSR
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
WORD 1
RCREG
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN = 1.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 113
PIC16F87X
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
RC7/RX/DT (pin)
bit0
bit1
bit8
Stop
bit
Start
bit
bit0
bit8
Stop
bit
Load RSR
Bit8 = 1, Address Byte
WORD 1
RCREG
Bit8 = 0, Data Byte
Read
RCIF
Note: This timing diagram shows an address byte followed by a data byte. The data byte is not read into the RCREG (receive buffer)
because ADEN was not updated and still = 0.
TABLE 10-7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
SPEN
RX9
SREN
18h
RCSTA
1Ah
RCREG USART Receive Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG
CREN ADDEN
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CSRC
TX9
TXEN
SYNC
—
Bit 2
Bit 1
Bit 0
CCP1IF TMR2IF TMR1IF
FERR
OERR
RX9D
CCP1IE TMR2IE TMR1IE
BRGH
Baud Rate Generator Register
TRMT
TX9D
Value on:
POR,
BOR
Value on
all other
Resets
0000 0000
0000 0000
0000 000x
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
DS30292A-page 114
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
10.3
USART Synchronous Master Mode
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
10.3.1
Steps to follow when setting up a Synchronous Master
Transmission:
USART SYNCHRONOUS MASTER
TRANSMISSION
1.
The USART transmitter block diagram is shown in
Figure 10-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and interrupt bit, TXIF (PIR1<4>) is set. The interrupt can be
TABLE 10-8
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
SPEN
RX9
SREN
CREN ADDEN
FERR
Bit 1
Bit 0
TMR2IF TMR1IF
OERR
RX9D
Value on:
POR,
BOR
Value on all
other Resets
0000 0000
0000 0000
0000 000x
0000 000x
18h
RCSTA
19h
TXREG
USART Transmit Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
0000 -010
0000 -010
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 115
PIC16F87X
FIGURE 10-9: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
Bit 0
Bit 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2
Bit 7
Bit 0
WORD 1
Bit 1
WORD 2
Bit 7
RC6/TX/CK pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
TXEN bit
'1'
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS30292A-page 116
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
10.3.2
3.
4.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set
then CREN takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. (Section 10.1)
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
2.
TABLE 10-9
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name
0Ch
PIR1
Value on:
POR,
BOR
Value on all
other Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
0000 000x
18h
RCSTA
RX9D
0000 000x
1Ah
RCREG
USART Receive Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 117
PIC16F87X
10.4
10.4.2
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in slave mode.
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a)
1.
10.4.1
b)
c)
d)
e)
USART SYNCHRONOUS SLAVE
TRANSMIT
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the interrupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
DS30292A-page 118
2.
3.
4.
5.
6.
7.
8.
Preliminary
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 10-10
Address Name
0Ch
PIR1
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
SPEN
RX9
SREN
CREN
ADDEN
Bit 2
Bit 1
Bit 0
CCP1IF TMR2IF TMR1IF
FERR
OERR
RX9D
Value on:
POR,
BOR
Value on all
other Resets
0000 0000
0000 0000
0000 000x
0000 000x
18h
RCSTA
19h
TXREG
USART Transmit Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
0000 -010
0000 -010
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
TABLE 10-11
Address Name
0Ch
PIR1
18h
RCSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
1Ah
RCRE
G
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 119
PIC16F87X
NOTES:
DS30292A-page 120
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
11.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers. These registers
are:
•
•
•
•
The analog-to-digital (A/D) converter module has five
inputs for the 28-pin devices, and eight for the other
devices.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a digital result of this analog level via successive approximation. This A/D conversion, of the analog input signal,
results in a corresponding 10-bit digital number.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in sleep, the A/D clock must be derived from the
A/D’s internal RC oscillator.
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Figure 11-1, controls
the operation of the A/D module. The ADCON1 register, shown in Figure 11-2, configures the functions of
the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage reference) or as
digital I/O.
FIGURE 11-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: These channels are not available on the 28-pin devices.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 121
PIC16F87X
FIGURE 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
ADFM
bit7
bit 7:
U-0
—
R/W-0
—
U-0
—
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n = Value at POR reset
ADFM: A/D Result format select
1 = Right Justified. 6 most significant bits of ADRESH are read as ‘0’.
0 = Left Justified. 6 least significant bits of ADRESL are read as ‘0’.
bit 6-4: Unimplemented: Read as '0'
bit 3-0: PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG3: AN7(1) AN6(1) AN5(1)
PCFG0 RE2
RE1
RE0
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
AN4
RA5
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
AN3
RA3
AN2
RA2
A
VREF+
A
VREF+
A
VREF+
D
VREF+
A
VREF+
VREF+
VREF+
VREF+
D
VREF+
A
A
A
A
D
D
D
VREFA
A
VREFVREFVREFD
VREF-
AN1
RA1
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
AN0
RA0
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VREF+
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VREFVSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
CHAN /
REFS
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the 28-pin devices.
DS30292A-page 122
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
The ADRESH:ADRESL registers contains the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared,
and A/D interrupt flag bit ADIF is set. The block diagram
of the A/D module is shown in Figure 11-3.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed the A/D conversion can be
started. The following steps should be followed for
doing an A/D conversion:
1.
2.
3.
4.
5.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
7.
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 123
PIC16F87X
FIGURE 11-3: A/D BLOCK DIAGRAM
CHS2:CHS0
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VAIN
011
(Input voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF-
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
X000 or
X010 or
X100
VREF+
(Reference
voltage)
X001 or
X011 or
X101
PCFG3:PCFG0
00XX or 0X0X or
1000 or 1010 or
1100
VREF1001 or
1011 or
1101
(Reference
voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on 28-pin devices.
DS30292A-page 124
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
sum of these two times is the sampling time. There is a
minimum acquisition time to ensure that the holding
capacitor is charged to a level that will give the desired
accuracy for the A/D conversion.
Figure 11-4 shows the conversion sequence, and the
terms that are used. Acquisition time is the time that the
A/D module’s holding capacitor is connected to the
external voltage level. Then there is the conversion time
of 12 TAD, which is started when the GO bit is set. The
FIGURE 11-4: A/D CONVERSION SEQUENCE
A/D Sample Time
Acquisition Time
A/D Conversion Time
A/D conversion complete, result is loaded in ADRES register.
Holding capacitor begins acquiring voltage level on selected
channel ADIF bit is set
When A/D conversion is started
(setting the GO bit)
When A/D holding capacitor starts to charge.
After A/D conversion, or when new A/D channel is selected
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 11-5. The maximum recommended impedance
for analog sources is 10 kW. As the impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed)
this acquisition must be done before the conversion
can be started.
EQUATION 11-1:
TACQ
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 11-1 shows the calculation of the minimum
required acquisition time TACQ.
This calculation is based on the following application
system assumptions.
CHOLD
=
120 pF
Rs
=
10 kΩ
Conversion Error
≤
1/2 LSb
VDD
=
5V → Rss = 7 kΩ
(see graph in Figure 11-5)
Temperature
=
50°C (system max.)
VHOLD
=
0V @ time = 0
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 125
PIC16F87X
EQUATION 11-2:
VHOLD
or
Tc
A/D MINIMUM CHARGING TIME
=
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
=
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 11-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ =
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ =
2 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
TC =
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0004885)
-120 pF (18 kΩ) ln(0.0004885)
-2.16 µs (-7.6241)
16.47 µs
TACQ =
2 µs + 16.47 µs + [(50°C - 25°C)(0.05 µs/°C)]
18.447 µs + 1.25 µs
19.72 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
Note 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.
Note 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-5: ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS RSS
CHOLD
= DAC capacitance
= 120 pF
I leakage
± 500 nA
VSS
Legend CPIN
= INPUT CAPACITANCE
VT
= THRESHOLD VOLTAGE
I LEAKAGE = LEAKAGE CURRENT AT THE PIN DUE TO
VARIOUS JUNCTIONS
RIC
SS
CHOLD
DS30292A-page 126
= INTERCONNECT RESISTANCE
= SAMPLING SWITCH
= SAMPLE/HOLD CAPACITANCE (FROM DAC)
Preliminary
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
 1998 Microchip Technology Inc.
PIC16F87X
11.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
•
•
•
•
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 11-1 and Table 11-2 show the resultant TAD
times derived from the device operating frequencies
and the A/D clock source selected.
2TOSC
8TOSC
32TOSC
Internal RC oscillator
TABLE 11-1
TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
Device Frequency
AD Clock Source (TAD)
Operation
ADCS1:ADCS0
2TOSC
00
20 MHz
100
ns(2)
400
ns(2)
5 MHz
1.25 MHz
333.33 kHz
1.6 µs
6 µs
1.6 µs
6.4 µs
24 µs(3)
400
ns(2)
8TOSC
01
32TOSC
10
1.6 µs
6.4 µs
25.6 µs(3)
96 µs(3)
RC
11
2 - 6 µs(1, 4)
2 - 6 µs(1, 4)
2 - 6 µs(1, 4)
2 - 6 µs(1)
Legend:
Note 1:
2:
3:
4:
Shaded cells are are outside of recommended ranges.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequencies is greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep operation.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
11.3
Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to consume current that is out of the devices
specification.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 127
PIC16F87X
11.4
A/D Conversions
Example 11-1 shows how to perform an A/D conversion. The analog pins are configured as analog inputs.
The analog references (VREF) are the device VDD and
VSS. The A/D interrupt is enabled, and the A/D conversion clock is FRC, with the result being left justified. The
conversion is performed on the RA0/AN0 pin (channel
0).
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started.
In Figure 11-6, after the GO bit is set, the first time segmant has a minimum of TCY and a maximum of TAD.
EXAMPLE 11-1: A/D CONVERSION
BSF
BCF
CLRF
BSF
BCF
MOVLW
MOVWF
BCF
BSF
BSF
;
;
;
;
STATUS, RP0
STATUS, RP1
ADCON1
PIE1,
ADIE
STATUS, RP0
11000001
ADCON0
PIR1,
ADIF
INTCON, PEIE
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
Select Bank 1
Configure A/D inputs
Enable A/D interrupts
Select Bank 0
RC Clock, A/D is on, Channel 0 is selected
Clear A/D interrupt flag bit
Enable peripheral interrupts
Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
:
ADCON0, GO
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
; is cleared upon completion of the A/D Conversion.
FIGURE 11-6: A/D CONVERSION TAD CYCLES
Tcy to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b3
b1
b2
b0
b4
b5
b7
b6
b8
b9
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
DS30292A-page 128
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 11-7: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
A/D Clock
= RC?
Yes
Yes
SLEEP
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
No
No
Device in
SLEEP?
Finish Conversion
GO = 0,
ADIF = 1
Yes
Abort Conversion
GO = 0,
ADIF = 0
Wake-up Yes
From Sleep?
Finish Conversion
GO = 0,
ADIF = 1
No
No
Finish Conversion
GO = 0,
ADIF = 1
Wait 2TAD
SLEEP
Power-down A/D
Stay in Sleep
Power-down A/D
Wait 2TAD
Wait 2TAD
11.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-8 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
11.5
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
 1998 Microchip Technology Inc.
Preliminary
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the conversion to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
DS30292A-page 129
PIC16F87X
11.6
Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 11-8: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
0
2107
7
7
0765
0000 00
0000 00
ADRESH
ADRESH
ADRESL
10-bit Result
ADRESL
10-bit Result
Left Justified
Right Justified
11.7
0
A/D Accuracy/Error
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator.
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from an actual transition versus an ideal
transition for any code. The absolute error of the A/D
converter is specified at < ±1 LSb for VDD = VREF (over
the device’s specified operating range). However, the
accuracy of the A/D converter will degrade as VREF
diverges from VDD.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization of
the analog input to a digital code. Quantization error is
typically ± 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D
converter or oversample.
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a system through the interaction of the total leakage current
and source impedance at the analog input.
full scale error is that full scale does not take offset error
into account. Gain error can be calibrated out in software.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition
adjusted by the gain error for each code.
Differential non-linearity measures the maximum
actual code width versus the ideal code width. This
measure is unadjusted.
The maximum pin leakage current is specified in the
Device Data Sheet electrical specification parameter
#D060.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be
minimized to reduce inaccuracies due to noise and
sampling capacitor bleed off.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
Gain error measures the maximum deviation of the last
actual transition and the last ideal transition adjusted
for offset error. This error appears as a change in slope
of the transfer function. The difference in gain error to
DS30292A-page 130
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
11.8
Connection Considerations
FIGURE 11-9: A/D TRANSFER FUNCTION
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.3V, then the accuracy of the conversion is out of specification.
3FFh
11.9
Digital code output3
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
FEh
003h
002h
Transfer Function
1023 LSb
1023.5 LSb
1022 LSb
3 LSb
2 LSb
2.5 LSb
1.5 LSb
1 LSb
0.5 LSb
000h
1022.5 LSb
001h
The transfer function of the A/D converter is as follows:
the first transition occurs when the analog input voltage
(VAIN) equals Analog VREF / 1024 (Figure 11-9).
Analog input voltage
11.10
References
A good reference for the undestanding A/D converter is
the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-03-2848-0).
TABLE 11-2
Addr
Name
0Bh
INTCON
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7
Bit 6
GIE
PEIE
(1)
Bit 5
T0IE
Bit 4
Bit 3
INTE
Bit 2
RBIE
T0IF
Bit 1
Bit 0
INTF
RBIF
POR,
BOR
MCLR, WDT
0000 000x
0000 000u
0Ch
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
—
—
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
0000 00-0
9Fh
ADCON1
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- 0000
--0- 0000
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111
--11 1111
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--0x 0000
--0u 0000
89h(1)
TRISE
IBF
OBF
IBOV
PSPMODE
—
0000 -111
0000 -111
09h(1)
PORTE
—
—
—
—
—
---- -xxx
---- -uuu
Legend:
Note 1:
PORTE Data Direction Bits
RE2
RE1
RE0
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
These registers/bits are not available on the 28-pin devices.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 131
PIC16F87X
NOTES:
DS30292A-page 132
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.0
SPECIAL FEATURES OF THE
CPU
These PICmicros have a host of features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power saving operating modes and offer code protection. These
are:
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
• Low Voltage Programming
• In-Circuit Debugger
12.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
These devices have a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 133
PIC16F87X
FIGURE 12-1: CONFIGURATION WORD
CP1
CP0
BKBUG
-
WRT
CPD
LVP
BODEN
CP1
CP0
PWRTE WDTE F0SC1 F0SC0
bit13
bit0
Register:
Address
CONFIG
2007h
bit 13-12:
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = 1F00h to 1FFFh code protected (PIC16F877, 876)
10 = 0F00h to 0FFFh code protected (PIC16F874, 873)
01 = 1000h to 1FFFh code protected (PIC16F877, 876)
01 = 0800h to 0FFFh code protected (PIC16F874, 873)
00 = 0000h to 1FFFh code protected (PIC16F877, 876)
00 = 0000h to 0FFFh code protected (PIC16F874, 873)
bit 11:
DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10:
Unimplemented: Read as ‘1’
bit 9:
WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8:
CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory code protected
bit 7:
LVP: Low voltage programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
12.2
Oscillator Configurations
12.2.1
OSCILLATOR TYPES
12.2.2
The PIC16F87X can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
DS30292A-page 134
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-2). The
PIC16F87X Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can
have an external clock source to drive the
OSC1/CLKIN pin (Figure 12-3).
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 12-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
C1(1)
TABLE 12-2
Osc Type
OSC1
XTAL
LP
RF(3)
OSC2
XT
SLEEP
RS(2)
C2(1)
To
internal
logic
HS
PIC16F87X
Note1:See Table 12-1 and Table 12-2 for recommended values of C1 and C2.
PIC16F87X
Open
TABLE 12-1
OSC2
CERAMIC RESONATORS
Ranges Tested:
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
OSC1
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
OSC2
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Cap. Range
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
Crystals Used
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
OSC1
Clock from
ext. system
HS
Cap. Range
C1
32 kHz
FIGURE 12-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
XT
Crystal
Freq
These values are for design guidance only.
See notes at bottom of page.
2:A series resistor (RS) may be required for AT strip
cut crystals.
Mode
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
All resonators used did not have built-in capacitors.
 1998 Microchip Technology Inc.
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 12-1).
2: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode as well as
XT mode to avoid overdriving crystals with
low drive level specification.
12.2.3
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 12-4 shows how the R/C combination is connected to the PIC16F87X.
Preliminary
DS30292A-page 135
PIC16F87X
FIGURE 12-4: RC OSCILLATOR MODE
12.3
Reset
The PIC16F87X differentiates between various kinds of
reset:
VDD
Rext
OSC1
Cext
Internal
clock
PIC16F87X
VSS
Fosc/4
Recommended values:
OSC2/CLKOUT
3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
•
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in
Table 12-4. These bits are used in software to determine the nature of the reset. See Table 12-6 for a full
description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 12-5.
These devices have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
DS30292A-page 136
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 12-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
WDT
SLEEP
Time-out
Reset
Vdd rise
detect
Power-on Reset
Vdd
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
R
10-bit Ripple counter
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 137
PIC16F87X
12.4
Power-On Reset (POR)
12.5
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For a
slow rise time, see Figure 12-6.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up conditions.
FIGURE 12-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
D
R
R1
MCLR
C
PIC16F87X
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
DS30292A-page 138
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
12.7
VDD
Power-up Timer (PWRT)
Brown-Out Reset (BOR)
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for
greater than parameter #35, the brown-out situation will
reset the chip. A reset may not occur if VDD falls below
4.0V for less than parameter #35. The chip will remain
in Brown-out Reset until VDD rises above BVDD. The
Power-up Timer will now be invoked and will keep the
chip in RESET an additional 72 ms. If VDD drops below
BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be initialized. Once VDD rises above BVDD,
the Power-up Timer will execute a 72 ms time delay.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled.
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.8
Time-out Sequence
12.9
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 12-7,
Figure 12-8, Figure 12-9 and Figure 12-10 depict timeout sequences on power-up.
Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 12-9). This is useful for testing purposes or to
synchronize more than one PIC16F87X device operating in parallel.
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Table 12-5 shows the reset conditions for some special
function registers, while Table 12-6 shows the reset
conditions for all the registers.
TABLE 12-3
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
1024TOSC
72 ms + 1024TOSC
1024TOSC
RC
72 ms
—
72 ms
—
TABLE 12-4
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 139
PIC16F87X
TABLE 12-6
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
873
874
876
877
N/A
N/A
N/A
TMR0
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
873
874
876
877
0000h
0000h
PC + 1(2)
STATUS
873
874
876
877
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
873
874
876
877
--0x 0000
--0u 0000
--uu uuuu
PORTB
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
873
874
876
877
---- -xxx
---- -uuu
---- -uuu
PCLATH
873
874
876
877
---0 0000
---0 0000
---u uuuu
INTCON
873
874
876
877
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
873
874
876
877
r000 0000
r000 0000
ruuu uuuu(1)
873
874
876
877
0000 0000
0000 0000
uuuu uuuu(1)
PIR2
873
874
876
877
-r-0 0--0
-r-0 0--0
-r-u u--u(1)
TMR1L
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
873
874
876
877
--00 0000
--uu uuuu
--uu uuuu
TMR2
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
T2CON
873
874
876
877
-000 0000
-000 0000
-uuu uuuu
SSPBUF
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
CCPR1L
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
873
874
876
877
--00 0000
--00 0000
--uu uuuu
RCSTA
873
874
876
877
0000 000x
0000 000x
uuuu uuuu
TXREG
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
RCREG
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
CCPR2L
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
ADRESH
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
873
874
876
877
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
873
874
876
877
1111 1111
1111 1111
uuuu uuuu
TRISA
873
874
876
877
--11 1111
--11 1111
--uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for reset value for specific condition.
DS30292A-page 140
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 12-6
INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
TRISB
873
874
876
877
1111 1111
1111 1111
uuuu uuuu
TRISC
873
874
876
877
1111 1111
1111 1111
uuuu uuuu
TRISD
873
874
876
877
1111 1111
1111 1111
uuuu uuuu
TRISE
873
874
876
877
0000 -111
0000 -111
uuuu -uuu
PIE1
873
874
876
877
r000 0000
r000 0000
ruuu uuuu
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
873
874
876
877
-r-0 0--0
-r-0 0--0
-r-u u--u
PIE2
PCON
873
874
876
877
---- --qq
---- --uu
---- --uu
PR2
873
874
876
877
1111 1111
1111 1111
1111 1111
SSPADD
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
873
874
876
877
--00 0000
--00 0000
--uu uuuu
TXSTA
873
874
876
877
0000 -010
0000 -010
uuuu -uuu
SPBRG
873
874
876
877
0000 0000
0000 0000
uuuu uuuu
ADRESL
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
873
874
876
877
--0- 0000
--0- 0000
--U- Uuuu
EEDATA
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATH
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADRH
873
874
876
877
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON1
873
874
876
877
x--- x000
u--- u000
u--- uuuu
EECON2
873
874
876
877
---- ----
---- ----
---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for reset value for specific condition.
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
Vdd
MCLR
INTERNAL POR
Tpwrt
PWRT TIME-OUT
Tost
OST TIME-OUT
INTERNAL RESET
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 141
PIC16F87X
FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
Vdd
MCLR
INTERNAL POR
Tpwrt
PWRT TIME-OUT
Tost
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
Vdd
MCLR
INTERNAL POR
Tpwrt
PWRT TIME-OUT
Tost
OST TIME-OUT
INTERNAL RESET
FIGURE 12-10: SLOW RISE TIME (MCLR TIED TO VDD)
5V
Vdd
1V
0V
MCLR
INTERNAL POR
Tpwrt
PWRT TIME-OUT
Tost
OST TIME-OUT
INTERNAL RESET
DS30292A-page 142
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.10
Interrupts
The PIC16F87X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 143
PIC16F87X
FIGURE 12-11: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
ADIF
ADIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
SSPIF
SSPIE
Interrupt to CPU
RBIF
RBIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
PIC16F876/873
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16F877/874
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DS30292A-page 144
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.10.1 INT INTERRUPT
12.11
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS
register. This will have to be implemented in software.
12.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
Example 12-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0, it must also be defined at 0xA0 in bank
1).
The example:
a)
b)
c)
d)
e)
f)
12.10.3 PORTB INTCON CHANGE
Context Saving During Interrupts
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register.
Executes the interrupt service routine code
(User-generated).
Restores the STATUS register (and bank select
bit).
Restores the W and PCLATH registers.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 145
PIC16F87X
12.12
Watchdog Timer (WDT)
WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
Note:
The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device RESET
condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
FIGURE 12-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-2)
0
Postscaler
M
U
X
1
WDT Timer
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-2)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 12-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h,181h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 12-1 for operation of these bits.
DS30292A-page 146
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.13
Power-down Mode (SLEEP)
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction was
executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
CCP capture mode interrupt.
Special event trigger (Timer1 in asynchronous
mode using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode (SPI/I2C).
USART RX or TX (synchronous slave mode).
A/D conversion (when A/D clock source is RC).
EEPROM Write operation completion
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 147
PIC16F87X
FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Tost(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
Inst(PC) = SLEEP
fetched
Instruction
Inst(PC - 1)
executed
Note 1:
2:
3:
4:
12.14
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
In-Circuit Debugger
12.16
ID Locations
When the DEBUG bit in the configuration word is programmed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging functions when used with MPLAB. When the microcontroller has this feature enabled, some of the resources are
not available for general use. Table 12-7 shows which
features are consumed by the background debugger.
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
TABLE 12-7
For ROM devices, these values are submitted along
with the ROM code.
DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Last 100h words
Data Memory
TBD
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/Vpp, Vdd, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
12.15
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
DS30292A-page 148
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
12.17
In-Circuit Serial Programming
12.18
PIC16F87X microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
The PIC16F87X devices can be programmed only (no
bulk operations such as erase) over the entire VDD
operating range using ICSP. Please refer to the
PIC16F87X Programming Specification, (DS39025).
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
Low Voltage Programming
The LVP bit of the configuration word enables low voltage programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in
the operating voltage range. This mode removes the
requirement of VIHH to be placed on the MCLR pin. The
LVP bit is normally erased to '1' which enables the low
voltage programming. In this mode, the RB3/PGM pin
is dedicated to the programming function and ceases to
be a general purpose I/O pin. VDD is applied to the
MCLR pin during low voltage programming. The device
will enter programming mode when a '1' is placed on
the RB3/PGM pin.
Note 1: The high voltage programming mode is
always available, regardless of the state of
the LVP bit, by applying VIMH to the MCLR
pin.
2: While in this mode the RB3 pin can no
longer be used as a general purpose I/O
pin.
3: VDD must be 5.0V +10% during erase/program operations while in low voltage programming mode.
If Low-voltage programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. To program the device, VIHH must be
placed onto MCLR during programming. The LVP bit
may only be programmed when programming is
entered with VIHH on MCLR. The LVP bit cannot be
programmed when programming is entered with
RB3/PGM.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is available and only high voltage programming mode can be
used to program the device.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 149
PIC16F87X
NOTES:
DS30292A-page 150
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
13.0
INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table 13-2 lists the instructions recognized by the
MPASM assembler.
Figure 13-1 shows the general formats that the instructions can have.
Note:
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
OPCODE
OPCODE
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Program Counter
PC
TO
PD
0
f (FILE #)
Bit-oriented file register operations
13
10 9
7 6
OPCODE FIELD
DESCRIPTIONS
Field
d
d
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 13-1
To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
Time-out bit
Power-down bit
10
0
k (literal)
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
A description of each instruction is available in the
PICmicro™
Mid-Range
Reference
Manual,
(DS33023).
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 151
PIC16F87X
TABLE 13-2
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30292A-page 152
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
14.0
DEVELOPMENT SUPPORT
14.1
Development Tools
14.3
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• MPLAB™-ICE Real-Time In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• SIMICE
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH−MP)
• KEELOQ® Evaluation Kits and Programmer
14.2
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 386 through Pentium based
machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.
14.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
MPLAB-ICE: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and
download, and source debugging from a single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip microcontrollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive
development tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x or
Windows 95 environment were chosen to best make
these features available to you, the end user.
MPLAB-ICE
is
available
in
two
versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed reange of the PICmicro
MCU.
 1998 Microchip Technology Inc.
ICEPIC: Low-Cost PICmicro
In-Circuit Emulator
14.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE
compliant.
14.6
SIMICE Entry-Level Hardware
Simulator
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment
with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment
(IDE) software. Specifically, SIMICE provides hardware
simulation for Microchip’s PIC12C5XX, PIC12CE5XX,
and PIC16C5X families of PICmicro 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to
provide non-real-time I/O port emulation. SIMICE
enables a developer to run simulator code for driving
the target system. In addition, the target system can
Preliminary
DS30292A-page 153
PIC16F87X
provide input to the simulator code. This capability
allows for simple and interactive debugging without
having to manually generate MPLAB-SIM stimulus
files. SIMICE is a valuable debugging tool for entrylevel system development.
14.7
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
14.8
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
14.9
14.10
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
14.11
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
DS30292A-page 154
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features
include an RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM-3 board is an LCD panel, with 4 commons
and 12 segments, that is capable of displaying time,
temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1
software for showing the demultiplexed LCD signals on
a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
MPASM allows full symbolic debugging from MPLABICE, Microchip’s Universal Emulator System.
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
14.12
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
14.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
14.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPASM. The Software Simulator
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
14.13
MPLAB-C17 Compiler
The MPLAB-C17 Code Development System is a
complete ANSI ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
14.14
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 155
Emulator Products
ICEPIC Low-Cost
In-Circuit Emulator
MPLAB
Integrated
Development
Environment
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB C17*
Compiler
ü
ü
ü
ü
ü
ü
HCS200
HCS300
HCS301
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
ü
ü
ü
ü
ü
ü
ü
ü
ü
Total Endurance
Software Model
ü
PICSTARTPlus
Programmers
Preliminary
Software Tools
ü
24CXX
25CXX
93CXX
Low-Cost
Universal Dev. Kit
PRO MATE II
Universal
Programmer
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
KEELOQ
Programmer
 1998 Microchip Technology Inc.
ü
Designers Kit
SIMICE
PICDEM-14A
PICDEM-1
PICDEM-2
PICDEM-3
ü
ü
SEEVAL
Demo Boards
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
KEELOQ®
Evaluation Kit
ü
KEELOQ
Transponder Kit
ü
PIC16F87X
ü
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX
DEVELOPMENT TOOLS FROM MICROCHIP
PIC14000
TABLE 14-1
DS30292A-page 156
MPLAB™-ICE
PIC12C5XX
PIC16F87X
15.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Voltage on RA4 with respect to Vss ..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) ..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the 28-pin devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 157
PIC16F87X
TABLE 15-1
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16F873-04
PIC16F873-20
PIC16LF873-04
PIC16F874-04
PIC16F874-20
PIC16LF874-04
OSC
PIC16F876-04
PIC16F876-20
PIC16LF876-04
PIC16F877-04
PIC16F877-20
PIC16LF877-04
VDD: 4.0V to 5.5V
VDD: 4.5V to 5.5V
VDD: 2.0V to 5.5V
IDD: 5 mA max.
IDD: 2.0 mA typ.
IDD: 3.8 mA max.
at 5.5V
at 5.5V
at 3.0V
RC
IPD: 16 µA max.
IPD: 1.5 µA typ.
IPD: 5 µA max. at 3V
at 4V
at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 4.0V to 5.5V
VDD: 4.5V to 5.5V
VDD: 2.0V to 5.5V
IDD: 5 mA max.
IDD: 2.0 mA typ.
IDD: 3.8 mA max.
at 5.5V
at 5.5V
XT
at 3.0V
IPD: 16 µA max.
IPD: 1.5 µA typ.
IPD: 5 µA max. at 3V
at 4V
at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ.
IDD: 20 mA max.
at 5.5V
at 5.5V
Not recommended for use in HS mode
HS
IPD: 1.5 µA typ.
IPD: 1.5 µA typ.
at 4.5V
at 4.5V
Freq: 4 MHz max.
Freq: 20 MHz max.
VDD: 4.0V to 5.5V
VDD: 2.0V to 5.5V
IDD: 52.5 µA typ.
IDD: 48 µA max.
at 32 kHz, 4.0V
at 32 kHz, 3.0V
LP
Not recommended for use in LP mode
IPD: 0.9 µA typ.
IPD: 5.0 µA max.
at 4.0V
at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
Note:
This is an advanced copy of the data sheet and therefore the contents and specifications are subject to
change based on device characterization.
DS30292A-page 158
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
15.1
DC Characteristics:
PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
-
5.5
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VPOR
VDD start voltage to
ensure internal Power-on
Reset signal
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
V
D010
Supply Current (Note 2,5) IDD
-
2.0
5
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
10
20
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
∆IBOR
-
85
200
µA
BOR enabled VDD = 5.0V
D020 Power-down Current
D021 (Note 3,5)
D021A
D021B
IPD
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D023*
∆IBOR
-
85
200
µA
BOR enabled VDD = 5.0V
D013
D015*
*
†
Note 1:
2:
3:
4:
5:
6:
Brown-out Reset Current
(Note 6)
Brown-out Reset Current
(Note 6)
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
BODEN bit in configuration word enabled
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 159
PIC16F87X
15.2
DC Characteristics:
PIC16LF873/874/876/877-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
Typ† Max Units
Conditions
D001
Supply Voltage
VDD
2.0
-
5.5
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Poweron Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
3.7
4.0
4.3
V
-
2.0
3.8
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
20
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D005
Brown-out Reset Voltage
BVDD
D010
Supply Current (Note
2,5)
IDD
D010A
LP, XT, RC osc configuration (DC - 4 MHz)
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
BODEN bit in configuration word enabled
D015*
Brown-out Reset Current ∆IBOR
(Note 6)
-
85
200
µA
BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5)
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023*
Brown-out Reset Current ∆IBOR
(Note 6)
-
85
200
µA
BOR enabled VDD = 5.0V
*
†
Note 1:
2:
3:
4:
5:
6:
IPD
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30292A-page 160
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
15.3
DC Characteristics:
PIC16F873/874/876/877-04 (Commercial, Industrial
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
D034
with Schmitt Trigger buffer
D034A
with SMBus
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
D042
MCLR
D042A OSC1 (XT, HS and LP)
D043
OSC1 (in RC mode)
Ports RC3 and RC4
D044
with Schmitt Trigger buffer
D044A
with SMBus
D070
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
D060
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Sym
Min Typ† Max Units
Conditions
VIL
VSS
VSS
VSS
VSS
VSS
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
VSS
-0.5
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
VDD
5.5
400
V For entire VDD range
V for VDD = 4.5 to 5.5V
µA VDD = 5V, VPIN = VSS
VIH
2.0
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
0.7VDD
1.4
IPURB
50
250
IIL
-
-
±1
-
-
±5
±5
Note1
Note1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 161
PIC16F87X
DC CHARACTERISTICS
Param
No.
Characteristic
Output Low Voltage
I/O ports
D080
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Sym
Min Typ† Max Units
Conditions
VOL
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
VOH VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
VOD
-
-
8.5
V
COSC2
-
-
15
pF
CIO
CB
-
-
50
400
pF
pF
ED
VDRW
100K
Vmin
-
5.5
TDEW
-
4
10
E/W 25°C at 5V
V Using EECON to read/write
Vmin = min operating voltage
ms
EP
VPR
VPEW
1000
Vmin
4.5
Vmin
-
5.5
5.5
5.5
E/W
V
V
V
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
Output High Voltage
I/O ports (Note 3)
D090
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D150*
Open-Drain High Voltage
D100
Capacitive Loading Specs on
Output Pins
OSC2 pin
D101
D102
All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode
Data EEPROM Memory
Endurance
VDD for read/write
D120
D121
D122
D130
D131
D132
D132a
Erase/write cycle time
Program FLASH Memory
Endurance
VDD for read
VDD for erase/write
VDD for erase/write
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when external clock is used to drive OSC1.
25°C at 5V
Vmin = min operating voltage
using ICSP port
using EECON to read/write, Vmin =
min operating voltage
D133
Erase/Write cycle time
TPEW
4
10
ms
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
*
†
DS30292A-page 162
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
15.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 15-1: LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as
ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the 28-pin devices.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 163
PIC16F87X
FIGURE 15-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 15-2
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3
TosL, External Clock in (OSC1) High or
100
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30292A-page 164
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 15-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-3
Param Sym
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH Port in valid before CLKOUT ↑
TOSC + 200
—
—
ns
Note 1
16*
TckH2ioI
0
—
—
ns
Note 1
17*
TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid
—
50
150
ns
18*
TosH2ioI
Standard (F)
100
—
—
ns
Extended (LF)
200
—
—
ns
Port in hold after CLKOUT ↑
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
19*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
Standard (F)
—
10
40
ns
Extended (LF)
—
—
80
ns
21*
TioF
Port output fall time
Standard (F)
—
10
40
ns
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
Extended (LF)
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 165
PIC16F87X
FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 15-1 for load conditions.
FIGURE 15-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 15-4
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
33*
Tpwrt
34
35
*
†
Min
Typ†
Max
Units
Conditions
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Power up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
µs
TBOR
Brown-out Reset pulse width
100
—
—
µs
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30292A-page 166
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 15-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-5
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16F7X
15
Prescaler =
PIC16LF7X
25
2,4,8
Asynchronous PIC16F7X
30
PIC16LF7X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16F7X
15
Prescaler =
PIC16LF7X
25
2,4,8
Asynchronous PIC16F7X
30
PIC16LF7X
50
Tt1P
T1CKI input period Synchronous PIC16F7X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LF7X
50 OR TCY + 40
N
Asynchronous PIC16F7X
60
PIC16LF7X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 167
PIC16F87X
FIGURE 15-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-6
Param
No.
50*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
Min
No Prescaler
Standard(F)
With Prescaler Extended(LF)
51*
TccH CCP1 and CCP2
input high time
No Prescaler
Standard(F)
With Prescaler Extended(LF)
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
—
10
25
ns
52*
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise time
Standard(F)
Extended(LF)
—
25
45
ns
54*
TccF CCP1 and CCP2 output fall time
Standard(F)
—
10
25
ns
Extended(LF)
—
25
45
ns
*
†
N = prescale
value (1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated.
These parameters are for design guidance only and are not tested.
DS30292A-page 168
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 15-8: PARALLEL SLAVE PORT TIMING (40-PIN DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-7
Parameter
No.
62
PARALLEL SLAVE PORT REQUIREMENTS (40-PIN DEVICES ONLY)
Sym
Characteristic
Min Typ† Max Units
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
63*
TwrH2dtI
WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)
64
65
*
†
TrdL2dtV
TrdH2dtI
RD↓ and CS↓ to data–out valid
RD↑ or CS↓ to data–out invalid
20
25
—
—
—
—
ns
ns
20
—
—
ns
35
—
—
ns
—
—
—
—
80
90
ns
ns
10
—
30
ns
Conditions
Extended
Range Only
Extended
Range Only
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 169
PIC16F87X
FIGURE 15-9: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Refer to Figure 15-1 for load conditions.
FIGURE 15-10: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Refer to Figure 15-1 for load conditions.
DS30292A-page 170
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 15-11: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Refer to Figure 15-1 for load conditions.
FIGURE 15-12: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Refer to Figure 15-1 for load conditions.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 171
PIC16F87X
TABLE 15-8
Parameter
No.
70*
71*
72*
73*
74*
75*
76*
77*
78*
79*
80*
SPI MODE REQUIREMENTS
Sym
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscR
TscF
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
TssL2doV
81*
82*
83*
*
†
Characteristic
Min
Typ†
Max
Units
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
100
—
—
ns
—
—
10
—
10
10
—
10
25
25
50
25
ns
ns
ns
ns
—
—
10
—
25
50
ns
ns
TCY
—
—
ns
—
—
50
ns
SCK input high time (slave mode)
SCK input low time (slave mode)
Setup time of SDI data input to SCK
edge
Hold time of SDI data input to SCK
edge
SDO data output rise time
SDO data output fall time
SS↑ to SDO output hi-impedance
SCK output rise time (master
mode)
SCK output fall time (master mode)
SDO data output valid after SCK
edge
SDO data output setup to SCK
edge
SDO data output valid after SS↓
edge
SS ↑ after SCK edge
Conditions
TscH2ssH,
1.5TCY + 40
—
—
ns
TscL2ssH
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-13: I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-9
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90
TSU:STA
91
THD:STA
92
TSU:STO
93
THD:STO
DS30292A-page 172
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Preliminary
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
 1998 Microchip Technology Inc.
PIC16F87X
FIGURE 15-14: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-1 for load conditions.
I2C BUS DATA REQUIREMENTS
TABLE 15-10
Parameter
No.
Sym
Characteristic
100
THIGH
Clock high time
101
102
103
TLOW
TR
TF
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Clock low time
SDA and SCL rise
time
90
TSU:STA
START condition
setup time
91
THD:STA
START condition hold
time
106
THD:DAT
Data input hold time
107
TSU:DAT
Data input setup time
92
TSU:STO
STOP condition setup
time
109
TAA
Output valid from
clock
110
TBUF
Bus free time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 173
PIC16F87X
FIGURE 15-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-11
Param
No.
120
121
Sym
Characteristic
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Tckrf
122
†:
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Tdtrf
Min
Typ†
Max
Units Conditions
Standard(F)
—
—
80
ns
Extended(LF)
—
—
100
ns
Clock out rise time and fall time Standard(F)
(Master Mode)
Extended(LF)
—
—
45
ns
—
—
50
ns
Data out rise time and fall time
Standard(F)
—
—
45
ns
Extended(LF)
—
—
50
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-12
Parameter
No.
†:
USART SYNCHRONOUS RECEIVE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
125
TdtV2ckL
126
TckL2dtl
Units Conditions
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
Data hold after CK ↓ (DT hold time)
15
—
—
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30292A-page 174
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
TABLE 15-13
Param
No.
Sym
A01
NR
A03
PIC16F873/874/876/877-04 (COMMERCIAL, INDUSTRIAL)
PIC16F873/874/876/877-20 (COMMERCIAL, INDUSTRIAL)
PIC16LF873/874/876/877-04 (COMMERCIAL, INDUSTRIAL)
Min
Typ†
Max
Units
Resolution
—
—
10-bits
bit
EIL
Integral linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF
Offset error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07
EGN
Gain error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity
—
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
A20
VREF
Reference voltage (VREF+ - VREF-)
2.0V
—
VDD + 0.3
V
Absolute minimum electrical
spec. To ensure 10-bit
accuracy.
A21
VREF+ Reference voltage High
AVDD
- 2.5V
AVDD
+ 0.3V
V
A22
VREF- Reference voltage low
AVSS
- 0.3V
VREF+
- 2.0V
V
A25
VAIN
Analog input voltage
A30
ZAIN
A40
IAD
A50
IREF
Characteristic
Conditions
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VSS - 0.3
—
VREF + 0.3
V
Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A/D conversion current (VDD)
Standard
—
220
—
µA
Extended
—
90
—
µA
10
—
1000
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 10.1.
—
—
10
µA
During A/D Conversion cycle
VREF input current (Note 2)
Average current consumption
when A/D is on.
(Note 1)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 175
PIC16F87X
FIGURE 15-17: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2) (1)
131
Q4
130
132
A/D CLK
9
A/D DATA
8
7
...
...
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 15-14
Param
No.
130
A/D CONVERSION REQUIREMENTS
Sym Characteristic
TAD
A/D clock period
Min
Conditions
1.6
—
—
µs
3.0
—
—
µs
TOSC based, VREF full range
Standard(F)
2.0
4.0
6.0
µs
A/D RC Mode
Extended(LF)
3.0
6.0
9.0
µs
A/D RC Mode
—
12
TAD
Note 2
40
—
µs
10*
—
—
µs
The minimum time is the amplifier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
132
TACQ Acquisition time
Q4 to A/D clock start
Units
Extended(LF)
TCNV Conversion time (not including S/H time)
(Note 1)
TGO
Max
Standard(F)
131
134
Typ†
TOSC based, VREF ≥ 3.0V
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30292A-page 176
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
16.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over
a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or 'min'
represents (mean + 3σ) or (mean - 3σ) respectively,
where σ is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 177
PIC16F87X
NOTES:
DS30292A-page 178
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
17.0
PACKAGING INFORMATION
17.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
MMMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXXX
PIC16F876-20/SP
AABBCDE
9817HAT
28-Lead SOIC
Example
MMMMMMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXXXXXXX
AABBCDE
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
PIC16F876-04/SO
9810/SAA
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 179
PIC16F87X
Package Marking Information (Cont’d)
40-Lead PDIP
Example
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
AABBCDE
PIC16F877-04/P
9812SAA
44-Lead TQFP
Example
PIC16F877
-04/PT
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
9811HAT
44-Lead MQFP
Example
PIC16F877
-20/PQ
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
9804SAT
44-Lead PLCC
Example
PIC16F877
-20/L
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
DS30292A-page 180
9803SAT
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
17.2
K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
E
D
2
n
α
1
E1
A1
A
R
L
c
β
B1
A2
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
p
B
INCHES*
NOM
0.300
28
0.100
0.019
0.016
0.053
0.040
0.005
0.000
0.010
0.008
0.150
0.140
0.090
0.070
0.020
0.015
0.130
0.125
1.365
1.345
0.288
0.280
0.270
0.283
0.320
0.350
5
10
5
10
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
MAX
0.022
0.065
0.010
0.012
0.160
0.110
0.025
0.135
1.385
0.295
0.295
0.380
15
15
MILLIMETERS
NOM
MAX
7.62
28
2.54
0.48
0.41
0.56
1.33
1.02
1.65
0.13
0.00
0.25
0.25
0.20
0.30
3.81
3.56
4.06
2.29
1.78
2.79
0.51
0.38
0.64
3.30
3.18
3.43
34.67
34.16
35.18
7.11
7.30
7.49
6.86
7.18
7.49
8.13
8.89
9.65
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 181
PIC16F87X
17.3
K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
E
p
D
B
2
1
n
X
α
45 °
L
R2
c
A
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A1
φ
R1
L1
A2
INCHES*
NOM
0.050
28
0.099
0.093
0.058
0.048
0.008
0.004
0.706
0.700
0.296
0.292
0.407
0.394
0.020
0.010
0.005
0.005
0.005
0.005
0.016
0.011
0
4
0.015
0.010
0.011
0.009
0.014
0.017
0
12
0
12
MIN
p
n
A
A1
A2
D‡
E‡
E1
X
R1
R2
L
φ
L1
c
B†
α
β
MAX
0.104
0.068
0.011
0.712
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
28
2.36
2.50
2.64
1.22
1.47
1.73
0.10
0.19
0.28
17.78
17.93
18.08
7.42
7.51
7.59
10.01
10.33
10.64
0.50
0.74
0.25
0.13
0.13
0.25
0.13
0.25
0.13
0.28
0.41
0.53
8
0
4
0.25
0.38
0.51
0.23
0.27
0.30
0.36
0.42
0.48
0
12
15
0
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30292A-page 182
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
17.4
K04-016 40-Lead Plastic Dual In-line (P) – 600 mil
E
D
α
2
1
n
A1
E1
A
R
L
c
B1
β
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
A2
INCHES*
NOM
0.600
40
0.100
0.018
0.016
0.050
0.045
0.005
0.000
0.010
0.009
0.160
0.110
0.073
0.093
0.020
0.020
0.125
0.130
2.013
2.018
0.530
0.535
0.565
0.545
0.630
0.610
5
10
10
5
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
p
B
MAX
0.020
0.055
0.010
0.011
0.160
0.113
0.040
0.135
2.023
0.540
0.585
0.670
15
15
MILLIMETERS
NOM
MAX
15.24
40
2.54
0.46
0.51
0.41
1.27
1.40
1.14
0.13
0.25
0.00
0.25
0.28
0.23
4.06
4.06
2.79
2.87
1.85
2.36
1.02
0.51
0.51
3.43
3.18
3.30
51.26
51.38
51.13
13.59
13.72
13.46
14.35
14.86
13.84
15.49
17.02
16.00
5
15
10
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 183
PIC16F87X
17.5
K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
L
α
A
R2
c
φ
L1
R1
β
Units
Dimension Limits
Pitch
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
p
n
n1
A
A1
A2
R1
R2
L
φ
L1
c
B†
D1
E1
D‡
E‡
X
α
β
0.039
0.015
0.002
0.003
0.003
0.005
0
0.003
0.004
0.012
0.463
0.463
0.390
0.390
0.025
5
5
A1
A2
INCHES
NOM
0.031
44
11
0.043
0.025
0.004
0.003
0.006
0.010
3.5
0.008
0.006
0.015
0.472
0.472
0.394
0.394
0.035
10
12
MAX
0.047
0.035
0.006
0.010
0.008
0.015
7
0.013
0.008
0.018
0.482
0.482
0.398
0.398
0.045
15
15
MILLIMETERS*
NOM
MAX
0.80
44
11
1.20
1.00
1.10
0.89
0.38
0.64
0.15
0.05
0.10
0.25
0.08
0.08
0.20
0.08
0.14
0.38
0.13
0.25
7
0
3.5
0.33
0.08
0.20
0.20
0.09
0.15
0.45
0.30
0.38
12.25
11.75
12.00
12.25
11.75
12.00
9.90
10.00
10.10
9.90
10.00
10.10
0.64
0.89
1.14
5
10
15
5
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-026 ACB
DS30292A-page 184
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
17.6
K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
E1
E
# leads = n1
p
D D1
2
1
B
n
X x 45°
α
L
R2
c
A
R1
β
L1
Units
Dimension Limits
Pitch
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
p
n
n1
A
A1
A2
R1
R2
L
φ
L1
c
B†
D1
E1
D‡
E‡
X
α
β
0.079
0.032
0.002
0.005
0.005
0.015
0
0.011
0.005
0.012
0.510
0.510
0.390
0.390
0.025
5
5
φ
A1
A2
INCHES
NOM
0.031
44
11
0.086
0.044
0.006
0.005
0.012
0.020
3.5
0.016
0.007
0.015
0.520
0.520
0.394
0.394
0.035
10
12
MAX
0.093
0.056
0.010
0.010
0.015
0.025
7
0.021
0.009
0.018
0.530
0.530
0.398
0.398
0.045
15
15
MILLIMETERS*
NOM
MAX
0.80
44
11
2.35
2.18
2.00
1.41
1.11
0.81
0.25
0.15
0.05
0.25
0.13
0.13
0.38
0.13
0.30
0.64
0.38
0.51
7
0
3.5
0.53
0.28
0.41
0.23
0.18
0.13
0.45
0.30
0.37
13.45
12.95
13.20
13.45
12.95
13.20
9.90
10.00
10.10
9.90
10.00
10.10
0.635
0.89
1.143
5
10
15
5
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-022 AB
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 185
PIC16F87X
17.7
K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D D1
n12
CH2 x 45°
α
A3
CH1 x 45°
R1
L
35°
A1
R2
β
c
A
B1
B
A2
p
E2
Units
Dimension Limits
Number of Pins
Pitch
Overall Pack. Height
Shoulder Height
Standoff
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer (other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
Footprint Length
Pins along Width
Lead Thickness
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
Mold Draft Angle Bottom
D2
MIN
n
p
A
A1
A2
A3
CH1
CH2
E1
D1
E‡
D‡
E2
D2
n1
c
B1†
B
L
R1
R2
α
β
0.165
0.095
0.015
0.024
0.040
0.000
0.685
0.685
0.650
0.650
0.610
0.610
0.008
0.026
0.015
0.050
0.003
0.015
0
0
INCHES*
NOM
44
0.050
0.173
0.103
0.023
0.029
0.045
0.005
0.690
0.690
0.653
0.653
0.620
0.620
11
0.010
0.029
0.018
0.058
0.005
0.025
5
5
MAX
0.180
0.110
0.030
0.034
0.050
0.010
0.695
0.695
0.656
0.656
0.630
0.630
0.012
0.032
0.021
0.065
0.010
0.035
10
10
MILLIMETERS
NOM
MAX
44
1.27
4.38
4.19
4.57
2.60
2.41
2.79
0.57
0.38
0.76
0.74
0.61
0.86
1.14
1.02
1.27
0.13
0.00
0.25
17.53
17.40
17.65
17.53
17.40
17.65
16.59
16.51
16.66
16.59
16.51
16.66
15.75
15.49
16.00
15.75
15.49
16.00
11
0.25
0.20
0.30
0.81
0.66
0.74
0.53
0.38
0.46
1.65
1.27
1.46
0.13
0.25
0.08
0.64
0.89
0.38
10
0
5
10
0
5
MIN
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MO-047 AC
DS30292A-page 186
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
98
This is a new data sheet. However, these devices are similar to the PIC16C7X
devices found in the PIC16C7X Data Sheet (DS30390)
B
98
Data Memory Map for PIC16F873/874, moved ADFM bit from ADCON1<5> to
ADCON1<7>
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Difference
PIC16F876/873
PIC16F877/874
A/D
5 channels, 10bits
8 channels, 10bits
Parallel Slave Port
no
yes
Packages
28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC, 28-pin SSOP
40-pin PDIP, 40-pin windowed CERDIP, 44-pin TQFP, 44-pin MQFP, 44pin PLCC
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of
devices to the ones listed in this data sheet are listed in
Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
Characteristic
PIC16C7X
PIC16F87X
Pins
28/40
28/40
Timers
3
3
Interrupts
11 or 12
13 or 14
Communication
PSP, USART, SSP (SPI, I2C Slave)
PSP, USART, SSP (SPI, I2C Master/Slave)
Frequency
20 MHz
20 MHz
A/D
8-bit
10-bit
CCP
2
2
Program Memory
4K, 8K EPROM
4K, 8K FLASH
RAM
192, 368 bytes
192, 368 bytes
EEPROM data
None
128, 256 bytes
Other
---
In-Circuit Debugger, Low Voltage Programming
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 187
PIC16F87X
NOTES:
DS30292A-page 188
Preliminary
 1998 Microchip Technology Inc.
PIC16F87X
A
A/D ................................................................................... 121
Accuracy/Error ......................................................... 130
ADCON0 Register .................................................... 121
ADCON1 Register .................................................... 122
ADIF bit .................................................................... 123
Analog Input Model Block Diagram .......................... 126
Analog Port Pins ...................................... 7, 8, 9, 37, 38
Block Diagram .......................................................... 124
Configuring Analog Port Pins ................................... 127
Configuring the Interrupt .......................................... 123
Configuring the Module ............................................ 123
Connection Considerations ...................................... 131
Conversion Clock ..................................................... 127
Conversions ............................................................. 128
Delays ...................................................................... 126
Effects of a Reset ..................................................... 130
Equations ................................................................. 126
Flowchart of A/D Operation ...................................... 129
GO/DONE bit ........................................................... 123
Internal Sampling Switch (Rss) Impedence ............. 125
Operation During Sleep ........................................... 129
Sampling Requirements ........................................... 125
Sampling Time ......................................................... 126
Source Impedence ................................................... 125
Special Event Trigger (CCP) ...................................... 57
Time Delays ............................................................. 126
Transfer Function ..................................................... 131
Absolute Maximum Ratings ............................................. 157
ACK .................................................................................... 72
Acknowledge Data bit, AKD ............................................... 64
Acknowledge Pulse ............................................................ 72
Acknowledge Sequence Enable bit, AKE .......................... 64
Acknowledge Status bit, AKS ............................................ 64
ADRES Register ........................................................ 16, 121
AKD .................................................................................... 64
AKE .................................................................................... 64
AKS .............................................................................. 64, 87
Application Note AN578, "Use of the SSP
Module in the I2C Multi-Master Environment." ................... 71
Architecture
PIC16C63A/PIC16C73B Block Diagram ...................... 5
PIC16C65B/PIC16C74B Block Diagram ...................... 6
Assembler
MPASM Assembler .................................................. 154
B
Banking, Data Memory ................................................ 12, 19
Baud Rate Generator ......................................................... 81
BCLIF ................................................................................. 25
BF .................................................................... 62, 72, 87, 90
Block Diagrams
A/D ........................................................................... 124
Analog Input Model .................................................. 126
Baud Rate Generator ................................................. 81
I2C Master Mode ........................................................ 79
I2C Module ................................................................. 71
SSP (I2C Mode) ......................................................... 71
SSP (SPI Mode) ......................................................... 65
BRG ................................................................................... 81
Brown-out Reset (BOR) ................... 133, 136, 138, 139, 140
BOR Status (BOR Bit) ................................................ 26
Buffer Full bit, BF ............................................................... 72
Buffer Full Status bit, BF .................................................... 62
Bus Arbitration ................................................................... 98
 1998 Microchip Technology Inc.
Bus Collision
Section ....................................................................... 98
Bus Collision During a RESTART Condition ................... 101
Bus Collision During a Start Condition .............................. 99
Bus Collision During a Stop Condition ............................. 102
Bus Collision Interrupt Flag bit, BCLIF .............................. 25
C
Capture (CCP Module) ...................................................... 56
Block Diagram ........................................................... 56
CCP Pin Configuration .............................................. 56
CCPR1H:CCPR1L Registers .................................... 56
Changing Between Capture Prescalers .................... 56
Software Interrupt ...................................................... 56
Timer1 Mode Selection .............................................. 56
Capture/Compare/PWM (CCP) ......................................... 55
CCP1 ......................................................................... 55
CCP1CON Register .......................................... 55
CCPR1H Register ............................................. 55
CCPR1L Register .............................................. 55
RC2/CCP1 Pin ................................................ 7, 9
CCP2 ......................................................................... 55
CCP2CON Register .......................................... 55
CCPR2H Register ............................................. 55
CCPR2L Register .............................................. 55
RC1/T1OSI/CCP2 Pin ..................................... 7, 9
Interaction of Two CCP Modules ............................... 55
Timer Resources ....................................................... 55
CCP1CON ......................................................................... 18
CCP1CON Register ........................................................... 55
CCP1M3:CCP1M0 Bits ............................................. 55
CCP1X:CCP1Y Bits ................................................... 55
CCP2CON ......................................................................... 18
CCP2CON Register ........................................................... 55
CCP2M3:CCP2M0 Bits ............................................. 55
CCP2X:CCP2Y Bits ................................................... 55
CCPR1H Register ....................................................... 16, 18
CCPR1L Register .............................................................. 18
CCPR2H Register ....................................................... 16, 18
CCPR2L Register ........................................................ 16, 18
CKE ................................................................................... 62
CKP ................................................................................... 63
Clock Polarity Select bit, CKP ........................................... 63
Code Examples
Loading the SSPBUF register ................................... 66
Code Protection ....................................................... 133, 148
Compare (CCP Module) .................................................... 57
Block Diagram ........................................................... 57
CCP Pin Configuration .............................................. 57
CCPR1H:CCPR1L Registers .................................... 57
Software Interrupt ...................................................... 57
Special Event Trigger .......................................... 51, 57
Timer1 Mode Selection .............................................. 57
Configuration Bits ............................................................ 133
Conversion Considerations ............................................. 187
D
D/A ..................................................................................... 62
Data Memory ..................................................................... 12
Bank Select (RP1:RP0 Bits) ................................ 12, 19
General Purpose Registers ....................................... 12
Register File Map ...................................................... 13
Special Function Registers ........................................ 15
Data/Address bit, D/A ........................................................ 62
DS30292A-page 189
PIC16F87X
DC Characteristics
PIC16C76 ................................................................ 159
PIC16C77 ................................................................ 159
Development Support ...................................................... 153
Development Tools .......................................................... 153
Device Differences ........................................................... 187
Direct Addressing ............................................................... 28
E
Electrical Characteristics .................................................. 157
Errata ................................................................................... 4
External Power-on Reset Circuit ...................................... 138
F
Firmware Instructions ....................................................... 151
Flowcharts
Acknowledge .............................................................. 94
Master Receiver ......................................................... 91
Master Transmit ......................................................... 88
Restart Condition ....................................................... 85
Start Condition ........................................................... 83
Stop Condition ........................................................... 96
FSR Register .......................................................... 16, 17, 18
Fuzzy Logic Dev. System (fuzzyTECH-MP) .................. 155
G
GCE ................................................................................... 64
General Call Address Sequence ........................................ 77
General Call Address Support ........................................... 77
General Call Enable bit, GCE ............................................ 64
I
I/O Ports ............................................................................. 29
I2C ...................................................................................... 71
I2C Master Mode Receiver Flowchart ................................ 91
I2C Master Mode Reception ............................................... 90
I2C Master Mode Restart Condition ................................... 84
I2C Mode Selection ............................................................ 71
I2C Module
Acknowledge Flowchart ............................................. 94
Acknowledge Sequence timing .................................. 93
Addressing ................................................................. 72
Baud Rate Generator ................................................. 81
Block Diagram ............................................................ 79
BRG Block Diagram ................................................... 81
BRG Reset due to SDA Collision ............................. 100
BRG Timing ............................................................... 81
Bus Arbitration ........................................................... 98
Bus Collision .............................................................. 98
Acknowledge ...................................................... 98
Restart Condition ............................................. 101
Restart Condition Timing (Case1) .................... 101
Restart Condition Timing (Case2) .................... 101
Start Condition ................................................... 99
Start Condition Timing ............................... 99, 100
Stop Condition ................................................. 102
Stop Condition Timing (Case1) ........................ 102
Stop Condition Timing (Case2) ........................ 102
Transmit Timing ................................................. 98
Bus Collision timing .................................................... 98
Clock Arbitration ......................................................... 97
Clock Arbitration Timing (Master Transmit) ............... 97
Conditions to not give ACK Pulse .............................. 72
General Call Address Support ................................... 77
Master Mode .............................................................. 79
Master Mode 7-bit Reception timing .......................... 92
Master Mode Operation ............................................. 80
DS30292A-page 190
Master Mode Start Condition ..................................... 82
Master Mode Transmission ....................................... 87
Master Mode Transmit Sequence ............................. 80
Master Transmit Flowchart ........................................ 88
Multi-Master Communication ..................................... 98
Multi-master Mode ..................................................... 80
Operation ................................................................... 71
Repeat Start Condition timing .................................... 84
Restart Condition Flowchart ...................................... 85
Slave Mode ................................................................ 72
Slave Reception ........................................................ 73
Slave Transmission ................................................... 73
SSPBUF .................................................................... 72
Start Condition Flowchart .......................................... 83
Stop Condition Flowchart .......................................... 96
Stop Condition Receive or Transmit timing ............... 95
Stop Condition timing ................................................ 95
Waveforms for 7-bit Reception .................................. 73
Waveforms for 7-bit Transmission ............................. 74
I2C Module Address Register, SSPADD ........................... 72
I2C Slave Mode .................................................................. 72
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ......... 153
ID Locations ............................................................. 133, 148
In-Circuit Serial Programming (ICSP) ...................... 133, 148
INDF .................................................................................. 18
INDF Register .............................................................. 16, 17
Indirect Addressing ............................................................ 28
FSR Register ............................................................. 12
Instruction Format ............................................................ 151
Instruction Set .................................................................. 151
Summary Table ....................................................... 152
INTCON ............................................................................. 18
INTCON Register ............................................................... 21
GIE Bit ....................................................................... 21
INTE Bit ..................................................................... 21
INTF Bit ..................................................................... 21
PEIE Bit ..................................................................... 21
RBIE Bit ..................................................................... 21
RBIF Bit ............................................................... 21, 31
T0IE Bit ...................................................................... 21
T0IF Bit ...................................................................... 21
Inter-Integrated Circuit (I2C) .............................................. 61
Internal Sampling Switch (Rss) Impedence ..................... 125
Interrupt Sources ..................................................... 133, 143
Block Diagram ......................................................... 144
Capture Complete (CCP) .......................................... 56
Compare Complete (CCP) ........................................ 57
Interrupt on Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ..................................... 7, 8, 145
TMR0 Overflow .................................................. 48, 145
TMR1 Overflow .................................................... 49, 51
TMR2 to PR2 Match .................................................. 54
TMR2 to PR2 Match (PWM) ................................ 53, 58
USART Receive/Transmit Complete ....................... 105
Interrupts
Bus Collision Interrupt ............................................... 25
Synchronous Serial Port Interrupt ............................. 23
Interrupts, Context Saving During .................................... 145
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ....................................... 56
Global Interrupt Enable (GIE Bit) ....................... 21, 143
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 21, 145
Peripheral Interrupt Enable (PEIE Bit) ....................... 21
RB0/INT Enable (INTE Bit) ........................................ 21
TMR0 Overflow Enable (T0IE Bit) ............................. 21
 1998 Microchip Technology Inc.
PIC16F87X
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit) ...................................... 56, 57
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) ..................................................... 21, 31, 145
RB0/INT Flag (INTF Bit) ............................................. 21
TMR0 Overflow Flag (T0IF Bit) .......................... 21, 145
K
KeeLoq Evaluation and Programming Tools ................. 155
M
Master Clear (MCLR) ....................................................... 7, 8
MCLR Reset, Normal Operation .............. 136, 139, 140
MCLR Reset, SLEEP ............................... 136, 139, 140
Memory Organization
Data Memory ............................................................. 12
Program Memory ....................................................... 11
MPLAB Integrated Development Environment Software . 154
Multi-Master Communication ............................................. 98
Multi-Master Mode ............................................................. 80
O
OPCODE Field Descriptions ............................................ 151
OPTION ............................................................................. 18
OPTION_REG Register ..................................................... 20
INTEDG Bit ................................................................ 20
PS2:PS0 Bits ....................................................... 20, 47
PSA Bit ................................................................. 20, 47
RBPU Bit .................................................................... 20
T0CS Bit ............................................................... 20, 47
T0SE Bit ............................................................... 20, 47
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin ......................................................... 7, 8
Oscillator Configuration ............................................ 133, 134
HS .................................................................... 134, 139
LP ..................................................................... 134, 139
RC ............................................................ 134, 135, 139
XT .................................................................... 134, 139
Oscillator, Timer1 ......................................................... 49, 51
Oscillator, WDT ................................................................ 146
P
P ......................................................................................... 62
Packaging ........................................................................ 179
Paging, Program Memory ............................................ 11, 27
Parallel Slave Port (PSP) ......................................... 9, 35, 38
Block Diagram ............................................................ 38
RE0/RD/AN5 Pin .............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................. 9, 37, 38
RE2/CS/AN7 Pin .............................................. 9, 37, 38
Read Waveforms ....................................................... 39
Select (PSPMODE Bit) .................................. 35, 36, 38
Write Waveforms ....................................................... 38
PCL Register .......................................................... 16, 17, 18
PCLATH Register .................................................. 16, 17, 18
PCON Register .................................................... 18, 26, 139
BOR Bit ...................................................................... 26
POR Bit ...................................................................... 26
PICDEM-1 Low-Cost PICmicro Demo Board ................... 154
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 154
PICDEM-3 Low-Cost PIC16CXXX Demo Board .............. 154
PICSTART Plus Entry Level Development System ...... 153
PIE1 Register ............................................................... 18, 22
PIE2 Register ............................................................... 18, 24
 1998 Microchip Technology Inc.
Pinout Descriptions
PIC16C63A/PIC16C73B ...............................................7
PIC16C65B/PIC16C74B ...............................................8
PIR1 Register .................................................................... 23
PIR2 Register .................................................................... 25
Pointer, FSR ...................................................................... 27
PORTA ...................................................................... 7, 8, 18
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 29
PORTA Register ........................................................ 29
RA3:RA0 and RA5 Port Pins ..................................... 29
RA4/T0CKI Pin .................................................. 7, 8, 29
RA5/SS/AN4 Pin ...................................................... 7, 8
TRISA Register .......................................................... 29
PORTA Register ................................................................ 16
PORTB ...................................................................... 7, 8, 18
Initialization ................................................................ 31
PORTB Register ........................................................ 31
Pull-up Enable (RBPU Bit) ......................................... 20
RB0/INT Edge Select (INTEDG Bit) .......................... 20
RB0/INT Pin, External ..................................... 7, 8, 145
RB3:RB0 Port Pins .................................................... 31
RB7:RB4 Interrupt on Change ................................. 145
RB7:RB4 Interrupt on Change Enable
(RBIE Bit) ........................................................... 21, 145
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) ..................................................... 21, 31, 145
RB7:RB4 Port Pins .................................................... 31
TRISB Register .......................................................... 31
PORTB Register ................................................................ 16
PORTC ...................................................................... 7, 9, 18
Block Diagram ........................................................... 33
Initialization ................................................................ 33
PORTC Register ........................................................ 33
RC0/T1OSO/T1CKI Pin ........................................... 7, 9
RC1/T1OSI/CCP2 Pin ............................................. 7, 9
RC2/CCP1 Pin ......................................................... 7, 9
RC3/SCK/SCL Pin ................................................... 7, 9
RC4/SDI/SDA Pin .................................................... 7, 9
RC5/SDO Pin .......................................................... 7, 9
RC6/TX/CK Pin ................................................ 7, 9, 106
RC7/RX/DT Pin ....................................... 7, 9, 106, 107
TRISC Register ................................................. 33, 105
PORTC Register ................................................................ 16
PORTD .................................................................... 9, 18, 38
Block Diagram ........................................................... 35
Parallel Slave Port (PSP) Function ............................ 35
PORTD Register ........................................................ 35
TRISD Register ......................................................... 35
PORTD Register ................................................................ 16
PORTE .......................................................................... 9, 18
Analog Port Pins .............................................. 9, 37, 38
Block Diagram ........................................................... 36
Input Buffer Full Status (IBF Bit) ................................ 36
Input Buffer Overflow (IBOV Bit) ................................ 36
Output Buffer Full Status (OBF Bit) ........................... 36
PORTE Register ........................................................ 36
PSP Mode Select (PSPMODE Bit) ................ 35, 36, 38
RE0/RD/AN5 Pin ............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................ 9, 37, 38
RE2/CS/AN7 Pin ............................................. 9, 37, 38
TRISE Register .......................................................... 36
PORTE Register ................................................................ 16
DS30292A-page 191
PIC16F87X
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................ 53
Postscaler, WDT ................................................................ 47
Assignment (PSA Bit) .......................................... 20, 47
Block Diagram ............................................................ 48
Rate Select (PS2:PS0 Bits) ................................. 20, 47
Switching Between Timer0 and WDT ........................ 48
Power-on Reset (POR) .................... 133, 136, 138, 139, 140
Oscillator Start-up Timer (OST) ....................... 133, 138
POR Status (POR Bit) ................................................ 26
Power Control (PCON) Register .............................. 139
Power-down (PD Bit) ......................................... 19, 136
Power-on Reset Circuit, External ............................. 138
Power-up Timer (PWRT) ................................. 133, 138
Time-out (TO Bit) ............................................... 19, 136
Time-out Sequence .................................................. 139
Time-out Sequence on Power-up .................... 141, 142
PR2 .................................................................................... 18
PR2 Register ...................................................................... 17
Prescaler, Capture ............................................................. 56
Prescaler, Timer0 ............................................................... 47
Assignment (PSA Bit) .......................................... 20, 47
Block Diagram ............................................................ 48
Rate Select (PS2:PS0 Bits) ................................. 20, 47
Switching Between Timer0 and WDT ........................ 48
Prescaler, Timer1 ............................................................... 50
Select (T1CKPS1:T1CKPS0 Bits) .............................. 49
Prescaler, Timer2 ............................................................... 58
Select (T2CKPS1:T2CKPS0 Bits) .............................. 53
PRO MATE II Universal Programmer ............................ 153
Product Identification System ........................................... 199
Program Counter
PCL Register .............................................................. 27
PCLATH Register .............................................. 27, 145
Reset Conditions ...................................................... 139
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging .................................................................. 11, 27
Program Memory Map ............................................... 11
Reset Vector .............................................................. 11
Program Verification ......................................................... 148
Programming Pin (Vpp) .................................................... 7, 8
Programming, Device Instructions ................................... 151
PWM (CCP Module) ........................................................... 58
Block Diagram ............................................................ 58
CCPR1H:CCPR1L Registers ..................................... 58
Duty Cycle .................................................................. 58
Example Frequencies/Resolutions ............................ 59
Output Diagram .......................................................... 58
Period ......................................................................... 58
Set-Up for PWM Operation ........................................ 59
TMR2 to PR2 Match ............................................ 53, 58
Q
Q-Clock .............................................................................. 58
R
R/W .................................................................................... 62
R/W bit ............................................................................... 72
R/W bit ............................................................................... 73
RCE,Receive Enable bit, RCE ........................................... 64
RCREG .............................................................................. 18
DS30292A-page 192
RCSTA Register ........................................................ 18, 106
CREN Bit ................................................................. 106
FERR Bit .................................................................. 106
OERR Bit ................................................................. 106
RX9 Bit .................................................................... 106
RX9D Bit .................................................................. 106
SPEN Bit .......................................................... 105, 106
SREN Bit ................................................................. 106
Read/Write bit, R/W ........................................................... 62
Receive Overflow Indicator bit, SSPOV ............................. 63
Register File ....................................................................... 12
Register File Map ............................................................... 13
Registers
FSR
Summary ........................................................... 18
INDF
Summary ........................................................... 18
INTCON
Summary ........................................................... 18
OPTION
Summary ........................................................... 18
PCL
Summary ........................................................... 18
PCLATH
Summary ........................................................... 18
PORTB
Summary ........................................................... 18
SSPSTAT .................................................................. 62
STATUS
Summary ........................................................... 18
Summary ................................................................... 16
TMR0
Summary ........................................................... 18
TRISB
Summary ........................................................... 18
Reset ....................................................................... 133, 136
Block Diagram ......................................................... 137
Reset Conditions for All Registers ........................... 140
Reset Conditions for PCON Register ...................... 139
Reset Conditions for Program Counter ................... 139
Reset Conditions for STATUS Register .................. 139
WDT Reset. See Watchdog Timer (WDT)
Restart Condition Enabled bit, RSE ................................... 64
Revision History ............................................................... 187
RSE ................................................................................... 64
S
S ........................................................................................ 62
SAE .................................................................................... 64
SCK ................................................................................... 65
SCL .................................................................................... 72
SDA ................................................................................... 72
SDI ..................................................................................... 65
SDO ................................................................................... 65
SEEVAL Evaluation and Programming System ............ 155
Serial Clock, SCK .............................................................. 65
Serial Clock, SCL ............................................................... 72
Serial Data Address, SDA ................................................. 72
Serial Data In, SDI ............................................................. 65
Serial Data Out, SDO ........................................................ 65
Slave Select Synchronization ............................................ 68
Slave Select, SS ................................................................ 65
SLEEP ............................................................. 133, 136, 147
SMP ................................................................................... 62
Software Simulator (MPLAB-SIM) ................................... 155
SPBRG .............................................................................. 18
 1998 Microchip Technology Inc.
PIC16F87X
SPBRG Register ................................................................ 17
SPE .................................................................................... 64
Special Features of the CPU ........................................... 133
Special Function Registers ................................................ 15
PIC16C73 .................................................................. 16
PIC16C73A ................................................................ 16
PIC16C74 .................................................................. 16
PIC16C74A ................................................................ 16
PIC16C76 .................................................................. 16
PIC16C77 .................................................................. 16
Speed, Operating ................................................................. 1
SPI
Master Mode .............................................................. 67
Serial Clock ................................................................ 65
Serial Data In ............................................................. 65
Serial Data Out .......................................................... 65
Serial Peripheral Interface (SPI) ................................ 61
Slave Select ............................................................... 65
SPI clock .................................................................... 67
SPI Mode ................................................................... 65
SPI Clock Edge Select, CKE ............................................. 62
SPI Data Input Sample Phase Select, SMP ...................... 62
SPI Master/Slave Connection ............................................ 66
SPI Module
Master/Slave Connection ........................................... 66
Slave Mode ................................................................ 68
Slave Select Synchronization .................................... 68
Slave Synch Timnig ................................................... 68
SS ...................................................................................... 65
SSP .................................................................................... 61
Block Diagram (SPI Mode) ........................................ 65
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 9
RC4/SDI/SDA Pin .................................................... 7, 9
RC5/SDO Pin ........................................................... 7, 9
SPI Mode ................................................................... 65
SSPADD .................................................................... 72
SSPBUF ............................................................... 67, 72
SSPCON1 .................................................................. 63
SSPCON2 .................................................................. 64
SSPSR ................................................................. 67, 72
SSPSTAT ............................................................. 62, 72
TMR2 Output for Clock Shift ................................ 53, 54
SSP I2C
SSP I2C Operation ..................................................... 71
SSP Module
SPI Master Mode ....................................................... 67
SPI Master./Slave Connection ................................... 66
SPI Slave Mode ......................................................... 68
SSPCON1 Register ................................................... 71
SSP Overflow Detect bit, SSPOV ...................................... 72
SSPADD Register ........................................................ 17, 18
SSPBUF ....................................................................... 18, 72
SSPBUF Register .............................................................. 16
SSPCON Register ............................................................. 16
SSPCON1 .................................................................... 63, 71
SSPCON2 .......................................................................... 64
SSPEN ............................................................................... 63
SSPIF ........................................................................... 23, 73
SSPM3:SSPM0 .................................................................. 63
SSPOV ................................................................... 63, 72, 90
SSPSTAT ..................................................................... 62, 72
SSPSTAT Register ...................................................... 17, 18
 1998 Microchip Technology Inc.
Stack .................................................................................. 27
Start bit (S) ........................................................................ 62
Start Condition Enabled bit, SAE ....................................... 64
STATUS Register ................................................ 18, 19, 145
C Bit ........................................................................... 19
DC Bit ........................................................................ 19
IRP Bit ....................................................................... 19
PD Bit ................................................................ 19, 136
RP1:RP0 Bits ............................................................. 19
TO Bit ................................................................ 19, 136
Z Bit ........................................................................... 19
Stop bit (P) ......................................................................... 62
Stop Condition Enable bit .................................................. 64
Synchronous Serial Port .................................................... 61
Synchronous Serial Port Enable bit, SSPEN ..................... 63
Synchronous Serial Port Interrupt ..................................... 23
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ................................................................. 63
T
T1CON .............................................................................. 18
T1CON Register .......................................................... 18, 49
T1CKPS1:T1CKPS0 Bits ........................................... 49
T1OSCEN Bit ............................................................ 49
T1SYNC Bit ............................................................... 49
TMR1CS Bit ............................................................... 49
TMR1ON Bit .............................................................. 49
T2CON Register .......................................................... 18, 53
T2CKPS1:T2CKPS0 Bits ........................................... 53
TMR2ON Bit .............................................................. 53
TOUTPS3:TOUTPS0 Bits ......................................... 53
TAD .................................................................................. 127
Timer0 ............................................................................... 47
Block Diagram ........................................................... 47
Clock Source Edge Select (T0SE Bit) ................. 20, 47
Clock Source Select (T0CS Bit) .......................... 20, 47
Overflow Enable (T0IE Bit) ........................................ 21
Overflow Flag (T0IF Bit) .................................... 21, 145
Overflow Interrupt .............................................. 48, 145
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ............................................................................... 49
Block Diagram ........................................................... 50
Capacitor Selection ................................................... 51
Clock Source Select (TMR1CS Bit) ........................... 49
External Clock Input Sync (T1SYNC Bit) ................... 49
Module On/Off (TMR1ON Bit) ................................... 49
Oscillator .............................................................. 49, 51
Oscillator Enable (T1OSCEN Bit) .............................. 49
Overflow Interrupt ................................................ 49, 51
RC0/T1OSO/T1CKI Pin ........................................... 7, 9
RC1/T1OSI/CCP2 Pin ............................................. 7, 9
Special Event Trigger (CCP) ............................... 51, 57
T1CON Register ........................................................ 49
TMR1H Register ........................................................ 49
TMR1L Register ........................................................ 49
Timer2
Block Diagram ........................................................... 54
PR2 Register ....................................................... 53, 58
SSP Clock Shift ................................................... 53, 54
T2CON Register ........................................................ 53
TMR2 Register .......................................................... 53
TMR2 to PR2 Match Interrupt ........................ 53, 54, 58
DS30292A-page 193
PIC16F87X
Timing Diagrams
A/D Conversion ........................................................ 176
Acknowledge Sequence Timing ................................. 93
Baud Rate Generator with Clock Arbitration .............. 81
BRG Reset Due to SDA Collision ............................ 100
Brown-out Reset ...................................................... 166
Bus Collision
Start Condition Timing ....................................... 99
Bus Collision During a Restart Condition (Case 1) .. 101
Bus Collision During a Restart Condition (Case2) ... 101
Bus Collision During a Start Condition (SCL = 0) .... 100
Bus Collision During a Stop Condition ..................... 102
Bus Collision for Transmit and Acknowledge ............. 98
Capture/Compare/PWM ........................................... 168
CLKOUT and I/O ...................................................... 165
I2C Bus Data ............................................................ 173
I2C Bus Start/Stop bits ............................................. 172
I2C Master Mode First Start bit timing ........................ 82
I2C Master Mode Reception timing ............................ 92
I2C Master Mode Transmission timing ....................... 89
Master Mode Transmit Clock Arbitration .................... 97
Power-up Timer ....................................................... 166
Repeat Start Condition ............................................... 84
Reset ........................................................................ 166
Slave Synchronization ............................................... 68
Start-up Timer .......................................................... 166
Stop Condition Receive or Transmit .......................... 95
Time-out Sequence on Power-up .................... 141, 142
Timer0 ...................................................................... 167
Timer1 ...................................................................... 167
USART Asynchronous Master Transmission ........... 111
USART Synchronous Receive ................................. 174
USART Synchronous Reception .............................. 117
USART Synchronous Transmission ................ 116, 174
USART, Asynchronous Reception ........................... 113
Wake-up from SLEEP via Interrupt .......................... 148
Watchdog Timer ....................................................... 166
TMR0 ................................................................................. 18
TMR0 Register ................................................................... 16
TMR1H ............................................................................... 18
TMR1H Register ................................................................ 16
TMR1L ............................................................................... 18
TMR1L Register ................................................................. 16
TMR2 ................................................................................. 18
TMR2 Register ................................................................... 16
TRISA ................................................................................. 18
TRISA Register .................................................................. 17
TRISB ................................................................................. 18
TRISB Register .................................................................. 17
TRISC ................................................................................ 18
TRISC Register .................................................................. 17
TRISD ................................................................................ 18
TRISD Register .................................................................. 17
TRISE ................................................................................. 18
TRISE Register ............................................................ 17, 36
IBF Bit ........................................................................ 36
IBOV Bit ..................................................................... 36
OBF Bit ...................................................................... 36
PSPMODE Bit ................................................ 35, 36, 38
TXREG ............................................................................... 18
TXSTA ................................................................................ 18
DS30292A-page 194
TXSTA Register ............................................................... 105
BRGH Bit ......................................................... 105, 107
CSRC Bit ................................................................. 105
SYNC Bit ................................................................. 105
TRMT Bit ................................................................. 105
TX9 Bit ..................................................................... 105
TX9D Bit .................................................................. 105
TXEN Bit .................................................................. 105
U
UA ...................................................................................... 62
Universal Synchronous Asynchronous Receiver Transmitter
(USART)
Asynchronous Receiver
Setting Up Reception ....................................... 112
Timing Diagram ............................................... 113
Update Address, UA .......................................................... 62
USART ............................................................................. 105
Asynchronous Mode ................................................ 110
Master Transmission ....................................... 111
Receive Block Diagram ................................... 113
Transmit Block Diagram .................................. 110
Baud Rate Generator (BRG) ................................... 107
Baud Rate Error, Calculating ........................... 107
Baud Rate Formula ......................................... 107
Baud Rates, Asynchronous Mode
(BRGH=0) ........................................................ 108
Baud Rates, Asynchronous
Mode (BRGH=1) .............................................. 109
Baud Rates, Synchronous Mode ..................... 108
High Baud Rate Select (BRGH Bit) ......... 105, 107
Sampling .......................................................... 107
Clock Source Select (CSRC Bit) ............................. 105
Continuous Receive Enable (CREN Bit) ................. 106
Framing Error (FERR Bit) ........................................ 106
Mode Select (SYNC Bit) .......................................... 105
Overrun Error (OERR Bit) ........................................ 106
RC6/TX/CK Pin ........................................................ 7, 9
RC7/RX/DT Pin ....................................................... 7, 9
RCSTA Register ...................................................... 106
Receive Data, 9th bit (RX9D Bit) ............................. 106
Receive Enable, 9-bit (RX9 Bit) ............................... 106
Serial Port Enable (SPEN Bit) ......................... 105, 106
Single Receive Enable (SREN Bit) .......................... 106
Synchronous Master Mode ...................................... 115
Reception ........................................................ 117
Transmission ................................................... 116
Synchronous Slave Mode ........................................ 118
Transmit Data, 9th Bit (TX9D) ................................. 105
Transmit Enable (TXEN Bit) .................................... 105
Transmit Enable, Nine-bit (TX9 Bit) ......................... 105
Transmit Shift Register Status (TRMT Bit) .............. 105
TXSTA Register ....................................................... 105
 1998 Microchip Technology Inc.
PIC16F87X
W
W Register ....................................................................... 145
Wake-up from SLEEP .............................................. 133, 147
Interrupts .......................................................... 139, 140
MCLR Reset ............................................................ 140
Timing Diagram ........................................................ 148
WDT Reset .............................................................. 140
Watchdog Timer (WDT) ........................................... 133, 146
Block Diagram .......................................................... 146
Enable (WDTE Bit) ................................................... 146
Programming Considerations .................................. 146
RC Oscillator ............................................................ 146
Time-out Period ....................................................... 146
WDT Reset, Normal Operation ................ 136, 139, 140
WDT Reset, SLEEP ................................. 136, 139, 140
Waveform for General Call Address Sequence ................. 77
WCOL .................................................. 63, 82, 87, 90, 93, 95
WCOL Status Flag ............................................................. 82
Write Collision Detect bit, WCOL ....................................... 63
WWW, On-Line Support ...................................................... 4
 1998 Microchip Technology Inc.
DS30292A-page 195
PIC16F87X
DS30292A-page 196
 1998 Microchip Technology Inc.
PIC16F87X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 1998 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
DS30292A-page 197
PIC16F87X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Telephone: (_______) _________ - _________
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Application (optional):
Would you like a reply?
Device: PIC16F87X
Y
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Literature Number: DS30292A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30292A-page 198
 1998 Microchip Technology Inc.
PIC16F87X
PIC16F87X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
Examples:
g)
h)
Device
PIC16F87X(1), PIC16F87XT(2);VDD range 4.0V to 5.5V
PIC16LF87X(1), PIC16LF87XT(2);VDD range 2.0V to 5.5V
PIC16F87X(1), PIC16F87XT(2);VDD range 4.0V to 5.5V
PIC16LF87X(1), PIC16LF87XT(2);VDD range 2.0V to 5.5V
Frequency Range
04
20
= 4 MHz
= 20 MHz
Temperature Range
b(3)
I
=
0°C to
= -40°C to
Package
PQ
PT
SO
SP
P
L
=
=
=
=
=
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
i)
PIC16F877 -20/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
PIC16F876 - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
PIC16F877 - 04I/P = Industrial temp., PDIP
package, 10MHz, normal VDD limits.
Note 1:
70°C
+85°C
(Commercial)
(Industrial)
2:
C
LC
T
b
= CMOS
= Low Power CMOS
= in tape and reel - SOIC, PLCC,
MQFP, TQFP packages only.
= blank
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
PLCC
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
 1998 Microchip Technology Inc.
Preliminary
DS30292A-page 199
M
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
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Microchip Technology Inc.
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San Jose
Microchip Technology Inc.
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San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1998 Microchip Technology Incorporated. Printed in the USA. 12/98
10/27/98
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro®
8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, related
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Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS30292A-page 200
 1998 Microchip Technology Inc.