MICROCHIP PIC16LF872T-I/SS

PIC16F872
28-Pin, 8-Bit CMOS FLASH Microcontroller
Devices Included in this Data Sheet:
Pin Diagram
• PIC16F872
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16C72A
• Interrupt capability (up to 10 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
 1999 Microchip Technology Inc.
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16F872
DIP, SOIC, SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
Mode) and I2C (Master/Slave)
• Brown-out detection circuitry for Brown-out Reset
(BOR)
Preliminary
DS30221A-page 1
PIC16F872
Key Features
PICmicro™ Mid-Range Reference Manual
(DS33023)
PIC16F872
Operating Frequency
DC - 20 MHz
Resets (and Delays)
POR, BOR
(PWRT, OST)
FLASH Program Memory
(14-bit words)
2K
Data Memory (bytes)
128
EEPROM Data Memory
64
Interrupts
10
I/O Ports
Ports A,B,C
Timers
3
Capture/Compare/PWM module
1
Serial Communications
MSSP
10-bit Analog-to-Digital Module
5 input channels
Instruction Set
DS30221A-page 2
35 Instructions
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
Table of Contents
1.0 Device Overview ........................................................................................................................................................................... 5
2.0 Memory Organization.................................................................................................................................................................... 7
3.0 I/O Ports...................................................................................................................................................................................... 23
4.0 Data EEPROM and FLASH Program Memory .......................................................................................................................... 29
5.0 Timer0 Module ............................................................................................................................................................................ 37
6.0 Timer1 Module ............................................................................................................................................................................ 41
7.0 Timer2 Module ........................................................................................................................................................................... 45
8.0 Capture/Compare/PWM (CCP) Module(s).................................................................................................................................. 47
9.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................... 53
10.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 85
11.0 Special Features of the CPU ...................................................................................................................................................... 95
12.0 Instruction Set Summary........................................................................................................................................................... 111
13.0 Development Support ............................................................................................................................................................... 119
14.0 Electrical Characteristics........................................................................................................................................................... 125
15.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 143
16.0 Packaging Information .............................................................................................................................................................. 145
Appendix A: Revision History......................................................................................................................................................... 149
Appendix B: Conversion Considerations........................................................................................................................................ 149
Index
................................................................................................................................................................................... 151
On-Line Support................................................................................................................................................................................. 157
Product Identification System ............................................................................................................................................................ 159
To Our Valued Customers
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
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 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 3
PIC16F872
NOTES:
DS30221A-page 4
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
1.0
DEVICE OVERVIEW
mentary document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
FIGURE 1-1:
This data sheet covers the PIC16F872 device. The
PIC16F872 is a 28-pin device and its block diagram is
shown in Figure 1-1.
PIC16F872 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F872
2K
128 Bytes
64 Bytes
13
FLASH
Program
Memory
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
14
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
MUX
ALU
Power-on
Reset
PORTC
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
W reg
Low-Voltage
Programming
MCLR
VDD, VSS
Timer0
Timer1
Timer2
Data EEPROM
CCP1
Synchronous
Serial Port
10-bit A/D
Note 1: Higher order bits are from the STATUS register.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 5
PIC16F872
TABLE 1-1:
PIC16F872 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
OSC1/CLKIN
9
9
I
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT,
which has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
MCLR/VPP/THV
1
1
I/P
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
RA0/AN0
2
2
I/O
TTL
RA1/AN1
3
3
I/O
TTL
RA1 can also be analog input1.
RA2/AN2/VREF-
4
4
I/O
TTL
RA2 can also be analog input2 or negative analog reference
voltage.
RA3/AN3/VREF+
5
5
I/O
TTL
RA3 can also be analog input3 or positive analog reference
voltage.
RA4/T0CKI
6
6
I/O
ST
RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
RA5/SS/AN4
7
7
I/O
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
Pin Name
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
RB0/INT
21
21
I/O
TTL/ST(1)
RB1
22
22
I/O
TTL
RB2
23
23
I/O
TTL
RB3/PGM
24
24
I/O
TTL/ST(1)
RB4
25
25
I/O
TTL
Interrupt on change pin.
RB5
26
26
I/O
TTL
Interrupt on change pin.
RB6/PGC
27
27
I/O
TTL/ST(2)
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD
28
28
I/O
TTL/ST(2)
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
RC0/T1OSO/T1CKI
11
11
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1/T1OSI
12
12
I/O
ST
RC1 can also be the Timer1 oscillator input.
RC2/CCP1
13
13
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL
14
14
I/O
ST
RC3 can also be the synchronous serial clock input/output for
both SPI and I2C modes.
RC4/SDI/SDA
15
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6
17
17
I/O
ST
ST
RB3 can also be the low voltage programming input.
PORTC is a bi-directional I/O port.
RC7
18
18
I/O
VSS
8, 19
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
20
P
—
Positive supply for logic and I/O pins.
Legend:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30221A-page 6
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.0
MEMORY ORGANIZATION
2.2
There are three memory blocks in each of these
PICmicro ® MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur, and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP<1:0>
Bank
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
00
0
01
1
10
2
2.1
11
3
Program Memory Organization
The PIC16F872 devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The PIC16F872 device has 2K x 14 words of
FLASH program memory. Accessing a location above
the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PIC16F872 PROGRAM
MEMORY MAP AND STACK
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
Note:
2.2.1
EEPROM Data Memory description can be
found in Section 4.0 of this Data Sheet
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
On-Chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
1FFFh
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 7
PIC16F872
FIGURE 2-2:
PIC16F872 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
Indirect addr.(*)
80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
88h
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
SSPCON2
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
General
Purpose
Register
A0h
32 Bytes
BFh
C0h
96 Bytes
7Fh
Bank 0
accesses
70h-7Fh
Bank 1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
120h
accesses
A0h - BFh
accesses
20h-7Fh
EFh
F0h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
1BFh
1C0h
accesses
70h-7Fh
FFh
Bank 2
16Fh
170h
17Fh
accesses
70h-7Fh
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
DS30221A-page 8
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
(3)
03h
STATUS
04h(3)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
(1,3)
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
PCLATH
—
—
—
0Bh(3)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
(4)
ADIF
(4)
(4)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000 r0rr 0000
—
(4)
—
EEIF
BCLIF
—
—
(4)
-r-0 0--r -r-0 0--r
0Ah
Write Buffer for the upper 5 bits of the Program Counter
0Dh
PIR2
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
—
—
T1SYNC
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 module’s register
—
---0 0000 ---0 0000
--00 0000 --uu uuuu
0000 0000 0000 0000
13h
SSPBUF
14h
SSPCON
Synchronous Serial Port Receive Buffer/Transmit Register
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
A/D Result Register High Byte
1Fh
ADCON0
WCOL
SSPOV
—
ADCS1
—
ADCS0
SSPEN
CCP1X
CHS2
CKP
CCP1Y
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 9
PIC16F872
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 1
80h(3)
INDF
81h
OPTION_REG
82h(3)
PCL
83h(3)
STATUS
84h(3)
FSR
85h
TRISA
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PS2
PS1
PS0
1111 1111 1111 1111
PD
Z
DC
C
0001 1xxx 000q quuu
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
0000 0000 0000 0000
TO
Indirect data memory address pointer
—
—
0000 0000 0000 0000
PSA
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
(1,3)
PCLATH
—
8Bh(3)
INTCON
8Ch
PIE1
8Dh
PIE2
8Eh
PCON
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
SSPCON2
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
94h
SSPSTAT
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
ADRESL
A/D Result Register Low Byte
9Fh
ADCON1
8Ah
—
—
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
(4)
ADIE
(4)
(4)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000 r0rr 0000
—
(4)
—
EEIE
BCLIE
—
—
(4)
-r-0 0--r -r-0 0--r
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
GCEN
SMP
ADFM
ACKSTAT
CKE
—
ACKDT
Write Buffer for the upper 5 bits of the Program Counter
ACKEN
RCEN
PEN
RSEN
SEN
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
D/A
—
P
0000 0000 0000 0000
S
R/W
UA
BF
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
—
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000
0--- 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
DS30221A-page 10
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
0000 0000
0000 0000
Bank 2
100h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
101h
TMR0
Timer0 module’s register
102h(3)
PCL
Program Counter's (PC) Least Significant Byte
103h(3)
STATUS
(3)
IRP
xxxx xxxx uuuu uuuu
RP1
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
0001 1xxx 000q quuu
104h
FSR
Indirect data memory address pointer
105h
—
Unimplemented
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
Unimplemented
—
—
10Ah
(1,3)
PCLATH
xxxx xxxx uuuu uuuu
—
—
—
—
GIE
PEIE
T0IE
10Bh(3)
INTCON
10Ch
EEDATA
EEPROM data register
10Dh
EEADR
EEPROM address register
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
—
xxxx xxxx uuuu uuuu
T0IF
INTF
RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM data register high byte
—
xxxx xxxx uuuu uuuu
EEPROM address register high byte
xxxx xxxx uuuu uuuu
Bank 3
180h(3)
INDF
181h
OPTION_REG
182h(3)
PCL
183h(3)
STATUS
(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
184h
FSR
Indirect data memory address pointer
185h
—
Unimplemented
186h
TRISB
PORTB Data Direction Register
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah
(1,3)
PCLATH
xxxx xxxx uuuu uuuu
—
—
—
—
—
1111 1111 1111 1111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
18Bh(3)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
18Ch
EECON1
EEPGD
—
—
—
WRERR
WREN
WR
RD
x--- x000 x--- u000
18Dh
EECON2
EEPROM control register2 (not a physical register)
---- ---- ---- ----
18Eh
—
Reserved maintain clear
0000 0000 0000 0000
18Fh
—
Reserved maintain clear
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 11
PIC16F872
2.2.2.1
STATUS REGISTER
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
DS30221A-page 12
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.2.2.2
OPTION_REG REGISTER
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-0: PS<2:0>: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
Note:
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 13
PIC16F872
2.2.2.3
INTCON REGISTER
Note:
The INTCON Register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
DS30221A-page 14
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.2.2.4
PIE1 REGISTER
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
R/W-0
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE TMR1IE
bit7
bit0
bit 7:
Reserved: Always maintain this bit clear
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 5-4: Reserved: Always maintain this bit clear
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 15
PIC16F872
2.2.2.5
PIR1 REGISTER
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an
interrupt.
R/W-0
R/W-0
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF TMR1IF
bit7
bit0
bit 7:
Reserved: Always maintain this bit clear
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 5-4: Reserved: Always maintain this bit clear
bit 3:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave
A transmission/reception has taken place.
I2C Master
A transmission/reception has taken place.
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = No SSP interrupt condition has occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS30221A-page 16
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.2.2.6
PIE2 REGISTER
The PIE2 register contains the individual enable bits for
the SSP bus collision interrupt and the EEPROM write
operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
—
EEIE
BCLIE
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
Reserved: Always maintain this bit clear
bit 5:
Unimplemented: Read as '0'
bit 4:
EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3:
BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-1: Unimplemented: Read as '0'
bit 0:
Reserved: Always maintain this bit clear
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 17
PIC16F872
2.2.2.7
PIR2 REGISTER
.
The PIR2 register contains the flag bits for the SSP bus
collision interrupt and the EEPROM write operation
interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
—
EEIF
BCLIF
—
—
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
Reserved: Always maintain this bit clear
bit 5:
Unimplemented: Read as '0'
bit 4:
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3:
BCLIF: Bus Collision Interrupt Flag
1 = A bus collision has occurred in the SSP, when configured for I2C master mode
0 = No bus collision has occurred
bit 2-1: Unimplemented: Read as '0'
bit 0:
Reserved: Always maintain this bit clear
DS30221A-page 18
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
2.2.2.8
PCON REGISTER
Note:
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watch-dog Reset
(WDT) and an external MCLR Reset.
BOR is unknown on POR. It must be set by
the user and checked on subsequent
resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-1
—
—
—
—
—
—
POR
BOR
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 19
PIC16F872
2.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 2-3 shows the two situations
for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
PCL
8
PC
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
2.3.2
2.4
Program Memory Paging
The PIC16CXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL and GOTO instructions provide 11 bits of the
address, which allows branches within any 2K program
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16FC872 has only 2K words of program memory or
one page, additional code is not required to ensure that
the correct page is selected before a CALL or GOTO
instruction is executed. The PCLATH<4:3> bits should
always be maintained as zeros. If a return from a CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.
GOTO,CALL
2
2.3.1
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt
address.
2.5
0
7
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
STACK
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
NEXT
movlw
movwf
clrf
incf
btfss
goto
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30221A-page 20
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
RP1:RP0
6
bank select
location select
0
IRP
7
bank select
00
01
10
FSR register
0
location select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Note 1:
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 2-2.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 21
PIC16F872
NOTES:
DS30221A-page 22
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
3.0
I/O PORTS
FIGURE 3-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™
Mid-Range
Reference
Manual,
(DS33023).
Data
Bus
BLOCK DIAGRAM OF
RA<3:0> AND RA5 PINS
D
Q
VDD
WR
Port
Q
CK
P
Data Latch
3.1
PORTA and the TRISA Register
D
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
TRIS Latch
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note:
Q
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data
Bus
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR
Port
STATUS, RP0
STATUS, RP1
PORTA
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BLOCK DIAGRAM OF RA4/
T0CKI PIN
D
Q
CK
Q
N
I/O pin(1)
Data Latch
INITIALIZING PORTA
BCF
BCF
CLRF
D
EN
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
EXAMPLE 3-1:
TTL
Input
Buffer
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
VSS
Analog
Input
Mode
Q
CK
I/O pin(1)
N
Q
WR
TRIS
Bank0
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as ’0’.
D
Q
CK
Q
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD TRIS
Q
D
ENEN
RD Port
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 23
PIC16F872
TABLE 3-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
Input/output or analog input
RA1/AN1
bit1
TTL
Input/output or analog input
RA2/AN2
bit2
TTL
Input/output or analog input
RA3/AN3/VREF
bit3
TTL
Input/output or analog input or VREF
RA4/T0CKI
bit4
ST
Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input.
TABLE 3-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA5
RA4
RA3
RA2
RA1
RA0
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1 ADFM
—
PORTA Data Direction Register
—
—
Value on: Value on all
POR,
other
BOR
resets
--0x 0000 --0u 0000
--11 1111 --11 1111
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG<3:0> = 0100,0101, 011x, 1101, 1110, 1111.
DS30221A-page 24
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the Low
Voltage Programming function; RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3:
BLOCK DIAGRAM OF
RB<3:0> PINS
Data Bus
WR Port
weak
P pull-up
Data Latch
D
Q
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 3-4:
I/O
pin(1)
CK
VDD
TTL
Input
Buffer
CK
weak
P pull-up
Data Latch
D
Q
Data Bus
WR Port
TRIS Latch
Q
D
D
WR TRIS
RD Port
TTL
Input
Buffer
RD TRIS
Schmitt Trigger
Buffer
RD Port
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB<7:4>) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
Note:
Q
CK
EN
RB0/INT
RB3/PGM
1:
2:
I/O
pin(1)
CK
RD TRIS
Note
BLOCK DIAGRAM OF
RB<7:4> PINS
RBPU(2)
TRIS Latch
D
Q
WR TRIS
a)
RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
Q
Latch
D
EN
RD Port
ST
Buffer
Q1
Set RBIF
From other
RB<7:4> pins
Q
D
RD Port
EN
Q3
RB<7:6> in serial programming mode
Note
1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 25
PIC16F872
TABLE 3-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
(1)
RB0/INT
bit0
TTL/ST
RB1
bit1
TTL
RB2
bit2
TTL
Function
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
(1)
RB3/PGM
bit3
TTL/ST
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6/PGC
bit6
TTL/ST(2)
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD
bit7
TTL/ST(2)
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h
PORTB
86h, 186h
TRISB
81h, 181h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTB Data Direction Register
RBPU
INTEDG
T0CS
T0SE
Value on:
POR,
BOR
Value on all
other
resets
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30221A-page 26
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
3.3
FIGURE 3-6:
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC (3:4) pins
can be configured with normal I2C levels or with
SMBUS levels by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<3:4>
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
WR
Port
D
VDD
0
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
Vss
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
RD
Port
D
EN
0
Schmitt
Trigger
with
SMBus
levels
SSPl Input
1
CKE
SSPSTAT<6>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<0:2>
RC<5:7>
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
WR
Port
VDD
0
D
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
RD
Port
Peripheral Input
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 27
PIC16F872
TABLE 3-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI
bit1
ST
Input/output port pin or Timer1 oscillator input.
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port data output.
RC6
bit6
ST
Input/output port pin.
RC7
bit7
ST
Input/output port pin.
Legend: ST = Schmitt Trigger input.
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
87h
TRISC
1111 1111
1111 1111
Address
PORTC Data Direction Register
Value on all
other resets
Legend: x = unknown, u = unchanged.
DS30221A-page 28
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. A bulk erase operation may not be
issued from user code (which includes removing code
protection). The data memory is not directly mapped in
the register file space.
Instead, it is indirectly
addressed through the Special Function Registers
(SFR).
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
•
•
•
•
•
•
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
4.1
EEADR
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH. However, the PIC16F872
has 64 bytes of data EEPROM and 2K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. The PIC16F872 device has 64 bytes
of data EEPROM with an address range from 0h to
3Fh.
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
The program memory allows word reads and writes.
Program memory access allows for checksum calculation and calibration table storage. A byte or word write
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease operation until the write is complete. The program memory cannot be accessed during the write,
therefore code cannot execute. During the write operation, the oscillator continues to clock the peripherals,
and therefore, they continue to operate. Interrupt
events will be detected and essentially “queued” until
the write is completed. When the write completes, the
next instruction in the pipeline is executed and the
branch to the interrupt vector address will occur.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two byte word,
which holds the 13-bit address of the FLASH location
being accessed. The PIC16F872 device has 2K words
of program FLASH with an address range from 0h to
7FFh. The unused upper bits in both the EEDATH and
EEDATA registers all read as “0’s”.
 1999 Microchip Technology Inc.
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that
forms an invalid instruction results in a NOP.
On the PIC16F872 device, the upper two bits of the
EEADR must always be cleared to prevent inadvertent
access to the wrong location in data EEPROM. This
also applies to the program memory. The upper five
MSbits of EEADRH must always be clear during program FLASH access.
4.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data memory. When set, any subsequent operations will operate
on the program memory.
Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
Interrupt flag bit EEIF, in the PIR2 register, is set when
write is complete. It must be cleared in software.
Preliminary
DS30221A-page 29
PIC16F872
REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
—
WRERR
WREN
WR
RD
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
EEPGD: Program / Data EEPROM Select bit
1 = Accesses Program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6-4: Unimplemented: Read as '0'
bit 3:
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2:
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1:
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete.) The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0:
RD: Read Control bit
1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0 = Does not initiate an EEPROM read
DS30221A-page 30
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
4.3
Reading the Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is written to by the user (during a write operation).
4.4
EXAMPLE 4-1:
DATA EEPROM READ
BSF
STATUS, RP1
;
BCF
STATUS, RP0
;Bank 2
MOVLW DATA_EE_ADDR ;
MOVWF EEADR
;Data Memory Address to read
BSF
STATUS, RP0
;Bank 3
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, RD
;EEPROM Read
BCF
STATUS, RP0
;Bank 2
MOVF
EEDATA, W
;W = EEDATA
Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data written to the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
EXAMPLE 4-2:
DATA EEPROM WRITE
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Data Memory Address to write
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BSF
STATUS, RP0
; Bank 3
BCF
EECON1, EEPGD ; Point to DATA memory
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
BSF
INTCON, GIE
; Enable Interrupts
SLEEP
BCF
; Wait for interrupt to signal write complete
EECON1, WREN
; Disable writes
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 31
PIC16F872
4.5
Reading the FLASH Program Memory
A program memory location may be read by writing two
bytes of the address to the EEADR and EEADRH registers, setting the EEPGD control bit (EECON1<7>)
and then setting control bit RD (EECON1<0>). Once
the read control bit is set, the microcontroller will use
the next two instruction cycles to read the data. The
EXAMPLE 4-3:
Required
data is available in the EEDATA and EEDATH registers
after the second NOP instruction. Therefore, it can be
read as two bytes in the following instructions. The
EEDATA and EEDATH registers will hold this value
until another read operation or until it is written to by the
user (during a write operation).
FLASH PROGRAM READ
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
ADDRH
;
MOVWF
EEADRH
; MSByte of Program Address to read
MOVLW
ADDRL
;
MOVWF
EEADR
; LSByte of Program Address to read
BSF
STATUS, RP0
; Bank 3
BSF
EECON1, EEPGD
; Point to PROGRAM memory
BSF
EECON1, RD
; EEPROM Read
Sequence
NOP
; memory is read in the next two cycles after BSF EECON1,RD
NOP
DS30221A-page 32
;
BCF
STATUS, RP0
; Bank 2
MOVF
EEDATA, W
; W = LSByte of Program EEDATA
MOVF
EEDATH, W
; W = MSByte of Program EEDATA
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
4.6
and then set control bit WR (EECON1<1>). The
sequence in Example 4-4 must be followed to initiate a
write to program memory.
Writing to the FLASH Program
Memory
When the PIC16F872 is fully code protected or not
code protected, a word of the FLASH program memory
may be written provided the WRT configuration bit is
set. If the PIC16F872 is partially code protected, then a
word of FLASH program memory may be written if the
word is in a non-code protected segment of memory
and the WRT configuration bit is set. To write a FLASH
program location, the first two bytes of the address
must be written to the EEADR and EEADRH registers
and two bytes of the data to the EEDATA and EEDATH
registers, set the EEPGD control bit (EECON1<7>),
EXAMPLE 4-4:
The microcontroller will then halt internal operations
during the next two instruction cycles for the TPEW
(parameter D133) in which the write takes place. This
is not SLEEP mode, as the clocks and peripherals will
continue to run. Therefore, the two instructions following the “BSF EECON, WR” should be NOP instructions.
After the write cycle, the microcontroller will resume
operation with the 3rd instruction after the EECON1
write instruction.
FLASH PROGRAM WRITE
BSF
STATUS, RP1
;
BCF
STATUS, RP0
; Bank 2
MOVLW
ADDRH
;
MOVWF
EEADRH
; MSByte of Program Address to read
MOVLW
ADDRL
;
MOVWF
EEADR
; LSByte of Program Address to read
MOVLW
DATAH
;
MOVWF
EEDATH
; MS Program Memory Value to write
MOVLW
DATAL
;
MOVWF
EEDATA
; LS Program Memory Value to write
BSF
STATUS, RP0
; Bank 3
BSF
EECON1, EEPGD
; Point to PROGRAM memory
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
NOP
; Instructions here are ignored by the microcontroller
NOP
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
BSF
INTCON,
BCF
EECON1, WREN
 1999 Microchip Technology Inc.
GIE
; Enable Interrupts
; Disable writes
Preliminary
DS30221A-page 33
PIC16F872
4.7
Write Verify
4.9
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
Generally a write failure will be a bit which was written
as a ’1’, but reads back as a ’0’ (due to leakage off the
bit).
4.8
Protection Against Spurious Write
4.8.1
EEPROM DATA MEMORY
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write operations are disabled if either of these mechanisms are
enabled.
4.9.1
DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
4.9.2
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
4.8.2
Operation during Code Protect
PROGRAM FLASH MEMORY
PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits. However, the WRT configuration bit and the code protect
bits have different effects on writing to program memory. Table 4-1 shows the various configurations and
status of reads and writes. To erase the WRT or code
protection bits in the configuration word requires that
the device be fully erased.
Note:
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequence must also be followed. WRT and the configuration word cannot be programmed by user code, only
through the use of an external programmer.
TABLE 4-1:
The PIC16F872 devices can perform self
writes to any location in program memory
when not code protected or fully code
protected.
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Memory Location
CP1
CP0
WRT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
1
DS30221A-page 34
Internal
Read
Internal
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
Yes
All program memory
All program memory
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
All program memory
All program memory
Preliminary
ICSP Read ICSP Write
No
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
 1999 Microchip Technology Inc.
PIC16F872
TABLE 4-2:
Address
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Name
0Bh, 8Bh,
INTCON
10Bh, 18Bh
10Dh
EEADR
10Fh
EEADRH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
xxxx xxxx
uuuu uuuu
—
—
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
EEPROM address register
—
—
—
10Ch
EEDATA
10Eh
EEDATH
—
—
18Ch
EECON1
EEPGD
—
18Dh
EECON2
8Dh
PIE2
—
(1)
—
EEIE
0Dh
PIR2
—
(1)
—
EEIF
EEPROM address high
EEPROM data resister
EEPROM data resister high
—
—
WREN
WR
RD
x--- x000
x--- u000
BCLIE
—
—
(1)
-r-0 0--r
-r-0 0--r
BCLIF
—
—
(1)
-r-0 0--r
-r-0 0--r
WRERR
EEPROM control resister2 (not a physical resister)
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by the
Timer1 module.
Note 1: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 35
PIC16F872
NOTES:
DS30221A-page 36
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
5.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The prescaler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Additional information on the Timer0 module is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
0
RA4/T0CKI
Pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
M
U
X
1
8-bit Prescaler
8
8 - to - 1MUX
PS<2:0>
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 37
PIC16F872
5.2
Using Timer0 with an External Clock
module means that there is no prescaler for the watchdog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 5-1).
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3
The PSA and PS<2:0> bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x...., etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
Prescaler
Note:
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
REGISTER 5-1: OPTION_REG REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7:
RBPU
bit 6:
INTEDG
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS<2:0>: Prescaler Rate Select bits
Note:
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30221A-page 38
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 5-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
01h,101h
TMR0
0Bh,8Bh,
10Bh,18Bh
INTCON
81h,181h
OPTION_REG RBPU INTEDG
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 39
PIC16F872
NOTES:
DS30221A-page 40
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
6.0
TIMER1 MODULE
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 8.0).
Register 6-1 shows the Timer1 control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
bit7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 41
PIC16F872
6.1
Timer1 Operation in Timer Mode
6.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
FIGURE 6-1:
Timer1 Counter Operation
Timer1 may operate in asynchronous or usynchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in counter mode, the module must first have
a falling edge before the counter begins to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized
Counter Mode
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter.
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
FIGURE 6-2:
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The prescaler however will continue to increment.
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
clock input
TMR1L
1
TMR1ON
on/off
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI
(2)
T1SYNC
(2)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS<1:0>
Q Clock
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F872, the Schmitt Trigger is not implemented in external clock mode.
DS30221A-page 42
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
6.4
Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
± 20 PPM
Note 1: Higher capacitance increases the stability of
oscillator, but also increases the start-up time.
2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
6.6
Resetting Timer1 using CCP1 Trigger
Output
If the CCP1 module is configured in compare mode to
generate a “special event trigger” (CCP1M<3:0> =
1011), this signal will reset Timer1.
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for
Timer1.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 special
event trigger.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 43
PIC16F872
TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
--00 0000
--uu uuuu
—
—
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by the
Timer1 module.
Note 1: These bits are reserved; always maintain these bits clear.
DS30221A-page 44
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
7.0
TIMER2 MODULE
7.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module. The TMR2 register
is readable and writable, and is cleared on any device
RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSPort module, which optionally uses it to generate
shift clock.
FIGURE 7-1:
Sets flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
output (1)
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
TMR2 reg
Register 7-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
EQ
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS<1:0>
4
PR2 reg
T2OUTPS<3:0>
Note 1: TMR2 register output can be software selected
by the SSP module as a baud clock.
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
R/W-0
R/W-0
T2CKPS1 T2CKPS0
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6-3:
TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0:
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 1999 Microchip Technology Inc.
Preliminary
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30221A-page 45
PIC16F872
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
0Bh,8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000 r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
Address
Name
11h
TMR2
12h
T2CON
92h
PR2
r0rr 0000 r0rr 0000
0000 0000 0000 0000
Timer2 module’s register
—
Value on
all other
resets
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by the
Timer2 module.
Note 1: These bits are reserved; always maintain these bits clear.
DS30221A-page 46
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
8.0
CAPTURE/COMPARE/PWM
MODULE
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
The Capture/Compare/PWM (CCP) module contains a
16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM master/slave Duty Cycle register
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note 594, “Using
the CCP Modules” (DS00594).
TABLE 8-1:
Table 8-1 shows the resources used by the CCP module. In the following sections, the operation of a CCP
module is described.
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
REGISTER 8-1: CCP1CON REGISTER (ADDRESS: 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as
‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: CCP1<X:Y>: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0: CCP1M<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP pin is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets
TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 47
PIC16F872
8.1
Capture Mode
8.1.2
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a capture condition.
FIGURE 8-1:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
Prescaler
÷ 1, 4, 16
Set flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
Pin
CCPR1H
and
edge detect
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
8.1.3
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
SOFTWARE INTERRUPT
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
8.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned off,
or the CCP module is not in capture mode, the prescaler counter is cleared. Any reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
CCPR1L
Capture
Enable
TMR1H
TIMER1 MODE SELECTION
TMR1L
CLRF
MOVLW
MOVWF
CCP1CON<3:0>
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new precscaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Q’s
DS30221A-page 48
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
8.2
.
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
8.3
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
COMPARE MODE OPERATION
BLOCK DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q
S
Output
Logic
match
RC2/CCP1
R
Pin
TRISC<2>
Output Enable CCP1CON<3:0>
Mode Select
8.2.1
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
PWM Mode (PWM)
In pulse width modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the CCP
module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
TMR1H
Duty Cycle Registers
TMR1L
CCP PIN CONFIGURATION
CCPR1H (Slave)
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
SOFTWARE INTERRUPT MODE
Q
RC2/CCP1
(Note 1)
S
TIMER1 MODE SELECTION
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.2.4
R
Comparator
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
CCP1CON<5:4>
CCPR1L
TMR2
8.2.2
SIMPLIFIED PWM BLOCK
DIAGRAM
Comparator
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
Note:
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 49
PIC16F872
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
PWM OUTPUT
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
Resolution
Duty Cycle
=
FOSC
log FPWM
(
log(2)
)
bits
TMR2 = PR2
Note:
TMR2 = Duty Cycle
TMR2 = PR2
8.3.3
8.3.1
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
4.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
5.
8.3.2
SET-UP FOR PWM OPERATION
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
DS30221A-page 50
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 8-2:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
--00 0000
--uu uuuu
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
--00 0000
--00 0000
—
—
—
—
T1CKPS1
CCP1X
T1CKPS0
CCP1Y
T1OSCEN
CCP1M3
T1SYNC
CCP1M2
TMR1CS
CCP1M1
TMR1ON
CCP1M0
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by Capture and
Timer1.
Note 1: These bits are reserved; always maintain these bits clear.
TABLE 8-3:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
92h
PR2
Timer2 module’s period register
1111 1111
1111 1111
12h
T2CON
-000 0000
-000 0000
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
--00 0000
--00 0000
—
TOUTPS3
—
—
TOUTPS2
CCP1X
TOUTPS1
CCP1Y
TOUTPS0
CCP1M3
TMR2ON
CCP1M2
T2CKPS1
CCP1M1
T2CKPS0
CCP1M0
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by PWM and
Timer2.
Note 1: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 51
PIC16F872
NOTES:
DS30221A-page 52
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP) MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I 2C)
Figure 9-1 shows a block diagram for the SPI mode,
while Figure 9-5 and Figure 9-9 show the block diagrams for the two different I2C modes of operation.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 53
PIC16F872
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 9-4, Figure 9-5 and Figure 9-6)
SPI Mode:
CKP = 0
1 = Transmit happens on transition from active clock state to idle clock state
0 = Transmit happens on transition from idle clock state to active clock state
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
In I2C Master or Slave Mode:
1 = Input levels conform to SMBUS spec
0 = Input levels conform to I2C specs
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a stop bit has been detected last (this bit is ’0’ on RESET)
0 = Stop bit was not detected last
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a start bit has been detected last (this bit is ’0’ on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next start bit, stop bit or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
DS30221A-page 54
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to SSPBUF was attempted while the I2C conditions were not valid
0 = No collision
Slave Mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In
slave mode, the user must read the SSPBUF, even if only transmitting data to avoid overflows. In master
mode, the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must
be cleared in software.)
0 = No overflow
In I2 C mode
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in transmit
mode. (Must be cleared in software.)
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode, when enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode, when enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C slave mode, SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2 C master mode
Unused in this mode
bit 3-0: SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled.
1111 = I2C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled.
1001, 1010, 1100, 1101 = reserved
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 55
PIC16F872
REGISTER 9-3:
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6:
ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave.
0 = Acknowledge was received from slave.
bit 5:
ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge.
0 = Acknowledge.
bit 4:
ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle.
bit 3:
RCEN: Receive Enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C.
0 = Receive idle.
bit 2:
PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle.
bit 1:
RSEN: Repeated Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0:
SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not
be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS30221A-page 56
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.1
SPI Mode
FIGURE 9-1:
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communication, typically three pins are used:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Write
SSPBUF reg
Additionally, a fourth pin may be used when in a slave
mode of operation:
SSPSR reg
SDI
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
•
•
•
•
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase
(middle or end of data output time)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Shift
Clock
bit0
SDO
SS Control
Enable
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
2
Figure 9-4 shows the block diagram of the MSSP module when in SPI mode.
Edge
Select
SCK
TMR2 output
2
Prescaler
4, 16, 64
TOSC
Data to TX/RX in SSPSR
Data direction bit
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON registers, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 57
PIC16F872
9.1.1
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
Figure 9-6, Figure 9-8 and Figure 9-9 where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 9-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit7
SDO
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
bit7
bit0
SSPIF
DS30221A-page 58
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.1.2
SLAVE MODE
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from sleep.
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
FIGURE 9-3:
Note:
When the SPI module is in Slave mode
with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
Note:
If the SPI is used in Slave mode with
CKE = ’1’, then SS pin control must be
enabled.
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit6
bit7
SDO
bit5
bit2
bit3
bit4
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 59
PIC16F872
TABLE 9-1
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR,
WDT
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Address
Name
0Bh, 8Bh,
10Bh,18Bh
INTCON
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
13h
SSPBUF
xxxx xxxx
uuuu uuuu
14h
SSPCON
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
DS30221A-page 60
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2
MSSP I2 C Operation
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call support) and provides interrupts-on-start and stop bits in
hardware to determine a free bus (multi-master function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 9-5:
I2C SLAVE MODE BLOCK
DIAGRAM
Write
Shift
Clock
SSPSR reg
SDA
MSb
LSb
Match detect
•
•
•
•
•
SSP Control Register (SSPCON)
SSP Control Register2 (SSPCON2)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
Before selecting any I 2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropriate TRIS bits. Selecting an I 2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I 2C mode.
SSPBUF reg
SCL
The MSSP module has six registers for I2C operation.
They are the:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Master mode, clock = OSC/4 (SSPADD +1)
Internal
Data Bus
Read
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically configured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
Addr Match
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBUS
specification. When CKE = 0, the levels will conform to
the I2C specification.
SSPADD reg
Start and
Stop bit detect
 1999 Microchip Technology Inc.
Set, Reset
S, P bits
(SSPSTAT reg)
Preliminary
DS30221A-page 61
PIC16F872
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the completion of 10-bit address, and if this will be a read or write
data transfer.
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
9.2.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs. The MSSP module will override the
input state with the output data when required (slavetransmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
9.2.1.1
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slavetransmitter:
1.
a)
4.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification, as well as the requirement of
the MSSP module, is shown in timing parameter #100
and parameter #101 of the electrical specifications.
DS30221A-page 62
Receive first (high) byte of Address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
Update the SSPADD register with the second
(low) byte of Address (clears bit UA and
releases the SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
2.
3.
b)
The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
The buffer full bit, BF, is set on the falling edge of
the 8th SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the 9th SCL pulse.
b)
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
ADDRESSING
5.
6.
7.
8.
9.
Note:
Preliminary
Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
 1999 Microchip Technology Inc.
PIC16F872
9.2.1.2
SLAVE RECEPTION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the received byte.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
Note:
The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSPBUF is updated.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
TABLE 9-2
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
Yes
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
9.2.1.3
SLAVE TRANSMISSION
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the status of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-7).
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 9-6:
R/W=0
ACK
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
S
1
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
2
3
4
5
6
7
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
8
9
1
2
3
4
5
6
7
8
9
Not
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
SSPIF
9
P
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 63
PIC16F872
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 9-7:
R/W = 1
ACK
Receiving Address
SDA
A7
SCL
S
A6
1
2
Data in
sampled
A5
A4
A3
A2
A1
3
4
5
6
7
D7
8
9
R/W = 0
Not ACK
Transmitting Data
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
9.2.2
GENERAL CALL ADDRESS SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPIF flag is set.
I2C
bus is such that
The addressing procedure for the
the first byte after the START condition usually determines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF to determine if the address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is configured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
acknowledge (Figure 9-8).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8 bits are shifted
into SSPSR and the address is compared against
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-8:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
R/W = 0
ACK D7
General Call Address
SDA
Receiving data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV
(SSPCON<6>)
’0’
GCEN
(SSPCON2<7>)
’1’
DS30221A-page 64
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2.3
SLEEP OPERATION
9.2.4
While in SLEEP mode, the I2C module can receive
addresses or data. When an address match or complete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
REGISTERS ASSOCIATED WITH I2C OPERATION
TABLE 9-3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR,
WDT
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
0Dh
PIR2
—
(1)
—
EEIF
BCLIF
—
—
(1)
-r-0 0--r
-r-0 0--r
—
(1)
—
EEIE
BCLIE
—
—
(1)
-r-0 0--r
-r-0 0--r
xxxx xxxx
uuuu uuuu
Address
Name
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Dh
PIE2
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, r= reserved, - = unimplemented read as ’0’. Shaded cells are not used by the SSP in I2C
mode.
Note 1: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 65
PIC16F872
MASTER MODE
In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I 2C bus may be TACKEN when
the P bit is set, or the bus is idle with both the S and P
bits clear.
FIGURE 9-9:
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
•
•
•
•
•
START condition
STOP condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
SSP BLOCK DIAGRAM (I2C MASTER MODE)
SSPM<3:0>,
SSPADD<6:0>
Internal
Data Bus
Read
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
SSPSR
SCL in
Bus Collision
DS30221A-page 66
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
Preliminary
clock cntl
SCL
Receive Enable
MSb
clock arbitrate/WCOL detect
(hold off clock source)
9.2.5
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
 1999 Microchip Technology Inc.
PIC16F872
9.2.6
MULTI-MASTER MODE
9.2.7.4
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I 2C
bus may be TACKEN when bit P (SSPSTAT<4>) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the
expected output level. This check is performed in hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
9.2.7
I2C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
- Assert a start condition on SDA and SCL.
- Assert a Repeated Start condition on SDA and
SCL.
- Write to the SSPBUF register initiating transmission of data/address.
- Generate a stop condition on SDA and SCL.
- Configure the I2C port to receive data.
- Generate an Acknowledge condition at the end
of a received byte of data.
I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
also the beginning of the next serial transfer, the I2C
bus will not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
A typical transmit sequence would go as follows:
Note:
The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a start condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
a)
b)
c)
d)
e)
f)
g)
h)
 1999 Microchip Technology Inc.
Preliminary
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
start time before any other operation takes
place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of
data.
DATA is shifted out the SDA pin until all 8 bits
are transmitted.
DS30221A-page 67
PIC16F872
i)
j)
k)
l)
The MSSP module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
Interrupt is generated once the STOP condition
is complete.
9.2.8
In I2C Master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place for instance, the BRG
will be reloaded when the SCL pin is sampled high
(Figure 9-11).
FIGURE 9-10: BAUD RATE GENERATOR
BLOCK DIAGRAM
SSPM<3:0>
BAUD RATE GENERATOR
SSPADD<6:0>
SSPM<3:0>
Reload
SCL
Control
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 9-10). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another
reload has TACKEN place. The BRG count is decremented twice per instruction cycle (TCY), on the Q2 and
Q4 clock.
CLKOUT
Reload
BRG Down Counter
FOSC/4
FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
DS30221A-page 68
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2.9
I2C MASTER MODE START CONDITION
TIMING
Note:
To initiate a START condition, the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
I2C module is reset into its IDLE state.
9.2.9.5
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-12: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
SCL = 1
TBRG
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st Bit
SDA
2nd Bit
TBRG
SCL
TBRG
S
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 69
PIC16F872
9.2.10
I2C MASTER MODE REPEATED START
CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C module is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). When the baud rate generator times out
if SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG, while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed-out.
9.2.10.6
WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
FIGURE 9-13: REPEAT START CONDITION WAVEFORM
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
Set S (SSPSTAT<3>)
SDA = 1,
SCL = 1
TBRG
At completion of start bit,
hardware clear RSEN bit
and set SSPIF
TBRG
TBRG
1st Bit
SDA
Falling edge of ninth clock
End of Xmit
Write to SSPBUF occurs here.
TBRG
SCL
TBRG
Sr = Repeated Start
DS30221A-page 70
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2.11
I2C MASTER MODE TRANSMISSION
9.2.11.9
Transmission of a data byte, a 7-bit address or either
half of a 10-bit address, is accomplished by simply writing a value to SSPBUF register. This action will set the
buffer full flag (BF) and allow the baud rate generator to
begin counting and start the next transmission. Each
bit of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before
SCL is released high (see data setup time spec).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF flag is cleared
and the master releases SDA allowing the slave device
being addressed to respond with an ACK bit during the
ninth bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge
status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock, the SSPIF is set and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF, leaving SCL low
and SDA unchanged (Figure 9-14).
ACKSTAT STATUS FLAG
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0) and is set when the slave does not acknowledge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
9.2.11.7
BF STATUS FLAG
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
9.2.11.8
WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 71
DS30221A-page 72
S
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
9
After start condition SEN cleared by hardware.
SSPBUF written
1
D7
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
From SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit address
From slave clear ACKSTAT bit SSPCON2<6>
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W
start transmit
A7
Transmit Address to Slave
SEN = 0
Write SSPCON2<0> SEN = 1
START condition begins
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
PIC16F872
FIGURE 9-14: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
 1999 Microchip Technology Inc.
PIC16F872
9.2.12
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note:
The SSP module must be in an IDLE
STATE before the RCEN bit is set or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to
low/low to high), and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive
enable flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is suspended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automatically cleared. The user can then send an acknowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
9.2.12.10 BF STATUS FLAG
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.11 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR and the BF flag is already set
from a previous reception.
9.2.12.12 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 73
DS30221A-page 74
S
Preliminary
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
2
1
A4
4
A5
3
5
A3
Cleared in software
A6
A7
6
A2
Transmit Address to Slave
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2<0> (SEN = 1)
Begin Start Condition
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
D6
3
D5
5
D3
6
D2
7
D1
8
D0
9
ACK
2
D6
3
D5
4
D4
5
D3
6
D2
Receiving Data from Slave
7
D1
Cleared in software
Set SSPIF interrupt
at end of acknowledge
sequence
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN start acknowledge sequence
SDA = ACKDT = 1
Data shifted in on falling edge of CLK
1
D7
RCEN = 1 start
next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
D4
Receiving Data from Slave
Cleared in software
1
D7
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1)
Write to SSPCON2<4>
to start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16F872
FIGURE 9-15: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
 1999 Microchip Technology Inc.
PIC16F872
9.2.13
ACKNOWLEDGE SEQUENCE TIMING
the baud rate generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off,
and the SSP module then goes into IDLE mode.
(Figure 9-16)
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
9.2.13.13 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledege
sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
ACK
D0
SCL
9
8
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: TBRG = one baud rate generator period.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 75
PIC16F872
9.2.14
STOP CONDITION TIMING
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-17).
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be deasserted. When the SDA pin is sampled high
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e., bus is free).
9.2.14.14 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: TBRG = one baud rate generator period.
DS30221A-page 76
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2.15
CLOCK ARBITRATION
9.2.16
Clock arbitration occurs when the master, during any
receive, transmit, or repeated start/stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-18).
SLEEP OPERATION
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
9.2.17
EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC • 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
 1999 Microchip Technology Inc.
TBRG
TBRG
Preliminary
DS30221A-page 77
PIC16F872
9.2.18
MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
a bus collision has taken place. The master will set the
Bus Collision Interrupt Flag, BCLIF, and reset the I2C
port to its IDLE state. (Figure 9-19).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I2C
bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated Start, STOP or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I2C bus is free, the user can resume communication by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of start and stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared.
FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt.
BCLIF
DS30221A-page 78
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
9.2.18.15 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-20).
SCL is sampled low before SDA is asserted low.
(Figure 9-21).
b)
During a START condition both the SDA and the SCL
pins are monitored.
If:
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-22). If, however, a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0. During this time, if the SCL pins are
sampled as ’0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-20).
The START condition begins with the SDA and SCL
pins deasserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address following the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, REPEATED
START or STOP conditions.
FIGURE 9-20: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, enable start
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
BCLIF
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 79
PIC16F872
FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF
SEN
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF
BCLIF
Interrupts cleared
in software
S
’0’
’0’
SSPIF
’0’
’0’
FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
TBRG
SDA pulled low by other master
Reset BRG and assert SDA
SCL
s
SCL pulled low after BRG
Timeout
SEN
BCLIF
Set SSPIF
’0’
Set SEN, enable start
sequence if SDA = 1, SCL = 1
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
DS30221A-page 80
Preliminary
Interrupts cleared
in software
 1999 Microchip Technology Inc.
PIC16F872
9.2.18.16 BUS COLLISION DURING A REPEATED
START CONDITION
sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times
out, no bus collision occurs, because no two masters
can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, a
bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ’1’.
If, at the end of the BRG time out, both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete (Figure 9-23).
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted, and
when sampled high, the SDA pin is sampled. If SDA is
low, a bus collision has occurred (i.e., another master is
attempting to transmit a data ’0’). If, however, SDA is
FIGURE 9-23: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
S
’0’
Cleared in software
’0’
SSPIF
’0’
’0’
FIGURE 9-24: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
BCLIF
Interrupt cleared
in software
RSEN
S
’0’
’0’
SSPIF
’0’
’0’
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 81
PIC16F872
9.2.18.17 BUS COLLISION DURING A STOP
CONDITION
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to float.
When the pin is sampled high (clock arbitration), the
baud rate generator is loaded with SSPADD<6:0> and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is a case of another master attempting to drive a
data ’0’ (Figure 9-25).
Bus collision occurs during a STOP condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 9-25: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA sampled
low after TBRG,
Set BCLIF.
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
’0’
’0’
FIGURE 9-26:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
SSPIF
’0’
DS30221A-page 82
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
Connection Considerations for I2C
Bus
For standard-mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-27 depend on the following parameters:
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of Rp is shown in Figure 9-27.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of Rs. Series resistors are
optional and used to improve ESD susceptibility.
• Supply voltage
• Bus capacitance
• Number of connected devices
(input current + leakage current).
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the maximum value of Rp due to the specified rise time
(Figure 9-27).
The supply voltage limits the minimum value of resistor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
9.3
FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
Rp
DEVICE
Rp
Rs
Rs
SDA
SCL
Cb=10 - 400 pF
Note:
I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
connected.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 83
PIC16F872
NOTES:
DS30221A-page 84
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
10.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers. These registers
are:
•
•
•
•
The Analog-to-Digital (A/D) Converter module has five
inputs.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the
input into the converter. The converter then generates
a digital result of this analog level via successive
approximation. The A/D conversion of the analog input
signal results in a corresponding 10-bit digital number.
The A/D module has high and low voltage reference
input that is software selectable to some combination
of VDD, VSS, RA2 or RA3.
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 10-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage reference) or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To
operate in SLEEP, the A/D clock must be derived from
the A/D’s internal RC oscillator.
REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1 ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS<1:0>: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5-3: CHS<2:0>: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion
is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 85
PIC16F872
REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit7
bit0
bit 7:
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
ADFM: A/D Result format select
1 = Right Justified. 6 most significant bits of ADRESH are read as ‘0’.
0 = Left Justified. 6 least significant bits of ADRESL are read as ‘0’.
bit 6-4: Unimplemented: Read as '0'
bit 3-0: PCFG<3:0>: A/D Port Configuration Control bits
PCFG<3:0>
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
VREF+
VREF-
CHAN /
Refs(1)
0000
A
A
A
A
A
VDD
VSS
5/0
0001
A
VREF+
A
A
A
RA3
VSS
4/1
0010
A
A
A
A
A
VDD
VSS
5/0
0011
A
VREF+
A
A
A
RA3
VSS
4/1
0100
D
A
D
A
A
VDD
VSS
3/0
0101
D
VREF+
D
A
A
RA3
VSS
2/1
011x
D
D
D
D
D
VDD
VSS
0/0
1000
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1001
A
A
A
A
A
VDD
VSS
5/0
1010
A
VREF+
A
A
A
RA3
VSS
4/1
1011
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1100
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1101
D
VREF+
VREF-
A
A
RA3
RA2
2/2
1110
D
D
D
D
A
VDD
VSS
1/0
1111
D
VREF+
VREF-
D
A
RA3
RA2
1/2
A = Analog input
D = Digital I/O
Note 1:
This column indicates the number of analog channels available as A/D inputs and the number of analog channels
used as voltage reference inputs.
DS30221A-page 86
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
1.
2.
3.
4.
5.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
7.
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 87
PIC16F872
FIGURE 10-1: A/D BLOCK DIAGRAM
CHS<2:0>
100
RA5/AN4
VAIN
011
(Input voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF-
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
VREF+
(Reference
voltage)
PCFG<3:0>
VREF(Reference
voltage)
VSS
PCFG<3:0>
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 10-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
DS30221A-page 88
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
EQUATION 10-1:
TACQ
TC
TACQ
ACQUISITION TIME
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µS
2µS + 16.47µS + [(50°C -25×C)(0.05µS/×C)
19.72µS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2: ANALOG INPUT MODEL
VDD
RS
VT = 0.6V
ANx
VA
CPIN
5 pF
VT = 0.6V
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
= 120 pF
I LEAKAGE
± 500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
 1999 Microchip Technology Inc.
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Preliminary
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30221A-page 89
PIC16F872
10.2
Selecting the A/D Conversion Clock
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
•
•
•
•
Table 10-1shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2TOSC
8TOSC
32TOSC
Internal RC oscillator
TABLE 10-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS<1:0>
Max.
2TOSC
00
1.25 MHz
8TOSC
01
5 MHz
32TOSC
10
20 MHz
RC(1, 2, 3)
11
Note 1
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep
operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
10.3
Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN<4:0>
pins), may cause the input buffer to consume current that is out of the device
specifications.
DS30221A-page 90
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
10.4
required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
That
is,
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is aborted, a 2TAD wait is
In Figure 10-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 10-3: A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
 1999 Microchip Technology Inc.
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
Preliminary
DS30221A-page 91
PIC16F872
10.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits
wide. The A/D module gives the flexibility to left or right
justify the 10-bit result in the 16-bit result register. The
A/D Format Select bit (ADFM) controls this justification. Figure 10-4 shows the operation of the A/D result
justification. The extra bits are loaded with ’0’s’. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
10.5
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS<1:0> = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
10.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS<1:0> = 11). To allow the conversion to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
Effects of a Reset
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 10-4: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS30221A-page 92
0
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 10-2:
Addr
Name
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR,
WDT
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
0000 00-0
9Fh
ADCON1
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- 0000
--0- 0000
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111
--11 1111
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--0x 0000
--0u 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 93
PIC16F872
NOTES:
DS30221A-page 94
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
11.0
SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving
operating modes and offer code protection. These are:
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
11.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h
through 3FFFh), which can be accessed only during
programming.
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up
only. It is designed to keep the part in RESET while the
power supply stabilizes. With these two timers on-chip,
most applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 95
PIC16F872
REGISTER 11-1: CONFIGURATION WORD
CP1
CP0
DEBUG
—
WRT
CPD
LVP
BODEN
CP1
CP0
PWRTE
WDTE
bit13
F0SC1
F0SC0
bit0
Register: CONFIG
Address 2007h
bit 13-12:
bit 5-4:
CP<1:0>: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = 0000h to 06FFh code protected
01 = 0000h to 03FFh code protected
00 = 0000h to 07FFh code protected
bit 11:
DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10:
Unimplemented: Read as ‘1’
bit 9:
WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8:
CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory code protected
bit 7:
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
DS30221A-page 96
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
11.2
Oscillator Configurations
11.2.1
OSCILLATOR TYPES
TABLE 11-1:
Ranges Tested:
The PIC16F872 can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
11.2.2
CERAMIC RESONATORS
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-1). The
PIC16F872 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-2).
455 kHz
Panasonic EFO-A455K04B
± 0.3%
2.0 MHz
Murata Erie CSA2.00MG
± 0.5%
4.0 MHz
Murata Erie CSA4.00MG
± 0.5%
8.0 MHz
Murata Erie CSA8.00MT
± 0.5%
16.0 MHz
Murata Erie CSA16.00MX
± 0.5%
All resonators used did not have built-in capacitors.
FIGURE 11-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
C1(1)
OSC1
XTAL
To
internal
logic
RF(3)
OSC2
SLEEP
RS(2)
PIC16F872
C2(1)
Note 1: See Table 11-1 and Table 11-2 for recommended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
3: RF varies with the crystal chosen.
FIGURE 11-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16F872
Open
OSC2
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 97
PIC16F872
TABLE 11-2:
Osc
Type
LP
XT
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Cap. Range
C1
Cap.
Range
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
11.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 11-3 shows how the R/C combination is connected to the PIC16F872.
FIGURE 11-3: RC OSCILLATOR MODE
These values are for design guidance only.
See notes at bottom of page.
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
CEXT
VSS
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
REXT
OSC1
PIC16F872
FOSC/4
Recommended values:
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
Internal
Clock
OSC2/CLKOUT
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
DS30221A-page 98
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
11.3
Reset
The PIC16F872 differentiates between various kinds of
reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Brown-out Reset (BOR)
Brown-out Reset (BOR). They are not affected by a
WDT Wake-up, which is viewed as the resumption of
normal operation. The TO and PD bits are set or
cleared differently in different reset situations as indicated in Table 11-4. These bits are used in software to
determine the nature of the reset. See Table 11-6 for a
full description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 11-4.
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“reset state” on Power-on Reset (POR), on the MCLR
and WDT Reset, on MCLR Reset during SLEEP, and
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
WDT
SLEEP
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
R
10-bit Ripple counter
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 99
PIC16F872
11.4
Power-On Reset (POR)
11.8
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note, AN007, “Power-up Trouble Shooting”,
(DS00007).
11.5
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
11.6
Time-out Sequence
On power-up, the Time-out Sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in
parallel.
Table 11-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 11-6 shows the
reset conditions for all the registers.
11.9
Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "don’t care" bit and is not necessarily predictable if
the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
11.7
Brown-Out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situation will reset the device. If VDD falls below VBOR for
less than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the Brown-out Reset
process will restart when VDD rises above VBOR with
the Power-up Timer reset. The Power-up Timer is
always enabled when the Brown-out Reset circuit is
enabled regardless of the state of the PWRT configuration bit.
DS30221A-page 100
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 11-3:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Brown-out
Wake-up from
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
1024TOSC
72 ms + 1024TOSC
1024TOSC
RC
72 ms
—
72 ms
—
TABLE 11-4:
POR
Power-up
BOR
STATUS BITS AND THEIR SIGNIFICANCE
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 101
PIC16F872
TABLE 11-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Power-on Reset,
MCLR Resets
Wake-up via WDT or
Brown-out Reset
WDT Reset
Interrupt
W
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
N/A
N/A
N/A
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000h
0000h
PC + 1(2)
(3)
STATUS
0001 1xxx
000q quuu
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
--0x 0000
--0u 0000
--uu uuuu
PORTB
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
r0rr 0000
r0rr 0000
rurr uuuu(1)
PIR2
-r-0 0--r
-r-0 0--r
-r-u u--r(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
SSPBUF
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
0000 0000
0000 0000
uuuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
ADRESH
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
1111 1111
1111 1111
uuuu uuuu
TRISA
--11 1111
--11 1111
--uu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
TRISC
1111 1111
1111 1111
uuuu uuuu
PIE1
r0rr 0000
r0rr 0000
rurr uuuu
PIE2
-r-0 0--r
-r-0 0--r
-r-u u--r
PCON
---- --qq
---- --uu
---- --uu
PR2
1111 1111
1111 1111
1111 1111
SSPADD
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
--00 0000
--00 0000
--uu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
0--- 0000
0--- 0000
u--- uuuu
EEDATA
0--- 0000
0--- 0000
u--- uuuu
EEADR
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATH
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADRH
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON1
x--- x000
u--- u000
u--- uuuu
EECON2
---- ------- ------- ---Legend: u = unchanged, x = unknown, r = reserved, - = unimplemented bit, read as ’0’, q = value depends
on condition, r = reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for reset value for specific condition.
DS30221A-page 102
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 103
PIC16F872
FIGURE 11-8: SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30221A-page 104
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
11.10
Interrupts
The PIC16F872 has 10 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and
global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special
Function Registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in Special Function
Register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
FIGURE 11-9: INTERRUPT LOGIC
T0IF
T0IE
EEIF
EEIE
INTF
INTE
ADIF
ADIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE
CCP1IF
CCP1IE
PEIE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
BCLIF
BCLIE
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 105
PIC16F872
11.10.1 INT INTERRUPT
11.11
Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 11.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Since the upper 16 bytes of each bank are common in
the PIC16F872 devices, temporary holding registers
W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for context save and restore. Example 11-1 can be used to
save and restore context for interrupts.
11.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
11.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 3.2).
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy
;Swap
;bank
;Save
;Only
;Save
;Page
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS30221A-page 106
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
required if using pages 1, 2 and/or 3
PCLATH into W
zero, regardless of current page
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
11.12
WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out.
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
WDT Timer
Postscaler
M
U
X
1
8
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION_REG register.
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h,181h
OPTION_REG
Bit 7
Bit 6
(1)
BODEN(1)
RBPU
INTEDG
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 107
PIC16F872
11.13
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
11.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
CCP capture mode interrupt.
Special event trigger (Timer1 in asynchronous
mode using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode (SPI/I2C).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
DS30221A-page 108
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
Inst(PC) = SLEEP
Inst(PC - 1)
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
11.14
11.16
In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a ’0’, the In-Circuit Debugger functionality
is enabled. This function allows simple debugging functions when used with MPLAB®. When the microcontroller has this feature enabled, some of the resources are
not available for general use. Table 11-7 shows which
features are consumed by the background debugger.
TABLE 11-7:
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070(0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
11.15
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 109
PIC16F872
11.17
In-Circuit Serial Programming
11.18
The PIC16F872 microcontroller can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
When using ICSP, the part must be supplied 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code protect both from an onstate to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs or user
code can be reprogrammed or added.
Low Voltage ICSP Programming
The LVP bit of the configuration word enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter programming mode, VDD must be applied
to the RB3/PGM provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
Note 1: The high voltage programming mode is
always available, regardless of the state of
the LVP bit, by applying VIHH to the MCLR
pin.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277).
2: While in low voltage ICSP mode, the RB3
pin can no longer be used as a general
purpose I/O pin.
3: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
If low-voltage programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is available and only high voltage programming mode can be
used to program the device.
When using low voltage ICSP, the part must be supplied 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal
operating voltage. This means calibration values,
unique user IDs or user code can be reprogrammed or
added.
DS30221A-page 110
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
12.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 12-2 lists byte-oriented, bitoriented, and literal and control operations.
Table 12-1 shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file register designator and ’d’ represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Table 12-2 lists the instructions recognized by the
MPASM assembler.
Figure 12-1 shows the general formats that the instructions can have.
Note:
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 12-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
TABLE 12-1:
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It
is the recommended form of use for compatibility with all Microchip software tools.
d
Program Counter
TO
Time-out bit
PD
0
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
OPCODE FIELD
DESCRIPTIONS
Field
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
Power-down bit
10
0
k (literal)
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
PICmicro™
Mid-Range
Reference
Manual,
(DS33023).
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 111
PIC16F872
TABLE 12-2:
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
C,DC,Z
Z
Z
Z
Z
Z
1,2
1,2
2
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
DS30221A-page 112
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
12.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[label] ADDLW
Syntax:
[label] ANDWF
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
k
f,d
Operation:
(W) + k → (W)
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Description:
The contents of the W register
are added to the eight bit literal ’k’
and the result is placed in the W
register.
Status Affected:
Z
Description:
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
BCF
Bit Clear f
Syntax:
[label] BCF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Status Affected:
None
Description:
Bit 'b' in register 'f' is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[label] ADDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in register ’f’.
f,d
ANDLW
AND Literal with W
Syntax:
[label] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
1 → (f<b>)
f,b
f,b
Syntax:
[label] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
Operation:
(W) .AND. (k) → (W)
Status Affected:
None
Status Affected:
Z
Description:
Bit 'b' in register 'f' is set.
Description:
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
 1999 Microchip Technology Inc.
k
Preliminary
DS30221A-page 113
PIC16F872
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
Operation:
skip if (f<b>) = 1
00h → (f)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
instruction is executed.
If bit ’b’ is ’1’, then the next instruction is discarded and a NOP is executed instead making this a 2TCY
instruction.
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
CLRW
Clear W
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h → (W)
1→Z
f
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0 ≤ k ≤ 2047
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
TO, PD
Status Affected:
None
Description:
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immediate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two cycle instruction.
CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
DS30221A-page 114
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
COMF
Complement f
GOTO
Unconditional Branch
Syntax:
[ label ] COMF
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 2047
Operation:
(f) → (destination)
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected:
Z
Status Affected:
None
Description:
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTO is an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two
cycle instruction.
DECF
Decrement f
Syntax:
[label] DECF f,d
INCF
Increment f
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(f) + 1 → (destination)
f,d
GOTO k
INCF f,d
Operation:
(f) - 1 → (destination)
Status Affected:
Z
Operation:
Description:
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W register. If ’d’ is 1, the result is stored
back in register ’f’.
Status Affected:
Z
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in register ’f’.
INCFSZ
Increment f, Skip if 0
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Status Affected:
None
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in register ’f’.
If the result is 1, the next instruction is executed. If the result is 0,
then a NOP is executed instead
making it a 2TCY instruction.
 1999 Microchip Technology Inc.
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in register ’f’.
If the result is 1, the next instruction is executed. If the result is 0, a
NOP is executed instead making it
a 2TCY instruction.
Preliminary
INCFSZ f,d
DS30221A-page 115
PIC16F872
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Description:
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Description:
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Move W to f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
Operation:
(W) → (f)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
None
Status Affected:
Z
Description:
Move data from W register to register 'f'.
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in register 'f'.
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
IORLW k
IORWF
f,d
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Z
Description:
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, destination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS30221A-page 116
MOVF f,d
Preliminary
MOVLW k
MOVWF
f
NOP
 1999 Microchip Technology Inc.
PIC16F872
RETFIE
Return from Interrupt
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC,
1 → GIE
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
None
Status Affected:
C
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
Status Affected:
RETFIE
RLF
C
RETLW
Return with Literal in W
Syntax:
[ label ]
Operands:
Operation:
RETLW k
f,d
Register f
RRF
Rotate Right f through Carry
0 ≤ k ≤ 255
Syntax:
[ label ]
k → (W);
TOS → PC
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
None
Operation:
See description below
Description:
The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
Status Affected:
C
Description:
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in register ’f’.
RRF f,d
C
Register f
RETURN
Return from Subroutine
Syntax:
[ label ]
Operands:
None
SLEEP
Operation:
TOS → PC
Syntax:
[ label ]
Status Affected:
None
Operands:
None
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
RETURN
 1999 Microchip Technology Inc.
Preliminary
SLEEP
DS30221A-page 117
PIC16F872
SUBLW
Syntax:
Subtract W from Literal
[ label ]
SUBLW k
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
The W register is subtracted (2’s
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
Description:
The contents of the W register
are XOR’ed with the eight bit literal 'k'. The result is placed in
the W register.
SUBWF
Syntax:
Subtract W from f
[ label ]
SUBWF f,d
XORWF
Exclusive OR W with f
Syntax:
[label]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (destination)
Operation:
(W) .XOR. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W register. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected:
None
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W register. If 'd' is 1, the result is placed in
register 'f'.
DS30221A-page 118
XORLW
Exclusive OR Literal with W
Syntax:
[label]
Preliminary
XORLW k
XORWF
f,d
 1999 Microchip Technology Inc.
PIC16F872
13.0
DEVELOPMENT SUPPORT
MPLAB allows you to:
PICmicro®
The
microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
Emulator
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
- KEELOQ
13.1
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
13.2
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB
debugging.
MPASM features include:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a Windows-based application which contains:
 1999 Microchip Technology Inc.
MPASM Assembler
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device programmers, or it can generate relocatable objects for
MPLINK.
MPLAB Integrated Development
Environment Software
• Multiple functionality
- editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
• On-line help
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
- object code
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi purpose source files.
• MPASM directives allow complete control over the
assembly process.
13.3
MPLAB-C17 and MPLAB-C18
C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and integrated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compilers provide symbol information that is compatible with the
MPLAB IDE memory display.
Preliminary
DS30221A-page 119
PIC16F872
13.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with precompiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes linking easier because single libraries can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
13.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and
debug code outside of the laboratory environment making it an excellent multi-project software development
tool.
13.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30221A-page 120
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcontrollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
13.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER systems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
13.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
13.9
MPLAB-ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Circuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
13.10
PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
13.11
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
13.12
SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry-level system development.
13.13
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
 1999 Microchip Technology Inc.
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
13.14
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
13.15
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
Preliminary
DS30221A-page 121
PIC16F872
13.16
PICDEM-17
The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and
modified using either emulator. Additionally, a generous
prototype area is available for user hardware.
13.17
SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
13.18
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS30221A-page 122
Preliminary
 1999 Microchip Technology Inc.
Software Tools
Emulators
 1999 Microchip Technology Inc.
Programmers Debugger
á
PIC17C4X
á á
á á á
á
á
PIC16C9XX
á
á á á á
á
á
PIC16F8XX
á
á á
á
á
PIC16C8X
á
á á á á
á
á
PIC16C7XX
á
á á á á
á
á
PIC16C7X
á
á á á á
á
á
PIC16F62X
á
á á
PIC16CXXX
á
á á á á
PIC16C6X
á
á á á á
á
á
PIC16C5X
á
á á á á
á
á
PIC14000
á
á á á
á
á
PIC12CXXX
á
á á á á
á
á
Preliminary
MCP2510
á
á
á á
á
á
á
á
á
á á
á
á
á
á á
á
á
®
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB -ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
MCP2510 CAN Developer’s Kit
MCRFXXX
á á á
13.56 MHz Anticollision microID
Developer’s Kit
125 kHz Anticollision microID
Developer’s Kit
125 kHz microID Developer’s Kit
microID™ Programmer’s Kit
KEELOQ Transponder Kit
KEELOQ® Evaluation Kit
PICDEM-17
á
PICDEM-14A
á
PICDEM-3
á
á
†
á
á
PICDEM-2
á
†
24CXX/
25CXX/
93CXX
á
†
á
PICDEM-1
á á á
**
**
HCSXXX
á
SIMICE
®
MPLAB -ICD In-Circuit
Debugger
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/PICMASTER-CE
*
á
PRO MATE II
Universal Programmer
á
PICSTARTPlus
Low-Cost Universal Dev. Kit
á á á
*
PIC17C7XX
á á
**
PIC18CXX2
á
á
MPASM/MPLINK
®
MPLAB -ICE
TABLE 13-1:
Demo Boards and Eval Kits
®
MPLAB Integrated
Development Environment
®
MPLAB C17 Compiler
®
MPLAB C18 Compiler
PIC16F872
DEVELOPMENT TOOLS FROM MICROCHIP
DS30221A-page 123
PIC16F872
NOTES:
DS30221A-page 124
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
14.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).............................................................................................0 to +13.25V
Voltage on RA4 with respect to Vss ..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined) ................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined) ...........................................................................200 mA
Maximum current sunk by PORTC........................................................................................................................200 mA
Maximum current sourced by PORTC ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS..
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 125
PIC16F872
FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
Eq
2.5 V
2.0 V
Eq
4 MHz
tio
ua
ti
ua
on
2
n1
10 MHz
20 MHz
Frequency
Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V
Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0 V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30221A-page 126
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
14.1
DC Characteristics:
PIC16F872 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
No.
Characteristic
D001 Supply Voltage
D001A
Sym
VDD
VDR
Min
Typ† Max Units
4.0
4.5
VBOR*
-
5.5
5.5
5.5
V
V
V
-
1.5
-
V
-
VSS
-
V
Conditions
XT, RC and LP osc configuration
HS osc configuration
BOR enabled, Fmax = 14MHz (Note 7)
D002*
RAM Data Retention
Voltage (Note 1)
D003
VDD start voltage to
VPOR
ensure internal Power-on
Reset signal
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
VBOR
3.7
4.0
4.35
V
D010
Supply Current (Note 2,5) IDD
-
1.6
4
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
7
15
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
∆IBOR
-
85
200
µA
BOR enabled VDD = 5.0V
D020 Power-down Current
D021 (Note 3,5)
D021A
IPD
-
10.5
1.5
1.5
42
16
19
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
D023*
∆IBOR
-
85
200
µA
BOR enabled VDD = 5.0V
D013
D015*
Brown-out Reset Current
(Note 6)
Brown-out Reset Current
(Note 6)
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
BODEN bit in configuration word enabled
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 127
PIC16F872
14.2
DC Characteristics:
PIC16LF872 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
Typ† Max Units
Conditions
D001
Supply Voltage
VDD
2.0
-
5.5
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VPOR
VDD start voltage to
ensure internal Power-on
Reset signal
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage VBOR
3.7
4.0
4.35
V
D010
Supply Current (Note 2,5) IDD
-
0.6
2.0
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
20
35
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010A
LP, XT, RC osc configuration (DC - 4 MHz)
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
BODEN bit in configuration word enabled
D015*
Brown-out Reset Current ∆IBOR
(Note 6)
-
85
200
µA
BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5)
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023*
Brown-out Reset Current ∆IBOR
(Note 6)
-
85
200
µA
BOR enabled VDD = 5.0V
IPD
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30221A-page 128
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
14.3
DC Characteristics:
PIC16F872 and PIC16LF872 (Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
D034
with Schmitt Trigger buffer
D034A
with SMBus
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
D042
MCLR
D042A OSC1 (XT, HS and LP)
D043
OSC1 (in RC mode)
Ports RC3 and RC4
D044
with Schmitt Trigger buffer
D044A
with SMBus
D070
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
D060
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (RC osc config)
D090
Output High Voltage
I/O ports (Note 3)
D092
OSC2/CLKOUT (RC osc config)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
Section 14.2.
Sym
Min Typ† Max Units
Conditions
VIL
VSS
VSS
VSS
VSS
VSS
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
VSS
-0.5
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
VDD
5.5
400
V For entire VDD range
V for VDD = 4.5 to 5.5V
µA VDD = 5V, VPIN = VSS
VIH
2.0
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
0.7VDD
1.4
IPURB
50
250
-
-
±1
-
-
±5
±5
-
-
0.6
V
-
-
0.6
V
VOH VDD - 0.7
-
-
V
VDD - 0.7
-
-
V
IIL
VOL
Note1
Note1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 129
PIC16F872
DC CHARACTERISTICS
Param
Characteristic
No.
D150* Open-Drain High Voltage
D100
D101
D102
D120
D121
D122
D130
D131
D132a
Capacitive Loading Specs on
Output Pins
OSC2 pin
All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode
Data EEPROM Memory
Endurance
VDD for read/write
Erase/write cycle time
Program FLASH Memory
Endurance
VDD for read
VDD for erase/write
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
Section 14.2.
Sym
Min Typ† Max Units
Conditions
VOD
-
-
8.5
V
RA4 pin
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
CIO
CB
-
-
50
400
pF
pF
ED
VDRW
100K
Vmin
-
5.5
TDEW
-
4
8
EP
VPR
1000
Vmin
Vmin
-
5.5
5.5
E/W 25°C at 5V
V Using EECON to read/write
Vmin = min operating voltage
ms
E/W 25°C at 5V
V Vmin = min operating voltage
V using EECON to read/write,
Vmin = min operating voltage
ms
D133
Erase/Write cycle time
TPEW
4
8
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30221A-page 130
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
14.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 14-3: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the 28-pin devices.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 131
PIC16F872
FIGURE 14-4: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 14-1:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
FOSC External CLKIN Frequency
(Note 1)
Oscillator Frequency
(Note 1)
1
TOSC External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
2
TCY
Instruction Cycle Time
(Note 1)
TosL, External Clock in (OSC1) High
TosH or Low Time
Min
Typ†
Max
DC
DC
DC
DC
DC
0.1
4
5
250
250
50
5
250
250
250
50
5
200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCY
4
4
20
200
4
4
20
200
—
—
—
—
—
10,000
250
250
—
DC
Units Conditions
MHz
MHz
MHz
kHz
MHz
MHz
MHz
kHz
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
XT and RC osc mode
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
RC osc mode
XT osc mode
HS osc mode
LP osc mode
XT and RC osc mode
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
RC osc mode
XT osc mode
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
TCY = 4/FOSC
100
—
—
ns XT oscillator
2.5
—
—
µs LP oscillator
15
—
—
ns HS oscillator
4
TosR, External Clock in (OSC1) Rise
—
—
25
ns XT oscillator
TosF or Fall Time
—
—
50
ns LP oscillator
—
—
15
ns HS oscillator
Legend: † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is
"DC" (no clock) for all devices.
3
DS30221A-page 132
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 14-5: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-2:
Param Sym
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH Port in valid before CLKOUT ↑
TOSC + 200
—
—
ns
Note 1
16*
TckH2ioI
0
—
—
ns
Note 1
17*
TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid
—
100
255
ns
18*
TosH2ioI
Standard (F)
100
—
—
ns
Extended (LF)
200
—
—
ns
Port in hold after CLKOUT ↑
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
19*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
Standard (F)
—
10
40
ns
Extended (LF)
—
—
145
ns
21*
TioF
Port output fall time
Standard (F)
—
10
40
ns
—
—
145
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
Extended (LF)
Legend: *
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 133
PIC16F872
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-7: BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 14-3:
Parameter
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
µs
35
TBOR
Brown-out Reset pulse width
100
—
—
µs
Legend: *
†
VDD ≤ VBOR (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS30221A-page 134
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-4:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
41*
Tt0L
T0CKI Low Pulse Width
42*
Tt0P
T0CKI Period
45*
46*
47*
Tt1H
Tt1L
Tt1P
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
T1CKI High Time
Synchronous, Prescaler = 1
Synchronous, Standard(F)
Prescaler =
Extended(LF)
2,4,8
Asynchronous Standard(F)
Extended(LF)
T1CKI Low Time
Synchronous, Prescaler = 1
Synchronous, Standard(F)
Prescaler =
Extended(LF)
2,4,8
Asynchronous Standard(F)
Extended(LF)
T1CKI input period Synchronous
Standard(F)
Extended(LF)
Asynchronous
48
*
†
Standard(F)
Extended(LF)
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5TCY + 20
15
25
30
50
0.5TCY + 20
15
25
30
50
Greater of:
30 OR TCY + 40
N
Greater of:
50 OR TCY + 40
N
60
100
DC
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 135
PIC16F872
FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-5:
Param
No.
50*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Sym Characteristic
TccL CCP1 input
low time
Min
No Prescaler
Standard(F)
With Prescaler
51*
TccH CCP1 input
high time
With Prescaler
52*
TccP CCP1 input period
53*
TccR CCP1 output rise time
54*
*
†
Extended(LF)
No Prescaler
TccF CCP1 output fall time
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
Standard(F)
10
—
—
ns
Extended(LF)
20
—
—
ns
3TCY + 40
N
—
—
ns
Standard(F)
—
10
25
ns
Extended(LF)
—
25
50
ns
Standard(F)
—
10
25
ns
Extended(LF)
—
25
45
ns
N = prescale
value (1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
These parameters are for design guidance only and are not tested.
DS30221A-page 136
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
FIGURE 14-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 14-3 for load conditions.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 137
PIC16F872
FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 14-3 for load conditions.
DS30221A-page 138
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 14-6:
Param
No.
SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
ns
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71*
TscH
SCK input high time (slave mode)
TCY + 20
—
—
72*
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75*
TdoR
SDO data output rise time
—
—
10
25
25
50
ns
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time (master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
TscF
SCK output fall time (master mode)
80*
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
81*
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
82*
TssL2doV
SDO data output valid after SS↓ edge
83*
TscH2ssH,
TscL2ssH
SS ↑ after SCK edge
*
†
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
—
10
25
ns
—
—
—
—
50
145
ns
TCY
—
—
ns
—
—
50
ns
1.5TCY + 40
—
—
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 14-14: I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-7:
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
90
TSU:STA
START condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
START condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
91
92
93
THD:STA
TSU:STO
THD:STO
 1999 Microchip Technology Inc.
Min Typ Max Units
Preliminary
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
DS30221A-page 139
PIC16F872
FIGURE 14-15: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 14-3 for load conditions.
I2C BUS DATA REQUIREMENTS
TABLE 14-8:
Param
No.
Sym
Characteristic
100
THIGH
Clock high time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
Device must operate at a minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 10 MHz
1.5TCY
—
100 kHz mode
4.7
—
µs
Device must operate at a minimum of 1.5 MHz
400 kHz mode
1.3
—
µs
Device must operate at a minimum of 10 MHz
SSP Module
101
TLOW
Clock low time
1.5TCY
—
SDA and SCL rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
SDA and SCL fall time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10 to 400 pF
START condition
setup time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Only relevant for repeated
START condition
START condition hold
time
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Data input hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
STOP condition setup
time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
—
400
pF
SSP Module
102
103
90
91
106
107
92
109
110
TR
TF
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
Cb
Data input setup time
Bus free time
Bus capacitive loading
Cb is specified to be from
10 to 400 pF
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;
DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
DS30221A-page 140
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
TABLE 14-9:
Param
No.
PIC16F872 AND PIC16LF872 (INDUSTRIAL)
Sym Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10-bits
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
EIL
Integral linearity error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF Offset error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07
EGN
Gain error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity(3)
—
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
2.0V
—
VDD + 0.3
V
Absolute minimum electrical
spec. To ensure 10-bit
accuracy.
AVDD + 0.3V
V
A20
VREF Reference voltage (VREF+ - VREF-)
A21
VREF Reference voltage High
+
AVDD - 2.5V
A22
VREF- Reference voltage low
AVSS - 0.3V
VREF+ - 2.0V
V
A25
VAIN Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
A30
ZAIN Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
Standard
—
220
—
µA
Extended
—
90
—
µA
10
—
1000
µA
During VAIN acquisition.
Based on differential of VHOLD
to VAIN to charge CHOLD, see
Section 10.1.
—
—
10
µA
During A/D Conversion cycle
A50
IREF
A/D conversion current (VDD)
VREF input current (Note 2)
Average current consumption
when A/D is on.
(Note 1)
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 141
PIC16F872
FIGURE 14-16: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2)(1)
131
Q4
130
132
A/D CLK
9
A/D DATA
8
...
7
...
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param
No.
130
Sym Characteristic
TAD
A/D clock period
Min
Conditions
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
3.0
—
—
µs
TOSC based, VREF ≥ 2.0V
Standard(F)
2.0
4.0
6.0
µs
A/D RC Mode
Extended(LF)
3.0
6.0
9.0
µs
A/D RC Mode
—
12
TAD
Note 2
40
—
µs
10*
—
—
µs
The minimum time is the amplifier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
132
TACQ Acquisition time
Q4 to A/D clock start
Units
Extended(LF)
TCNV Conversion time (not including S/H time)
(Note 1)
TGO
Max
Standard(F)
131
134
Typ†
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30221A-page 142
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
15.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified
VDD range). This is for information only and devices
are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’
represents (mean + 3σ) or (mean - 3σ) respectively,
where σ is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 143
PIC16F872
NOTES:
DS30221A-page 144
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
16.0
PACKAGING INFORMATION
16.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F872-I/SP
9910SAA
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F872-I/SO
YYWWNNN
9910SAA
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F872-I/SS
YYWWNNN
Legend: MM...M
XX...X
YY
WW
NNN
Note:
*
9910SAA
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 145
PIC16F872
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
A
c
A2
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
φ
B
α
β
MIN
.068
.064
.002
.299
.201
.396
.022
.004
0
.010
0
0
INCHES
NOM
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.319
.212
.407
.037
.010
8
.015
10
10
MILLIMETERS*
NOM
MAX
28
0.65
1.73
1.85
1.98
1.63
1.73
1.83
0.05
0.15
0.25
7.59
7.85
8.10
5.11
5.25
5.38
10.06
10.20
10.34
0.56
0.75
0.94
0.10
0.18
0.25
0.00
101.60
203.20
0.25
0.32
0.38
0
5
10
0
5
10
MIN
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS30221A-page 146
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
β
B1
A1
eB
Units
Number of Pins
Pitch
p
B
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
28
MAX
28
.100
2.54
Top to Seating Plane
A
.140
.150
.160
3.56
3.81
4.06
Molded Package Thickness
A2
.125
.130
.135
3.18
3.30
3.43
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.310
.325
7.62
7.87
8.26
Molded Package Width
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
D
1.345
1.365
1.385
34.16
34.67
35.18
Tip to Seating Plane
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
B1
.040
.053
.065
1.02
1.33
1.65
Lower Lead Width
B
.016
.019
.022
0.41
0.48
0.56
Overall Row Spacing
eB
α
.320
.350
.430
8.13
8.89
10.92
5
10
15
5
10
15
5
10
15
5
10
15
Lead Thickness
Upper Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0.38
*Controlling Parameter
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 147
PIC16F872
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
A1
MIN
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MIN
Number of Pins
Pitch
Overall Height
A
.093
.104
Molded Package Thickness
A2
.088
.094
Standoff
A1
.004
.012
Overall Width
E
.394
.420
Molded Package Width
E1
.288
.299
Overall Length
D
.695
.712
Chamfer Distance
h
.010
.029
Foot Length
L
.016
.050
φ
Foot Angle Top
0
8
c
Lead Thickness
.009
.013
Lead Width
B
.014
.020
α
Mold Draft Angle Top
0
15
β
Mold Draft Angle Bottom
0
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS30221A-page 148
Preliminary
MAX
2.64
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
0.33
0.51
15
15
 1999 Microchip Technology Inc.
PIC16F872
APPENDIX A:
REVISION HISTORY
Version
Date
Revision Description
A
1999
This is a new data sheet. However, these devices are similar to the PIC16C72A
devices found in the PIC16C62B/72A Data Sheet (DS35008A).
APPENDIX B:
CONVERSION CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table B-1.
TABLE B-1:
CONVERSION CONSIDERATIONS
Characteristic
PIC16C72A
PIC16F872
Pins
28
28
Timers
3
3
Interrupts
8
10
2C
Slave)
SSP (SPI, I2C Master/Slave)
Communication
SSP (SPI, I
Frequency
20 MHz
20 MHz
A/D
8-bit
10-bit
CCP
1
1
Program Memory
2K EPROM
2K FLASH
RAM
128 bytes
128 bytes
EEPROM data
None
64 bytes
Other

In-Circuit Debugger, Low Voltage Programming
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 149
PIC16F872
NOTES:
DS30221A-page 150
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
INDEX
A
A/D ..................................................................................... 85
ADCON0 Register ...................................................... 85
ADCON1 Register ...................................................... 86
ADIF bit ...................................................................... 87
Analog Input Model Block Diagram ............................ 89
Analog Port Pins .......................................................... 6
Block Diagram ............................................................ 88
Configuring Analog Port Pins ..................................... 90
Configuring the Interrupt ............................................ 87
Configuring the Module .............................................. 87
Conversion Clock ....................................................... 90
Conversions ............................................................... 91
Delays ........................................................................ 89
Effects of a Reset ....................................................... 92
GO/DONE bit ............................................................. 87
Internal Sampling Switch (Rss) Impedence ............... 88
Operation During Sleep ............................................. 92
Sampling Requirements ............................................. 88
Source Impedence ..................................................... 88
Time Delays ............................................................... 89
Absolute Maximum Ratings ............................................. 125
ACK .................................................................................... 62
Acknowledge Data bit ........................................................ 56
Acknowledge Pulse ............................................................ 62
Acknowledge Sequence Enable bit ................................... 56
Acknowledge Status bit ...................................................... 56
ADRES Register ............................................................ 9, 85
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." ............................... 61
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) .................................................... 25
AN556 (Table Reading Using PIC16CXX) ................. 20
Architecture
PIC16F872 Block Diagram .......................................... 5
Assembler
MPASM Assembler .................................................. 119
B
Banking, Data Memory .................................................. 7, 12
Baud Rate Generator ......................................................... 68
BCLIF ................................................................................. 18
BF .................................................................... 54, 62, 71, 73
Block Diagrams
A/D ............................................................................. 88
Analog Input Model .................................................... 89
Baud Rate Generator ................................................. 68
Capture ...................................................................... 48
Compare .................................................................... 49
I2C Master Mode ........................................................ 66
I2C Module ................................................................. 61
PWM .......................................................................... 49
SSP (I2C Mode) ......................................................... 61
SSP (SPI Mode) ......................................................... 57
Timer0/WDT Prescaler .............................................. 37
Timer2 ........................................................................ 45
BRG ................................................................................... 68
Brown-out Reset (BOR) ............................... 95, 99, 101, 102
BOR Status (BOR Bit) ................................................ 19
Buffer Full bit, BF ............................................................... 62
Buffer Full Status bit, BF .................................................... 54
Bus Arbitration ................................................................... 78
Bus Collision During a RESTART Condition ...................... 81
 1999 Microchip Technology Inc.
Bus Collision During a Start Condition ............................... 79
Bus Collision During a Stop Condition ............................... 82
Bus Collision Interrupt Flag bit, BCLIF ............................... 18
Bus Collision Section ......................................................... 78
C
Capture/Compare/PWM
Capture
Block Diagram ................................................... 48
CCP1CON Register ........................................... 47
CCP1IF .............................................................. 48
Mode ................................................................. 48
Prescaler ........................................................... 48
CCP Timer Resources ............................................... 47
Compare
Block Diagram ................................................... 49
Mode ................................................................. 49
Software Interrupt Mode .................................... 49
Special Event Trigger ........................................ 49
Special Trigger Output of CCP1 ........................ 49
Section ....................................................................... 47
Special Event Trigger and A/D Conversions ............. 49
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ..................................................... 6
PWM Block Diagram ................................................. 49
PWM Mode ................................................................ 49
CCP1CON ......................................................................... 11
CCP1M0 bit ....................................................................... 47
CCP1M1 bit ....................................................................... 47
CCP1M2 bit ....................................................................... 47
CCP1M3 bit ....................................................................... 47
CCP1X bit .......................................................................... 47
CCP1Y bit .......................................................................... 47
CCPR1H Register .................................................... 9, 11, 47
CCPR1L Register ........................................................ 11, 47
CKE ................................................................................... 54
CKP ................................................................................... 55
Clock Polarity Select bit, CKP ............................................ 55
Code Examples
Indirect Addressing .................................................... 20
Code Protection ......................................................... 95, 109
Computed GOTO ............................................................... 20
Configuration Bits .............................................................. 95
Conversion Considerations .............................................. 149
D
D/A ..................................................................................... 54
Data Memory ....................................................................... 7
Bank Select (RP1:RP0 Bits) .................................. 7, 12
General Purpose Registers ......................................... 7
Register File Map ........................................................ 8
Special Function Registers .......................................... 9
Data/Address bit, D/A ........................................................ 54
DC Characteristics ........................................................... 127
Development Support ...................................................... 119
Device Overview .................................................................. 5
Direct Addressing .............................................................. 21
E
Electrical Characteristics ................................................. 125
Errata ................................................................................... 3
F
Firmware Instructions ...................................................... 111
FSR Register ..................................................... 9, 10, 11, 20
DS30221A-page 151
PIC16F872
G
General Call Address Sequence ........................................ 64
General Call Address Support ........................................... 64
General Call Enable bit ...................................................... 56
I
I/O Ports ............................................................................. 23
I2C ...................................................................................... 61
I2C Master Mode Reception ............................................... 73
I2C Master Mode Restart Condition ................................... 70
I2C Mode Selection ............................................................ 61
I2C Module
Acknowledge Sequence timing .................................. 75
Addressing ................................................................. 62
Baud Rate Generator ................................................. 68
Block Diagram ............................................................ 66
BRG Block Diagram ................................................... 68
BRG Reset due to SDA Collision ............................... 80
BRG Timing ............................................................... 68
Bus Arbitration ........................................................... 78
Bus Collision .............................................................. 78
Acknowledge ...................................................... 78
Restart Condition ............................................... 81
Restart Condition Timing (Case1) ...................... 81
Restart Condition Timing (Case2) ...................... 81
Start Condition ................................................... 79
Start Condition Timing ................................. 79, 80
Stop Condition ................................................... 82
Stop Condition Timing (Case1) .......................... 82
Stop Condition Timing (Case2) .......................... 82
Transmit Timing ................................................. 78
Bus Collision timing .................................................... 78
Clock Arbitration ......................................................... 77
Clock Arbitration Timing (Master Transmit) ................ 77
Conditions to not give ACK Pulse .............................. 62
General Call Address Support ................................... 64
Master Mode .............................................................. 66
Master Mode 7-bit Reception timing .......................... 74
Master Mode Operation ............................................. 67
Master Mode Start Condition ..................................... 69
Master Mode Transmission ........................................ 71
Master Mode Transmit Sequence .............................. 67
Multi-Master Communication ..................................... 78
Multi-master Mode ..................................................... 67
Operation ................................................................... 61
Repeat Start Condition timing .................................... 70
Slave Mode ................................................................ 62
Slave Reception ......................................................... 63
Slave Transmission .................................................... 63
SSPBUF ..................................................................... 62
Stop Condition Receive or Transmit timing ................ 76
Stop Condition timing ................................................. 76
Waveforms for 7-bit Reception .................................. 63
Waveforms for 7-bit Transmission ............................. 64
I2C Module Address Register, SSPADD ............................ 62
I2C Slave Mode .................................................................. 62
ID Locations ............................................................... 95, 109
In-Circuit Serial Programming (ICSP) ........................ 95, 110
INDF ................................................................................... 11
INDF Register .......................................................... 9, 10, 20
Indirect Addressing ...................................................... 20, 21
FSR Register ............................................................... 7
Instruction Format ............................................................ 111
DS30221A-page 152
Instruction Set .................................................................. 111
ADDLW .................................................................... 113
ADDWF .................................................................... 113
ANDLW .................................................................... 113
ANDWF .................................................................... 113
BCF ......................................................................... 113
BSF .......................................................................... 113
BTFSC ..................................................................... 114
BTFSS ..................................................................... 114
CALL ........................................................................ 114
CLRF ....................................................................... 114
CLRW ...................................................................... 114
CLRWDT ................................................................. 114
COMF ...................................................................... 115
DECF ....................................................................... 115
DECFSZ .................................................................. 115
GOTO ...................................................................... 115
INCF ........................................................................ 115
INCFSZ .................................................................... 115
IORLW ..................................................................... 116
IORWF ..................................................................... 116
MOVF ...................................................................... 116
MOVLW ................................................................... 116
MOVWF ................................................................... 116
NOP ......................................................................... 116
RETFIE .................................................................... 117
RETLW .................................................................... 117
RETURN .................................................................. 117
RLF .......................................................................... 117
RRF ......................................................................... 117
SLEEP ..................................................................... 117
SUBLW .................................................................... 118
SUBWF .................................................................... 118
SWAPF .................................................................... 118
XORLW ................................................................... 118
XORWF ................................................................... 118
Summary Table ....................................................... 112
INTCON ............................................................................. 11
INTCON Register ............................................................... 14
GIE Bit ....................................................................... 14
INTE Bit ..................................................................... 14
INTF Bit ..................................................................... 14
PEIE Bit ..................................................................... 14
RBIE Bit ..................................................................... 14
RBIF Bit ............................................................... 14, 25
T0IE Bit ...................................................................... 14
T0IF Bit ...................................................................... 14
Inter-Integrated Circuit (I2C) .............................................. 53
Internal Sampling Switch (Rss) Impedence ....................... 88
Interrupt Sources ....................................................... 95, 105
Block Diagram ......................................................... 105
Interrupt on Change (RB7:RB4 ) ............................... 25
RB0/INT Pin, External .......................................... 6, 106
TMR0 Overflow ........................................................ 106
Interrupts
Bus Collision Interrupt ................................................ 18
Synchronous Serial Port Interrupt .............................. 16
Interrupts, Context Saving During .................................... 106
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ....................... 14, 105
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 14, 106
Peripheral Interrupt Enable (PEIE Bit) ....................... 14
RB0/INT Enable (INTE Bit) ........................................ 14
TMR0 Overflow Enable (T0IE Bit) ............................. 14
 1999 Microchip Technology Inc.
PIC16F872
Interrupts, Flag Bits
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) ..................................................... 14, 25, 106
RB0/INT Flag (INTF Bit) ............................................. 14
TMR0 Overflow Flag (T0IF Bit) .......................... 14, 106
K
KeeLoq Evaluation and Programming Tools ................. 122
L
Loading of PC .................................................................... 20
M
Master Clear (MCLR) ........................................................... 6
MCLR Reset, Normal Operation ................ 99, 101, 102
MCLR Reset, SLEEP ................................. 99, 101, 102
Memory Organization
Data Memory ............................................................... 7
Program Memory ......................................................... 7
MPLAB Integrated Development Environment Software . 119
Multi-Master Communication ............................................. 78
Multi-Master Mode ............................................................. 67
O
OPCODE Field Descriptions ............................................ 111
OPTION ............................................................................. 11
OPTION_REG Register ..................................................... 13
INTEDG Bit ................................................................ 13
PS2:PS0 Bits ............................................................. 13
PSA Bit ....................................................................... 13
RBPU Bit .................................................................... 13
T0CS Bit ..................................................................... 13
T0SE Bit ..................................................................... 13
OSC1/CLKIN Pin ................................................................. 6
OSC2/CLKOUT Pin ............................................................. 6
Oscillator Configuration ................................................ 95, 97
HS ...................................................................... 97, 101
LP ....................................................................... 97, 101
RC ................................................................ 97, 98, 101
XT ...................................................................... 97, 101
Oscillator, WDT ................................................................ 107
Output of TMR2 ................................................................. 45
P
P (Stop bit) ......................................................................... 54
Packaging ........................................................................ 145
Paging, Program Memory .............................................. 7, 20
PCL Register ...................................................... 9, 10, 11, 20
PCLATH Register .............................................. 9, 10, 11, 20
PCON Register .................................................... 11, 19, 100
BOR Bit ...................................................................... 19
POR Bit ...................................................................... 19
PICDEM-1 Low-Cost PICmicro Demo Board ................... 121
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 121
PICDEM-3 Low-Cost PIC16CXXX Demo Board .............. 121
PICSTART Plus Entry Level Development System ...... 121
PIE1 Register ............................................................... 11, 15
PIE2 Register ............................................................... 11, 17
Pinout Descriptions
PIC16F872 ................................................................... 6
PIR1 Register ..................................................................... 16
PIR2 Register ..................................................................... 18
POP ................................................................................... 20
 1999 Microchip Technology Inc.
PORTA .......................................................................... 6, 11
Analog Port Pins .......................................................... 6
Initialization ................................................................ 23
PORTA Register ........................................................ 23
RA3, RA0 and RA5 Port Pins .................................... 23
RA4/T0CKI Pin ...................................................... 6, 23
RA5/SS/AN4 Pin .......................................................... 6
TRISA Register .......................................................... 23
PORTA Register .................................................................. 9
PORTB .......................................................................... 6, 11
PORTB Register ........................................................ 25
Pull-up Enable (RBPU Bit) ......................................... 13
RB0/INT Edge Select (INTEDG Bit) .......................... 13
RB0/INT Pin, External ......................................... 6, 106
RB3:RB0 Port Pins .................................................... 25
RB7:RB4 Interrupt on Change ................................. 106
RB7:RB4 Interrupt on Change Enable
(RBIE Bit) ........................................................... 14, 106
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) ..................................................... 14, 25, 106
RB7:RB4 Port Pins .................................................... 25
TRISB Register .......................................................... 25
PORTB Register .................................................................. 9
PORTC .......................................................................... 6, 11
Block Diagram ........................................................... 27
PORTC Register ........................................................ 27
RC0/T1OSO/T1CKI Pin ............................................... 6
RC1/T1OSI Pin ............................................................ 6
RC2/CCP1 Pin ............................................................. 6
RC3/SCK/SCL Pin ....................................................... 6
RC4/SDI/SDA Pin ........................................................ 6
RC5/SDO Pin .............................................................. 6
RC6 Pin ....................................................................... 6
RC7 Pin ....................................................................... 6
TRISC Register ......................................................... 27
PORTC Register .................................................................. 9
Postscaler, WDT
Assignment (PSA Bit) ................................................ 13
Rate Select (PS2:PS0 Bits) ....................................... 13
Power-on Reset (POR) ........................ 95, 99, 100, 101, 102
Oscillator Start-up Timer (OST) ......................... 95, 100
POR Status (POR Bit) ............................................... 19
Power Control (PCON) Register .............................. 100
Power-down (PD Bit) ........................................... 12, 99
Power-up Timer (PWRT) ................................... 95, 100
Time-out (TO Bit) ................................................. 12, 99
Time-out Sequence on Power-up .................... 103, 104
PR2 .................................................................................... 11
PR2 Register ............................................................... 10, 45
Prescaler, Timer0
Assignment (PSA Bit) ................................................ 13
Rate Select (PS2:PS0 Bits) ....................................... 13
PRO MATE II Universal Programmer ........................... 121
Product Identification System .......................................... 158
Program Counter
Reset Conditions ..................................................... 101
Program Memory ................................................................. 7
Interrupt Vector ............................................................ 7
Paging ................................................................... 7, 20
Program Memory Map ................................................. 7
Reset Vector ................................................................ 7
Program Verification ........................................................ 109
Programming Pin (VPP) ....................................................... 6
Programming, Device Instructions ................................... 111
PUSH ................................................................................. 20
DS30221A-page 153
PIC16F872
R
R/W .................................................................................... 54
R/W bit ............................................................................... 62
R/W bit ............................................................................... 63
Read/Write bit, R/W ........................................................... 54
Receive Enable bit ............................................................. 56
Receive Overflow Indicator bit, SSPOV ............................. 55
Register File ......................................................................... 7
Register File Map ................................................................. 8
Registers
FSR Summary ........................................................... 11
INDF Summary .......................................................... 11
INTCON Summary ..................................................... 11
OPTION Summary ..................................................... 11
PCL Summary ............................................................ 11
PCLATH Summary .................................................... 11
PORTB Summary ...................................................... 11
SSPSTAT ................................................................... 54
STATUS Summary .................................................... 11
Summary ...................................................................... 9
TMR0 Summary ......................................................... 11
TRISB Summary ........................................................ 11
Reset ............................................................................ 95, 99
Block Diagram ............................................................ 99
Reset Conditions for All Registers ........................... 102
Reset Conditions for PCON Register ....................... 101
Reset Conditions for Program Counter .................... 101
Reset Conditions for STATUS Register ................... 101
Restart Condition Enabled bit ............................................ 56
Revision History ............................................................... 149
S
S (Start bit) ......................................................................... 54
SCK .................................................................................... 57
SCL .................................................................................... 62
SDA .................................................................................... 62
SDI ..................................................................................... 57
SDO ................................................................................... 57
SEEVAL Evaluation and Programming System ............ 122
Serial Clock, SCK ............................................................... 57
Serial Clock, SCL ............................................................... 62
Serial Data Address, SDA .................................................. 62
Serial Data In, SDI ............................................................. 57
Serial Data Out, SDO ......................................................... 57
Slave Select, SS ................................................................ 57
SLEEP .................................................................. 95, 99, 108
SMP ................................................................................... 54
Software Simulator (MPLAB-SIM) .................................... 120
Special Features of the CPU .............................................. 95
Special Function Registers .................................................. 9
Speed, Operating ................................................................. 1
SPI
Master Mode .............................................................. 58
Master Mode Timing .................................................. 58
Serial Clock ................................................................ 57
Serial Data In ............................................................. 57
Serial Data Out .......................................................... 57
Serial Peripheral Interface (SPI) ................................ 53
Slave Mode Timing .................................................... 59
Slave Mode Timing Diagram ...................................... 59
Slave Select ............................................................... 57
SPI clock .................................................................... 58
SPI Mode ................................................................... 57
SPI Clock Edge Select, CKE .............................................. 54
SPI Data Input Sample Phase Select, SMP ....................... 54
DS30221A-page 154
SPI Module
Slave Mode ................................................................ 59
SS ...................................................................................... 57
SSP .................................................................................... 53
Block Diagram (SPI Mode) ........................................ 57
RA5/SS/AN4 Pin .......................................................... 6
RC3/SCK/SCL Pin ....................................................... 6
RC4/SDI/SDA Pin ........................................................ 6
RC5/SDO Pin ............................................................... 6
SPI Mode ................................................................... 57
SSPADD .................................................................... 62
SSPBUF .............................................................. 58, 62
SSPCON1 ................................................................. 55
SSPCON2 ................................................................. 56
SSPSR ................................................................ 58, 62
SSPSTAT ............................................................ 54, 62
SSP I2C
SSP I2C Operation .................................................... 61
SSP Module
SPI Master Mode ....................................................... 58
SPI Slave Mode ......................................................... 59
SSPCON1 Register ................................................... 61
SSP Overflow Detect bit, SSPOV ...................................... 62
SSPADD Register ........................................................ 10, 11
SSPBUF ...................................................................... 11, 62
SSPBUF Register ................................................................ 9
SSPCON Register ............................................................... 9
SSPCON1 .................................................................... 55, 61
SSPCON2 .......................................................................... 56
SSPEN ............................................................................... 55
SSPIF .......................................................................... 16, 63
SSPM3:SSPM0 ................................................................. 55
SSPOV .................................................................. 55, 62, 73
SSPSTAT .............................................................. 11, 54, 62
SSPSTAT Register ............................................................ 10
Stack .................................................................................. 20
Overflows ................................................................... 20
Underflow .................................................................. 20
Start bit (S) ......................................................................... 54
Start Condition Enabled bit ................................................ 56
STATUS Register ........................................................ 11, 12
C Bit ........................................................................... 12
DC Bit ........................................................................ 12
IRP Bit ....................................................................... 12
PD Bit .................................................................. 12, 99
RP1:RP0 Bits ............................................................. 12
TO Bit .................................................................. 12, 99
Z Bit ........................................................................... 12
Stop bit (P) ......................................................................... 54
Stop Condition Enable bit .................................................. 56
Synchronous Serial Port .................................................... 53
Synchronous Serial Port Enable bit, SSPEN ..................... 55
Synchronous Serial Port Interrupt ...................................... 16
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ................................................................. 55
T
T1CKPS0 bit ...................................................................... 41
T1CKPS1 bit ...................................................................... 41
T1CON ............................................................................... 11
T1CON Register .......................................................... 11, 41
T1OSCEN bit ..................................................................... 41
T1SYNC bit ........................................................................ 41
T2CKPS0 bit ...................................................................... 45
T2CKPS1 bit ...................................................................... 45
T2CON Register .......................................................... 11, 45
 1999 Microchip Technology Inc.
PIC16F872
TAD ..................................................................................... 90
Timer0
Clock Source Edge Select (T0SE Bit) ........................ 13
Clock Source Select (T0CS Bit) ................................. 13
Overflow Enable (T0IE Bit) ........................................ 14
Overflow Flag (T0IF Bit) ..................................... 14, 106
Overflow Interrupt .................................................... 106
RA4/T0CKI Pin, External Clock ................................... 6
Timer1 ................................................................................ 41
RC0/T1OSO/T1CKI Pin ............................................... 6
RC1/T1OSI Pin ............................................................ 6
Timers
Timer0
External Clock .................................................... 38
Interrupt ............................................................. 37
Prescaler ............................................................ 38
Prescaler Block Diagram ................................... 37
Section ............................................................... 37
T0CKI ................................................................. 38
Timer1
Asynchronous Counter Mode ............................ 43
Capacitor Selection ............................................ 43
Operation in Timer Mode ................................... 42
Oscillator ............................................................ 43
Prescaler ............................................................ 43
Resetting of Timer1 Registers ........................... 43
Resetting Timer1 using a CCP Trigger Output .. 43
Synchronized Counter Mode ............................. 42
T1CON ............................................................... 41
TMR1H .............................................................. 43
TMR1L ............................................................... 43
Timer2
Block Diagram ................................................... 45
Postscaler .......................................................... 45
Prescaler ............................................................ 45
T2CON ............................................................... 45
Timing Diagrams
A/D Conversion ........................................................ 142
Acknowledge Sequence Timing ................................. 75
Baud Rate Generator with Clock Arbitration .............. 68
BRG Reset Due to SDA Collision .............................. 80
Brown-out Reset ...................................................... 134
Bus Collision
Start Condition Timing ....................................... 79
Bus Collision During a Restart Condition (Case 1) .... 81
Bus Collision During a Restart Condition (Case2) ..... 81
Bus Collision During a Start Condition (SCL = 0) ...... 80
Bus Collision During a Stop Condition ....................... 82
Bus Collision for Transmit and Acknowledge ............. 78
Capture/Compare/PWM ........................................... 136
CLKOUT and I/O ...................................................... 133
I2C Bus Data ............................................................ 140
I2C Bus Start/Stop bits ............................................. 139
I2C Master Mode First Start bit timing ........................ 69
I2C Master Mode Reception timing ............................ 74
I2C Master Mode Transmission timing ....................... 72
Master Mode Transmit Clock Arbitration .................... 77
Power-up Timer ....................................................... 134
Repeat Start Condition ............................................... 70
Reset ........................................................................ 134
SPI Master Mode ....................................................... 58
SPI Slave Mode (CKE = 1) ........................................ 59
SPI Slave Mode Timing (CKE = 0) ............................ 59
Start-up Timer .......................................................... 134
Stop Condition Receive or Transmit .......................... 76
Time-out Sequence on Power-up .................... 103, 104
 1999 Microchip Technology Inc.
Timer0 ..................................................................... 135
Timer1 ..................................................................... 135
Wake-up from SLEEP via Interrupt ......................... 109
Watchdog Timer ...................................................... 134
TMR0 ................................................................................. 11
TMR0 Register ..................................................................... 9
TMR1CS bit ....................................................................... 41
TMR1H .............................................................................. 11
TMR1H Register .................................................................. 9
TMR1L ............................................................................... 11
TMR1L Register ................................................................... 9
TMR1ON bit ....................................................................... 41
TMR2 ................................................................................. 11
TMR2 Register ..................................................................... 9
TMR2ON bit ....................................................................... 45
TOUTPS0 bit ..................................................................... 45
TOUTPS1 bit ..................................................................... 45
TOUTPS2 bit ..................................................................... 45
TOUTPS3 bit ..................................................................... 45
TRISA ................................................................................ 11
TRISA Register .................................................................. 10
TRISB ................................................................................ 11
TRISB Register .................................................................. 10
TRISC ................................................................................ 11
TRISC Register .................................................................. 10
U
UA ...................................................................................... 54
Update Address, UA .......................................................... 54
W
Wake-up from SLEEP ................................................ 95, 108
Interrupts ......................................................... 101, 102
MCLR Reset ............................................................ 102
Timing Diagram ....................................................... 109
WDT Reset .............................................................. 102
Watchdog Timer (WDT) ............................................. 95, 107
Block Diagram ......................................................... 107
Enable (WDTE Bit) .................................................. 107
Programming Considerations .................................. 107
RC Oscillator ........................................................... 107
Time-out Period ....................................................... 107
WDT Reset, Normal Operation .................. 99, 101, 102
WDT Reset, SLEEP .................................. 99, 101, 102
Waveform for General Call Address Sequence ................. 64
WCOL .................................................. 55, 69, 71, 73, 75, 76
WCOL Status Flag ............................................................. 69
Write Collision Detect bit, WCOL ....................................... 55
WWW, On-Line Support ...................................................... 3
DS30221A-page 155
PIC16F872
NOTES:
DS30221A-page 156
 1999 Microchip Technology Inc.
PIC16F872
ON-LINE SUPPORT
Systems Information and Upgrade Hot Line
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events
 1999 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are
registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM and
fuzzyLAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
Preliminary
DS30221A-page 157
PIC16F872
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16F872
Y
N
Literature Number: DS30221A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30221A-page 158
Preliminary
 1999 Microchip Technology Inc.
PIC16F872
PIC16F872 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC16F872, PIC16F872T;VDD range 4.0V to 5.5V
PIC16LF872, PIC16LF872T;VDD range 2.0V to 5.5V
F
LF
T
= CMOS FLASH
= Low Power CMOS FLASH
= in tape and reel - SOIC, SSOP,
packages only.
Temperature Range
blank
I
=
0°C to
= -40°C to
Package
SO
SP
SS
=
=
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
70°C
+85°C
c)
d)
PIC16F872-I/SP 301 = Industrial temp., PDIP
package, 20MHz, normal VDD limits, QTP pattern #301.
PIC16F872-I/SO = Industrial temp., SOIC
package, 20 MHz, normal VDD limits.
PIC16F872/P = Industrial temp., PDIP package, 10MHz, normal VDD limits.
PIC16LF872-I/SS = Industrial temp., SSOP
package, DC - 20MHz, extended VDD limits.
(Commercial)
(Industrial)
SOIC
Skinny plastic dip
SSOP
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 159
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
ASIA/PACIFIC
Hong Kong
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
India
Denmark
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Korea
Germany
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 12/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30221A-page 160
 1999 Microchip Technology Inc.