24LCS21A 1K 2.5V Dual Mode I2C Serial EEPROM FEATURES PACKAGE TYPES PDIP 8 VCC 7 VCLK 6 SCL 4 5 SDA NC 1 8 VCC NC 2 7 VCLK WP 3 6 SCL VSS 4 5 SDA NC 1 NC 2 WP 3 VSS 24LCS21A • Single supply with operation down to 2.5V • Completely implements DDC1/DDC2 interface for monitor identification, including recovery to DDC1 • Low power CMOS technology - 1 mA typical active current - 10 µA standby current typical at 5.5V • 2-wire serial interface bus, I2C compatible • 100 kHz (2.5V) and 400 kHz (5V) compatibility • Self-timed write cycle (including auto-erase) • Hardware write-protect pin • Page-write buffer for up to eight bytes • 10,000,000 erase/write cycles guaranteed • Data retention > 200 years • ESD Protection > 4000V • 8-pin PDIP and SOIC package • Available for extended temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +70°C SOIC 24LCS21A DESCRIPTION The Microchip Technology Inc. 24LCS21A is a 128 x 8bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-Only Mode and Bi-directional Mode. Upon power-up, the device will be in the Transmit-Only Mode, sending a serial bit stream of the memory array from 00h to 7Fh, clocked by the VCLK pin. A valid high to low transition on the SCL pin will cause the device to enter the transition mode, and look for a valid control byte on the I2C bus. If it detects a valid control byte from the master, it will switch into Bi-directional Mode, with byte selectable read/write capability of the memory array using SCL. If no control byte is received, the device will revert to the Transmit-Only Mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LCS21A also enables the user to write-protect the entire memory array using its writeprotect pin. The 24LCS21A is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges. BLOCK DIAGRAM WP HV GENERATOR I/O CONTROL LOGIC MEMORY CONTROL LOGIC XDEC EEPROM ARRAY PAGE LATCHES SDA SCL YDEC VCLK VCC SENSE AMP R/W CONTROL VSS DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation. 1996 Microchip Technology Inc. Preliminary This document was created with FrameMaker 4 0 4 DS21161C-page 1 24LCS21A 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name VCC ........................................................................7.0V All inputs and outputs w.r.t. VSS .... -0.6V to VCC +1.0V Storage temperature ..........................-65°C to +150°C Ambient temp. with power applied .....-65°C to +125°C Soldering temperature of leads (10 seconds) .. +300°C ESD protection on all pins ..................................... ≥ 4 kV Function WP Write Protect (active low) VSS Ground SDA Serial Address/Data I/O SCL Serial Clock (Bi-directional Mode) VCLK Serial Clock (Transmit-Only Mode) VCC +2.5V to 5.5V Power Supply NC No Connection *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE DC CHARACTERISTICS VCC = +2.5V to 5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb =-40°C to +85°C Parameter Symbol Min Max Units SCL and SDA pins: High level input voltage Low level input voltage VIH VIL 0.7 VCC — — 0.3 VCC V V Input levels on VCLK pin: High level input voltage Low level input voltage VIH VIL 2.0 — — 0.2 VCC V V VCC ≥ 2.7V (Note) VCC < 2.7V (Note) Hysteresis of Schmitt trigger inputs VHYS .05 VCC — V (Note) Low level output voltage VOL1 — 0.4 V IOL = 3 mA, VCC = 2.5V (Note) Low level output voltage VOL2 — 0.6 V IOL = 6 mA, VCC = 2.5V Input leakage current ILI -10 10 µA VIN = 0.1V to VCC Output leakage current ILO -10 10 µA VOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) Cin, Cout — 10 pF VCC = 5.0V (Note) Tamb = 25°C, FCLK = 1 MHz Operating current ICC Write ICC Read — — 3 1 mA mA VCC = 5.5V VCC = 5.5V, SCL = 400 kHz ICCS — — 30 100 µA µA VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC Standby current Note: Conditions This parameter is periodically sampled and not 100% tested. DS21161C-page 2 Preliminary 1996 Microchip Technology Inc. 24LCS21A TABLE 1-3: AC CHARACTERISTICS Parameter Symbol Vcc= 2.5-4.5V Standard Mode Vcc= 4.5 - 5.5V Fast Mode Min Max Min Max Units Clock frequency Clock high time Clock low time SDA and SCL rise time FCLK THIGH TLOW TR — 4000 4700 — 100 — — 1000 — 600 1300 — 400 — — 300 kHz ns ns ns SDA and SCL fall time TF — 300 — 300 ns START condition hold time THD:STA 4000 — 600 — ns START condition setup time Data input hold time 4700 — 600 — ns TSU:STA THD:DAT Remarks (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition 0 — 0 — ns Data input setup time TSU:DAT STOP condition setup time TSU:STO Output valid from clock TAA 250 4000 — — — 3500 100 600 — — — 900 ns ns ns Bus free time 4700 — 1300 — ns (Note 2) Time the bus must be free before a new transmission can start — 250 250 ns (Note 1), CB ≤ 100 pF — 50 20 + 0.1 CB — 50 ns (Note 3) — 10 — 10 ms Byte or Page mode — 4000 4700 0 4000 — 0 2000 — — — — 1000 — — 600 1300 0 600 — 0 1000 — — — — 500 — ns ns ns ns ns ns ns — 100 — 100 ns 10M — 10M — cycles TBUF Output fall time from VIH TOF minimum to VIL maximum Input filter spike suppresTSP sion (SDA and SCL pins) Write cycle time TWR Transmit-Only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW VCLK setup time TVHST VCLK hold time TSPVL Mode transition time TVHZ Transmit-Only power up TVPU time Input filter spike suppresTSPV sion (VCLK pin) Endurance — (Note 2) 25°C, Vcc = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. 1996 Microchip Technology Inc. Preliminary DS21161C-page 3 24LCS21A 2.0 FUNCTIONAL DESCRIPTION mit-Only Mode (Section 2.2). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit-Only Mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted most significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. The Bi-directional Mode Clock (SCL) pin must be held high for the device to remain in the Transmit-Only Mode. The 24LCS21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-Only Mode and the Bi-directional Mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high to low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional Mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bi-directional Mode. Otherwise, it will revert to the Transmit-Only Mode after it sees 128 VCLK pulses. 2.1 2.2 After VCC has stabilized, the device will be in the Transmit-Only Mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit in address 00h. (Figure 2-2). Transmit-Only Mode The device will power up in the Transmit-Only Mode at address 00H. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Trans- FIGURE 2-1: Initialization Procedure TRANSMIT-ONLY MODE SCL Tvaa Tvaa SDA Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7 VCLK Tvhigh Tvlow FIGURE 2-2: DEVICE INITIALIZATION Vcc SCL SDA Tvaa High Impedance for 9 clock cycles Tvaa Bit 8 Bit 7 Tvpu VCLK DS21161C-page 4 1 2 8 Preliminary 9 10 11 1996 Microchip Technology Inc. 24LCS21A 3.0 BI-DIRECTIONAL MODE Once the device has switched into the Bi-directional Mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bi-directional data transmission protocol (I2C). In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bi-directional Mode Clock (SCL), controls access to the bus and generates the START and STOP conditions, while the 24LCS21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In the Bi-directional mode, the 24LCS21A only responds to commands for device 1010 000X. Before the 24LCS21A can be switched into the Bidirectional Mode (Figure 3-1), it must enter the transition mode, which is done by applying a valid high to low transition on the Bi-directional Mode Clock (SCL). As soon it enters the transition mode, it looks for a control byte 1010 000X on the I2C bus, and starts to count pulses on VCLK. Any high to low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-Only Mode, and transmit its contents starting with the most significant bit in address 00h. However, if it detects the control byte on the I2C bus, (Figure 3-2) it will switch to the in the Bi-directional Mode. Once the device has made the transition to the Bi-directional mode, the only way to switch the device back to the Transmit-Only Mode is to remove power from the device. The mode transition process is shown in detail in Figure 3-3. FIGURE 3-1: MODE MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE Transmit Only Recovery to Transmit-Only Mode Bi-directional TVHZ SCL (MSB of data in 00h) Bit8 SDA VCLK count = VCLK FIGURE 3-2: 1 2 3 4 127 128 SUCCESSFUL MODE TRANSITION TO BI-DIRECTIONAL MODE Transmit Only Mode Transition Mode with possibility to return to Transmit-Only Mode Bi-directional permanently MODE SCL SDA VCLK count = VCLK S 1 2 n 1 0 1 0 0 0 0 0 ACK 0 n < 128 1996 Microchip Technology Inc. Preliminary DS21161C-page 5 24LCS21A FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA The 24LCS21A was designed to comply to the portion of flowchart inside dash box Display Power-on or DDC Circuit Powered from +5 volts Communication is idle Is Vsync present? No Yes High to low transition on SCL? Send EDID continuously using Vsync as clock No Yes High to low transition on SCL? No Yes Stop sending EDID. Switch to DDC2 mode. Display has optional transition state ? DDC2 communication idle. Display waiting for address byte. No DDC2B address received? Yes Set Vsync counter = 0 or start timer Yes Receive DDC2B command No Reset counter or timer Respond to DDC2B command Change on SCL, SDA or VCLK lines? No Yes No Is display Access.busTM capable? High - low transition on SCL ? Yes Yes Reset Vsync counter = 0 Valid DDC2 address received? No Valid Access.bus address? No Yes Yes No No VCLK cycle? See Access.bus specification to determine correct procedure. Yes Increment VCLK counter (if appropriate) No Counter=128 or timer expired? Yes Switch back to DDC1 mode. Note 1: The base flowchart is copyright 1993, 1994, 1995 Video Electronic Standard Association (VESA) from VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology, Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A. DS21161C-page 6 Preliminary 1996 Microchip Technology Inc. 24LCS21A 3.1 Bi-directional Mode Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-4). 3.1.1 START DATA TRANSFER (B) STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 3.1.4 3.1.5 Note: A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.1.3 Note: Once switched into Bi-directional Mode, the 24LCS21A will remain in that mode until power is removed. Removing power is the only way to reset the 24LCS21A into the Transmit-only mode. ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. BUS NOT BUSY (A) Both data and clock lines remain HIGH. 3.1.2 STOP conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The 24LCS21A does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and FIGURE 3-4: DSCL or MSCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) DSCL or MSCL 1996 Microchip Technology Inc. DATA ALLOWED TO CHANGE Preliminary STOP CONDITION DS21161C-page 7 24LCS21A FIGURE 3-5: BUS TIMING START/STOP SCL VHYS THD:STA TSU:STO TSU:STA SDA START FIGURE 3-6: STOP BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TBUF TAA TAA SDA OUT 3.1.6 FIGURE 3-7: SLAVE ADDRESS After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24LCS21A. START The eighth bit of slave address determines whether the master device wants to read or write to the 24LCS21A (Figure 3-7). The 24LCS21A monitors the bus for its corresponding slave address continuously. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. Operation Slave Address R/W Read Write 1010000 1010000 1 0 DS21161C-page 8 Preliminary CONTROL BYTE ALLOCATION READ/WRITE R/W SLAVE ADDRESS 1 0 1 0 0 0 A 0 1996 Microchip Technology Inc. 24LCS21A 4.0 WRITE OPERATION 4.2 4.1 Byte Write The write control byte, word address and the first data byte are transmitted to the 24LCS21A in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24LCS21A which are temporarily stored in the onchip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 5-2). Following the start signal from the master, the slave address (four bits), three zero bits (000) and the R/W bit which is a logic low are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LCS21A. After receiving another acknowledge signal from the 24LCS21A the master device will transmit the data word to be written into the addressed memory location. The 24LCS21A acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LCS21A will not generate acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high to low during the self-timed program operation will not halt programming of the device. It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high to low during the self-timed program operation will not halt programming of the device. FIGURE 4-1: Page Write BYTE WRITE BUS ACTIVITY MASTER SDA LINE S T A R T WORD ADDRESS CONTROL BYTE S T O P DATA S P A C K A C K BUS ACTIVITY A C K VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL THD:STA SDA IN TSU:STO VCLK TVHST 1996 Microchip Technology Inc. TSPVL Preliminary DS21161C-page 9 24LCS21A 5.0 ACKNOWLEDGE POLLING FIGURE 5-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for the flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation FIGURE 5-2: PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S BUS ACTIVITY WORD ADDRESS (1) CONTROL BYTE DATA n + 7 DATA n + 1 DATA (n) S T O P P A C K A C K A C K A C K A C K VCLK DS21161C-page 10 Preliminary 1996 Microchip Technology Inc. 24LCS21A 6.0 WRITE PROTECTION 7.0 When using the 24LCS21A in the Bi-directional Mode, the VCLK pin can be used as a write protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LCS21A to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-Only Mode. Additionally, Pin three performs a flexible write protect function. The 24LCS21A contains a write-protection control fuse whose factory default state is cleared. Writing any data to address 7Fh (normally the checksum in DDC applications) sets the fuse which enables the WP pin. Until this fuse is set, the 24LCS21A is always write enabled (if VCLK = 1). After the fuse is set, the write capability of the 24LCS21A is determined by both VCLK and WP pins (Table 6-1). TABLE 6-1: VCLK 0 1 1 1 WRITE PROTECT TRUTH TABLE WP X X 1/open 0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. 7.1 Current Address Read The 24LCS21A contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LCS21A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LCS21A discontinues transmission (Figure 7-1). FIGURE 7-1: Address 7Fh Written Mode for 00h - 7Fh X No X Yes Read Only R/W R/W Read Only BUS ACTIVITY MASTER SDA LINE CURRENT ADDRESS READ S T A R T CONTROL BYTE DATA n S10100001 BUS ACTIVITY 7.2 S T O P P A C K N O A C K Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LCS21A as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LCS21A will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LCS21A discontinues transmission (Figure 7-2). 1996 Microchip Technology Inc. Preliminary DS21161C-page 11 24LCS21A FIGURE 7-2: RANDOM READ S T A R T BUS ACTIVITY MASTER SDA LINE CONTROL BYTE WORD ADDRESS (n) S 1 0 1 0 0 0 0 0 CONTROL BYTE S T O P DATA n S 1 0 1 0 0 0 0 1 A C K BUS ACTIVITY FIGURE 7-3: S T A R T A C K P N O A C K A C K SEQUENTIAL READ BUS ACTIVITY MASTER DATA n CONTROL BYTE DATA n+2 DATA n+1 S T O P DATA n+X P SDA LINE BUS ACTIVITY 7.3 A C K A C K A C K Sequential Read To provide sequential reads the 24LCS21A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. Noise Protection The 24LCS21A employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SDA, SCL and VCLK inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS21161C-page 12 N O A C K Sequential reads are initiated in the same way as a random read except that after the 24LCS21A transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LCS21A to transmit the next sequentially addressed 8-bit word (Figure 7-3). 7.4 A C K 8.0 PIN DESCRIPTIONS 8.1 SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bi-directional Mode. In the Transmit-Only Mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10 KΩ for 100 kHz, 1 KΩ for 400 kHz). For normal data transfer in the Bi-directional Mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 8.2 SCL This pin is the clock input for the Bi-directional Mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-Only Mode to the Bi-directional Mode. It must remain high for the chip to continue operation in the Transmit-Only Mode. Preliminary 1996 Microchip Technology Inc. 24LCS21A 8.3 VCLK This pin is the clock input for the Transmit-Only Mode (DDC1). In the Transmit-Only Mode, each bit is clocked out on the rising edge of this signal. In the Bi-directional Mode, a high logic level is required on this pin to enable write capability. 8.4 WP This pin is used for flexible write protection of the 24LCS21A. When the last memory location (7Fh) is written with any data, this pin is enabled and determines the write capability of the 24LCS21A (Table 6-1). The WP pin has an internal pull up resistor which will allow write capability (assuming VCLK = 1) at all times if this pin is floated. 1996 Microchip Technology Inc. Preliminary DS21161C-page 13 24LCS21A NOTES: DS21161C-page 14 Preliminary 1996 Microchip Technology Inc. 24LCS21A 24LCS21A Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 24LCS21A - /P Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead Temperature Range: Device: Blank = 24LCS21A 24LCS21AT 1996 Microchip Technology Inc. 0°C to +70°C I = -40°C to +85°C Dual Mode I2C Serial EEPROM Dual Mode I2C Serial EEPROM (Tape and Reel) Preliminary DS21161C-page 15 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. Suite 150 Two Prestige Place Miamisburg, OH 45342 Tel: 513 291-1654 Fax: 513 291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technmgy Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279 Fax: 905 405-6253 China Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 011 86 21 6275 5060 Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan, R.O.C Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/3/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21161C-page 16 Preliminary 1996 Microchip Technology Inc.