24C01SC/02SC 1K/2K 5.0V I2C Serial EEPROMs for Smart Cards FEATURES DIE LAYOUT • ISO Standard 7816 pad locations • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V • Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8) • Two-wire serial interface bus, I2C compatible • 100 kHz and 400 kHz compatibility • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 8 bytes • 2 ms typical write cycle time for page-write • ESD protection > 4 kV • 1,000,000 E/W cycles guaranteed • Data retention > 200 years • Available for extended temperature ranges - Commercial (C): 0°C to +70°C DESCRIPTION VSS VCC SDA DC SCL BLOCK DIAGRAM HV GENERATOR I/O CONTROL LOGIC MEMORY CONTROL LOGIC XDEC EEPROM ARRAY PAGE LATCHES The Microchip Technology Inc. 24C01SC and 24C02SC are 1K-bit and 2K-bit Electrically Erasable PROMs with bondpad positions optimized for smart card applications. The devices are organized as a single block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. The 24C01SC and 24C02SC also have page-write capability for up to 8 bytes of data. SDA SCL YDEC VCC VSS SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation. 1996 Microchip Technology Inc. Preliminary This document was created with FrameMaker 4 0 4 DS21170A-page 1 24C01SC/02SC 1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: Maximum Ratings* Name VCC ........................................................................ 7.0V All inputs and outputs w.r.t. VSS...... -0.6V to VCC +1.0V Storage temperature ...........................-65˚C to +150˚C Ambient temp. with power applied.......-65˚C to +125˚C ESD protection on all pads .....................................≥ 4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PAD FUNCTION TABLE Function VSS Ground SDA Serial Address/Data I/O SCL Serial Clock VCC +4.5V to 5.5V Power Supply DC Don’t connect DC CHARACTERISTICS VCC = +4.5V to +5.5V Parameter Commercial (C): Tamb = 0˚C to +70˚C Symbol Min. Max. Units SCL and SDA pads: High level input voltage VIH .7 VCC — — Low level input voltage VIL — .3 VCC V Hysteresis of Schmidt trigger inputs VHYS .05 VCC — V (Note) Low level output voltage VOL — .40 V IOL = 3.0 mA, VCC = 4.5V Input leakage current (SCL) ILI -10 10 µA VIN = .1V to 5.5V Output leakage current (SDA) ILO -10 10 µA VOUT = .1V to 5.5V CIN, COUT — 10 pF VCC = 5.0V (Note 1) Tamb = 25˚C, FCLK = 1 MHz ICC Write — 3 mA VCC = 5.5V ICC Read — 1 mA Vcc = 5.5V, SCL = 400 KHz ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC Pin capacitance (all inputs/outputs) Operating current Standby current Note: Conditions This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS21170A-page 2 STOP Preliminary 1996 Microchip Technology Inc. 24C01SC/02SC TABLE 1-3: AC CHARACTERISTICS Parameter Symbol Min. Max. Units Clock frequency FCLK — 400 kHz Clock high time THIGH 600 — ns Clock low time TLOW 1300 — ns SDA and SCL rise time TR — 300 ns (Note 1) SDA and SCL fall time TF — 300 ns (Note 1) START condition hold time THD:STA 600 — ns After this period the first clock pulse is generated START condition setup time TSU:STA 600 — ns Only relevant for repeated START condition Data input hold time THD:DAT 0 — ns (Note 2) Data input setup time TSU:DAT 100 — ns STOP condition setup time TSU:STO 600 — ns Output valid from clock TAA — 900 ns (Note 2) Bus free time TBUF 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum TOF 20 +0.1 CB 250 ns (Note 1), CB ≤ 100 pF Input filter spike suppression (SDA and SCL pins) TSP — 50 ns (Note 3) Write cycle time TWR — 10 ms Byte or Page mode — cycles Endurance — 6 10 Remarks 25°C, Vcc = 5V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-2: BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA SDA IN THD:DAT TSU:DAT TSU:STO THD:STA TSP TAA THD:STA TAA TBUF SDA OUT 1996 Microchip Technology Inc. Preliminary DS21170A-page 3 24C01SC/02SC 2.0 FUNCTIONAL DESCRIPTION 3.4 The 24C01SC/02SC supports a bi-directional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C01SC/02SC works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion. 3.5 Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: (A ) Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Bus not Busy (A) Data Valid (D) The 24C01SC/02SC does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SCL SDA DS21170A-page 4 DATA ALLOWED TO CHANGE Preliminary STOP CONDITION 1996 Microchip Technology Inc. 24C01SC/02SC 4.0 BUS CHARACTERISTICS 5.0 WRITE OPERATION 4.1 Slave Address 5.1 Byte Write After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01SC/02SC, followed by three don't care bits. Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01SC/02SC. After receiving another acknowledge signal from the 24C01SC/02SC, the master device will transmit the data word to be written into the addressed memory location. The 24C01SC/02SC acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01SC/02SC will not generate acknowledge signals (Figure 5-1). The eighth bit of slave address determines if the master device wants to read or write to the 24C01SC/02SC (Figure 4-1). The 24C01SC/02SC monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true, and it is not in a programming mode. Operation Control Code Chip Select R/W Read Write 1010 1010 XXX XXX 1 0 FIGURE 4-1: START R/W 0 1 0 X X A X X = Don’t care FIGURE 5-1: BUS ACTIVITY MASTER SDA LINE BYTE WRITE S T A R T CONTROL BYTE WORD ADDRESS S T O P DATA S P A C K BUS ACTIVITY FIGURE 5-2: Page Write The write control byte, word address, and the first data byte are transmitted to the 24C01SC/02SC in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to eight data bytes to the 24C01SC/02SC, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 5-2). READ/WRITE SLAVE ADDRESS 1 5.2 CONTROL BYTE ALLOCATION A C K A C K PAGE WRITE BUS ACTIVITY MASTER SDA LINE S T A R T CONTROL BYTE WORD ADDRESS (n) DATA n S T O P DATAn + 7 DATAn + 1 S BUS ACTIVITY 1996 Microchip Technology Inc. P A C K A C K Preliminary A C K A C K A C K DS21170A-page 5 24C01SC/02SC 6.0 ACKNOWLEDGE POLLING 7.0 Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then NO ACK will be returned. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next read or write command. See Figure 6-1 for flow diagram. FIGURE 6-1: ACKNOWLEDGE POLLING FLOW Send Write Command Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 7.1 Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO Current Address Read The 24C01SC/02SC contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C01SC/02SC issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01SC/02SC discontinues transmission (Figure 8-2). 7.2 Send Stop Condition to Initiate Write Cycle READ OPERATION Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C01SC/02SC as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one. The 24C01SC/02SC will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01SC/02SC discontinues transmission (Figure 8-3). 7.3 Sequential Read YES Next Operation Sequential reads are initiated in the same way as a random read except that after the 24C01SC/02SC transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01SC/02SC to transmit the next sequentially addressed 8-bit word (Figure 9-1). To provide sequential reads the 24C01SC/02SC contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. DS21170A-page 6 Preliminary 1996 Microchip Technology Inc. 24C01SC/02SC 7.4 Noise Protection The 24C01SC/02SC employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. FIGURE 7-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE S T O P DATA n P A C K BUS ACTIVITY N O A C K FIGURE 7-2: RANDOM READ T S T A R T S S S T CONTROL BYTE BUS ACTIVITY A MASTER R SDA LINE WORD ADDRESS (n) S T O P DATA n P A C K A C K BUS ACTIVITY CONTROL BYTE N O A C K A C K FIGURE 7-3: SEQUENTIAL READ BUS ACTIVITY MASTER A C K CONTROL BYTE S T O P A C K A C K P SDA LINE BUS ACTIVITY A C K DATA n DATA n + 1 DATA n + 2 DATA n + X N O A C K 1996 Microchip Technology Inc. Preliminary DS21170A-page 7 24C01SC/02SC 8.0 PAD DESCRIPTIONS 9.0 8.1 SDA Serial Address/Data Input/Output Figure 9-1 shows the die layout of the 24C01SC/02SC, including bondpad positions. Table 9-1 shows the actual coordinates of the bondpad midpoints with respect to the center of the die. This is a bi-directional pad used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400 kHz). DIE CHARACTERISTICS FIGURE 9-1: DIP VSS For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 8.2 VCC SCL Serial Clock SDA This input is used to synchronize the data transfer from and to the device. 8.3 DIE LAYOUT DC SCL DC Don’t Connect This pad is used for test purposes and should not be bonded out. It will be pulled to VSS through an internal resistor. TABLE 9-1: Pad Name BONDPAD COORDINATES Pad Midpoint, X dir. Pad Midpoint, Y dir. -495.000 749.130 VSS SDA -605.875 -271.875 SCL 479.875 -746.625 VCC 605.875 -261.375 Note 1: Dimensions are in microns. 2: Center of die is at the 0,0 point. DS21170A-page 8 Preliminary 1996 Microchip Technology Inc. 24C01SC/02SC NOTES: 1996 Microchip Technology Inc. Preliminary DS21170A-page 9 24C01SC/02SC NOTES: DS21170A-page 10 Preliminary 1996 Microchip Technology Inc. 24C01SC/02SC 24C01SC/02SC Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 24C01SC/02SC — /S XX Die Thickness Blank = 11 mils 08 = 8 mils Other die thicknesses available, please consult factory. Package: Temperature Range: Device: 1996 Microchip Technology Inc. S = Die in Wafer Pak W = Wafer WF = Sawed Wafer on Frame Blank = 0°C to +70°C 24C01SC 1K 12C ISO Smart Card die 24C02SC 2K 12C ISO Smart Card die Preliminary DS21170A-page 11 WORLDWIDE SALES & SERVICE AMERICAS AMERICAS (continued) EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com/ New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279 Fax: 905 405-6253 United Kingdom Arizona Microchip Technology Ltd. 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Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 5/10/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. 5/96 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21170A-page 12 Preliminary 1996 Microchip Technology Inc.