MICROCHIP PIC24FJ64GA004

PIC24FJ64GA004 Family
Data Sheet
28/44-Pin General Purpose,
16-Bit Flash Microcontrollers
© 2007 Microchip Technology Inc.
Preliminary
DS39881B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS39881B-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
Analog Features:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture:
- 76 base instructions
- Flexible addressing modes
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• 10-Bit, up to 13-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable
Input/Output Configuration
Peripheral Features:
Special Microcontroller Features:
•
•
•
•
•
•
•
•
•
•
•
Operating Voltage Range of 2.0V to 3.6V
5.5V Tolerant Input (digital pins only)
High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Flash Program Memory:
- 10,000 erase/write
- 20-year data retention minimum
Power Management modes:
- Sleep, Idle, Doze and Alternate Clock modes
- Operating current 650 μA/MIPS typical at 2.0V
- Sleep current 150 nA typical at 2.0V
Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
On-Chip, 2.5V Regulator with Tracking mode
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
JTAG Boundary Scan and Programming Support
• Peripheral Pin Select:
- Allows independent I/O mapping of many peripherals
- Up to 26 available pins (44-pin devices)
- Continuous hardware integrity checking and safety
interlocks prevent unintentional configuration changes
• 8-Bit Parallel Master/Slave Port (PMP/PSP):
- Up to 16-bit multiplexed addressing, with up to
11 dedicated address pins on 44-pin devices
- Programmable polarity on control lines
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• Programmable Cyclic Redundancy Check (CRC)
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
• Two I2C™ modules support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Two UART modules:
- Supports RS-485, RS-232, and LIN 1.2
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Start bit
- Auto-Baud Detect
- 4-level deep FIFO buffer
• Five 16-Bit Timers/Counters with Programmable Prescaler
• Five 16-Bit Capture Inputs
• Five 16-Bit Compare/PWM Outputs
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to 4 External Interrupt Sources
PIC24FJ
Device
Pins
Program
Memory
(bytes)
SRAM
(bytes)
Remappable
Pins
Timers
16-Bit
Capture
Input
Compare/
PWM
Output
UART w/
IrDA®
SPI
I2C™
10-Bit A/D
(ch)
Comparators
PMP/PSP
JTAG
Remappable Peripherals
16GA002
28
16K
4K
16
5
5
5
2
2
2
10
2
Y
Y
32GA002
28
32K
8K
16
5
5
5
2
2
2
10
2
Y
Y
48GA002
28
48K
8K
16
5
5
5
2
2
2
10
2
Y
Y
64GA002
28
64K
8K
16
5
5
5
2
2
2
10
2
Y
Y
16GA004
44
16K
4K
26
5
5
5
2
2
2
13
2
Y
Y
32GA004
44
32K
8K
26
5
5
5
2
2
2
13
2
Y
Y
48GA004
44
48K
8K
26
5
5
5
2
2
2
13
2
Y
Y
64GA004
44
64K
8K
26
5
5
5
2
2
2
13
2
Y
Y
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 1
PIC24FJ64GA004 FAMILY
Pin Diagrams
28-Pin QFN(1)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
AN9/RP15/CN11/PMCS1/RB15
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
VCAP/VDDCORE
DISVREG
TDO/RP9/SDA1/CN21/PMD3/RB9
TCK/RP8/SCL1/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGC3/EMUC3/RP6/SCL1(2)/CN24/PMD6/RB6
28 27 26 25 24 23 22
1
21
2
20
3
19
4 PIC24FJXXGA002 18
5
17
6
16
7
15
8 9 10 11 12 13 14
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
VCAP/VDDCORE
DISVREG
TDO/RP9/SDA1/CN21/PMD3/RB9
SOSCI/RP4/PMBE/CN1/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGD3/EMUD3/RP5/SDA1(2)/CN27/PMD7/RB5
(2)
PGC3/EMUC3/RP6/SCL1 /CN24/PMD6/RB6
RP7/INT0/CN23/PMD5/RB7
TCK/RP8/SCL1/CN22/PMD4/RB8
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
AN4/C1IN-/RP2/SDA2/CN6/RB2
AN5/C1IN+/RP3/SCL2/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AN1/VREF-/CN3/RA1
AN0/VREF+/CN2/RA0
MCLR
VDD
VSS
AN9/RP15/CN11/PMCS1/RB15
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
AN4/C1IN-/RP2/SDA2/CN6/RB2
AN5/C1IN+/RP3/SCL2/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
SOSCI/RP4/PMBE/CN1/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGD3/EMUD3/RP5/SDA1(2)/CN27/x/RB5
PIC24FJXXGA002
28-Pin SPDIP, SSOP, SOIC(1)
Legend:
Note 1:
2:
RPn represents remappable peripheral pins.
RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output
compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin
Select” and the specific peripheral sections.
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
DS39881B-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
44
43
42
41
40
39
38
37
36
35
34
44-Pin QFN
RP8/SCL1/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGC3/EMUC3/RP6/SCL1(2)/CN24/PMD6/RB6
PGD3/EMUD3/RP5/SDA1(2)/CN27/PMD7/RB5
VDD
VSS
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
RP19/CN28/PMBE/RC3
TDI/PMA9/RA9
SOSCO/T1CK/CN0/RA4
Pin Diagrams (Continued)
PIC24FJXXGA004
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
SOSCI/RP4/CN1/RB4
TDO/PMA8/RA8
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
VSS
VDD
AN8/RP18/CN10/PMA2/RC2
AN7/RP17/CN9/RC1
AN6/RP16/CN8/RC0
AN5/C1IN+/RP3/SCL2/CN7/RB3
AN4/C1IN-/RP2/SDA2/CN6/RB2
TMS/PMA10/RA10
TCK/PMA7/RA7
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN9/RP15/CN11/PMCS1/RB15
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
RP9/SDA1/CN21/PMD3/RB9
RP22/CN18/PMA1/RC6
RP23/CN17/PMA0/RC7
RP24/CN20/PMA5/RC8
RP25/CN19/PMA6/RC9
DISVREG
VCAP/VDDCORE
PGD2/EMUD2/RP10/CN16/PMD2/RB10
PGC2/EMUC2/RP11/CN15/PMD1/RB11
AN12/RP12/CN14/PMD0/RB12
AN11/RP13/CN13/PMRD/RB13
Legend:
Note 1:
2:
RPn represents remappable peripheral pins.
RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output
compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin
Select” and the specific peripheral sections.
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 3
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
RP8/SCL1/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGC3/EMUC3/RP6/SCL1(2)/CN24/PMD6/RB6
PGD3/EMUD3/RP5/SDA1(2)/CN27/PMD7/RB5
VDD
VSS
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
RP19/CN28/PMBE/RC3
TDI/PMA9/RA9
SOSCO/T1CK/CN0/RA4
44-Pin TQFP
PIC24FJXXGA004
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
SOSCI/RP4/CN1/RB4
TDO/PMA8/RA8
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
VSS
VDD
AN8/RP18/CN10/PMA2/RC2
AN7/RP17/CN9/RC1
AN6/RP16/CN8/RC0
AN5/C1IN+/RP3/SCL2/CN7/RB3
AN4/C1IN-/RP2/SDA2/CN6/RB2
TMS/PMA10/RA10
TCK/PMA7/RA7
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN9/RP15/CN11/PMCS1/RB15
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
RP9/SDA1/CN21/PMD3/RB9
RP22/CN18/PMA1/RC6
RP23/CN17/PMA0/RC7
RP24/CN20/PMA5/RC8
RP25/CN19/PMA6/RC9
DISVREG
VCAP/VDDCORE
PGD2/EMUD2/RP10/CN16/PMD2/RB10
PGC2/EMUC2/RP11/CN15/PMD1/RB11
AN12/RP12/CN14/PMD0/RB12
AN11/RP13/CN13/PMRD/RB13
Legend:
Note 1:
2:
RPn represents remappable peripheral pins.
RPn pins can be configured to function as any of the following peripherals: timers, UART, input capture, output
compare, PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin
Select” and the specific peripheral sections.
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
DS39881B-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 CPU ........................................................................................................................................................................................... 17
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Flash Program Memory.............................................................................................................................................................. 41
5.0 Resets ........................................................................................................................................................................................ 47
6.0 Interrupt Controller ..................................................................................................................................................................... 53
7.0 Oscillator Configuration .............................................................................................................................................................. 87
8.0 Power-Saving Features.............................................................................................................................................................. 95
9.0 I/O Ports ..................................................................................................................................................................................... 97
10.0 Timer1 ...................................................................................................................................................................................... 117
11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 119
12.0 Input Capture............................................................................................................................................................................ 125
13.0 Output Compare....................................................................................................................................................................... 127
14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133
15.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 143
16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 153
17.0 Parallel Master Port (PMP)....................................................................................................................................................... 161
18.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 171
19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 181
20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 185
21.0 Comparator Module.................................................................................................................................................................. 195
22.0 Comparator Voltage Reference................................................................................................................................................ 199
23.0 Special Features ...................................................................................................................................................................... 201
24.0 Development Support............................................................................................................................................................... 211
25.0 Instruction Set Summary .......................................................................................................................................................... 215
26.0 Electrical Characteristics .......................................................................................................................................................... 223
27.0 Packaging Information.............................................................................................................................................................. 237
Appendix A: Revision History............................................................................................................................................................. 245
Index ................................................................................................................................................................................................. 247
The Microchip Web Site ..................................................................................................................................................................... 251
Customer Change Notification Service .............................................................................................................................................. 251
Customer Support .............................................................................................................................................................................. 251
Reader Response .............................................................................................................................................................................. 252
Product Identification System ............................................................................................................................................................ 253
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 5
PIC24FJ64GA004 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS39881B-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
1.0
DEVICE OVERVIEW
1.1.2
This document contains device-specific information for
the following devices:
•
•
•
•
•
•
•
•
PIC24FJ16GA002
PIC24FJ32GA002
PIC24FJ48GA002
PIC24FJ64GA002
PIC24FJ16GA004
PIC24FJ32GA004
PIC24FJ48GA004
PIC24FJ64GA004
This family introduces a new line of Microchip devices:
a 16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
The PIC24FJ64GA004 family offers a new migration
option for those high-performance applications which
may be outgrowing their 8-bit platforms, but don’t
require the numerical processing power of a digital
signal processor.
1.1
Core Features
All of the devices in the PIC24FJ64GA004 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.
1.1.3
1.1.1
POWER-SAVING TECHNOLOGY
16-BIT ARCHITECTURE
OSCILLATOR OPTIONS AND
FEATURES
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
All of the devices in the PIC24FJ64GA004 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages such as ‘C’
• Operational performance up to 16 MIPS
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 7
PIC24FJ64GA004 FAMILY
1.1.4
EASY MIGRATION
1.3
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 28-pin to
44-pin devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
Devices in the PIC24FJ64GA004 family are available
in 28-pin and 44-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in two
ways:
1.
2.
3.
1.2
Other Special Features
• Communications: The PIC24FJ64GA004 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C
modules that support both Master and Slave
modes of operation. Devices also have, through
the peripheral pin select feature, two independent UARTs with built-in IrDA encoder/decoders
and two SPI modules.
• Peripheral Pin Select: The peripheral pin select
feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communications. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.
DS39881B-page 8
Details on Individual Family
Members
Flash program memory (64 Kbytes for
PIC24FJ64GA devices, 48 Kbytes for
PIC24FJ48GA devices, 32 Kbytes for
PIC24FJ32GA devices and 16 Kbytes for
PIC24FJ16GA devices).
Internal SRAM memory (4k for PIC24FJ16GA
devices, 8k for all other devices in the family).
Available I/O pins and ports (21 pins on 2 ports
for 28-pin devices and 35 pins on 3 ports for
44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
A list of the pin features available on the
PIC24FJ64GA004 family devices, sorted by function, is
shown in Table 1-2. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Operating Frequency
Program Memory (bytes)
64GA004
48GA004
32GA004
16GA004
64GA002
48GA002
Features
32GA002
DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY
16GA002
TABLE 1-1:
DC – 32 MHz
16K
32K
48K
64K
16K
32K
48K
64K
Program Memory (instructions)
5,504
11,008
16,512
22,016
5,504
11,008
16,512
22,016
Data Memory (bytes)
4096
8192
Interrupt Sources
(soft vectors/NMI traps)
I/O Ports
Total I/O Pins
4096
8192
43
(39/4)
Ports A, B
Ports A, B, C
21
35
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
5(1)
Output Compare/PWM Channels
5(1)
Input Change Notification Interrupt
21
30
Serial Communications:
UART
2(1)
SPI (3-wire/4-wire)
2(1)
I2C™
2
Parallel Communications (PMP/PSP)
Yes
JTAG Boundary Scan
Yes
10-Bit Analog-to-Digital Module
(input channels)
10
Analog Comparators
Remappable Pins
Resets (and delays)
Instruction Set
Packages
Note 1:
13
2
16
26
POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode,
REPEAT Instruction Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
76 Base Instructions, Multiple Addressing Mode Variations
28-Pin SPDIP/SSOP/SOIC/QFN
44-Pin QFN/TQFP
Peripherals are accessible through remappable pins.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 9
PIC24FJ64GA004 FAMILY
FIGURE 1-1:
PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
16
16
8
16
Data Latch
PSV & Table
Data Access
Control Block
Data RAM
PCU PCH PCL
Program Counter
Repeat
Stack
Control
Control
Logic
Logic
23
Address
Latch
PORTA(1)
RA0:RA9
16
23
16
Read AGU
Write AGU
Address Latch
PORTB
Program Memory
RB0:RB15
Data Latch
16
EA MUX
24
Inst Latch
Literal Data
Address Bus
PORTC(1)
16
16
RC0:RC9
Inst Register
RP(1)
Instruction
Decode &
Control
RP0:RP25
Control Signals
OSCO/CLKO
OSCI/CLKI
Timing
Generation
FRC/LPRC
Oscillators
16-Bit ALU
Power-on
Reset
Voltage
Regulator
BOR and
LVD(2)
Timer1
16 x 16
W Reg Array
Oscillator
Start-up Timer
Watchdog
Timer
VDDCORE/VCAP
17x17
Multiplier
Power-up
Timer
Precision
Band Gap
Reference
DISVREG
Divide
Support
VDD, VSS
16
MCLR
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
ADC
Comparators(3)
PMP/PSP
IC1-5(3)
Note
1:
2:
3:
PWM/
OC1-5(3)
CN1-22(1)
SPI1/2(3)
I2C1/2
UART1/2(3)
Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.
BOR functionality is provided when the on-board voltage regulator is enabled.
Peripheral I/Os are accessible through remappable pins.
DS39881B-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Pin Number
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
2
27
19
I
ANA
AN1
3
28
20
I
ANA
AN2
4
1
21
I
ANA
AN3
5
2
22
I
ANA
AN4
6
3
23
I
ANA
Function
AN0
Description
A/D Analog Inputs.
AN5
7
4
24
I
ANA
AN6
—
—
25
I
ANA
AN7
—
—
26
I
ANA
AN8
—
—
27
I
ANA
AN9
26
23
15
I
ANA
AN10
25
22
14
I
ANA
AN11
24
21
11
I
ANA
AN12
23
20
10
I
ANA
AVDD
—
—
17
P
—
Positive Supply for Analog Modules.
AVSS
—
—
16
P
—
Ground Reference for Analog Modules.
C1IN-
6
3
23
I
ANA
Comparator 1 Negative Input.
C1IN+
7
4
24
I
ANA
Comparator 1 Positive Input.
C2IN-
4
1
21
I
ANA
Comparator 2 Negative Input.
C2IN+
5
2
22
I
ANA
Comparator 2 Positive Input.
CLKI
9
6
30
I
ANA
CLKO
10
7
31
O
—
Legend:
Note 1:
Main Clock Input Connection.
System Clock Output.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 11
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
CN0
12
9
34
I
ST
CN1
11
8
33
I
ST
CN2
2
27
19
I
ST
CN3
3
28
20
I
ST
CN4
4
1
21
I
ST
CN5
5
2
22
I
ST
CN6
6
3
23
I
ST
CN7
7
4
24
I
ST
CN8
—
—
25
I
ST
CN9
—
—
26
I
ST
Function
CN10
—
—
27
I
ST
CN11
26
23
15
I
ST
CN12
25
22
14
I
ST
CN13
24
21
11
I
ST
CN14
23
20
10
I
ST
CN15
22
19
9
I
ST
CN16
21
18
8
I
ST
CN17
—
—
3
I
ST
CN18
—
—
2
I
ST
CN19
—
—
5
I
ST
CN20
—
—
4
I
ST
CN21
18
15
1
I
ST
CN22
17
14
44
I
ST
CN23
16
13
43
I
ST
CN24
15
12
42
I
ST
CN25
—
—
37
I
ST
CN26
—
—
38
I
ST
CN27
14
11
41
I
ST
CN28
—
—
36
I
ST
CN29
10
7
31
I
ST
Description
Interrupt-on-Change Inputs.
CN30
9
6
30
I
ST
CVREF
25
22
14
O
ANA
DISVREG
19
16
6
I
ST
Voltage Regulator Disable.
EMUC1
5
2
21
I/O
ST
In-Circuit Emulator Clock Input/Output.
Comparator Voltage Reference Output.
EMUD1
4
1
22
I/O
ST
In-Circuit Emulator Data Input/Output.
EMUC2
22
19
9
I/O
ST
In-Circuit Emulator Clock Input/Output.
EMUD2
21
18
8
I/O
ST
In-Circuit Emulator Data Input/Output.
EMUC3
15
12
42
I/O
ST
In-Circuit Emulator Clock Input/Output.
EMUD3
14
11
41
I/O
ST
In-Circuit Emulator Data Input/Output.
INT0
16
13
43
I
ST
External Interrupt Input.
MCLR
1
26
18
I
ST
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
Legend:
Note 1:
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
DS39881B-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
Description
OSCI
9
6
30
I
ANA
Main Oscillator Input Connection.
OSCO
10
7
31
O
ANA
Main Oscillator Output Connection.
PGC1
5
2
22
I/O
ST
In-Circuit Debugger and ICSP™ Programming Clock
PGD1
4
1
21
I/O
ST
In-Circuit Debugger and ICSP Programming Data.
PGC2
22
19
9
I/O
ST
In-Circuit Debugger and ICSP Programming Clock.
PGD2
21
18
8
I/O
ST
In-Circuit Debugger and ICSP Programming Data.
PGC3
14
12
42
I/O
ST
In-Circuit Debugger and ICSP Programming Clock.
PGD3
15
11
41
I/O
ST
In-Circuit Debugger and ICSP Programming Data.
PMA0
10
7
3
I/O
ST
Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1
12
9
2
I/O
ST
Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
Parallel Master Port Address (Demultiplexed Master
modes).
PMA2
—
—
27
O
—
PMA3
—
—
38
O
—
PMA4
—
—
37
O
—
PMA5
—
—
4
O
—
PMA6
—
—
5
O
—
PMA7
—
—
13
O
—
PMA8
—
—
32
O
—
PMA9
—
—
35
O
—
PMA10
—
—
12
O
—
PMA11
—
—
—
O
—
PMA12
—
—
—
O
—
PMA13
—
—
—
O
—
PMBE
11
8
36
O
—
Parallel Master Port Byte Enable Strobe.
PMCS1
26
23
15
O
—
Parallel Master Port Chip Select 1 Strobe/Address Bit 14.
Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
PMD0
23
20
10
I/O
ST
PMD1
22
19
9
I/O
ST
PMD2
21
18
8
I/O
ST
PMD3
18
15
1
I/O
ST
PMD4
17
14
44
I/O
ST
PMD5
16
13
43
I/O
ST
PMD6
15
12
42
I/O
ST
PMD7
14
11
41
I/O
ST
PMRD
24
21
11
O
—
Parallel Master Port Read Strobe.
PMWR
25
22
14
O
—
Parallel Master Port Write Strobe.
Legend:
Note 1:
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 13
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Input
Buffer
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
RA0
2
27
19
I/O
ST
RA1
3
28
20
I/O
ST
Function
44-Pin
QFN/TQFP
I/O
RA2
9
6
30
I/O
ST
RA3
10
7
31
I/O
ST
RA4
12
9
34
I/O
ST
RA7
—
—
13
I/O
ST
RA8
—
—
32
I/O
ST
RA9
—
—
35
I/O
ST
RA10
—
—
12
I/O
ST
RB0
4
1
21
I/O
ST
RB1
5
2
22
I/O
ST
RB2
6
3
23
I/O
ST
RB3
7
4
24
I/O
ST
RB4
11
8
33
I/O
ST
RB5
14
11
41
I/O
ST
RB6
15
12
42
I/O
ST
RB7
16
13
43
I/O
ST
RB8
17
14
44
I/O
ST
RB9
18
15
1
I/O
ST
RB10
21
18
8
I/O
ST
RB11
22
19
9
I/O
ST
RB12
23
20
10
I/O
ST
RB13
24
21
11
I/O
ST
RB14
25
22
14
I/O
ST
RB15
26
23
15
I/O
ST
RC0
—
—
25
I/O
ST
RC1
—
—
26
I/O
ST
RC2
—
—
27
I/O
ST
RC3
—
—
36
I/O
ST
RC4
—
—
37
I/O
ST
RC5
—
—
38
I/O
ST
RC6
—
—
2
I/O
ST
RC7
—
—
3
I/O
ST
RC8
—
—
4
I/O
ST
—
—
5
I/O
ST
RC9
Legend:
Note 1:
Description
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
DS39881B-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Input
Buffer
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
RP0
4
1
21
I/O
ST
RP1
5
2
22
I/O
ST
RP2
6
3
23
I/O
ST
RP3
7
4
24
I/O
ST
RP4
11
8
33
I/O
ST
RP5
14
11
41
I/O
ST
RP6
15
12
42
I/O
ST
RP7
16
13
43
I/O
ST
RP8
17
14
44
I/O
ST
RP9
18
15
1
I/O
ST
RP10
21
18
8
I/O
ST
RP11
22
19
9
I/O
ST
RP12
23
20
10
I/O
ST
RP13
24
21
11
I/O
ST
RP14
25
22
14
I/O
ST
RP15
26
23
15
I/O
ST
RP16
—
—
25
I/O
ST
RP17
—
—
26
I/O
ST
RP18
—
—
27
I/O
ST
RP19
—
—
36
I/O
ST
RP20
—
—
37
I/O
ST
RP21
—
—
38
I/O
ST
RP22
—
—
2
I/O
ST
RP23
—
—
3
I/O
ST
RP24
—
—
4
I/O
ST
RP25
—
—
5
I/O
ST
Function
Description
Remappable Peripheral.
RTCC
25
22
14
O
—
Real-Time Clock Alarm Output.
SCL1
17, 15(1)
14, 12(1)
44, 42(1)
I/O
I2C
I2C1 Synchronous Serial Clock Input/Output.
SCL2
7
4
I/O
I2C
I2C2 Synchronous Serial Clock Input/Output.
SDA1
18, 14(1)
15, 11(1)
I/O
I2C
I2C1 Data Input/Output.
I2C2 Data Input/Output.
1, 41(1)
SDA2
6
3
I/O
I2C
SOSCI
11
8
33
I
ANA
Secondary Oscillator/Timer1 Clock Input.
SOSCO
12
9
34
O
ANA
Secondary Oscillator/Timer1 Clock Output.
Legend:
Note 1:
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 15
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
Description
T1CK
12
9
34
I
ST
Timer1 Clock.
TCK
17
14
13
I
ST
JTAG Test Clock/Programming Clock Input.
TDI
21
18
35
I
ST
JTAG Test Data/Programming Data Input.
TDO
18
15
32
O
—
JTAG Test Data Output.
TMS
22
19
12
I
ST
JTAG Test Mode Select Input.
VDD
13, 28
10, 25
28, 40
P
—
Positive Supply for Peripheral Digital Logic and I/O Pins.
VDDCAP
20
17
7
P
—
External Filter Capacitor Connection (regulator enabled).
VDDCORE
20
17
7
P
—
Positive Supply for Microcontroller Core Logic (regulator
disabled).
VREF-
3
28
20
I
ANA
VREF+
2
27
19
I
ANA
8, 27
5, 24
29, 39
P
—
VSS
Legend:
Note 1:
A/D and Comparator Reference Voltage (low) Input.
A/D and Comparator Reference Voltage (high) Input.
Ground Reference for Logic and I/O Pins.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared.
DS39881B-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.0
Note:
CPU
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a
single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using
the REPEAT instructions, which are interruptible at any
point.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as
a Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three-parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit, integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit, integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to
one of seven priority levels.
A block diagram of the CPU is shown in Figure 2-1.
2.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 2-2. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions. A description of each register is provided
in Table 2-1. All registers associated with the
programmer’s model are memory mapped.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 17
PIC24FJ64GA004 FAMILY
FIGURE 2-1:
PIC24F CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
16
Data Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
Data RAM
Address
Latch
23
16
RAGU
WAGU
Address Latch
Program Memory
EA MUX
Address Bus
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Hardware
Multiplier
Divide
Support
16
Literal Data
Instruction
Decode &
Control
16
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS39881B-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 2-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
Working Register Array
PC
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
PSVPAG
Program Space Visibility Page Address Register
RCOUNT
Repeat Loop Counter Register
CORCON
CPU Control Register
FIGURE 2-2:
PROGRAMMER’S MODEL
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
22
0
0
PC
7
Program Counter
0
Table Memory Page
Address Register
TBLPAG
7
0
PSVPAG
15
0
RCOUNT
SRH
SRL
— — — — — — — DC
IPL
2 1 0 RA N OV Z C
15
Stack Pointer Limit
Value Register
15
Program Space Visibility
Page Address Register
Repeat Loop Counter
Register
0
ALU STATUS Register (SR)
0
— — — — — — — — — — — — IPL3 PSV — —
CPU Control Register (CORCON)
Registers or bits shadowed for PUSH.S and POP.S instructions.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 19
PIC24FJ64GA004 FAMILY
2.2
CPU Control Registers
REGISTER 2-1:
SR: ALU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
IPL2
R/W-0(1)
(2)
IPL1
(2)
R/W-0(1)
IPL0
(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU interrupt priority level is 7 (15); user interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1
Z: ALU Zero bit
1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS39881B-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 2-2:
CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
—
R/C-0
(1)
IPL3
R/W-0
U-0
U-0
PSV
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
2.3
x = Bit is unknown
User interrupts are disabled when IPL3 = 1.
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
© 2007 Microchip Technology Inc.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a dedicated hardware multiplier and support hardware for
16-bit divisor division.
2.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
1.
2.
3.
4.
5.
6.
7.
Preliminary
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
DS39881B-page 21
PIC24FJ64GA004 FAMILY
2.3.2
DIVIDER
2.3.3
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
TABLE 2-2:
Instruction
MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided below in Table 2-2.
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description
ASR
Arithmetic shift right source register by one or more bits.
SL
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
DS39881B-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
3.1
Program Address Space
The
program
address
memory
space
of
PIC24FJ64GA004 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 3-1:
from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space
remapping, as described in Section 3.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ64GA004 family of
devices are shown in Figure 3-1.
PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ16GA
PIC24FJ32GA
PIC24FJ48GA
PIC24FJ64GA
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Reserved
Reserved
Reserved
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
User Flash
Program Memory
(11K instructions)
User Flash
Program Memory
(16K instructions)
User Flash
Program Memory
(5.5K instructions)
User Memory Space
Flash Config Words
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
002BFEh
002C00h
User Flash
Program Memory
(22K instructions)
0057FEh
005800h
Flash Config Words
0083FEh
008400h
Flash Config Words
Flash Config Words
Unimplemented
Read ‘0’
Unimplemented
Read ‘0’
Unimplemented
Read ‘0’
00ABFEh
00AC00h
Unimplemented
Read ‘0’
Configuration Memory Space
7FFFFFh
800000h
Reserved
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
Reserved
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFFh
Note:
Memory areas are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 23
PIC24FJ64GA004 FAMILY
3.1.1
PROGRAM MEMORY
ORGANIZATION
3.1.3
In PIC24FJ64GA004 family devices, the top two words
of on-chip program memory are reserved for configuration information. On device Reset, the configuration
information is copied into the appropriate Configuration
registers. The addresses of the Flash Configuration
Word for devices in the PIC24FJ64GA004 family are
shown in Table 3-1. Their location in the memory map
is shown with the other memory vectors in Figure 3-1.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 3-2).
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words do not reflect a corresponding arrangement in the
configuration space. Additional details on the device
Configuration Words are provided in Section 23.1
“Configuration Bits”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
3.1.2
FLASH CONFIGURATION WORDS
HARD MEMORY VECTORS
TABLE 3-1:
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
FIGURE 3-2:
msw
Address
PIC24FJ16GA
5.5
002BFCh:
002BFEh
PIC24FJ32GA
11
0057FCh:
0057FEh
PIC24FJ48GA
16
0083FCh:
0083FEh
PIC24FJ64GA
22
00ABFCh:
00ABFEh
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
000000h
000002h
000004h
000006h
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS39881B-page 24
Configuration
Word
Addresses
PROGRAM MEMORY ORGANIZATION
23
000001h
000003h
000005h
000007h
Program
Memory
(K words)
Device
PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Table”.
FLASH CONFIGURATION
WORDS FOR PIC24FJ64GA004
FAMILY DEVICES
Instruction Width
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2
Data Address Space
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 3-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the program space visibility area (see
Section 3.3.3 “Reading Data from Program Memory
Using Program Space Visibility”).
PIC24FJ64GA family devices implement a total of
8 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
3.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)
FIGURE 3-3:
MSB
Address
0001h
07FFh
0801h
MSB
LSB
SFR Space
LSB
Address
0000h
07FEh
0800h
SFR
Space
Near
Data Space
Data RAM
Implemented
Data RAM
1FFFh
2001h
27FFh(2)
2801h
1FFEh
2000h
27FEh(2)
2800h
Unimplemented
Read as ‘0’
7FFFh
8001h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
Note 1:
2:
FFFEh
Data memory areas are not shown to scale.
Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 25
PIC24FJ64GA004 FAMILY
3.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
3.2.3
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
3.2.4
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
SFR SPACE
The first 2 Kbytes of the near data space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where SFRs are actually implemented, is
shown in Table 3-2. Each implemented area indicates
a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented
SFRs, including their addresses, is shown in Tables 3-3
through 3-24.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
TABLE 3-2:
NEAR DATA SPACE
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
000h
xx60
Core
100h
200h
xx40
Timers
I
2C™
300h
ICN
Capture
UART
A/D
xx80
—
SPI
xxA0
xxC0
xxE0
Interrupts
Compare
—
—
—
—
—
—
I/O
—
—
—
—
—
—
400h
—
—
—
—
—
—
—
—
500h
—
—
—
—
—
—
—
—
600h
PMP
RTC/Comp
CRC
—
700h
—
—
System
NVM/PMD
—
—
—
—
PPS
Legend: — = No implemented SFRs in this block
DS39881B-page 26
Preliminary
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
Preliminary
0052
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DISICNT
Legend:
CN29IE
CN30IE
—
CNEN2 0062
Legend:
Note 1:
(1)
CN26IE(1)
—
IPL1
—
IPL0
CN6PUE
CN5PUE
CN21IE
CN5IE
Bit 5
CN4PUE
CN20IE(1)
CN4IE
Bit 4
—
RA
CN3PUE
CN19IE(1)
CN3IE
Bit 3
IPL3
N
CN2PUE
CN18IE(1)
CN2IE
Bit 2
PSV
OV
Program Space Visibility Page Address Register
Table Memory Page Address Register
CN1PUE
CN17IE(1)
CN1IE
Bit 1
—
Z
Bit 1
CN16IE
CN0IE
Bit 0
—
C
Bit 0
0000
0000
All
Resets
xxxx
0000
0000
xxxx
0000
0000
0000
0000
xxxx
0800
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
Resets
0000
CN7PUE
CN22IE
CN6IE
Bit 6
Bit 2
0000
CN8PUE
CN23IE
CN7IE
Bit 7
Bit 3
CN0PUE
CN9PUE
(1)
CN24IE
CN8IE(1)
Bit 8
—
IPL2
Bit 4
Program Counter High Byte Register
Disable Interrupts Counter Register
—
DC
Repeat Loop Counter Register
—
—
—
Working Register 15
Bit 5
CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE
(1)
CN25IE(1)
CN9IE(1)
CN10IE(1)
—
—
—
Bit 9
—
—
—
—
Bit 10
—
—
CN11PUE CN10PUE
CN27IE
CN28IE(1)
CN12PUE
CN11IE
CN12IE
Bit 12
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bits not available on 28-pin devices; read as ‘0’.
—
CNPU1 0068 CN15PUE CN14PUE CN13PUE
CN13IE
CN14IE
CN15IE
CNEN1 0060
Bit 13
Bit 14
CNPU2 006A
—
—
ICN REGISTER MAP
—
—
—
Bit 15
File
Addr
Name
—
—
—
Bit 11
0044
TABLE 3-4:
0042
CORCON
—
—
SR
—
—
0036
—
—
RCOUNT
—
—
0034
—
PSVPAG
—
0032
TBLPAG
—
Program Counter Low Byte Register
0030
—
002E
PCL
PCH
—
0020
—
Stack Pointer Limit Value Register
001E
WREG15
SPLIM
Working Register 13
Working Register 14
001A
001C
WREG13
Working Register 12
Working Register 9
Working Register 8
Working Register 7
Working Register 6
Working Register 5
Working Register 4
Bit 6
WREG14
—
0014
WREG10
—
0012
WREG9
—
Working Register 11
0010
WREG8
0016
000E
WREG7
0018
000C
WREG6
WREG11
000A
WREG5
WREG12
Working Register 10
0008
Working Register 3
Working Register 2
Working Register 1
Working Register 0
WREG4
Bit 7
0006
Bit 8
WREG3
Bit 9
0004
Bit 10
WREG2
Bit 11
0002
Bit 12
0000
Bit 13
WREG1
Bit 14
WREG0
Bit 15
Addr
CPU CORE REGISTERS MAP
File
Name
TABLE 3-3:
PIC24FJ64GA004 FAMILY
DS39881B-page 27
DS39881B-page 28
Preliminary
00B2
00B4
00B6
00B8
00BA
00BC
00C2
00C4
00C8
IPC7
IPC8
IPC9
IPC10
IPC11
IPC12
IPC15
IPC16
IPC18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U2TXIE
—
—
—
—
U2TXIF
—
ALTIVT
NSTDIS
Bit 15
—
AD1IF
T2IP1
T1IP1
—
—
PMPIE
INT2IE
AD1IE
—
—
PMPIF
INT2IF
T2IP0
T1IP0
—
—
—
T5IE
U1TXIE
—
—
—
T5IF
U1TXIF
—
—
Bit 12
—
CRCIP2
—
—
—
—
IC5IP2
—
U2TXIP2
T4IP2
—
CNIP2
—
—
CRCIP1
—
—
—
—
IC5IP1
—
U2TXIP1
T4IP1
—
CNIP1
—
—
CRCIP0
—
—
—
—
IC5IP0
—
U2TXIP0
T4IP0
—
CNIP0
—
U1RXIP2 U1RXIP1 U1RXIP0
T2IP2
T1IP2
—
RTCIE
—
U2RXIE
—
—
RTCIF
—
U2RXIF
—
—
—
DISI
Bit 13
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T4IE
U1RXIE
—
—
—
T4IF
U1RXIF
—
—
Bit 11
OC4IP1
—
CMIP1
—
SPI1IP1
OC2IP1
OC1IP1
—
—
OC5IE
OC3IE
SPF1IE
—
—
OC5IF
OC3IF
SPF1IF
—
—
Bit 9
OC4IP0
—
CMIP0
—
SPI1IP0
OC2IP0
OC1IP0
LVDIE
—
—
—
T3IE
LVDIF
—
—
—
T3IF
—
—
Bit 8
—
—
—
IC4IP1
—
—
—
IC4IP0
RTCIP1
RTCIP0
—
—
—
U2ERIP2 U2ERIP1 U2ERIP0
RTCIP2
MI2C2P2 MI2C2P1 MI2C2P0
—
—
IC4IP2
—
U2RXIP2 U2RXIP1 U2RXIP0
OC4IP2
—
CMIP2
—
SPI1IP2
OC2IP2
OC1IP2
—
—
—
OC4IE
SPI1IE
—
—
—
OC4IF
SPI1IF
—
—
Bit 10
INTERRUPT CONTROLLER REGISTER MAP
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
00B0
IPC6
Legend:
00AE
00A8
IPC2
IPC5
00A6
IPC1
00AA
00A4
IPC0
00AC
009C
IEC4
IPC4
009A
IEC3
IPC3
0096
0098
0094
IEC0
IEC1
008C
IFS4
IEC2
0088
008A
0086
IFS1
IFS3
0084
IFS0
IFS2
0080
0082
INTCON1
INTCON2
Addr
File
Name
TABLE 3-5:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC5IE
—
T2IE
—
—
IC5IF
—
T2IF
—
—
Bit 7
AD1IP1
SPF1IP1
IC2IP1
IC1IP1
—
—
IC3IE
—
IC2IE
—
—
IC3IF
—
IC2IF
—
—
Bit 5
—
SI2C2P1
PMPIP1
OC5IP1
IC3IP1
SPI2IP1
INT2IP1
OC3IP1
—
—
—
U1ERIP2 U1ERIP1
—
SI2C2P2
PMPIP2
OC5IP2
IC3IP2
SPI2IP2
INT2IP2
OC3IP2
—
MI2C1P2 MI2C1P1
AD1IP2
SPF1IP2
IC2IP2
IC1IP2
—
—
IC4IE
—
OC2IE
—
—
IC4IF
—
OC2IF
—
—
Bit 6
Bit 3
Bit 2
Bit 1
—
U1ERIP0
—
SI2C2P0
PMPIP0
OC5IP0
IC3IP0
SPI2IP0
INT2IP0
OC3IP0
—
MI2C1P0
AD1IP0
SPF1IP0
IC2IP0
IC1IP0
—
—
—
INT1IE
—
—
—
—
INT1IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRCIE
—
—
CNIE
T1IE
CRCIF
—
—
CNIF
T1IF
—
LVDIP2
—
—
—
—
—
—
SPF2IP2
T5IP2
—
INT1IP2
SI2C1P2
U1TXIP2
T3IP2
—
INT0IP2
U2ERIE
MI2C2IE
—
CMIE
OC1IE
U2ERIF
MI2C2IF
—
CMIF
OC1IF
INT2EP
LVDIP1
—
—
—
—
—
—
SPF2IP1
T5IP1
—
INT1IP1
SI2C1P1
U1TXIP1
T3IP1
—
INT0IP1
U1ERIE
SI2C2IE
SPI2IE
MI2C1IE
IC1IE
U1ERIF
SI2C2IF
SPI2IF
MI2C1IF
IC1IF
INT1EP
MATHERR ADDRERR STKERR OSCFAIL
Bit 4
LVDIP0
—
—
—
—
—
—
SPF2IP0
T5IP0
—
INT1IP0
SI2C1P0
U1TXIP0
T3IP0
—
INT0IP0
—
—
SPF2IE
SI2C1IE
INT0IE
—
—
SPF2IF
SI2C1IF
INT0IF
INT0EP
—
Bit 0
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
4444
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
Resets
PIC24FJ64GA004 FAMILY
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
Preliminary
011A
011C
011E
0120
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PR4
PR5
T4CON
T5CON
Legend:
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
Bit 13
—
—
—
—
—
Bit 12
—
—
—
—
—
Bit 11
—
—
—
—
—
Bit 10
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
Bit 14
Legend:
—
—
—
—
—
Bit 15
—
—
0150
IC4CON
—
—
0152
014E
IC4BUF
TSIDL
TSIDL
Bit 7
—
Timer2 Register
—
Timer1 Period Register
Timer1 Register
Bit 8
TGATE
Bit 6
Bit 5
TCKPS1
—
—
—
—
Timer4 Register
—
—
Timer3 Period Register
Timer2 Period Register
Timer3 Register
TGATE
TGATE
TCKPS1
TCKPS1
—
—
—
—
—
Bit 9
—
—
Bit 7
—
—
ICTMR
ICTMR
ICTMR
ICTMR
—
ICTMR
Input 5 Capture Register
—
Input 4 Capture Register
—
Input 3 Capture Register
—
Input 2 Capture Register
—
Input 1 Capture Register
Bit 8
—
—
Timer5 Period Register
Timer4 Period Register
Timer5 Register
ICI1
ICI1
ICI1
ICI1
ICI1
Bit 6
TGATE
TGATE
ICI0
ICI0
ICI0
ICI0
ICI0
Bit 5
TCKPS1
TCKPS1
Timer5 Holding Register (for 32-bit operations only)
IC5CON
014C
IC3CON
—
—
INPUT CAPTURE REGISTER MAP
TON
TON
—
—
IC5BUF
0148
014A
IC3BUF
0144
0146
IC2CON
IC1CON
IC2BUF
0140
0142
IC1BUF
Addr
File
Name
TABLE 3-7:
0118
TMR5
—
0116
—
TMR5H
TSIDL
0114
—
—
TMR4
TON
—
0112
TSIDL
T3CON
—
0110
T2CON
TON
010E
PR3
—
Bit 9
Timer3 Holding Register (for 32-bit timer operations only)
010C
—
PR2
—
Bit 10
010A
—
Bit 11
TMR3
TSIDL
Bit 12
0106
—
Bit 13
0108
TON
Bit 14
TMR3H
0104
T1CON
Bit 15
TIMER REGISTER MAP
TMR2
0100
0102
PR1
Addr
TMR1
File
Name
TABLE 3-6:
ICOV
ICOV
ICOV
ICOV
ICOV
Bit 4
TCKPS0
TCKPS0
TCKPS0
TCKPS0
TCKPS0
Bit 4
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
Bit 3
—
T32
—
T32
—
Bit 3
ICM2
ICM2
ICM2
ICM2
ICM2
Bit 2
—
—
—
—
TSYNC
Bit 2
ICM1
ICM1
ICM1
ICM1
ICM1
Bit 1
TCS
TCS
TCS
TCS
TCS
Bit 1
ICM0
ICM0
ICM0
ICM0
ICM0
Bit 0
—
—
—
—
—
Bit 0
0000
FFFF
0000
FFFF
0000
FFFF
0000
FFFF
0000
FFFF
All
Resets
0000
0000
FFFF
FFFF
0000
0000
0000
0000
0000
FFFF
FFFF
0000
0000
0000
0000
FFFF
0000
All
Resets
PIC24FJ64GA004 FAMILY
DS39881B-page 29
DS39881B-page 30
018C
018E
0190
0192
0194
0196
0198
019A
019C
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
OC3RS
OC3R
OC3CON
OC4RS
OC4R
OC4CON
OC5RS
OC5R
OC5CON
Legend:
Preliminary
ACKSTAT
—
0212
0214
0216
0218
I2C2BRG
I2C2CON
I2C2STAT
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCL
Legend:
—
—
—
A10M
—
—
—
—
—
021A
—
—
IPMIEN
—
—
—
—
—
BCL
A10M
—
—
—
Bit 10
—
—
—
—
021C
SCLREL
—
—
—
I2CSIDL
—
—
—
—
—
IPMIEN
—
—
—
Bit 11
—
—
—
—
I2C2ADD
TRSTAT
—
—
—
—
—
—
—
—
—
SCLREL
—
—
—
Bit 12
I2CSIDL
—
—
—
Bit 13
—
—
—
—
I2C2MSK
I2CEN
—
—
—
—
I2C2TRN
—
—
—
TRSTAT
—
—
AKSTAT
0210
0208
I2C1STAT
I2CEN
I2C2RCV
0206
I2C1CON
—
020A
0204
I2C1BRG
—
—
—
—
020C
0202
Bit 14
Bit 15
I2C1ADD
0200
I2C1RCV
I2C1TRN
—
—
—
—
I2C™ REGISTER MAP
—
—
—
—
I2C1MSK
Addr
File
Name
TABLE 3-9:
018A
—
OC2CON
—
0188
—
0186
OCSIDL
OC2R
—
OC2RS
—
0184
Bit 10
OC1CON
Bit 11
0182
Bit 12
0180
Bit 13
OC1R
Bit 14
OC1RS
Bit 15
Addr
OUTPUT COMPARE REGISTER MAP
File
Name
TABLE 3-8:
Bit 8
Bit 7
Bit 6
—
—
—
—
—
—
—
—
—
—
—
—
AMSK9
GCSTAT
DISSLW
—
—
—
AMSK9
GCSTAT
DISSLW
—
—
—
Bit 9
—
AMSK8
ADD10
SMEN
—
—
AMSK8
ADD10
SMEN
—
—
Bit 8
—
AMSK7
IWCOL
GCEN
AMSK7
IWCOL
GCEN
Bit 7
—
Output Compare 5 Register
AMSK6
I2COV
STREN
AMSK6
I2COV
STREN
Bit 6
—
Output Compare 5 Secondary Register
—
Output Compare 4 Register
Output Compare 4 Secondary Register
—
Output Compare 3 Register
Output Compare 3 Secondary Register
—
Output Compare 2 Register
Output Compare 2 Secondary Register
—
Output Compare 1 Register
Output Compare 1 Secondary Register
Bit 9
Bit 3
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
Bit 3
Transmit Register 1
Receive Register 1
Bit 4
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
Bit 4
P
ACKEN
AMSK3
Transmit Register 2
Receive Register 2
AMSK4
S
RCEN
P
ACKEN
AMSK5
AMSK4
Address Register 2
D/A
ACKDT
AMSK3
S
RCEN
Baud Rate Generator Register 2
AMSK5
Address Register 1
D/A
AKDT
Baud Rate Generator Register 1
Bit 5
—
—
—
—
—
Bit 5
AMSK2
R/W
PEN
AMSK2
R/W
PEN
Bit 2
OCM2
OCM2
OCM2
OCM2
OCM2
Bit 2
AMSK1
RBF
RSEN
AMSK1
RBF
RSEN
Bit 1
OCM1
OCM1
OCM1
OCM1
OCM1
Bit 1
AMSK‘
TBF
SEN
AMSK‘
TBF
SEN
Bit 0
OCM0
OCM0
OCM0
OCM0
OCM0
Bit 0
0000
0000
0000
1000
0000
00FF
0000
0000
0000
0000
1000
0000
00FF
0000
All
Resets
0000
FFFF
FFFF
0000
FFFF
FFFF
0000
FFFF
FFFF
0000
FFFF
FFFF
0000
FFFF
FFFF
All
Resets
PIC24FJ64GA004 FAMILY
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
Preliminary
0264
0268
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2CON2
SPI2BUF
Legend:
FRMEN
—
SPIFSD
—
—
SPIFPOL
—
SPISIDL
—
DISSCK
—
—
DISSDO
—
—
MODE16
WAKE
Bit 7
LPBACK
Bit 6
URX7
UTX7
URX6
UTX6
URXISEL1 URXISEL0
Bit 9
—
—
UTXBF
UEN1
Bit 8
URX8
UTX8
TRMT
UEN0
—
SMP
—
SMP
LPBACK
—
SSEN
—
Bit 7
URX7
UTX7
—
SSEN
—
CKP
SPIROV
SPI2 Transmit/Receive Buffer
—
CKE
—
—
CKP
SPIROV
Bit 6
URX6
UTX6
SPI1 Transmit/Receive Buffer
—
CKE
WAKE
URCISEL1 URCISEL0
SPIBEC2 SPIBEC1 SPIBEC0
—
MODE16
0262
SPIEN
—
URX8
UTX8
TRMT
UEN0
Bit 8
Baud Rate Generator Prescaler Register
—
—
UTXBF
UEN1
Bit 9
SPIBEC2 SPIBEC1 SPIBEC0
SPI2CON1
—
DISSDO
0260
—
DISSCK
0248
SPIFPOL
—
SPI2STAT
SPIFSD
—
SPI1BUF
FRMEN
—
0244
—
Bit 10
SPI1CON2
SPISIDL
—
Bit 11
0240
SPIEN
Bit 12
0242
Bit 13
Bit 14
—
SPI1STAT
Bit 15
Addr
SPI REGISTER MAP
—
—
SPI1CON1
File Name
TABLE 3-11:
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
UTXEN
—
Legend:
—
—
Baud Rate Generator Prescaler
—
—
UTXBRK
RTSMD
—
—
0238
—
—
IREN
—
—
0236
USIDL
—
—
—
UTXEN
U2BRG
—
—
—
UTXISEL1 UTXINV UTXISEL0
UARTEN
—
—
RTSMD
UTXBRK
U2RXREG
0230
U2MODE
—
—
—
IREN
0232
0228
U1BRG
USIDL
Bit 10
0234
0226
U1RXREG
—
Bit 11
U2TXREG
0224
U1TXREG
UARTEN
UTXISEL1 UTXINV UTXISEL0
Bit 12
U2STA
0220
0222
U1MODE
U1STA
Bit 13
Bit 15
Addr
File Name
Bit 14
UART REGISTER MAP
TABLE 3-10:
—
MSTEN
—
—
MSTEN
—
Bit 5
URX5
UTX5
ADDEN
ABAUD
URX5
UTX5
ADDEN
ABAUD
Bit 5
—
SPRE2
—
—
SPRE2
—
Bit 4
URX4
UTX4
RIDLE
RXINV
URX4
UTX4
RIDLE
RXINV
Bit 4
—
SPRE1
—
—
SPRE1
—
Bit 3
URX3
UTX3
PERR
BRGH
URX3
UTX3
PERR
BRGH
Bit 3
—
SPRE0
—
—
SPRE0
—
Bit 2
URX2
UTX2
FERR
PDSEL1
URX2
UTX2
FERR
PDSEL1
Bit 2
SPIFE
PPRE1
SPITBF
SPIFE
PPRE1
SPITBF
Bit 1
URX1
UTX1
OERR
PDSEL0
URX1
UTX1
OERR
PDSEL0
Bit 1
SPIBEN
PPRE0
SPIRBF
SPIBEN
PPRE0
SPIRBF
Bit 0
URX0
UTX0
URXDA
STSEL
URX0
UTX0
URXDA
STSEL
Bit 0
0000
0000
0000
0000
0000
0000
0000
0000
All
Resets
0000
0000
0000
0110
0000
0000
0000
0000
0110
0000
All
Resets
PIC24FJ64GA004 FAMILY
DS39881B-page 31
DS39881B-page 32
02C4
02C6
LATA
ODCA
—
—
—
—
Bit 14
Preliminary
—
—
—
—
Bit 12
—
—
—
—
Bit 11
Bit 14
Bit 12
ODB13
ODB12
LATB12
RB12
— = unimplemented, read as ‘0’
Bits not available on 28-pin devices; read as ‘0’.
Legend:
Note 1:
Bit 9
Bit 8
Bit 7
RA9(1)
LATA9(1)
ODA9(1)
RA10(1)
LATA10(1)
ODA10(1)
ODA8(1)
LATA8(1)
RA8(1)
ODA7(1)
LATA7(1)
RA7(1)
TRISA10(1) TRISA9(1) TRISA8(1) TRISA7(1)
Bit 10
Bit 11
—
—
—
—
—
—
—
—
—
Bit 11
ODB11
LATB11
RB11
—
—
—
—
Bit 10
ODB10
LATB10
RB10
TRISB10
Bit 10
—
— = unimplemented, read as ‘0’
—
02FC
PADCFG1
Bit 14
Legend:
Bit 15
Addr
—
Bit 13
—
Bit 12
—
Bit 11
—
Bit 10
PAD CONFIGURATION REGISTER MAP
—
—
File Name
TABLE 3-15:
02D6
ODCC(1)
—
—
—
02D4
—
—
LATC(1)
—
—
02D2
—
—
02D0
TRISC(1)
Bit 12
PORTC(1)
Bit 13
Bit 15
Addr
Bit 14
PORTC REGISTER MAP
ODB14
— = unimplemented, read as ‘0’
ODB15
RB13
LATB13
Legend:
LATB14
RB14
02CE
LATB15
RB15
ODCB
TABLE 3-14:
Bit 13
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
Bit 15
PORTB REGISTER MAP
02CC
PORTB
File
Name
—
—
—
—
Bit 13
LATB
02C8
02CA
TRISB
Addr
TABLE 3-13:
File
Name
—
—
—
—
Bit 15
PORTA REGISTER MAP
—
—
—
—
Bit 6
—
—
—
—
Bit 5
ODA4
LATA4
RA4
TRISA4
Bit 4
Bit 2
ODA3(2)
LATA3(2)
RA3(2)
ODA2(3)
LATA2(3)
RA2(3)
TRISA3(2) TRISA2(3)
Bit 3
ODA1
LATA1
RA1
TRISA1
Bit 1
—
Bit 9
ODC9
LATC9
RC9
TRISC9
Bit 9
ODB9
LATB9
RB9
TRISB9
Bit 9
—
Bit 8
OSC8
LATC8
RC8
TRISC8
Bit 8
ODB8
LATB8
RB8
TRISB8
Bit 8
—
Bit 7
ODC7
LATC7
RC7
TRISC7
Bit 7
ODB7
LATB7
RB7
TRISB7
Bit 7
—
Bit 6
ODC6
LATC6
RC6
TRISC6
Bit 6
ODB6
LATB6
RB6
TRISB6
Bit 6
—
Bit 5
ODC5
LATC5
RC5
TRISC5
Bit 5
ODB5
LATB5
RB5
TRISB5
Bit 5
—
Bit 4
ODC4
LATC4
RC4
TRISC4
Bit 4
ODB4
LATB4
RB4
TRISB4
Bit 4
—
Bit 3
ODC3
LATC3
RC3
TRISC3
Bit 3
ODB3
LATB3
RB3
TRISB3
Bit 3
—
Bit 2
ODC2
LATC2
RC2
TRISC2
Bit 2
ODB2
LATB2
RB2
TRISB2
Bit 2
Bit 0
ODC0
LATC0
RC0
TRISC0
Bit 0
ODB0
LATB0
RB0
TRISB0
Bit 0
ODA0
LATA0
RA0
TRISA0
Bit 0
RTSECSEL PMPTTL
Bit 1
ODC1
LATC1
RC1
TRISC1
Bit 1
ODB1
LATB1
RB1
TRISB1
Bit 1
— = unimplemented, read as ‘0’.
Bits are not available on 28-pin devices; read as ‘0’.
Bits are available only when the primary oscillator is disabled (POSCMD<1:0> = 00); otherwise read as ‘0’.
Bits are available only when the primary oscillator is disabled or EC mode is selected (POSCMD<1:0> = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise, read as ‘0’.
02C2
PORTA
Legend:
Note 1:
2:
3:
02C0
Addr
TRISA
File
Name
TABLE 3-12:
0000
All
Resets
0000
0000
0000
03FF
All
Resets
0000
0000
0000
FFFF
All
Resets
0000
0000
0000
079F
All
Resets
PIC24FJ64GA004 FAMILY
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
030E
0310
0312
0314
0316
0318
031A
031C
AD1BUF7
AD1BUF8
AD1BUF9
AD1BUFA
AD1BUFB
AD1BUFC
AD1BUFD
AD1BUFE
032C
0330
— = unimplemented, read as ‘0’
AD1CSSL
Legend:
Preliminary
Legend:
IBOV
—
— = unimplemented, read as ‘0’.
IBF
—
—
—
IB3F
—
060E
PTEN14
PMSTAT
—
060C
IB2F
PTEN10
IB1F
PTEN9
IB0F
PTEN8
OBE
PTEN7
OBUF
PTEN6
Parallel Port Data In Register 2 (Buffers 2 and 3)
PMAEN
ADDR6
060A
ADDR7
PMDIN2
ADDR8
CSF0
WAITB0
Parallel Port Data In Register 1 (Buffers 0 and 1)
ADDR9
CSF1
WAITB1
0608
ADDR10
MODE0
PMDIN1
—
MODE1
Parallel Port Data Out Register 2 (Buffers 2 and 3)
—
MODE16
Bit 6
CSSL6
PCFG6
—
ADCS6
—
SSRC1
PMDOUT2 0606
—
INCM0
Bit 7
CSSL7
PCFG7
CH0NA
ADCS7
BUFS
SSRC2
Parallel Port Data Out Register 1 (Buffers 0 and 1)
CS1
Bit 8
CSSL8
PCFG8
CH0SB0
SAMC0
—
FORM0
ADC Data Buffer 15
ADC Data Buffer 14
ADC Data Buffer 13
ADC Data Buffer 12
ADC Data Buffer 11
ADC Data Buffer 10
ADC Data Buffer 9
ADC Data Buffer 8
ADC Data Buffer 7
ADC Data Buffer 6
ADC Data Buffer 5
ADC Data Buffer 4
ADC Data Buffer 3
ADC Data Buffer 2
ADC Data Buffer 1
Bit 6
PMDOUT1
—
INCM1
Bit 7
ADC Data Buffer 0
Bit 8
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
Bit 9
0604
PSIDL
IRQM0
—
IRQM1
Bit 10
PMADDR
BUSY
Bit 11
PMPEN
Bit 12
0602
Bit 13
Bit 14
0600
CSSL9
PMCON
CSSL10
PCFG9
PMMODE
CSSL11
PCFG10
CH0SB1
SAMC1
—
FORM1
Bit 9
Bit 15
CSSL12
PCFG11
CH0SB2
SAMC2
CSCNA
—
Bit 10
File Name Addr
—
PCFG12
CH0SB3
SAMC3
—
—
Bit 11
PARALLEL MASTER/SLAVE PORT REGISTER MAP
—
—
—
—
SAMC4
—
—
Bit 12
TABLE 3-17:
—
—
—
—
—
—
AD1PCFG
ADRC
CH0NB
0324
0328
VCFG0
VCFG1
ADSIDL
AD1CHS0
VCFG2
—
AD1CON3
0322
030C
AD1BUF6
AD1CON2
030A
AD1BUF5
ADON
0308
AD1BUF4
0320
0306
AD1BUF3
031E
0304
AD1BUF2
AD1BUFF
0302
AD1BUF1
AD1CON1
0300
AD1BUF0
Bit 13
Bit 15
Addr
File Name
Bit 14
ADC REGISTER MAP
TABLE 3-16:
—
PTEN5
ADDR5
WAITM3
ALP
Bit 5
CSSL5
PCFG5
—
ADCS5
SMPI3
SSRC0
Bit 5
—
PTEN4
ADDR4
WAITM2
—
Bit 4
CSSL4
PCFG4
—
ADCS4
SMPI2
—
Bit 4
OB3E
PTEN3
ADDR3
WAITM1
CS1P
Bit 3
CSSL3
PCFG3
CH0SA3
ADCS3
SMPI1
—
Bit 3
OB2E
PTEN2
ADDR2
WAITM0
BEP
Bit 2
CSSL2
PCFG2
CH0SA2
ADCS2
SMPI0
ASAM
Bit 2
OB1E
PTEN1
ADDR1
WAITE1
WRSP
Bit 1
CSSL1
PCFG1
CH0SA1
ADCS1
BUFM
SAMP
Bit 1
OB0E
PTEN0
ADDR0
WAITE0
RDSP
Bit 0
CSSL0
PCFG0
CH0SA0
ADCS0
ALTS
DONE
Bit 0
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
Resets
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
All
Resets
PIC24FJ64GA004 FAMILY
DS39881B-page 33
0624
0626
— = unimplemented, read as ‘0’
RTCVAL
RCFGCAL
DS39881B-page 34
Legend:
Preliminary
0644
0646
— = unimplemented, read as ‘0’
Legend:
X14
—
Bit 14
CRCWDAT
X15
—
Bit 15
X13
CSIDL
Bit 13
CRC REGISTER MAP
CRCDAT
0640
0642
CRCCON
CRCXOR
Addr
File Name
TABLE 3-20:
— = unimplemented, read as ‘0’
—
—
C2EVT
—
Legend:
—
CVRCON
CMIDL
0630
0632
CMCON
Bit 11
—
C2EN
Bit 11
C1EN
Bit 10
Bit 10
—
Bit 7
Bit 6
ARPT7
ARPT6
Bit 8
Bit 9
—
Bit 8
—
Bit 7
CVREN
CAL6
Bit 6
CVROE
C1OUT
Bit 6
CAL7
C2OUT
Bit 7
RTCPTR0
C2OUTEN C1OUTEN
Bit 9
RTCPTR1
X12
X11
X10
X9
X7
CRC Result Register
CRC Data Input Register
X8
X6
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT
Bit 12
—
C1EVT
Bit 12
Bit 15
Bit 13
Bit 8
CAL5
X5
—
Bit 5
CVRR
C2INV
Bit 4
CVRSS
C1INV
Bit 4
CAL4
ARPT4
Bit 4
X4
CRCGO
ARPT5
Bit 5
Bit 5
RTCC Value Register Window Based on RTCPTR<1:0>
RTCOE
Addr
Bit 14
Bit 9
Alarm Value Register Window Based on APTR<1:0>
Bit 10
AMASK0 ALRMPTR1 ALRMPTR0
File Name
RTCWREN RTCSYNC HALFSEC
AMASK1
Bit 11
DUAL COMPARATOR REGISTER MAP
—
AMASK2
Bit 12
TABLE 3-19:
RTCEN
AMASK3
0622
ALRMEN CHIME
0620
Bit 13
ALCFGRPT
Bit 14
ALRMVAL
Bit 15
Addr
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File Name
TABLE 3-18:
X3
PLEN3
Bit 3
CVR3
C2NEG
Bit 3
CAL3
ARPT3
Bit 3
X2
PLEN2
Bit 2
CVR2
C2POS
Bit 2
CAL2
ARPT2
Bit 2
X1
PLEN1
Bit 1
CVR1
C1NEG
Bit 1
CAL1
ARPT1
Bit 1
—
PLEN0
Bit 0
CVR0
C1POS
Bit 0
CAL0
ARPT0
Bit 0
0000
0000
0000
0040
All
Resets
0000
0000
All
Resets
0000
xxxx
0000
xxxx
All
Resets
PIC24FJ64GA004 FAMILY
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
Preliminary
06D0
06D2
06D4
06D6
06D8
RPOR8
RPOR9
RPOR10
RPOR11
RPOR12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 14
Bit 15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 13
OCFBR3
—
IC4R3
IC2R3
T5CKR3
T3CKR3
—
INTR3
Bit 11
OCFBR2
—
IC4R2
IC2R2
T5CKR2
T3CKR2
—
INTR2
Bit 10
OCFBR1
—
IC4R1
IC2R1
T5CKR1
T3CKR1
—
INTR1
Bit 9
OCFBR0
—
IC4R0
IC2R0
T5CKR0
T3CKR0
—
INTR0
Bit 8
—
—
—
—
RP21R4(1) RP21R3(1) RP21R2(1) RP21R1(1) RP21R0(1)
RP23R4(1) RP23R3(1) RP23R2(1) RP23R1(1) RP23R0(1)
RP25R4(1) RP25R3(1) RP25R2(1) RP25R1(1) RP25R0(1)
—
—
—
—
—
—
—
—
—
—
—
RP19R4(1) RP19R3(1) RP19R2(1) RP19R1(1) RP19R0(1)
RP13R0
RP11R0
RP9R0
RP7R0
RP5R0
RP3R0
RP1R0
—
SCK2R0
—
SCK1R0
—
RP15R1
RP13R1
RP11R1
RP9R1
RP7R1
RP5R1
RP3R1
RP1R1
—
SCK2R1
—
SCK1R1
RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1)
RP15R2
RP13R2
RP11R2
RP9R2
RP7R2
RP5R2
RP3R2
RP1R2
—
SCK2R2
—
SCK1R2
—
RP15R3
RP13R3
RP11R3
RP9R3
RP7R3
RP5R3
RP3R3
RP1R3
—
SCK2R3
—
SCK1R3
—
—
—
—
—
—
—
—
—
—
Bit 7
RP15R0
RP15R4
RP13R4
RP11R4
RP9R4
RP7R4
RP5R4
RP3R4
RP1R4
—
SCK2R4
—
SCK1R4
U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
OCFBR4
—
IC4R4
IC2R4
T5CKR4
T3CKR4
—
INTR4
Bit 12
PERIPHERAL PIN SELECT REGISTER MAP
— = unimplemented, read as ‘0’
Bits only available on the 44-pin devices; otherwise, they read as ‘0’.
06CE
RPOR7
Legend:
Note 1:
06CC
RPOR6
06AE
RPINR23
06CA
06AC
RPINR22
RPOR5
06AA
RPINR21
06C8
06A8
RPINR20
RPOR4
06A6
RPINR19
06C6
06A4
RPINR18
RPOR3
0696
RPINR11
06C4
0692
RPINR9
RPOR2
0690
RPINR8
06C2
068E
RPINR7
RPOR1
0688
RPINR4
06C0
0686
RPINR3
RPOR0
0680
0682
RPINR0
RPINR1
Addr
File
Name
TABLE 3-21:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
RP14R3
RP12R3
RP10R3
RP8R3
RP6R3
RP4R3
RP2R3
RP0R3
SS2R3
SDI2R3
SS1R3
SDI1R3
U2RXR3
U1RXR3
OCFAR3
IC5R3
IC3R3
IC1R3
T4CKR3
T2CKR3
INTR3
—
Bit 3
RP14R2
RP12R2
RP10R2
RP8R2
RP6R2
RP4R2
RP2R2
RP0R2
SS2R2
SDI2R2
SS1R2
SDI1R2
U2RXR2
U1RXR2
OCFAR2
IC5R2
IC3R2
IC1R2
T4CKR2
T2CKR2
INTR2
—
Bit 2
RP14R1
RP12R1
RP10R1
RP8R1
RP6R1
RP4R1
RP2R1
RP0R1
SS2R1
SDI2R1
SS1R1
SDI1R1
U2RXR1
U1RXR1
OCFAR1
IC5R1
IC3R1
IC1R1
T4CKR1
T2CKR1
INTR1
—
Bit 1
RP14R0
RP12R0
RP10R0
RP8R0
RP6R0
RP4R0
RP2R0
RP0R0
SS2R0
SDI2R0
SS1R0
SDI1R0
U2RXR0
U1RXR0
OCFAR0
IC5R0
IC3R0
IC1R0
T4CKR0
T2CKR0
INTR0
—
Bit 0
RP24R4(1) RP24R3(1) RP24R2(1) RP24R1(1) RP24R0(1)
RP22R4(1) RP22R3(1) RP22R2(1) RP22R1(1) RP22R0(1)
RP20R4(1) RP20R3(1) RP20R2(1) RP20R1(1) RP20R0(1)
RP18R4(1) RP18R3(1) RP18R2(1) RP18R1(1) RP18R0(1)
RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1)
RP14R4
RP12R4
RP10R4
RP8R4
RP6R4
RP4R4
RP2R4
RP0R4
SS2R4
SDI2R4
SS1R4
SDI1R4
U2RXR4
U1RXR4
OCFAR4
IC5R4
IC3R4
IC1R4
T4CKR4
T2CKR4
INTR4
—
Bit 4
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
001F
1F1F
001F
1F1F
1F1F
1F1F
1F1F
001F
1F1F
1F1F
1F1F
1F1F
001F
1F00
All
Resets
PIC24FJ64GA004 FAMILY
DS39881B-page 35
DS39881B-page 36
—
—
CM
VREGS
Bit 6
Bit 5
Bit 4
Bit 3
Preliminary
—
—
0772
0774
— = unimplemented, read as ‘0’
PMD3
Legend:
T5MD
0770
PMD2
—
—
T4MD
—
—
T3MD
Bit 13
PMD1
Bit 14
Bit 15
Addr
File Name
—
PMD REGISTER MAP
—
TABLE 3-24:
—
WRERR
—
IC5MD
T2MD
Bit 12
—
—
—
IC4MD
T1MD
Bit 11
—
—
CMPMD
IC3MD
—
Bit 10
—
—
RTCCMD
IC2MD
—
Bit 9
—
—
PMPMD
IC1MD
—
Bit 8
—
—
CRCPMD
—
I2C1MD
Bit 7
—
—
—
U2MD
Bit 6
ERASE
—
—
U1MD
Bit 5
—
—
OC5MD
SPI2MD
Bit 4
Bit 2
TUN2
—
—
IDLE
Bit 2
Bit 1
TUN1
—
SOSCEN
BOR
Bit 1
(Note 1)
All
Resets
Bit 0
TUN0
—
All
Resets
0000
0100
OSWEN (Note 2)
POR
Bit 0
—
OC4MD
SPI1MD
Bit 3
—
OC3MD
—
Bit 2
I2C2MD
OC2MD
—
Bit 1
—
OC1MD
ADC1MD
Bit 0
0000
0000
0000
All
Resets
0000
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY<7:0>
—
— = unimplemented, read as ‘0’
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
Bit 7
—
TUN3
0766
Bit 8
—
TUN4
Legend:
Note 1:
WREN
Bit 9
—
TUN5
CF
SLEEP
NVMKEY
WR
Bit 10
—
—
—
WDTO
0760
Bit 13
Bit 11
—
—
LOCK
SWDTEN
Bit 3
NVMCON
Bit 14
Bit 12
—
RCDIV0
SWR
IOLOCK
Bit 4
Bit 15
—
RCDIV1
EXTR
CLKLOCK
Bit 5
Addr
—
RCDIV2
NOSC0
Bit 6
File Name
—
DOZEN
NOSC1
Bit 7
NVM REGISTER MAP
—
DOZE0
NOSC2
Bit 8
TABLE 3-23:
—
DOZE1
—
— = unimplemented, read as ‘0’
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on configuration fuses and by type of Reset.
—
DOZE2
COSC0
Legend:
Note 1:
2:
—
ROI
COSC1
0748
COSC2
0744
—
—
Bit 9
OSCTUN
—
IOPUWR
Bit 10
CLKDIV
TRAPR
Bit 11
0740
Bit 12
Bit 13
0742
Bit 14
RCON
Bit 15
Addr
CLOCK CONTROL REGISTER MAP
OSCCON
File
Name
TABLE 3-22:
PIC24FJ64GA004 FAMILY
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2.5
SOFTWARE STACK
3.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-4. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
The Stack Pointer Limit Value register (SPLIM) associated with the Stack Pointer sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM<0> is
forced to ‘0’ because all stack operations must be
word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a
stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the
stack grows beyond address 2000h in RAM, initialize
the SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-4:
Stack Grows Towards
Higher Address
0000h
CALL STACK FRAME
15
0
PC<15:0>
000000000 PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
© 2007 Microchip Technology Inc.
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (program space visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word of the program word.
3.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit of
TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG<7> = 0) or the configuration
memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
define a 16K word page in the program space. When
the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a
23-bit program space address. Unlike table operations,
this limits remapping operations strictly to the user
memory area.
Table 3-25 and Figure 3-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
Preliminary
DS39881B-page 37
PIC24FJ64GA004 FAMILY
TABLE 3-25:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG<7:0>
Data EA<15:0>
0xxx xxxx
xxxx xxxx xxxx xxxx
Configuration
TBLPAG<7:0>
Data EA<15:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
0
0xx xxxx xxxx xxxx xxxx xxx0
Program Space Visibility
(Block Remap/Read)
Note 1:
PC<22:1>
0
User
0
PSVPAG<7:0>
Data EA<14:0>(1)
0
xxxx xxxx
xxx xxxx xxxx xxxx
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
1
EA
0
PSVPAG
0
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of
data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.
DS39881B-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
2.
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the “phantom byte”, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper “phantom” byte is
selected (byte select = 1).
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
data space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper 8 bits of a
program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 3-6:
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 4.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
Note:
Only table read operations will execute in
the configuration memory space, and only
then, in implemented areas such as the
device ID. Table write operations are not
allowed.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA<15:0>
23
15
0
000000h
23
16
8
0
00000000
00000000
020000h
00000000
030000h
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
800000h
© 2007 Microchip Technology Inc.
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
Preliminary
DS39881B-page 39
PIC24FJ64GA004 FAMILY
3.3.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the CPU Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page Address register (PSVPAG). This
8-bit register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 3-7), only the lower 16 bits of the
FIGURE 3-7:
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
000000h
0000h
Data EA<14:0>
010000h
018000h
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
8000h
PSV Area
FFFFh
800000h
DS39881B-page 40
Preliminary
...while the lower 15
bits of the EA specify
an exact address
within the PSV area.
This corresponds
exactly to the same
lower 15 bits of the
actual program space
address.
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.0
Note:
FLASH PROGRAM MEMORY
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory
in blocks of 512 instructions (1536 bytes) at a time.
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
4.1
The PIC24FJ64GA004 family of devices contains internal Flash program memory for storing and executing
application code. The memory is readable, writable and
erasable during normal operation over the entire VDD
range.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG<7:0> bits and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 4-1.
Flash memory can be programmed in four ways:
•
•
•
•
In-Circuit Serial Programming (ICSP)
Run-Time Self-Programming (RTSP)
JTAG
Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
ICSP allows a PIC24FJ64GA004 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (which are named PGCx
and PGDx, respectively), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the microcontroller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FIGURE 4-1:
Table Instructions and Flash
Programming
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
Counter
Program Counter
0
0
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
© 2007 Microchip Technology Inc.
1/0
TBLPAG Reg
8 Bits
16 Bits
24-Bit EA
Preliminary
Byte
Select
DS39881B-page 41
PIC24FJ64GA004 FAMILY
4.2
RTSP Operation
4.4
The PIC24F Flash program memory array is organized
into rows of 64 instructions or 192 bytes. RTSP allows
the user to erase blocks of eight rows (512 instructions)
at a time and to program one row at a time. It is also
possible to program single words.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
64 TBLWT instructions are required to write the full row
of memory.
To ensure that no data is corrupted during a write, any
unused addresses should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding registers can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
Note:
Writing to a page multiple times without
erasing it is not recommended.
All of the table write operations are single-word writes
(2 instruction cycles), because only the buffers are written. A programming cycle is required for programming
each row.
4.3
Enhanced In-Circuit Serial
Programming
Enhanced In-Circuit Serial Programming uses an
on-board boot loader, known as the program executive,
to manage the programming process. Using an SPI
data frame format, the program executive can erase,
program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.
4.5
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 4-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 4.6 “Programming
Operations” for further details.
4.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the
operation is finished.
Configuration Word values are stored in the last two
locations of program memory. Performing a page erase
operation on the last page of program memory clears
these values and enables code protection. As a result,
avoid performing page erase operations on the last
page of program memory.
JTAG Operation
The PIC24F family supports JTAG programming and
boundary scan. Boundary scan can improve the manufacturing process by verifying pin-to-PCB connectivity.
Programming can be performed with industry standard
JTAG programmers supporting Serial Vector Format
(SVF).
DS39881B-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 4-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0(1)
U-0
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
—
ERASE
—
—
NVMOP3(2)
NVMOP2(2)
NVMOP1(2)
NVMOP0(2)
bit 7
bit 0
Legend:
SO = Set-Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit(1)
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit(1)
1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command
0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP3:NVMOP0: NVM Operation Select bits(1,2)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1:
2:
3:
These bits can only be reset on POR.
All other combinations of NVMOP3:NVMOP0 are unimplemented.
Available in ICSP™ mode only. Refer to device programming specification.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 43
PIC24FJ64GA004 FAMILY
4.6.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of program Flash memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 4-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 4-1:
DS39881B-page 44
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 4-3.
ERASING A PROGRAM MEMORY BLOCK
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 4-1).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash
memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority <7
for next 5 instructions
Write the 55 key
Write the AA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
EXAMPLE 4-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
#0x4001, W0
;
MOV
W0, NVMCON
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
#0x0000, W0
;
MOV
W0, TBLPAG
; Initialize PM Page Boundary SFR
MOV
#0x6000, W0
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
#LOW_WORD_0, W2
;
MOV
#HIGH_BYTE_0, W3
;
TBLWTL
W2, [W0]
; Write PM low word into program latch
TBLWTH
W3, [W0++]
; Write PM high byte into program latch
; 1st_program_word
MOV
#LOW_WORD_1, W2
;
MOV
#HIGH_BYTE_1, W3
;
TBLWTL
W2, [W0]
; Write PM low word into program latch
TBLWTH
W3, [W0++]
; Write PM high byte into program latch
; 2nd_program_word
MOV
#LOW_WORD_2, W2
;
MOV
#HIGH_BYTE_2, W3
;
; Write PM low word into program latch
TBLWTL
W2, [W0]
; Write PM high byte into program latch
TBLWTH
W3, [W0++]
•
•
•
; 63rd_program_word
MOV
#LOW_WORD_31, W2
;
MOV
#HIGH_BYTE_31, W3
;
; Write PM low word into program latch
TBLWTL
W2, [W0]
; Write PM high byte into program latch
TBLWTH
W3, [W0]
EXAMPLE 4-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
MOV
MOV
MOV
MOV
BSET
BTSC
BRA
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
NVMCON, #15
$-2
© 2007 Microchip Technology Inc.
; Block all interrupts with priority <7
; for next 5 instructions
;
;
;
;
;
;
Write the 55 key
Write the AA key
Start the erase sequence
and wait for it to be
completed
Preliminary
DS39881B-page 45
PIC24FJ64GA004 FAMILY
4.6.2
PROGRAMMING A SINGLE WORD
OF FLASH PROGRAM MEMORY
If a Flash location has been erased, it can be programmed using table write instructions to write an
instruction word (24-bit) into the write latch. The
TBLPAG register is loaded with the 8 Most Significant
Bytes of the Flash address. The TBLWTL and TBLWTH
EXAMPLE 4-4:
instructions write the desired data into the write latches
and specify the lower 16 bits of the program memory
address to write to. To configure the NVMCON register
for a word write, set the NVMOP bits (NVMCON<3:0>)
to ‘0011’. The write is performed by executing the
unlock sequence and setting the WR bit (see
Example 4-4).
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
; Setup a pointer to data Program Memory
MOV
#tblpage(PROG_ADDR), W0
;
MOV
W0, TBLPAG
;Initialize PM Page Boundary SFR
MOV
#tbloffset(PROG_ADDR), W0
;Initialize a register with program memory address
MOV
MOV
TBLWTL
TBLWTH
#LOW_WORD_N, W2
#HIGH_BYTE_N, W3
W2, [W0]
W3, [W0++]
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
; Setup NVMCON for programming one word to data Program Memory
MOV
#0x4003, W0
;
MOV
W0, NVMCON
; Set NVMOP bits to 0011
DISI
MOV
MOV
MOV
MOV
BSET
#5
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
DS39881B-page 46
; Disable interrupts while the KEY sequence is written
; Write the key sequence
; Start the write cycle
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
5.0
Note:
RESETS
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A Power-on Reset will clear all bits
except for the BOR and POR bits (RCON<1:0>) which
are set. The user may set or clear any bit at any time
during code execution. The RCON bits only serve as
status bits. Setting a particular Reset status bit in
software will not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
•
•
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
POR: Power-on Reset
MCLR: Pin Reset
SWR: RESET Instruction
WDT: Watchdog Timer Reset
BOR: Brown-out Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Opcode Reset
UWR: Uninitialized W Register Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
A simplified block diagram of the Reset module is
shown in Figure 5-1.
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
VDD Rise
Detect
POR
SYSRST
VDD
Brown-out
Reset
BOR
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Uninitialized W Register
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 47
PIC24FJ64GA004 FAMILY
RCON: RESET CONTROL REGISTER(1)
REGISTER 5-1:
R/W-0
TRAPR
bit 15
R/W-0
IOPUWR
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CM
R/W-0
VREGS
bit 8
R/W-0
EXTR
bit 7
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
SLEEP
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
VREGS: Voltage Regulator Standby Enable bit
1 = Regulator remains active during Sleep
0 = Regulator goes to standby during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up From Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.
0 = A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS39881B-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 5-1:
RESET FLAG BIT OPERATION
Flag Bit
Setting Event
Clearing Event
TRAPR (RCON<15>)
Trap Conflict Event
POR
IOPUWR (RCON<14>)
Illegal Opcode or Uninitialized W Register Access
POR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET Instruction
POR
WDTO (RCON<4>)
WDT Time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP Instruction
POR
IDLE (RCON<2>)
PWRSAV #IDLE Instruction
POR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note:
5.1
PWRSAV Instruction, POR
All Reset flag bits may be set or cleared by the user software.
Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 5-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator configuration bits.
Refer to Section 7.0 “Oscillator Configuration” for
further details.
TABLE 5-2:
Reset Type
POR
BOR
MCLR
WDTO
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Oscillator Configuration Bits
(CW2<10:8>)
5.2
Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 5-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time that the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
COSC Control bits
(OSCCON<14:12>)
SWR
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 49
PIC24FJ64GA004 FAMILY
TABLE 5-3:
Reset Type
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Clock Source
SYSRST Delay
EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST
POR
BOR
System Clock
Delay
FSCM
Delay
—
—
Notes
1, 2, 3
ECPLL, FRCPLL
TPOR + TSTARTUP + TRST
TLOCK
TFSCM
1, 2, 3, 5, 6
XT, HS, SOSC
TPOR + TSTARTUP + TRST
TOST
TFSCM
1, 2, 3, 4, 6
XTPLL, HSPLL
TPOR + TSTARTUP + TRST TOST + TLOCK
EC, FRC, FRCDIV, LPRC
TFSCM
1, 2, 3, 4, 5, 6
TSTARTUP + TRST
—
—
2, 3
ECPLL, FRCPLL
TSTARTUP + TRST
TLOCK
TFSCM
2, 3, 5, 6
XT, HS, SOSC
TSTARTUP + TRST
TOST
TFSCM
2, 3, 4, 6
XTPLL, HSPLL
TSTARTUP + TRST
TOST + TLOCK
TFSCM
2, 3, 4, 5, 6
MCLR
Any Clock
TRST
—
—
3
WDT
Any Clock
TRST
—
—
3
Software
Any clock
TRST
—
—
3
Illegal Opcode
Any Clock
TRST
—
—
3
Uninitialized W
Any Clock
TRST
—
—
3
Trap Conflict
Any Clock
TRST
—
—
3
Note 1:
2:
3:
4:
5:
6:
TPOR = Power-on Reset delay (10 μs nominal).
TSTARTUP = TVREG (10 μs nominal) if on-chip regulator is enabled or TPWRT (64 ms nominal) if on-chip
regulator is disabled.
TRST = Internal state Reset time (20 μs nominal).
TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
TLOCK = PLL lock time (20 μs nominal).
TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).
DS39881B-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
5.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
5.2.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
5.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine.
© 2007 Microchip Technology Inc.
FSCM Delay for Crystal and PLL
Clock Sources
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, TFSCM, will
automatically be inserted after the POR and PWRT
delay times. The FSCM will not begin to monitor the
system clock source until this delay expires. The FSCM
delay time is nominally 100 μs and provides additional
time for the oscillator and/or PLL to stabilize. In most
cases, the FSCM delay will prevent an oscillator failure
trap at a device Reset when the PWRT is disabled.
5.3
Special Function Register Reset
States
Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in the CW2 register (see
Table 5-2). The RCFGCAL and NVMCON registers are
only affected by a POR.
Preliminary
DS39881B-page 51
PIC24FJ64GA004 FAMILY
NOTES:
DS39881B-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
6.0
Note:
INTERRUPT CONTROLLER
6.1.1
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
•
•
•
•
Up to 8 processor exceptions and software traps
7 user-selectable priority levels
Interrupt Vector Table (IVT) with up to 118 vectors
A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
6.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 6-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 6-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
6.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset which forces the PC to zero. The microcontroller then begins program execution at location
000000h. The user programs a GOTO instruction at the
Reset address, which redirects program execution to
the appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ64GA004
family
devices
implement
non-maskable traps and unique interrupts. These are
summarized in Table 6-1 and Table 6-2.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 53
PIC24FJ64GA004 FAMILY
FIGURE 6-1:
PIC24F INTERRUPT VECTOR TABLE
Decreasing Natural Order Priority
Reset – GOTO Instruction
Reset – GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
—
—
Interrupt Vector 116
Interrupt Vector 117
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
—
—
Interrupt Vector 116
Interrupt Vector 117
Start of Code
Note 1:
TABLE 6-1:
000000h
000002h
000004h
000014h
00007Ch
00007Eh
000080h
Interrupt Vector Table (IVT)(1)
0000FCh
0000FEh
000100h
000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1)
00017Ch
00017Eh
000180h
0001FEh
000200h
See Table 6-2 for the interrupt vector list.
TRAP VECTOR DETAILS
Vector Number
IVT Address
AIVT Address
Trap Source
0
000004h
000104h
1
000006h
000106h
Oscillator Failure
2
000008h
000108h
Address Error
Reserved
3
00000Ah
00010Ah
Stack Error
4
00000Ch
00010Ch
Math Error
5
00000Eh
00010Eh
Reserved
6
000010h
000110h
Reserved
7
000012h
0001172h
Reserved
DS39881B-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 6-2:
IMPLEMENTED INTERRUPT VECTORS
Interrupt Source
ADC1 Conversion Done
Vector
Number
IVT Address
13
00002Eh
Interrupt Bit Locations
AIVT
Address
Flag
Enable
Priority
00012Eh
IFS0<13>
IEC0<13>
IPC3<6:4>
Comparator Event
18
000038h
000138h
IFS1<2>
IEC1<2>
IPC4<10:8>
CRC Generator
67
00009Ah
00019Ah
IFS4<3>
IEC4<3>
IPC16<14:12>
External Interrupt 0
0
000014h
000114h
IFS0<0>
IEC0<0>
IPC0<2:0>
External Interrupt 1
20
00003Ch
00013Ch
IFS1<4>
IEC1<4>
IPC5<2:0>
External Interrupt 2
29
00004Eh
00014Eh
IFS1<13>
IEC1<13>
IPC7<6:4>
I2C1 Master Event
17
000036h
000136h
IFS1<1>
IEC1<1>
IPC4<6:4>
I2C1 Slave Event
16
000034h
000034h
IFS1<0>
IEC1<0>
IPC4<2:0>
I2C2 Master Event
50
000078h
000178h
IFS3<2>
IEC3<2>
IPC12<10:8>
I2C2 Slave Event
49
000076h
000176h
IFS3<1>
IEC3<1>
IPC12<6:4>
Input Capture 1
1
000016h
000116h
IFS0<1>
IEC0<1>
IPC0<6:4>
Input Capture 2
5
00001Eh
00011Eh
IFS0<5>
IEC0<5>
IPC1<6:4>
Input Capture 3
37
00005Eh
00015Eh
IFS2<5>
IEC2<5>
IPC9<6:4>
Input Capture 4
38
000060h
000160h
IFS2<6>
IEC2<6>
IPC9<10:8>
Input Capture 5
39
000062h
000162h
IFS2<7>
IEC2<7>
IPC9<14:12>
Input Change Notification
19
00003Ah
00013Ah
IFS1<3>
IEC1<3>
IPC4<14:12>
Output Compare 1
2
000018h
000118h
IFS0<2>
IEC0<2>
IPC0<10:8>
Output Compare 2
6
000020h
000120h
IFS0<6>
IEC0<6>
IPC1<10:8>
Output Compare 3
25
000046h
000146h
IFS1<9>
IEC1<9>
IPC6<6:4>
Output Compare 4
26
000048h
000148h
IFS1<10>
IEC1<10>
IPC6<10:8>
Output Compare 5
41
000066h
000166h
IFS2<9>
IEC2<9>
IPC10<6:4>
Parallel Master Port
45
00006Eh
00016Eh
IFS2<13>
IEC2<13>
IPC11<6:4>
Real-Time Clock/Calendar
62
000090h
000190h
IFS3<14>
IEC3<13>
IPC15<10:8>
SPI1 Error
9
000026h
000126h
IFS0<9>
IEC0<9>
IPC2<6:4>
SPI1 Event
10
000028h
000128h
IFS0<10>
IEC0<10>
IPC2<10:8>
SPI2 Error
32
000054h
000154h
IFS2<0>
IEC0<0>
IPC8<2:0>
SPI2 Event
33
000056h
000156h
IFS2<1>
IEC2<1>
IPC8<6:4>
Timer1
3
00001Ah
00011Ah
IFS0<3>
IEC0<3>
IPC0<14:12>
Timer2
7
000022h
000122h
IFS0<7>
IEC0<7>
IPC1<14:12>
Timer3
8
000024h
000124h
IFS0<8>
IEC0<8>
IPC2<2:0>
Timer4
27
00004Ah
00014Ah
IFS1<11>
IEC1<11>
IPC6<14:12>
Timer5
28
00004Ch
00014Ch
IFS1<12>
IEC1<12>
IPC7<2:0>
UART1 Error
65
000096h
000196h
IFS4<1>
IEC4<1>
IPC16<6:4>
IPC2<14:12>
UART1 Receiver
11
00002Ah
00012Ah
IFS0<11>
IEC0<11>
UART1 Transmitter
12
00002Ch
00012Ch
IFS0<12>
IEC0<12>
IPC3<2:0>
UART2 Error
66
000098h
000198h
IFS4<2>
IEC4<2>
IPC16<10:8>
UART2 Receiver
30
000050h
000150h
IFS1<14>
IEC1<14>
IPC7<10:8>
UART2 Transmitter
31
000052h
000152h
IFS1<15>
IEC1<15>
IPC7<14:12>
LVD Low-Voltage Detect
72
0000A4h
000124h
IFS4<8>
IEC4<8>
IPC17<2:0>
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 55
PIC24FJ64GA004 FAMILY
6.3
Interrupt Control and Status
Registers
The PIC24FJ64GA004 family of devices implement a
total of 28 registers for the interrupt controller:
•
•
•
•
•
INTCON1
INTCON2
IFS0 through IFS4
IEC0 through IEC4
IPC0 through IPC12, IPC15, IPC16 and IPC18
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit which is
set by the respective peripherals, or external signal,
and is cleared via software.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 6-2. For example, the INT0 (External
Interrupt 0) is shown as having a vector number and a
natural order priority of 0. Thus, the INT0IF status bit is
found in IFS0<0>, the INT0IE enable bit in IEC0<0>
and the INT0IP<2:0> priority bits in the first position of
IPC0 (IPC0<2:0>).
Although they are not specifically part of the interrupt
control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU
STATUS register (SR) contains the IPL2:IPL0 bits
(SR<7:5>). These indicate the current CPU interrupt
priority level. The user may change the current CPU
priority level by writing to the IPL bits.
The CORCON register contains the IPL3 bit, which
together with IPL2:IPL0, also indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
All interrupt registers are described in Register 6-1
through Register 6-29, in the following pages.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The IPCx registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
DS39881B-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-1:
SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
DC(1)
bit 15
bit 8
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL1(2,3)
IPL0(2,3)
RA(1)
N(1)
OV(1)
Z(1)
C(1)
R/W-0
IPL2
(2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
IPL2:IPL0: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU interrupt priority level is 7 (15). User interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
bit 7-5
Note 1:
2:
3:
See Register 2-1 for the description of the remaining bit (s) that are not dedicated to interrupt control
functions.
The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 6-2:
CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
—
IPL3(2)
PSV(1)
—
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
IPL3: CPU Interrupt Priority Level Status bit(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 8
Note 1:
2:
See Register 2-2 for the description of remaining bit (s) that are not dedicated to interrupt control
functions.
The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 57
PIC24FJ64GA004 FAMILY
REGISTER 6-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
NSTDIS
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14-5
Unimplemented: Read as ‘0’
bit 4
MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
DS39881B-page 58
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ALTIVT
DISI
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use Alternate Interrupt Vector Table
0 = Use standard (default) vector table
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3
Unimplemented: Read as ‘0’
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 59
PIC24FJ64GA004 FAMILY
REGISTER 6-5:
U-0
—
bit 15
R/W-0
T2IF
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
AD1IF
R/W-0
U1TXIF
R/W-0
U1RXIF
R/W-0
SPI1IF
R/W-0
SPF1IF
R/W-0
T3IF
bit 8
R/W-0
OC2IF
R/W-0
IC2IF
U-0
—
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
SPF1IF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Unimplemented: Read as ‘0’
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS39881B-page 60
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-6:
R/W-0
U2TXIF
bit 15
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
U2RXIF
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
U-0
—
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
OC3IF
U-0
—
bit 8
U-0
—
bit 15
R/W-0
OC4IF
W = Writable bit
‘1’ = Bit is set
R/W-0
CMIF
R/W-0
MI2C1IF
R/W-0
SI2C1IF
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
CMIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 61
PIC24FJ64GA004 FAMILY
REGISTER 6-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
U-0
—
—
PMPIF
—
—
—
OC5IF
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
IC5IF
IC4IF
IC3IF
—
—
—
SPI2IF
SPF2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
PMPIF: Parallel Master Port Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-10
Unimplemented: Read as ‘0’
bit 9
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-2
Unimplemented: Read as ‘0’
bit 1
SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
SPI2IF: SPI2 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS39881B-page 62
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
RTCIF
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
MI2C2IF
SI2C2IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 63
PIC24FJ64GA004 FAMILY
REGISTER 6-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
LVDIF
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
CRCIF
U2ERIF
U1ERIF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 8
LVDIF: Low-Voltage Detect Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
U2ERIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
U1ERIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
DS39881B-page 64
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-10:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
bit 15
U-0
—
R/W-0
AD1IE
R/W-0
U1TXIE
R/W-0
U1RXIE
R/W-0
SPI1IE
R/W-0
SPF1IE
R/W-0
T2IE
bit 7
R/W-0
OC2IE
R/W-0
IC2IE
U-0
—
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
W = Writable bit
‘1’ = Bit is set
R/W-0
T3IE
bit 8
R/W-0
INT0IE(1)
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
AD1IE: A/D Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPF1IE: SPI1 Fault Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit(1)
1 = Interrupt request enabled
0 = Interrupt request not enabled
If INTxIE = 1, this external interrupt input must be configured to an available RPx pin. See Section 9.4
”Peripheral Pin Select” for more information.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 65
PIC24FJ64GA004 FAMILY
REGISTER 6-11:
R/W-0
U2TXIE
bit 15
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
U2RXIE
R/W-0
INT2IE(1)
R/W-0
T5IE
R/W-0
T4IE
U-0
—
U-0
—
R/W-0
INT1IE(1)
R/W-0
CNIE
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
OC3IE
U-0
—
bit 8
U-0
—
bit 15
R/W-0
OC4IE
W = Writable bit
‘1’ = Bit is set
R/W-0
CMIE
R/W-0
MI2C1IE
R/W-0
SI2C1IE
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
U2TXIE: UART2 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
INT2IE: External Interrupt 2 Enable bit(1)
1 = Interrupt request enabled
0 = Interrupt request not enabled
T5IE: Timer5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T4IE: Timer4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit(1)
1 = Interrupt request enabled
0 = Interrupt request not enabled
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
CMIE: Comparator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
MI2C1IE: Master I2C1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SI2C1IE: Slave I2C1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
If INTxIE = 1, this external interrupt input must be configured to an available RPx pin. See Section 9.4
”Peripheral Pin Select” for more information.
DS39881B-page 66
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-12:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
U-0
—
—
PMPIE
—
—
—
OC5IE
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
IC5IE
IC4IE
IC3IE
—
—
—
SPI2IE
SPF2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
PMPIE: Parallel Master Port Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12-10
Unimplemented: Read as ‘0’
bit 9
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8
Unimplemented: Read as ‘0’
bit 7
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4-2
Unimplemented: Read as ‘0’
bit 1
SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
SPF2IE: SPI2 Fault Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 67
PIC24FJ64GA004 FAMILY
REGISTER 6-13:
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
RTCIE
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
MI2C2IE
SI2C2IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IE: Master I2C2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
SI2C2IE: Slave I2C2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
Unimplemented: Read as ‘0’
DS39881B-page 68
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-14:
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
LVDIE
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
CRCIE
U2ERIE
U1ERIE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 8
LVDIE: Low-Voltage Detect Interrupt Enable Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2
U2ERIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
U1ERIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 69
PIC24FJ64GA004 FAMILY
REGISTER 6-15:
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T1IP2:T1IP0: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP2:INT0IP0: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS39881B-page 70
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-16:
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T2IP2:T2IP0: Timer2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 71
PIC24FJ64GA004 FAMILY
REGISTER 6-17:
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPF1IP2
SPF1IP1
SPF1IP0
—
T3IP2
T3IP1
T3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP2:T3IP0: Timer3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS39881B-page 72
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-18:
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 73
PIC24FJ64GA004 FAMILY
REGISTER 6-19:
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
MI2C1P2
MI2C1P1
MI2C1P0
—
SI2C1P2
SI2C1P1
SI2C1P0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP2:CNIP0: Input Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMIP2:CMIP0: Comparator Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS39881B-page 74
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-20:
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP2:INT1IP0: External Interrupt 1 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 75
PIC24FJ64GA004 FAMILY
REGISTER 6-21:
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T4IP2:T4IP0: Timer4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS39881B-page 76
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-22:
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP2:INT2IP0: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP2:T5IP0: Timer5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 77
PIC24FJ64GA004 FAMILY
REGISTER 6-23:
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPF2IP2
SPF2IP1
SPF2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS39881B-page 78
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-24:
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 79
PIC24FJ64GA004 FAMILY
REGISTER 6-25:
IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
OC5IP2
OC5IP1
OC5IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 6-26:
IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
PMPIP2
PMPIP1
PMPIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS39881B-page 80
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-27:
IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
MI2C2P2
MI2C2P1
MI2C2P0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
SI2C2P2
SI2C2P1
SI2C2P0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 81
PIC24FJ64GA004 FAMILY
REGISTER 6-28:
IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
RTCIP2
RTCIP1
RTCIP0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS39881B-page 82
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 6-29:
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
CRCIP2
CRCIP1
CRCIP0
—
U2ERIP2
U2ERIP1
U2ERIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
U1ERIP2
U1ERIP1
U1ERIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39881B-page 83
PIC24FJ64GA004 FAMILY
REGISTER 6-30:
IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
LVDIP2
LVDIP1
LVDIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 12-0
LVDIP2:LVDIP0: Low-Voltage Detect Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS39881B-page 84
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
6.4
6.4.3
Interrupt Setup Procedures
6.4.1
INITIALIZATION
To configure an interrupt source:
1.
2.
Set the NSTDIS Control bit (INTCON1<15>) if
nested interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
Note:
3.
4.
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
6.4.2
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
6.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following
procedure:
1.
2.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-15) cannot
be disabled.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., ‘C’ or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of the interrupt that the ISR handles. Otherwise,
the ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 85
PIC24FJ64GA004 FAMILY
NOTES:
DS39881B-page 86
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
7.0
OSCILLATOR
CONFIGURATION
Note:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
• Software-controllable switching between various
clock sources
• Software-controllable postscaler for selective
clocking of CPU for system power savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
The oscillator system for PIC24FJ64GA004 family
devices has the following features:
A simplified diagram of the oscillator system is shown
in Figure 7-1.
PIC24FJ64GA004 FAMILY CLOCK DIAGRAM
PIC24FJ64GA004 Family
Primary Oscillator
XT, HS, EC
OSCO
OSCI
4 x PLL
8 MHz
(nominal)
CLKDIV<10:8>
LPRC
Oscillator
CLKDIV<14:12>
XTPLL, HSPLL
ECPLL,FRCPLL
8 MHz
4 MHz
Postscaler
FRC
Oscillator
CLKO
Postscaler
FIGURE 7-1:
CPU
FRCDIV
Peripherals
FRC
LPRC
31 kHz (nominal)
Secondary Oscillator
SOSC
SOSCO
SOSCI
SOSCEN
Enable
Oscillator
Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Clock Source Option
for Other Modules
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 87
PIC24FJ64GA004 FAMILY
7.1
CPU Clocking Scheme
7.2
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some
operating modes of the primary oscillator.
Oscillator Configuration
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration
registers in the program memory (refer to
Section 23.1 “Configuration Bits” for further
details). The Primary Oscillator Configuration bits,
POSCMD1:POSCMD0 (Configuration Word 2<1:0>),
and the Initial Oscillator Select Configuration bits,
FNOSC2:FNOSC0
(Configuration Word 2<10:8>),
select the oscillator source that is used at a Power-on
Reset. The FRC primary oscillator with postscaler
(FRCDIV) is the default (unprogrammed) selection.
The secondary oscillator, or one of the internal
oscillators, may be chosen by programming these bit
locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 7-1.
7.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM1:FCKSM0 are both programmed (‘00’).
TABLE 7-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Source
POSCMD1:
POSCMD0
FNOSC2:
FNOSC0
Note
Fast RC Oscillator with Postscaler
(FRCDIV)
Internal
00
111
1, 2
(Reserved)
Internal
00
110
1
Oscillator Mode
Low-Power RC Oscillator (LPRC)
Internal
00
101
1
Secondary
00
100
1
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL Module
(FRCPLL)
Internal
00
001
1
Fast RC Oscillator (FRC)
Internal
00
000
1
Secondary (Timer1) Oscillator
(SOSC)
Note 1:
2:
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
DS39881B-page 88
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
7.3
Control Registers
The operation of the oscillator is controlled by three
Special Function Registers:
• OSCCON
• CLKDIV
• OSCTUN
The OSCCON register (Register 7-1) is the main control register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
© 2007 Microchip Technology Inc.
The Clock Divider register (Register 7-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The FRC Oscillator Tune register (Register 7-3) allows
the user to fine tune the FRC oscillator over a range of
approximately ±12%. Each bit increment or decrement
changes the factory calibrated frequency of the FRC
oscillator by a fixed amount.
Preliminary
DS39881B-page 89
PIC24FJ64GA004 FAMILY
REGISTER 7-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
R-0
R-0
R-0
U-0
R/W-x(1)
R/W-x(1)
R/W-x(1)
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
bit 15
bit 8
R/SO-0
R/W-0
R-0(3)
U-0
R/CO-0
U-0
R/W-0
R/W-0
CLKLOCK
IOLOCK(2)
LOCK
—
CF
—
SOSCEN
OSWEN
bit 7
bit 0
Legend:
CO = Clear-Only bit
SO = Set-Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC2:COSC0: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC2:NOSC0: New Oscillator Selection bits(1)
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
IOLOCK: I/O Lock Enable bit(2)
1 = I/O lock is active
0 = I/O lock is not active
bit 5
LOCK: PLL Lock Status bit(3)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Reset values for these bits are determined by the FNOSC Configuration bits.
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected.
DS39881B-page 90
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 7-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2
Unimplemented: Read as ‘0’
bit 1
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits
0 = Oscillator switch is complete
Note 1:
2:
3:
Reset values for these bits are determined by the FNOSC Configuration bits.
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 91
PIC24FJ64GA004 FAMILY
REGISTER 7-2:
R/W-0
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
DOZE2
R/W-0
DOZE1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
DOZE0
DOZEN(1)
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11
DOZEN: DOZE Enable bit(1)
1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio set to 1:1
bit 10-8
RCDIV2:RCDIV0: FRC Postscaler Select bits
111 = 31.25 kHz (divide by 256)
110 = 125 kHz (divide by 64)
101 = 250 kHz (divide by 32)
100 = 500 kHz (divide by 16)
011 = 1 MHz (divide by 8)
010 = 2 MHz (divide by 4)
001 = 4 MHz (divide by 2)
000 = 8 MHz (divide by 1)
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
DS39881B-page 92
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 7-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN5:TUN0: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation
011110 =
•
•
•
000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =
•
•
•
100001 =
100000 = Minimum frequency deviation
7.4
Clock Switching Operation
7.4.1
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
Note:
The primary oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from primary oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
© 2007 Microchip Technology Inc.
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in Flash Configuration Word 2 must be programmed
to ‘0’. (Refer to Section 23.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
Preliminary
DS39881B-page 93
PIC24FJ64GA004 FAMILY
7.4.2
OSCILLATOR SWITCHING
SEQUENCE
A recommended code sequence for a clock switch
includes the following:
At a minimum, performing a clock switch requires this
basic sequence:
1.
1.
2.
2.
3.
4.
5.
If
desired,
read
the
COSCx
bits
(OSCCON<14:12>), to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSCx bits
(OSCCON<10:8>) for the new oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit to initiate the oscillator
switch.
3.
4.
5.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
6.
1.
7.
2.
3.
4.
5.
6.
The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bit values are transferred to the COSCx
bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or SOSC (if SOSCEN remains
set).
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing sensitive code should
not be executed during this time.
8.
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8>
in
two
back-to-back
instructions.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue to execute code that is not clock
sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 7-1.
EXAMPLE 7-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
#OSCCONH, w1
MOV
#0x78, w2
MOV
#0x9A, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Set new oscillator selection
MOV.b
WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV
#OSCCONL, w1
MOV
#0x46, w2
MOV
#0x57, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Start oscillator switch operation
BSET
OSCCON,#0
2: Direct clock switches between any
primary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direction. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
DS39881B-page 94
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
8.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
The PIC24FJ64GA004 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
•
•
•
•
Clock frequency
Instruction-based Sleep and Idle modes
Software controlled Doze mode
Selective peripheral control in software
Combinations of these methods can be used to selectively tailor an application’s power consumption, while
still maintaining critical application features, such as
timing-sensitive communications.
8.1
Clock Frequency and Clock
Switching
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the
process, are discussed in more detail in Section 7.0
“Oscillator Configuration”.
8.2
Instruction-Based Power-Saving
Modes
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAV instruction is shown in Example 8-1.
EXAMPLE 8-1:
PWRSAV
PWRSAV
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
Note:
8.2.1
SLEEP_MODE and IDLE_MODE are constants defined in the assembler include
file for the selected device.
SLEEP MODE
Sleep mode has these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
The device will wake-up from Sleep mode on any of the
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
PWRSAV INSTRUCTION SYNTAX
#SLEEP_MODE
#IDLE_MODE
© 2007 Microchip Technology Inc.
; Put the device into SLEEP mode
; Put the device into IDLE mode
Preliminary
DS39881B-page 95
PIC24FJ64GA004 FAMILY
8.2.2
IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 8.4
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled.
• Any device Reset.
• A WDT time-out.
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
8.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
8.3
Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
while using a power-saving mode may stop
communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock continues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed while the CPU clock speed is reduced.
Synchronization between the two clock domains is
maintained, allowing the peripherals to access the
SFRs while the CPU executes code at a slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE2:DOZE0 bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:256, with 1:1 being the
default.
DS39881B-page 96
It is also possible to use Doze mode to selectively
reduce power consumption in event driven applications. This allows clock sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
8.4
Selective Peripheral Module
Control
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked and thus consume power. There may be cases
where the application needs what these modes do not
provide: the allocation of power resources to CPU
processing with minimal power consumption from the
peripherals.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD control registers.
Both bits have similar functions in enabling or disabling
its associated module. Setting the PMD bit for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
registers will have no effect and read values will be
invalid. Many peripheral modules have a corresponding
PMD bit.
In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. Power consumption
is reduced, but not by as much as the PMD bit does.
Most peripheral modules have an enable bit;
exceptions include capture, compare and RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the
control bit of the generic name format, “XXXIDL”. By
default, all modules that can operate during Idle mode
will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode,
enhancing power savings for extremely critical power
applications.
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
9.0
Note:
I/O PORTS
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
All of the device pins (except VDD, VSS, MCLR and
OSCI/CLKI) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
9.1
Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 9-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
FIGURE 9-1:
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the Output Latch register (LATx),
read the latch. Writes to the latch, write the latch.
Reads from the port (PORTx), read the port pins, while
writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is, nevertheless,
regarded as a dedicated port because there is no
other competing source of outputs.
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
1
Peripheral Output Data
0
PIO Module
1
Output Enable
Output Data
0
Read TRIS
Data Bus
D
WR TRIS
CK
Q
I/O Pin
TRIS Latch
D
WR LAT +
WR PORT
Q
CK
Data Latch
Read LAT
Input Data
Read PORT
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 97
PIC24FJ64GA004 FAMILY
9.1.1
OPEN-DRAIN CONFIGURATION
9.3
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
9.2
Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
9.2.1
I/O PORT WRITE/READ TIMING
The input change notification function of the I/O ports
allows the PIC24FJ64GA004 family of devices to generate interrupt requests to the processor in response to
a change of state on selected input pins. This feature is
capable of detecting input change of states even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, there are up to 22 external signals (CN0 through CN21) that may be selected
(enabled) for generating an interrupt request on a
change of state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin, and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
When the internal pull-up is selected, the pin uses
VDDCORE as the pull-up source voltage. Make sure that
there is no external pull-up source when the internal
pull-ups are enabled, as the voltage difference can
cause a current path.
Note:
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
EXAMPLE 9-1:
MOV
MOV
NOP
BTSS
0xFF00, W0
W0, TRISBB
PORTB, #13
DS39881B-page 98
Input Change Notification
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
PORT WRITE/READ EXAMPLE
;
;
;
;
Configure PORTB<15:8> as inputs
and PORTB<7:0> as outputs
Delay 1 cycle
Next Instruction
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
9.4
Peripheral Pin Select
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices similar
to the PIC24FJ64GA family. In an application that
needs to use more than one peripheral multiplexed on
single pin, inconvenient workarounds in application
code or a complete redesign may be the only option.
A key difference between pin select and non pin select
peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
9.4.2.1
Peripheral Pin Select Function
Priority
The peripheral pin select feature provides an alternative to these choices by enabling the user’s peripheral
set selection and their placement on a wide range of
I/O pins. By increasing the pinout options available on
a particular device, users can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
When a pin selectable peripheral is active on a given
I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Pin select peripherals never take priority
over any analog functions associated with the pin.
The peripheral pin select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. Peripheral pin
select is performed in software and generally does not
require the device to be reprogrammed. Hardware
safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has
been established.
9.4.3
9.4.1
The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on
if an input or an output is being mapped.
AVAILABLE PINS
The peripheral pin select feature is used with a range
of up to 26 pins; the number of available pins is dependent on the particular device and its pincount. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number. See Table 1-2 for pinout
options in each package offering.
9.4.2
AVAILABLE PERIPHERALS
The peripherals managed by the peripheral pin select
are all digital only peripherals. These include general
serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare) and external interrupt
inputs. Also included are the outputs of the comparator
module, since these are discrete digital signals.
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral pin select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs, and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
9.4.3.1
Input Mapping
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 9-1
through Register 9-14). Each register contains two sets
of 5-bit fields, with each set associated with one of the
pin selectable peripherals. Programming a given
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral. For
any given device, the valid range of values for any of
the bit fields corresponds to the maximum number of
peripheral pin selections supported by the device.
The peripheral pin select module is not applied to
I2C™, change notification inputs, RTCC alarm outputs
or peripherals with analog inputs.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 99
PIC24FJ64GA004 FAMILY
TABLE 9-1:
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Name
Register
Configuration
Bits
External Interrupt 1
External Interrupt 2
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
Input Capture 1
Input Capture 2
Input Capture 3
Input Capture 4
Input Capture 5
Output Compare Fault A
Output Compare Fault B
UART1 Receive
INT1
INT2
T2CK
T3CK
T4CK
T5CK
IC1
IC2
IC3
IC4
IC5
OCFA
OCFB
U1RX
RPINR0
RPINR1
RPINR3
RPINR3
RPINR4
RPINR4
RPINR7
RPINR7
RPINR8
RPINR8
RPINR9
RPINR11
RPINR11
RPINR18
INTR1<4:0>
INTR2R<4:0>
T2CKR<4:0>
T3CKR<4:0>
T4CKR<4:0>
T5CKR<4:0>
IC1R<4:0>
IC2R<4:0>
IC3R<4:0>
IC4R<4:0>
IC5R<4:0>
OCFAR<4:0>
OCFBR<4:0>
U1RXR<4:0>
UART1 Clear To Send
UART2 Receive
U1CTS
U2RX
RPINR18
RPINR19
U1CTSR<4:0>
U2RXR<4:0>
Input Name
UART2 Clear To Send
U2CTS
RPINR19
SPI1 Data Input
SDI1
RPINR20
SPI1 Clock Input
SCK1IN
RPINR20
SPI1 Slave Select Input
SS1IN
RPINR21
SPI2 Data Input
SDI2
RPINR22
SPI2 Clock Input
SCK2IN
RPINR22
SPI2 Slave Select Input
SS2IN
RPINR23
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
9.4.3.2
Output Mapping
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains two
5-bit fields; each field being associated with one RPn
pin (see Register 9-15). The value of the bit field corresponds to one of the peripherals and that peripheral’s
output is mapped to the pin (see Table 9-2).
DS39881B-page 100
U2CTSR<4:0>
SDI1R<4:0>
SCK1R<4:0>
SS1R<4:0>
SDI2R<4:0>
SCK2R<4:0>
SS2R<4:0>
Because of the mapping technique, the list of peripherals for output mapping also includes a null value of
‘00000’. This permits any given pin to remain disconnected from the output of any of the pin selectable
peripherals.
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 9-2:
Function
SELECTABLE OUTPUT
SOURCES (MAPS FUNCTION
TO OUTPUT)
Output Function
Number(1)
Output Name
NULL(2)
C1OUT
C2OUT
U1TX
0
1
2
3
NULL
Comparator 1 Output
Comparator 2 Output
UART1 Transmit
U1RTS(3)
U2TX
4
5
UART1 Request To Send
UART2 Transmit
U2RTS(3)
6
UART2 Request To Send
SDO1
7
SPI1 Data Output
SCK1OUT
8
SPI1 Clock Output
SS1OUT
9
SPI1 Slave Select Output
SDO2
10
SPI2 Data Output
SCK2OUT
11
SPI2 Clock Output
SS2OUT
12
SPI2 Slave Select Output
OC1
18
Output Compare 1
OC2
19
Output Compare 2
OC3
20
Output Compare 3
OC4
21
Output Compare 4
OC5
22
Output Compare 5
Note 1: Value assigned to the RPn<4:0> pins corresponds to the peripheral output function
number.
2: The NULL function is assigned to all RPn
outputs at device Reset and disables the
RPn output function.
3: IrDA® BCLK functionality uses this output.
9.4.3.3
Mapping Limitations
The control schema of the peripheral pin select is
extremely flexible. Other than systematic blocks that
prevent signal contention caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
9.4.4
CONTROLLING CONFIGURATION
CHANGES
9.4.4.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed; attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Write 46h to OSCCON<7:0>.
Write 57h to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
9.4.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
9.4.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be configured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CW2<4>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the peripheral pin select control registers cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the peripheral
pin select registers.
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 101
PIC24FJ64GA004 FAMILY
9.4.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control peripheral pin selection introduces
several considerations into application design that
could be overlooked. This is particularly true for several
common peripherals that are available only as
remappable peripherals.
The main consideration is that the peripheral pin
selects are not available on default pins in the device’s
default (Reset) state. Since all RPINRx registers reset
to ‘11111’ and all RPORx registers reset to ‘00000’, all
peripheral pin select inputs are tied to RP31 and all
peripheral pin select outputs are disconnected.
Note:
In tying peripheral pin select inputs to
RP31, RP31 does not have to exist on a
device for the registers to be reset to it.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset.
For application safety, however, it is best to set
IOLOCK and lock the configuration after writing to the
control registers.
Because the unlock sequence is timing critical, it must
be executed as an assembly language routine, in the
same manner as changes to the oscillator configuration. If the bulk of the application is written in C or
another high-level language, the unlock sequence
should be performed by writing inline assembly.
Choosing the configuration requires the review of all
peripheral pin selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a
pin-selectable output to a pin may mean inadvertently
driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured
for operation and enabled, as if it were tied to a fixed pin.
Where this happens in the application code (immediately
following device Reset and peripheral configuration or
inside the main application routine) depends on the
peripheral and its use in the application.
DS39881B-page 102
A final consideration is that peripheral pin select functions neither override analog inputs, nor reconfigure
pins with analog functions for digital I/O. If a pin is
configured as an analog input on device Reset, it must
be explicitly reconfigured as digital I/O when used with
a peripheral pin select.
Example 9-2 shows a configuration for bidirectional
communication with flow control using UART1. The
following input and output functions are used:
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
EXAMPLE 9-2:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
//*************************************
// Unlock Registers
//*************************************
asm volatile ( "MOV
#OSCCON, w1 \n"
"MOV
#0x46, w2
\n"
"MOV
#0x57, w3
\n"
"MOV.b w2, <w1>
\n"
"MOV.b w3, <w1>
\n"
"BCLR OSCCON,#6");
//***************************
// Configure Input Functions
// (See Table 9-1)
//***************************
//***************************
// Assign U1RX To Pin RP0
//***************************
RPINR18bits.U1RXR = 0;
//***************************
// Assign U1CTS To Pin RP1
//***************************
RPINR18bits.U1CTSR = 1;
//***************************
// Configure Output Functions
// (See Table 9-2)
//***************************
//***************************
// Assign U1TX To Pin RP2
//***************************
RPOR1bits.RP2R = 3;
//***************************
// Assign U1RTS To Pin RP3
//***************************
RPOR1bits.RP3R = 4;
//*************************************
// Lock Registers
//*************************************
asm volatile ( "MOV
#OSCCON, w1 \n"
"MOV
#0x46, w2
\n"
"MOV
#0x57, w3
\n"
"MOV.b w2, <w1>
\n"
"MOV.b w3, <w1>
\n"
"BSET
OSCCON, #6" );
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
9.5
Peripheral Pin Select Registers
The PIC24FJ64GA004 family of devices implements a
total of 27 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (14)
• Output Remappable Peripheral Registers (13)
REGISTER 9-1:
Note:
Input and output register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 9.4.4.1 “Control Register
Lock” for a specific command sequence.
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
INTR1R4
INTR1R3
INTR1R2
INTR1R1
INTR1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
INTR1R4:INTR1R0: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 9-2:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
INTR2R4
INTR2R3
INTR2R2
INTR2R1
INTR2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
INTR2R4:INTR2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 103
PIC24FJ64GA004 FAMILY
REGISTER 9-3:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
T3CKR4:T3CKR0: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T2CKR4:T2CKR0: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
REGISTER 9-4:
RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
T5CKR4:T5CKR0: Assign Timer5 External Clock (T5CK) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T4CKR4:T4CKR0: Assign Timer4 External Clock (T4CK) to the Corresponding RPn Pin bits
DS39881B-page 104
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-5:
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
IC2R4:IC2R0: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
IC1R4:IC1R0: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
REGISTER 9-6:
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC4R4
IC4R3
IC4R2
IC4R1
IC4R0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC3R4
IC3R3
IC3R2
IC3R1
IC3R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 105
PIC24FJ64GA004 FAMILY
REGISTER 9-7:
RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
IC5R4
IC5R3
IC5R2
IC5R1
IC5R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
IC5R4:IC5R0: Assign Input Capture 5 (IC5) to the Corresponding RPn Pin bits
REGISTER 9-8:
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
OCFBR4
OCFBR3
OCFBR2
OCFBR1
OCFBR0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
OCFBR4:OCFBR0: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
OCFAR4:OCFAR0: Assign Output Compare Fault B (OCFB) to the Corresponding RPn Pin bits
DS39881B-page 106
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-9:
RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
U1CTSR4:U1CTSR0: Assign UART1 Clear to Send (U1CTS) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
U1RXR4:U1RXR0: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
REGISTER 9-10:
RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 107
PIC24FJ64GA004 FAMILY
REGISTER 9-11:
RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
SCK1R4:SCK1R0: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
SDI1R4:SDI1R0: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
REGISTER 9-12:
RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
SS1R4:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits
DS39881B-page 108
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-13:
RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
SCK2R4:SCK2R0: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn Pin bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
SDI2R4:SDI2R0: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
REGISTER 9-14:
RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 109
PIC24FJ64GA004 FAMILY
REGISTER 9-15:
RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP1R4
RP1R3
RP1R2
RP1R1
RP1R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP0R4
RP0R3
RP0R2
RP0R1
RP0R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP1R4:RP1R0: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP0R4:RP0R0: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-16:
RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP3R4
RP3R3
RP3R2
RP3R1
RP3R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP2R4
RP2R3
RP2R2
RP2R1
RP2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP3R4:RP3R0: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP2R4:RP2R0: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-2 for
peripheral function numbers)
DS39881B-page 110
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-17:
RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP5R4
RP5R3
RP5R2
RP5R1
RP5R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP4R4
RP4R3
RP4R2
RP4R1
RP4R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP5R4:RP5R0: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP4R4:RP4R0: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-18:
RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP7R4
RP7R3
RP7R2
RP7R1
RP7R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP6R4
RP6R3
RP6R2
RP6R1
RP6R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP7R4:RP7R0: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for
peripheral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 111
PIC24FJ64GA004 FAMILY
REGISTER 9-19:
RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP9R4
RP9R3
RP9R2
RP9R1
RP9R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP8R4
RP8R3
RP8R2
RP8R1
RP8R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP9R4:RP9R0: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP8R4:RP8R0: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-20:
RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP11R4
RP11R3
RP11R2
RP11R1
RP11R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP10R4
RP10R3
RP10R2
RP10R1
RP10R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP11R4:RP11R0: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP10R4:RP10R0: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 9-2 for
peripheral function numbers)
DS39881B-page 112
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-21:
RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP13R4
RP13R3
RP13R2
RP13R1
RP13R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP12R4
RP12R3
RP12R2
RP12R1
RP12R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP13R4:RP13R0: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP12R4:RP12R0: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-22:
RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP15R4
RP15R3
RP15R2
RP15R1
RP15R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP14R4
RP14R3
RP14R2
RP14R1
RP14R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP15R4:RP15R0: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for
peripheral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 113
PIC24FJ64GA004 FAMILY
REGISTER 9-23:
RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP17R4
RP17R3
RP17R2
RP17R1
RP17R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP16R4
RP16R3
RP16R2
RP16R1
RP16R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP17R4:RP17R0: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP16R4:RP16R0: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-24:
RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP19R4
RP19R3
RP19R2
RP19R1
RP19R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP18R4
RP18R3
RP18R2
RP18R1
RP18R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP19R4:RP19R0: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP18R4:RP18R0: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 9-2 for
peripheral function numbers)
DS39881B-page 114
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 9-25:
RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP21R4
RP21R3
RP21R2
RP21R1
RP21R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP20R4
RP20R3
RP20R2
RP20R1
RP20R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP21R4:RP21R0: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP20R4:RP20R0: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-2 for
peripheral function numbers)
REGISTER 9-26:
RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP23R4
RP23R3
RP23R2
RP23R1
RP23R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP22R4
RP22R3
RP22R2
RP22R1
RP22R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP23R4:RP23R0: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-2 for
peripheral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 115
PIC24FJ64GA004 FAMILY
REGISTER 9-27:
RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP25R4
RP25R3
RP25R2
RP25R1
RP25R0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RP24R4
RP24R3
RP24R2
RP24R1
RP24R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP25R4:RP25R0: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 9-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP24R4:RP24R0: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-2 for
peripheral function numbers)
DS39881B-page 116
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
10.0
Note:
TIMER1
Figure 10-1 presents a block diagram of the 16-bit
timer module.
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
To configure Timer1 for operation:
1.
2.
3.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter. Timer1
can operate in three modes:
4.
5.
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
6.
Set the TON bit (= 1).
Select the timer prescaler ratio using the
TCKPS1:TCKPS0 bits.
Set the Clock and Gating modes using the TCS
and TGATE bits.
Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
Load the timer period value into the PR1
register.
If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP2:T1IP0, to
set the interrupt priority.
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 10-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS1:TCKPS0
2
TON
SOSCO/
T1CK
1x
SOSCEN
SOSCI
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
TGATE
TCS
TGATE
1
Q
D
0
Q
CK
Set T1IF
0
Reset
TMR1
1
Equal
Comparator
Sync
TSYNC
PR1
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 117
PIC24FJ64GA004 FAMILY
REGISTER 10-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4
TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronize external clock input
0 = Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit
1 = External clock from T1CK pin (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
DS39881B-page 118
Preliminary
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
11.0
TIMER2/3 AND TIMER4/5
To configure Timer2/3 or Timer4/5 for 32-bit operation:
Note 1: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to the associated “PIC24F Family
Reference Manual” chapter.
2: This peripheral contains input functions
that may need to be configured by the
peripheral pin select feature. For more
information, see Section 9.4 “Peripheral
Pin Select”.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent 16-bit
timers with selectable operating modes.
1.
2.
3.
4.
5.
As a 32-bit timer, Timer2/3 and Timer4/5 operate in
three modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
• Single 32-bit timer
• Single 32-bit synchronous counter
6.
The timer value at any point is stored in the register
pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)
always contains the most significant word of the count,
while TMR2 (TMR4) contains the least significant word.
They also support these features:
•
•
•
•
•
Set the T32 bit (T2CON<3> or T4CON<3> = 1).
Select the prescaler ratio for Timer2 or Timer4
using the TCKPS1:TCKPS0 bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to external clock,
RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin
Select” for more information.
Load the timer period value. PR3 (or PR5) will
contain the most significant word of the value
while PR2 (or PR4) contains the least significant
word.
If interrupts are required, set the interrupt enable
bit, T3IE or T5IE; use the priority bits,
T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt
priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3
or Timer5 interrupt.
Set the TON bit (= 1).
To configure any of the timers for individual 16-bit
operation:
Timer gate operation
Selectable prescaler settings
Timer operation during Idle and Sleep modes
Interrupt on a 32-Bit Period register match
ADC Event Trigger (Timer4/5 only)
1.
2.
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the ADC Event
Trigger; this is implemented only with Timer5. The
operating modes and enabled features are determined
by setting the appropriate bit(s) in the T2CON, T3CON,
T4CON and T5CON registers. T2CON and T4CON are
shown in generic form in Register 11-1; T3CON and
T5CON are shown in Register 11-2.
3.
4.
5.
6.
Clear the T32 bit corresponding to that timer
(T2CON<3> for Timer2 and Timer3 or
T4CON<3> for Timer4 and Timer5).
Select the timer prescaler ratio using the
TCKPS1:TCKPS0 bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. See Section 9.4 “Peripheral
Pin Select” for more information.
Load the timer period value into the PRx register.
If interrupts are required, set the interrupt enable
bit, TxIE; use the priority bits, TxIP2:TxIP0, to
set the interrupt priority.
Set the TON bit (TxCON<15> = 1).
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word; Timer3 and Timer4 are
the most significant word of the 32-bit timers.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated with
the Timer3 or Timer5 interrupt flags.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 119
PIC24FJ64GA004 FAMILY
FIGURE 11-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS1:TCKPS0
2
TON
T2CK
(T4CK)
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
TGATE(2)
TGATE
TCS(2)
Q
1
Set T3IF (T5IF)
Q
0
PR3
(PR5)
ADC Event Trigger(3)
Equal
D
CK
PR2
(PR4)
Comparator
MSB
LSB
TMR3
(TMR5)
Reset
TMR2
(TMR4)
Sync
16
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)(1)
16
TMR3H
(TMR5H)
16
Data Bus<15:0>
Note 1:
2:
3:
The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral
Pin Select” for more information.
The ADC Event Trigger is available only on Timer4/5.
DS39881B-page 120
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 11-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
T2CK
(T4CK)
TCKPS1:TCKPS0
2
1x
Gate
Sync
Prescaler
1, 8, 64, 256
01
00
TGATE
TCS(1)
TCY
1
Set T2IF (T4IF)
0
Reset
Equal
Q
D
Q
CK
TGATE(1)
TMR2 (TMR4)
Sync
Comparator
PR2 (PR4)
Note 1:
This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral
Pin Select” for more information.
FIGURE 11-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
T3CK
(T5CK)
Sync
1x
TON
TCKPS1:TCKPS0
2
Prescaler
1, 8, 64, 256
01
00
TGATE
TCY
1
Set T3IF (T5IF)
0
Reset
ADC Event Trigger(2)
Equal
Q
D
Q
CK
TCS(1)
TGATE(1)
TMR3 (TMR5)
Comparator
PR3 (PR5)
Note 1:
2:
This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral
Pin Select” for more information.
The ADC Event Trigger is available only on Timer4/5.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 121
PIC24FJ64GA004 FAMILY
REGISTER 11-1:
TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32(1)
—
TCS(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timerx On bit
When TxCON<3> = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON<3> = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4
TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
T32: 32-Bit Timer Mode Select bit(1)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit(2)
1 = External clock from pin, TxCK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see
Section 9.4 “Peripheral Pin Select”.
DS39881B-page 122
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 11-2:
TyCON: TIMER3 AND TIMER5 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON(1)
—
TSIDL(1)
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE(1)
TCKPS1(1)
TCKPS0(1)
—
—
TCS(1,2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timery On bit(1)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Stop in Idle Mode bit(1)
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4
TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(1,2)
1 = External clock from pin TyCK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral
Pin Select” for more information.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 123
PIC24FJ64GA004 FAMILY
NOTES:
DS39881B-page 124
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
12.0
INPUT CAPTURE
Note 1: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to the associated “PIC24F Family
Reference Manual” chapter.
2: This peripheral contains input functions
that may need to be configured by the
peripheral pin select feature. For more
information, see Section 9.4 “Peripheral
Pin Select”.
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-Bit Timers
TMRy TMRx
16
1
Prescaler
Counter
(1, 4, 16)
ICTMR
(ICxCON<7>)
ICM<2:0> (ICxCON<2:0>)
Mode Select
FIFO
3
0
FIFO
R/W
Logic
Edge Detection Logic
and
Clock Synchronizer
ICx Pin
16
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICI<1:0>
ICxCON
Interrupt
Logic
System Bus
Set Flag ICxIF
(in IFSn Register)
Note 1:
2:
An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4
“Peripheral Pin Select” for more information.
© 2007 Microchip Technology Inc.
Preliminary
DS39881B-page 125
PIC24FJ64GA004 FAMILY
12.1
Input Capture Registers
REGISTER 12-1:
ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
ICSIDL
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
ICTMR
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
ICTMR: Input Capture x Timer Select bit
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5
ICI1:ICI0: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag (Read-Only) bit
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3
ICBNE: Input Capture x Buffer Empty Status (Read-Only) bit
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0
ICM2:ICM0: Input Capture x Mode Select bits(1)
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation
for this mode
000 = Input capture module turned off
Note 1:
RPINRx (ICxRx) must be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
DS39881B-page 126
Preliminary
© 2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
13.0
OUTPUT COMPARE
Note 1: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
2: This peripheral contains input functions
that may need to be configured by the
peripheral pin select feature. For more
information, see Section 9.4 “Peripheral
Pin Select”.
13.1
Setup for Single Output Pulse
Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculat