TI MSP430F123IPW

MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
D Low Supply Voltage Range 1.8 V – 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
– Active Mode: 200 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in 6 µs
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
Basic Clock Module Configurations:
– Various Internal Resistors
– Single External Resistor
– 32 kHz Crystal
– High Frequency Crystal
– Resonator
– External Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D Serial Communication Interface (USART)
D
D
D
D
Software-Selects Asynchronous UART or
Synchronous SPI
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Family Members Include:
MSP430F122: 4KB + 256B Flash Memory
256B RAM
MSP430F123: 8KB + 256B Flash Memory
256B RAM
Available in a 28-Pin Plastic Small-Outline
Wide Body (SOWB) Package and 28-Pin
Plastic Thin Shrink Small-Outline Package
(TSSOP)
For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
DW OR PW PACKAGE
(TOP VIEW)
TEST
VCC
P2.5/Rosc
VSS
XOUT
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TAO
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/CA1/TA2
P2.3/CA0/TA1
P3.7
P3.6
P3.5/URXD0
P3.4/UTXD0
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, – 2003 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
description (continued)
The MSP430F12x series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and
twenty-two I/O pins.The MSP430F12x series also has a built-in communication capability using asynchronous
(UART) and synchronous (SPI) protocols in addition to a versatile analog comparator.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another
area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 28-PIN SOWB
(DW)
PLASTIC 28-PIN TSSOP
(PW)
– 40°C
° to 85°C
°
MSP430F122IDW
MSP430F123IDW
MSP430F122IPW
MSP430F123IPW
functional block diagram
XIN
VCC
XOUT
VSS
RST/NMI
P1.0–7
P3.0-7
JTAG
8
Rosc
ACLK
Oscillator
System Clock
4KB/8KB Flash
+
SMCLK
Flash INFO
256B
RAM
Outx
CCIxA
Power-onReset
TACLK
SMCLK
I/O Port P1
8 I/O’s, All With
Interrupt
Capabililty
I/O
Port P3
MCLK
MAB,
16 bit
CPU
Incl. 16 Reg.
Test
JTAG
MAB, 4 Bit
MCB
MDB,
16 Bit
MDB, 8 Bit
Bus
Conv
TEST
ACLK
SMCLK
Watchdog
Timer
Timer_A
3 CC
Register
15/16 Bit
CCR0/1/2
x = 0, 1, 2
TACLK
or
INCLK
INCLK
Comparator_A
CCI1 Input Multiplexer CCI1
Outx RC Filtered O/P
Out0
Internal Vref
CCIx
Analog Switch CCI0
CCIx
P2.0 / ACLK
P2.1 / INCLK
P2.2 / CAOUT/TA0
2
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USART
I/O Port P2
6 I/O’s All With
Interrupt
Capabililty
UART
Mode
SPI
Mode
ACLK
DCOR
P2.5 / Rosc
P2.4 / CA1/TA2
P2.3 / CA0/TA1
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
I/O
P1.0/TACLK
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
P1.2/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
25
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming
and test
P1.5/TA0/TMS
26
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for
device programming and test
P1.6/TA1/TDI
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
P1.7/TA2/TDO/TDI†
28
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input
during programming
P2.0/ACLK
8
I/O
General-purpose digital I/O pin/ACLK output
P2.1/INCLK
9
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
10
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output
P2.3/CA0/TA1
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input
P2.4/CA1/TA2
20
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input
P2.5/Rosc
P3.0/STE0
3
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
11
I/O
General digital I/O, slave transmit enable—USART0/SPI mode
P3.1/SIMO0
12
I/O
General digital I/O, slave in/master out of USART0/SPI mode
P3.2/SOMI0
13
I/O
General digital I/O, slave out/master in of USART0/SPI mode
P3.3/UCLK0
14
I/O
General digital I/O, external clock input—USART0/UART or SPI mode, clock output—USART0/SPI
mode clock input
P3.4/UTXD0
15
I/O
General digital I/O, transmit data out—USART0/UART mode
P3.5/URXD0
16
I/O
General digital I/O, receive data in—USART0/UART mode
P3.6
17
I/O
General digital I/O
P3.7
18
I/O
General digital I/O
RST/NMI
7
I
Reset or nonmaskable interrupt input
TEST
1
I
Select of test mode for JTAG pins on Port1
VCC
VSS
2
XIN
6
Supply voltage
4
Ground reference
I
Input terminal of crystal oscillator
XOUT
5
I/O Output terminal of crystal oscillator
† TDO or TDI is selected via JTAG instruction.
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3
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 –––> R5
Single operands, destination only
e.g. CALL
PC ––>(TOS), R8––> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
n n
MOV Rs,Rd
MOV R10,R11
Indexed
n n
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
n n
MOV EDE,TONI
M(EDE) ––> M(TONI)
n n
MOV and MEM,and
TCDAT
M(MEM) ––> M(TCDAT)
Absolute
EXAMPLE
OPERATION
R10
––> R11
M(2+R5)––> M(6+R6)
Indirect
n
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ––> M(Tab+R6)
Indirect
autoincrement
n
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ––> R11
R10 + 2––> R10
Immediate
n
MOV #X,TONI
MOV #45,TONI
NOTE: S = source
4
SYNTAX
D = destination
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#45
––> M(TONI)
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
–
All clocks are active
D Low-power mode 0 (LPM0);
–
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
–
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
–
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
–
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
–
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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5
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the memory with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
Power-up, external reset, watchdog
WDTIFG (see Note1)
KEYV (see Note 1)
NMI, oscillator fault, flash memory
access violation
NMIIFG (see Notes 1 and 4)
OFIFG (see Notes 1 and 4)
ACCVIFG (see Notes 1 and 4)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0FFFEh
15, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
Comparator_A
CAIFG
maskable
0FFF6h
11
Watchdog timer
WDTIFG
maskable
0FFF4h
10
Timer_A
TACCR0 CCIFG (see Note 2)
maskable
0FFF2h
9
Timer_A
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)
maskable
0FFF0h
8
USART0 receive
URXIFG0
maskable
0FFEEh
7
USART0 transmit
UTXIFG0
maskable
0FFECh
6
0FFEAh
5
0FFE8h
4
I/O Port P2 (eight flags – see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
maskable
0FFE6h
3
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
maskable
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
NOTES: 1.
2.
3.
4.
6
Multiple source flags
Interrupt flags are located in the module
There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the ’12x devices.
(non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
Address
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
Address
7
6
5
4
3
2
01h
1
UTXIE0
USART0, UART, and SPI receive-interrupt enable
UTXIE0:
USART0, UART, and SPI transmit-interrupt enable
URXIE0
rw-0
rw-0
URXIE0:
0
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
NMIIFG
1
OFIFG
rw-0
rw-1
0
WDTIFG
rw-0
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
Address
7
6
5
4
3
03h
2
1
UTXIFG0
rw-0
URXIFG0:
USART0, UART, and SPI receive flag
UTXIFG0:
USART0, UART, and SPI transmit flag
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0
URXIFG0
rw-0
7
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
module enable registers 1 and 2
Address
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
04h
Address
05h
UTXE0
rw-0
URXE0:
USART0, UART receive enable
UTXE0:
USART0, UART transmit enable
USPIE0:
USART0, SPI (synchronous peripheral interface) transmit and receive enable
Legend
rw:
rw-0:
Bit can be read and written.
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.
memory organization
MSP430F123
MSP430F122
FFFFh
FFE0h
FFDFh
F000h
Int. Vector
4 KB Flash
Segment0–7
FFFFh
FFE0h
FFDFh
Int. Vector
8 KB
Flash
Segment0–15
Main
Memory
E000h
10FFh
1000h
0FFFh
0C00h
2 × 128B
Flash
SegmentA,B
1 KB
Boot ROM
10FFh
1000h
0FFFh
2 × 128B
Flash
SegmentA,B
1 KB
Boot ROM
0C00h
02FFh
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
8
256B RAM
256B RAM
16b Per.
8b Per.
SFR
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0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
16b Per.
8b Per.
SFR
• DALLAS, TEXAS 75265
Information
Memory
0
URXE0
USPIE0
rw-0
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0–n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
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9
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions.
oscillator and system clock
The clock system in the MSP430x12x devices is supported by the basic clock module that includes support for
a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal
oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are three 8-bit I/O ports implemented—ports P1, P2, and P3 (only six port P2 I/O signals are available
on external pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins – but all control and data bits for port
P2 are implemented. Port P3 has no interrupt capability.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430x12x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
comparator_A
The primary function of the comparator_A module is to support precision slope analog–to–digital conversions,
battery–voltage supervision, and monitoring of external analog signals.
10
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MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Flash Memory
Watchdog
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog/timer control
WDTCTL
0120h
TACCR2
TACCR1
TACCR0
TAR
PERIPHERALS WITH BYTE ACCESS
USART0
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
077h
076h
075h
074h
073h
072h
071h
070h
Comparator_A
Comparator_A port disable
Comparator_A control2
Comparator_A control1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
Port P3
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Port P2
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
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11
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special Function
Module enable2
Module enable1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V
Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
recommended operating conditions
MIN
Supply voltage during program execution, VCC (see Note 1)
MSP430F12x
1.8
Supply voltage during program/erase flash memory, VCC
MSP430F12x
2.7
Supply voltage, VSS
NOM
MAX
V
3.6
V
85
°C
0
Operating free-air temperature range, TA
MSP430F12x
LF mode selected, XTS=0
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
V
–40
Watch crystal
32 768
Ceramic resonator
UNITS
3.6
Hz
450
8000
1000
8000
VCC = 1.8 V,
MSP430F12x
dc
4.15
VCC = 3.6 V,
MSP430F12x
dc
8
Flash timing generator frequency, f(FTG)
MSP430F12x
257
476
kHz
Cumulative program time, block write, t(CPT) (see Note 3)
VCC = 2.7 V/3.6 V
MSP430F12x
3
ms
XT1 selected mode, XTS=1
Processor frequency f(system) (MCLK signal)
Low-level input voltage (TEST, RST/NMI), VIL (excluding XIN, XOUT)
VIL(XIN, XOUT)
VIH(XIN, XOUT)
kHz
MHz
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
High-level input voltage (TEST, RST/NMI), VIH (excluding XIN, XOUT)
Input levels at XIN, XOUT
Crystal
VSS
0.8VCC
VSS
VCC = 2.2 V/3 V
VSS+0.6
VCC
0.2×VCC
VCC
0.8×VCC
NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.
2. The LFXT1 oscillator in LF-mode requires a watch crystal.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.
3. The cumulative program time must not be exceeded during a block-write operation.
V
V
V
f (system) – Maximum Processor Frequency – MHz
MSP430F12x Devices
9
8 MHz at
3.6 V
8
7
6
4.15 MHz
at 1.8 V
5
4
3
2
1
0
0
1
2
3
VCC – Supply Voltage – V
4
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum VCC of 2.7 V.
Figure 1. Frequency vs Supply Voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current
PARAMETER
I(AM)
TEST CONDITIONS
Active mode
I(CPUOff)
Low-power mode, (LPM0)
I(LPM2)
Low-power mode, (LPM2)
Low-power mode, (LPM3)
Low-power mode, (LPM4)
MAX
VCC = 2.2 V
200
250
VCC = 3 V
300
350
TA = –40°C +85°C,
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz,
Program executes in Flash
VCC = 2.2 V
3
5
VCC = 3 V
11
18
TA = –40°C +85°C,
f(MCLK) = 0, f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
TA = –40°C +85°C,
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0
VCC = 2.2 V
32
45
VCC = 3 V
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.2
0.7
1
1.6
2.3
1.8
2.2
1.6
1.9
2.3
3.4
0.1
0.5
0.1
0.5
0.8
1.9
TYP
MAX
TA = 85°C
TA = –40°C
VCC = 3 V
TA = –40°C
TA = 25°C
UNIT
µ
µA
VCC = 2.2 V
TA = 25°C
TA = 85°C
I(LPM4)
TYP
TA = –40°C +85°C,
fMCLK = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz,
Program executes in Flash
TA = –40°C
TA = 25°C
I(LPM3)
MIN
VCC = 2.2 V/3 V
TA = 85°C
NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
µ
µA
µ
µA
µ
µA
µA
µ
µA
µ
µA
µ
current consumption of active mode versus system frequency
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage
IAM = IAM[3 V] + 120 µA/V × (VCC–3 V)
Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis, (VIT+ – VIT–)
14
POST OFFICE BOX 655303
MIN
VCC = 2.2 V
VCC = 3 V
1.1
1.5
1.5
1.9
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
0.4
0.9
0.9
1.3
0.3
1.1
VCC = 3 V
0.5
1
• DALLAS, TEXAS 75265
UNIT
V
V
V
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Port 1 to P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VOL
Low-level output voltage
I(OHmax) = –1.5 mA
I(OHmax) = –6 mA
VCC = 2.2 V
I(OHmax) = –1.5 mA
I(OHmax) = –6 mA
VCC = 3 V
I(OLmax) = 1.5 mA
I(OLmax) = 6 mA
VCC = 2.2 V
MIN
See Note 1
MAX
VCC–0.25
VCC–0.6
VCC
VCC
VCC–0.25
VCC–0.6
VCC
VCC
See Note 2
VSS
VSS
VSS+0.25
VSS+0.6
See Note 1
VSS
VSS+0.25
See Note 2
See Note 1
See Note 2
See Note 1
I(OLmax) = 1.5 mA
TYP
UNIT
V
V
VCC = 3 V
I(OLmax) = 6 mA
See Note 2
VSS
VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
outputs – Ports P1, P2, and P3
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
I OL – Typical Low-Level Output Current – mA
I OL – Typical Low-Level Output Current – mA
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
32
28
VCC = 2.2 V
P1.0
TA = 25°C
24
TA = 85°C
20
16
12
8
4
0
0.0
0.5
1.0
1.5
2.0
2.5
50
VCC = 3 V
P1.0
TA = 25°C
40
TA = 85°C
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 2
Figure 3
NOTE: Only one output is loaded at a time.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs – Ports P1, P2, and P3 (continued)
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
I OH – Typical High-Level Output Current – mA
I OH – Typical High-Level Output Current – mA
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
–4
VCC = 2.2 V
P1.0
–8
–12
–16
–20
TA = 85°C
–24
TA = 25°C
–28
0.0
0.5
1.0
1.5
2.0
0
VCC = 3 V
P1.0
–10
–20
–30
–40
TA = 85°C
–50
–60
0.0
2.5
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 5
Figure 4
NOTE: Only one output is loaded at a time.
leakage current
PARAMETER
Ilkg(Px.x)
High-impedance leakage current
TEST CONDITIONS
VCC
MIN
TYP
MAX
Port P1: P1.x, 0 ≤ × ≤ 7
(see Notes 1 and 2)
2.2 V/3 V
±50
Port P2: P2.x, 0 ≤ × ≤ 5
(see Notes 1 and 2)
2.2 V/3 V
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
inputs Px.x, TAx
PARAMETER
t(int)
TEST CONDITIONS
External interrupt timing
t(cap)
Timer_A, capture timing
VCC
2.2 V/3 V
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2 (see Note 2)
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK T(H) = T(L)
f(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
MIN
TYP
MAX
1.5
2.2 V
62
3V
50
2.2 V/3 V
1.5
2.2 V
62
3V
50
UNIT
cycle
ns
cycle
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.
USART (see Note 1)
PARAMETER
t(τ)
USART: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
TYP
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD line.
outputs P1.x, P2.x, P3.x, TAx
PARAMETER
f(P20)
f(TAx)
TEST CONDITIONS
P2.0/ACLK,
Output frequency
CL = 20 pF
TA0, TA1, TA2,
CL = 20 pF,
Internal clock source, SMCLK signal applied (see Note 1)
VCC
2.2 V/3 V
MIN
2.2 V/3 V
dc
fSystem
40%
60%
fSMCLK = fLFXT1 = fXT1
P1.4/SMCLK,
CL = 20 pF
t(Xdc)
Duty cycle of O/P
frequency
fSMCLK = fLFXT1 = fLF
2.2 V/3 V
fSMCLK = fLFXT1/n
fSMCLK = fDCOCLK
2.2 V/3 V
fP20 = fLFXT1 = fXT1
P2.0/ACLK,
CL = 20 pF
fP20 = fLFXT1 = fLF
2.2 V/3 V
35%
65%
50%–
15 ns
50%
50%+
15 ns
50%–
15 ns
50%
50%+
15 ns
40%
60%
30%
70%
fP20 = fLFXT1/n
• DALLAS, TEXAS 75265
MAX
UNIT
fSystem
t(TAdc)
TA0, TA1, TA2,
CL = 20 pF, Duty cycle = 50% 2.2 V/3 V
NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
POST OFFICE BOX 655303
TYP
MHz
50%
0
±50
ns
17
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(DD)
CAON=1, CARSEL=0, CAREF=0
I(Refladder/
RefDiode)
CAON=1, CARSEL=0,
CAREF=1/2/3, No load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V(IC)
V(Ref025)
Common-mode input voltage
Voltage at 0.25 V
V
V(Ref050)
t(response LH)
t(response HL)
node
CC
Voltage at 0.5V
V
CC
CC
node
MIN
TYP
MAX
25
40
3V
45
60
2.2 V
30
50
3V
45
71
CAON =1
2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, TA = 85°C
V(RefVT)
V(offset)
Vhys
CC
VCC
2.2 V
VCC–1
UNIT
µ
µA
µ
µA
V
mV
Offset voltage
See Note 2
2.2 V/3 V
–30
30
mV
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
TA = 25
25°C,
C, Overdrive 10 mV, Without
filter: CAF=0
2.2 V
160
210
300
3V
80
150
240
25°C,
TA = 25
C, Overdrive 10 mV, With filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF=0
2.2 V
130
210
300
3V
80
150
240
TA = 25
25°C,
C,
Overdrive 10 mV, with filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
ns
µ
µs
ns
µ
µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
650
650
VCC = 2.2 V
600
V(REFVT) – Reference Volts –mV
V(REFVT) – Reference Volts –mV
VCC = 3 V
Typical
550
500
450
400
–45
–25
–5
15
35
55
75
600
Typical
550
500
450
400
–45
95
–25
TA – Free-Air Temperature – °C
–5
15
35
55
75
95
TA – Free-Air Temperature – °C
Figure 6. V(RefVT) vs Temperature, VCC = 3 V
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
0 V VCC
0
1
CAF
CAON
Low Pass Filter
V+
V–
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V–
400 mV
V+
t(response)
Figure 9. Overdrive Definition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
150
250
µs
1.4
1.8
V
1.1
1.5
V
0.8
1.2
V
0
0.4
t(POR_Delay)
VPOR
TA = –40°C
TA = 25°C
POR
VCC = 2.2 V/3 V
TA = 85°C
V(min)
t(reset)
PUC/POR
Reset is accepted internally
V
µs
2
V
VCC
V
POR
No POR
POR
V
(min)
POR
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2.0
1.8
1.8
V POR [V]
1.6
1.4
1.2
1.5
Max
1.2
1.4
1.0
Min
1.1
0.8
0.8
0.6
0.4
0.2
25°C
0
–40
–20
0
20
40
60
80
Temperature [°C]
Figure 11. VPOR vs Temperature
RAM
PARAMETER
MIN
NOM
MAX
UNIT
V(RAMh)
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator,LFXT1
PARAMETER
TEST CONDITIONS
VCC
XTS=0; LF mode selected
C(XIN)
TYP
MAX
UNIT
12
2.2 V / 3 V
Input capacitance
pF
XTS=1; XT1 mode selected (see Note 1)
C(XOUT)
MIN
Output capacitance
2
2.2 V / 3 V
XTS=0; LF mode selected
2.2 V / 3 V
12
XTS=1; XT1 mode selected (see Note 1)
2.2 V / 3 V
2
pF
NOTE 1: Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
DCO
PARAMETER
TEST CONDITIONS
VCC
2.2 V
MIN
TYP
MAX
0.08
0.12
0.15
3V
0.08
0.13
0.16
2.2 V
0.14
0.19
0.23
3V
0.14
0.18
0.22
2.2 V
0.22
0.30
0.36
3V
0.22
0.28
0.34
2.2 V
0.37
0.49
0.59
3V
0.37
0.47
0.56
2.2 V
0.61
0.77
0.93
3V
0.61
0.75
0.9
2.2 V
1
1.2
1.5
3V
1
1.3
1.5
2.2 V
1.6
1.9
2.2
3V
1.69
2
2.29
2.2 V
2.4
2.9
3.4
3V
2.7
3.2
3.65
4
4.5
4.9
4.4
4.9
5.4
f(DCO03)
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO13)
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO23)
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO33)
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO43)
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0,
°
TA = 25°C
f(DCO53)
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO63)
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO73)
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0,
°
TA = 25°C
f(DCO77)
Rsel = 7, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
°
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
°
S(Rsel)
SR = fRsel+1/fRsel
2.2 V/3 V
1.35
1.65
2
S(DCO)
SDCO = fDCO+1/fDCO
2.2 V/3 V
1.07
1.12
1.16
2.2 V
–0.31
–0.36
–0.40
Dt
Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1)
3V
–0.33
–0.38
–0.43
DV
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 1)
0
5
10
2.2 V
3V
2.2 V/3 V
2.2 V/3 V
FDCO40 FDCO40 FDCO40
x1.7
x2.1
x2.5
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
%/°C
°
%/V
NOTES: 1. These parameters are not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
f(DCOx7)
f(DCOx0)
Max
Min
Max
Min
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
f DCOCLK
Frequency Variance
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
2.2 V
0
3V
1
2
VCC
3
4
5
6
7
DCO Steps
Figure 12. DCO Characteristics
principle characteristics of the DCO
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
fDCOx0 to fDCOx7 are valid for all devices
D The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO.
D The modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK
cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO × (2MOD/32).
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7.
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
t(LPM0)
t(LPM2)
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
6
t(LPM3)
f(MCLK) = 1 MHz,
f(MCLK) = 2 MHz,
f(MCLK) = 3 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 1 MHz,
f(MCLK) = 2 MHz,
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
6
f(MCLK) = 3 MHz,
NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.
VCC = 2.2 V/3 V
6
t(LPM4)
22
Delay time (see Note 1)
POST OFFICE BOX 655303
UNIT
100
ns
100
• DALLAS, TEXAS 75265
6
6
µs
µ
µs
µ
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG, program memory and fuse
PARAMETER
TEST CONDITIONS
f(TCK)
TCK frequency, JTAG/test (see Note 3)
VCC(FB)
Supply voltage during fuse-blow condition,
T(A) = 25°C
V(FB)
I(FB)
Fuse blow voltage (see Notes 1 and 2)
t(FB)
I(DD-PGM)
Time to blow the fuse (see Note 2)
I(DD-ERASE)
Current during erase cycle (see Note 4)
t(retention)
MIN
VCC = 2.2 V
VCC = 3 V
TYP
dc
5
dc
10
2.5
6
VCC = 2.7 V/3.6 V
VCC = 2.7 V/3.6 V
104
Write/erase cycles
UNIT
MHz
V
7
Supply current on TEST during fuse blow (see Note 2)
Current during program cycle (see Note 4)
MAX
V
100
mA
1
ms
3
5
mA
3
7
mA
105
Data retention TJ = 25°C
100
Year
NOTES: 1. The power source to blow the fuse is applied to TEST pin.
2. Once the JTAG fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass
mode.
3. f(TCK) may be restricted to meet the timing requirements of the module selected.
4. f(TCK) may be restricted to meet the timing requirements of the module selected. Duration of the program/erase cycle is determined
by f(FTG) applied to the flash timing controller. It can be calculated as follows:
t(word write) = 35
1/f(FTG)
t(block write, byte 0) = 30
1/f(FTG)
t(block write, bytes 1–63) = 20
1/f(FTG)
t(block write end sequence) = 6
1/f(FTG)
t(mass erase) = 5297
1/f(FTG)
t(segment erase) = 4819
1/f(FTG)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
1
Module X OUT
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
P1IFG.x
Q
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
P1Sel.2
P1DIR.2
P1DIR.2
P1Sel.3
P1DIR.3
P1DIR.3
† Signal from or to Timer_A
24
P1IN.0
P1OUT.2
VSS
Out0 signal†
Out1 signal†
P1OUT.3
Out2 signal†
P1IN.3
POST OFFICE BOX 655303
P1IN.1
P1IN.2
TACLK†
CCI0A†
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
CCI1A†
CCI2A†
P1IE.2
P1IFG.2
P1IES.2
P1IE.3
P1IFG.3
P1IES.3
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
P1.4–P1.7
1
Module X OUT
TST
Bus Keeper
P1IN.x
EN
Module X IN
P1IRQ.x
DVCC
D
P1IE.x
P1IFG.x
Q
Set
Interrupt
Flag
TEST
60 kΩ
Typical
Interrupt
Edge
Select
EN
Control by
JTAG
P1IES.x
P1SEL.x
Bum
and
Test Fuse
P1.x
TDO
Controlled By JTAG
P1.7/TA2/TDO/TDI
Controlled by JTAG
TDI
TST
P1.x
P1.6/TA1/TDI
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TST
P1.x
TMS
P1.5/TA0/TMS
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
P1Sel.4
P1DIR.4
P1DIR.4
TST
P1.x
TCK
P1.4/SMCLK/TCK
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
Out0 signal†
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out1 signal†
Out2 signal†
† Signal from or to Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
0: Input
1
Direction Control
From Module
1: Output
Pad Logic
0
P2OUT.x
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
1
Module X OUT
Bus Keeper
P2IN.x
EN
D
Module X IN
CAPD.X
P2IRQ.x
P2IE.x
P2IFG.x
Q
Set
Interrupt
Flag
NOTE: x = Bit identifier, 0 to 2 for port P2
Interrupt
Edge
Select
EN
P2IES.x
P2SEL.x
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
P2IFG.0
P1IES.0
P2DIR.1
P2DIR.1
P2OUT.1
P2IN.1
P2IE.1
P2IFG.1
P1IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
VSS
CAOUT
unused
INCLK†
CCI0B†
P2IE.0
P2Sel.1
P2IE.2
P2IFG.2
P1IES.2
P2IN.2
† Signal from or to Timer_A
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
P2DIR.3
0
Direction Control
From Module
P2OUT.3
0: Input
1
1: Output
0
Pad Logic
P2.3/CA0/TA1
1
Module X
OUT
P2IN.3
Bus Keeper
EN
D
Module X IN
P2IE.3
P2IRQ.3
P2IFG.3
EN
Q
Set
Interrupt
Flag
Interrupt
Edge
Select
CAPD.3
Comparator_A
CAREF P2CA CAEX
P2IES.3 P2SEL.3
CAF
+
_
CCI1B
0V
Interrupt
Flag
P2IFG.4
P2IRQ.4
Q
Set
EN
P2IE.4
P2IES.4 P2SEL.4
CAREF
Interrupt
Edge
Select
Reference Block
CAPD.4
D
Module X IN
EN
Bus Keeper
P2IN.4
Module X OUT
P2OUT.4
1
0
Pad Logic
Direction Control
From Module
1
1: Output
P2DIR.4
P2SEL.4
0
P2.4/CA1/TA2
0: Input
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
P2IN.3
unused
P2IE.3
P2IFG.3
P1IES.3
P2DIR.4
P2OUT.4
Out1 signal†
Out2 signal†
P2IN.4
unused
P2IE.4
P2IFG.4
P1IES.4
P2Sel.4 P2DIR.4
† Signal from Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
P2SEL.5
0: Input
1: Output
0
P2DIR.5
Pad Logic
1
Direction Control
From Module
0
P2OUT.5
P2.5/ROSC
1
Module X OUT
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
P2IFG.5
Q
EN
Set
Interrupt
Flag
Internal to
Basic Clock
Module
0
VCC
Interrupt
Edge
Select
P2IES.5
1
DC
Generator
DCOR
P2SEL.5
CAPD.5
NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
VSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x
0: Input
1: Output
0
P2DIR.x
1
Direction Control
From Module
0
P2OUT.x
1
Module X OUT
P2IN.x
Node Is Reset With PUC
EN
Bus Keeper
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
Q
PUC
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x
P2DIR.x
DIRECTIONCONTROL
FROM MODULE
P2OUT.x
MODULE X OUT
P2IN.x
MODULE X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
VSS
VSS
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
Pad Logic
P3OUT.x
Module X OUT
0
P3.0/STE0
1
P3.4/UTXD0
P3.5/URXD0
P3.6
P3.7
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.4
P3DIR.4
P3Sel.5
P3DIR.5
P3Sel.6
P3Sel.7
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
VSS
VCC
P3OUT.0
VSS
UTXD0†
P3IN.0
STE0
P3IN.4
P3OUT.5
Unused
URXD0‡
P3OUT.6
VSS
VSS
P3IN.5
P3DIR.6
VSS
VSS
P3IN.6
Unused
P3DIR.7
VSS
P3OUT.7
VSS
P3IN.7
Unused
P3OUT.4
† Output from USART0 module
‡ Input to USART0 module
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
SYNC
MM
STC
STE
0
P3DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
P3.1/SIMO0
0
P3OUT1
(SI)MO0
From USART0
1
P3IN.1
EN
SI(MO)0
To USART0
30
D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
APPLICATION INFORMATION
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2
SYNC
MM
STC
STE
0
P3DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
P3.2/SOMI0
0
P3OUT.2
SO(MI)0
From USART0
1
P3IN.2
EN
(SO)MI0
To USART0
D
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3
SYNC
MM
STC
STE
0
P3DIR.3
0: Input
1: Output
1
DCM_UCLK
Pad Logic
P3.3/UCLK0
0
P3OUT.3
UCLK.0
From USART0
1
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from from the TEST pin to ground if
the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing
overall system power consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITEST
ITF
Figure 13. Fuse Check Mode Current, MSP430F12x
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also see the bootstrap loader section for more information.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / D 01/00
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430x12x
MIXED SIGNAL MICROCONTROLLER
SLAS312A – JULY 2001 – REVISED MARCH 2003
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
34
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265