DAC7513 DAC 751 3 SBAS157A – OCTOBER 2000 – REVISED MARCH 2003 Low-Power, Rail-to-Rail Output, 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● microPOWER OPERATION: 115µA at 5V ● POWER-ON RESET TO ZERO ● POWER SUPPLY: +2.7V to +5.5V ● ENSURED MONOTONIC BY DESIGN ● SETTLING TIME: 10µs to 1LSB ● LOW-POWER SERIAL INTERFACE WITH SCHMITT-TRIGGERED INPUTS ● ON-CHIP OUTPUT BUFFER AMPLIFIER, RAIL-TO-RAIL OPERATION ● SYNC INTERRUPT FACILITY ● SOT23-8 AND MSOP-8 PACKAGES The DAC7513 is a low-power, single, 12-bit buffered voltage output Digital-to-Analog Connector (DAC). The on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC7513 uses a versatile 3-wire serial interface that operates at clock rates up to 30MHz and is compatible with standard SPI™, QSPI™, Microwire™, and DSP interfaces. The DAC7513 requires an external reference voltage to set the output range of the DAC, this allows the DAC7513 to be used in a multiplying mode. The DAC7513 incorporates a power-on reset circuit which ensures that the DAC output powers up at 0V and remains there until a valid write takes place to the device. The DAC7513 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200nA at 5V. APPLICATIONS ● ● ● ● ● ● The low-power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.5mW at 5V reducing to 1µW in power-down mode. PROCESS CONTROL DATA ACQUISITION SYSTEMS CLOSED-LOOP SERVO-CONTROL PC PERIPHERALS PORTABLE INSTRUMENTATION PROGRAMMABLE ATTENUATION The DAC7513 is available in an SOT23-8 package and an MSOP-8 package. SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor. VDD VFB VREF Ref (+) VOUT 12-Bit DAC 12 DAC Register 12 SYNC CLK DIN Shift Register Power-Down Control Logic Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2000, 2003 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY VDD to GND ........................................................................... –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V VOUT to GND .......................................................... –0.3V to +VDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature Range (TJ max) ........................................ +150°C SOT23 Package: Power Dissipation .................................................... (TJ max – TA)/θJA θJA Thermal Impedance ......................................................... 240°C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215°C Infrared (15s) ........................................................................ +220°C MSOP Package: Power Dissipation .......................................................... (TJ max – TA)/θJA θJA Thermal Impedance ......................................................... 206°C/W θJC Thermal Impedance .......................................................... 44°C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215°C Infrared (15s) ........................................................................ +220°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT DAC7513E " DAC7513N " MINIMUM RELATIVE DIFFERENTIAL ACCURACY NONLINEARITY (LSB) (LSB) PACKAGE-LEAD SPECIFICATION PACKAGE TEMPERATURE PACKAGE DESIGNATOR(1) RANGE MARKING ±8 ±1 MSOP-8 DGK –40°C to +105°C D13E " " " " " " ±8 ±1 SOT23-8 DCN –40°C to +105°C D13N " " " " " " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC7513E/250 DAC7513E/2K5 DAC7513N/250 DAC7513N/3K Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATIONS Top View 2 MSOP-8 SOT23-8 8 SYNC VDD 1 7 SCLK VREF 2 VFB VOUT VOUT 1 VFB 2 VREF 3 6 DIN VDD 4 5 GND DAC7513 8 GND 7 DIN 3 6 SCLK 4 5 SYNC DAC7513 DAC7513 www.ti.com SBAS157A MARKING ARTWORK Top View MSOP-8 SOT23-8 D13N YMLL D13E Pin 1 Identifier Pin 1 Lot Trace Code Bottom View Pin 1 YMLL Model Code (4 Characters Max.) GRS00035 Option 1 Lot Trace Code GRS00035 Option 1 PIN DESCRIPTIONS MSOP-8 SOT23-8 NAME 1 4 VDD Power Supply Input, +2.7V to +5.5V DESCRIPTION 2 3 VREF Reference Voltage Input 3 2 VFB Feedback connection for the output amplifier. 4 1 VOUT 5 8 SYNC Level triggered control input (active LOW), this is the frame sychronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC7513. 6 7 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. 7 6 DIN 8 5 GND Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Serial Data Input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock input. Ground reference point for all circuitry on the part. DAC7513 SBAS157A www.ti.com 3 ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, RL = 2kΩ to GND, and CL = 200pF to GND, unless otherwise noted. DAC7513E, N PARAMETER STATIC PERFORMANCE (1) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUT Reference Current CONDITIONS MIN TYP MAX 12 Tested Monotonic by Design All Zeroes Loaded to DAC Register All Ones Loaded to DAC Register +5 –0.15 ±8 ±1 +20 –1.25 ±1.25 –20 –5 0 1/4 Scale to 3/4 Scale Change (400H to C00H) RL = 2kΩ; 0pF < CL < 200pF RL = 2kΩ; CL = 500pF 8 RL = ∞ RL = 2kΩ 1LSB Change Around Major Carry VDD = +5V VDD = +3V Coming Out of Power-Down Mode VDD = +5V Coming Out of Power-Down Mode VDD = +3V VREF = VDD = +5V VREF = VDD = +3.6V Reference Input Range Reference Input Impedance UNITS Bits LSB LSB mV % of FSR % of FSR µV/°C ppm of FSR/°C VREF V 10 µs 12 1 470 1000 20 0.5 1 50 20 µs V/µs pF pF nV-s nV-s Ω mA mA 2.5 µs 5 µs 17 12 0 25 18 VDD µA µA V kΩ ±1 0.8 0.6 3 µA V V V V pF 5.5 V 300 INPUTS (2) LOGIC Input Current VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (normal mode) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V IDD (all power-down modes) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V POWER EFFICIENCY IOUT/IDD VDD VDD VDD VDD = = = = +5V +3V +5V +3V 2.4 2.1 2.7 DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 115 100 170 145 µA µA VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.05 1 1 µA µA ILOAD = 2mA, VDD = +5V 93 TEMPERATURE RANGE Specified Performance –40 % +105 °C NOTES: (1) Linearity calculated using a reduced code range of 48 to 4047; output unloaded. (2) Ensured by design and characterization, not production tested. 4 DAC7513 www.ti.com SBAS157A TIMING CHARACTERISTICS(1, 2) VDD = +2.7V to +5.5V, all specifications –40°C to +105°C, unless otherwise noted. DAC7513E, N PARAMETER t1(3) t2 t3 t4 t5 t6 t7 t8 DESCRIPTION CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 13 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 22.5 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 5 5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 4.5 4.5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns SCLK Cycle Time SCLK HIGH Time SCLK LOW Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC HIGH Time NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V. SERIAL WRITE OPERATION t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB15 DB0 DAC7513 SBAS157A www.ti.com 5 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C and +VDD = +5V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 1.0 1.0 0.5 0.5 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 0.0 –0.5 –1.0 0.0 –0.5 –1.0 0 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 600H Code E00H FFFH 8 TUE (LSBs) LE (LSB) DLE (LSB) C00H TYPICAL TOTAL UNADJUSTED ERROR 16 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 1.0 0.5 0 –8 0.0 –0.5 –16 –1.0 0 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 20 20 10 10 Error (mV) 30 0 –10 –20 –20 40 A00H C00H E00H FFFH 0 –10 0 800H FULL-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 30 –30 –40 600H Code Code Error (mV) A00H Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 80 –30 –40 120 0 40 80 120 Temperature (°C) Temperature (°C) 6 800H DAC7513 www.ti.com SBAS157A TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C and +VDD = +5V, unless otherwise noted. NOTE: All references to IDD include IREF current. SOURCE AND SINK CURRENT CAPABILITY IDD HISTOGRAM 3000 5 VREF tied to VDD. 2500 DAC Loaded with FFFH 4 VOUT (V) Frequency 2000 1500 3 2 1000 1 500 DAC Loaded with 000H 0 190 180 170 160 150 140 130 120 110 90 100 80 70 60 50 0 0 5 10 15 ISOURCE/SINK (mA) IDD (µA) SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 300 500 VREF tied to VDD. VREF tied to VDD. 250 400 IDD (µA) IDD (µA) 200 300 200 150 100 100 50 0 0 0 200H 400H 600H 800H A00H C00H –40 E00H FFFH 0 40 Code 120 POWER-DOWN CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 100 300 90 VREF tied to VDD. 250 80 70 IDD (nA) 200 IDD (µA) 80 Temperature (°C) 150 100 60 +105°C 50 –40°C 40 30 20 50 +25°C 10 0 0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 5.7 DAC7513 SBAS157A 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) VDD (V) www.ti.com 7 TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C and +VDD = +5V, unless otherwise noted. NOTE: All references to IDD include IREF current. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME 2500 CLK (5V/div) IDD (µA) 2000 1500 VOUT (1V/div) 1000 Full-Scale Code Change 000H to FFFH Output Loaded with 2kΩ and 200pF to GND 500 0 0 1 2 3 4 5 Time (1µs/div) VLOGIC (V) FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) VOUT (1V/div) Full-Scale Code Change FFFH to 000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change 400H to C00H Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) Time (1µs/div) Time (1µs/div) HALF-SCALE SETTLING TIME CLK (5V/div) POWER-ON RESET TO 0V Loaded with 2kΩ to VDD. Half-Scale Code Change C00H to 400H Output Loaded with 2kΩ and 200pF to GND VDD (1V/div) VOUT (1V/div) VOUT (1V/div) Time (1µs/div) 8 Time (20µs/div) DAC7513 www.ti.com SBAS157A TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C and +VDD = +5V, unless otherwise noted. EXITING POWER-DOWN (800H Loaded) CODE CHANGE GLITCH Loaded with 2kΩ and 200pF to GND. Code Change: 800H to 7FFH. VOUT (20mV/div) CLK (5V/div) VOUT (1V/div) Time (5µs/div) Time (0.5µs/div) TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C and +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 1.0 1.0 0.5 0.5 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 0.0 –0.5 –1.0 0.0 –0.5 –1.0 0 200H 400H 600H 800H A00H C00H E00H FFFH 0 200H 400H 600H Code C00H E00H FFFH TYPICAL TOTAL UNADJUSTED ERROR 16 16.0 12.0 8.0 4.0 0.0 –4.0 –8.0 –12.0 –16.0 8 TUE (LSBs) LE (LSB) A00H Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 1.0 DLE (LSB) 800H 0.5 0 –8 0 –0.5 –1.0 000H –16 200H 400H 600H 800H A00H C00H E00H FFFH 200H 400H 600H 800H A00H C00H E00H FFFH Code Code DAC7513 SBAS157A 0 www.ti.com 9 TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C and +VDD = +2.7V, unless otherwise noted. NOTE: All references to IDD include IREF current. FULL-SCALE ERROR vs TEMPERATURE 30 20 20 10 10 Error (mV) Error (mV) ZERO-SCALE ERROR vs TEMPERATURE 30 0 0 –10 –10 –20 –20 –30 –40 0 40 80 –30 –40 120 0 40 Temperature (°C) IDD HISTOGRAM 3000 80 120 Temperature (°C) SOURCE AND SINK CURRENT CAPABILITY 3 VDD = +3V VREF tied to VDD. 2500 DAC Loaded with FFFH 2 VOUT (V) Frequency 2000 1500 1000 1 DAC Loaded with 000H 500 0 190 180 170 160 150 140 130 120 110 90 100 80 70 60 50 0 0 5 10 15 ISOURCE/SINK (mA) IDD (µA) SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 300 500 VREF tied to VDD. VREF tied to VDD. 250 400 IDD (µA) IDD (µA) 200 300 200 150 100 100 50 0 0 0 200H 400H 600H 800H A00H C00H E00H FFFH 10 –40 0 40 80 120 Temperature (°C) Code DAC7513 www.ti.com SBAS157A TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C and +VDD = +2.7V, unless otherwise noted. NOTE: All references to IDD include IREF current. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME 2500 CLK (2.7V/div) IDD (µA) 2000 1500 1000 Full-Scale Code Change 000H to FFFH Output Loaded with 2kΩ and 200pF to GND 500 VOUT (1V/div) 0 0 1 2 3 4 5 Time (1µs/div) VLOGIC (V) HALF-SCALE SETTLING TIME FULL-SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full-Scale Code Change FFFH to 000H Output Loaded with 2kΩ and 200pF to GND VOUT (1V/div) VOUT (1V/div) Half-Scale Code Change 400H to C00H Output Loaded with 2kΩ and 200pF to GND Time (1µs/div) Time (1µs/div) HALF-SCALE SETTLING TIME POWER-ON RESET to 0V CLK (2.7V/div) Half-Scale Code Change C00H to 400H VOUT (1V/div) Output Loaded with 2kΩ and 200pF to GND Time (1µs/div) Time (20µs/div) DAC7513 SBAS157A www.ti.com 11 TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C and +VDD = +2.7V, unless otherwise noted. EXITING POWER-DOWN (800H Loaded) CODE CHANGE GLITCH Loaded with 2kΩ and 200pF to GND. Code Change: 800H to 7FFH. VOUT (20mV/div) CLK (2.7V/div) VOUT (1V/div) Time (0.5µs/div) Time (5µs/div) THEORY OF OPERATION DAC SECTION R The architecture consists of a string DAC followed by an output buffer amplifier. Figure 1 shows a block diagram of the DAC architecture. R DAC Register VDD VFB REF (+) Resistor String REF (–) VOUT R To Output Amplifier Output Amplifier GND FIGURE 1. DAC7513 Architecture. R The input coding to the DAC7513 is straight binary, so the ideal output voltage is given by: V OUT = VREF • D 4096 R (1) where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095. FIGURE 2. Resistor String. RESISTOR STRING OUTPUT AMPLIFIER The resistor string shown in Figure 2 is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because it is a string of resistors. The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to VDD, it is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a half-scale settling time of 8µs with the output unloaded. 12 DAC7513 www.ti.com SBAS157A The inverting input of the output amplifier is brought out to the VFB pin. This allows for better accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning circuitry can also be connected between these points for specific applications. SERIAL INTERFACE The DAC7513 has a 3-wire serial interface SYNC, SCLK, and DIN, which is compatible with SPI, QSPI, and Microwire interface standards as well as most Digital Signal Processors (DSPs). See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW, data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC7513 compatible with high-speed DSPs. On the 16th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (i.e., a change in the DAC register contents and/or a change in the mode of operation). At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As the SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC must be idled LOW between write sequences for lowest power operation of the part. As mentioned above, however, it must be brought HIGH again just before the next write sequence. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought HIGH before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 4. POWER-ON RESET The DAC7513 contains a power-on reset circuit that controls the output voltage during power-up. Upon power up, the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. POWER-DOWN MODES The DAC7513 contains four separate modes of operation, which are programmable by setting two bits (PD1 and PD0) in the control register. Table I shows how the state of the bits corresponds to the mode of operation of the device. INPUT SHIFT REGISTER The input shift register is 16 bits wide, as shown in Figure 3. The first two bits are don’t cares. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next 12 bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. DB13 DB12 0 0 OPERATING MODE Normal Operation 0 1 Power-Down Modes Output 1kΩ to GND 1 0 Output 100kΩ to GND 1 1 High-Z TABLE I. Modes of Operation for the DAC7513. When both bits are set to 0, the part works normally with its normal power consumption of 115µA at 5V. However, for the three power-down modes, the supply current falls to 200nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has DB15 X DB0 X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 3. Data Input Register. CLK SYNC DIN DB15 DB0 DB15 Invalid Write Sequence: SYNC HIGH before 16th Falling Edge DB0 Valid Write Sequence: Output Updates on the 16th Falling Edge FIGURE 4. SYNC Interrupt Facility. DAC7513 SBAS157A www.ti.com 13 the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options: the output is connected internally to GND through a 1kΩ resistor; a 100kΩ resistor; or it is left opencircuited (High-Z). The output stage is illustrated in Figure 5. All linear circuitry is shut down when the power-down mode is activated, however, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V, (see the Typical Chacteristics for more information). of data, and P3.3 is taken HIGH following the completion of this cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC7513 requires its data with the MSB as the first bit received, thus, the 8051 transmit routine must therefore take this into account and mirror the data as needed. DAC7513 TO Microwire INTERFACE Figure 7 shows an interface between the DAC7513 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC7513 on the rising edge of the SK signal. VFB MicrowireTM Resistor String DAC Amplifier Power-down Circuitry VOUT DAC7513(1) CS SYNC SK SCLK SO DIN NOTE: (1) Additional pins omitted for clarity. Resistor Network FIGURE 7. DAC7513 to Microwire Interface. DAC7513 TO 68HC11 INTERFACE FIGURE 5. Output Stage During Power-Down. Figure 8 shows a serial interface between the DAC7513 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC7513, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051. MICROPROCESSOR INTERFACING DAC7513 TO 8051 INTERFACE Figure 6 shows a serial interface between the DAC7513 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC7513, while RXD drives the serial data line of the part; the SYNC signal is derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the DAC7513, P3.3 is taken LOW. The 8051 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, a second write cycle is initiated to transmit the second byte The 68HC11 must be configured so that its CPOL bit is a 0 and its CPHA bit is a 1, this configuration causes data appearing on the MOSI output as valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is taken LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the DAC7513, PC7 is left LOW after the first eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken HIGH at the end of this procedure. 68HC11(1) 80C51/80L51(1) DAC7513(1) P3.3 SYNC TXD SCLK PC7 SYNC SCK SCLK MOSI RXD DAC7513(1) DIN DIN NOTE: (1) Additional pins omitted for clarity. NOTE: (1) Additional pins omitted for clarity. FIGURE 6. DAC7513 to 80C51/80L51 Interface. 14 FIGURE 8. DAC7513 to 68HC11 Interface. DAC7513 www.ti.com SBAS157A BIPOLAR OPERATION USING THE DAC7513 APPLICATIONS The DAC7513 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 10 which will give an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. USING REF02 AS A POWER SUPPLY FOR THE DAC7513 Due to the extremely low supply current required by the DAC7513, an alternative option is to use a REF02 +5V precision voltage reference to supply the required voltage to the part, as shown in Figure 9. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC7513; if the REF02 is used, the current it needs to supply to the DAC7513 is 132µA. This is with no load on the output of the DAC, so when the DAC output is loaded, the REF02 also needs to supply the current to the load. The total current required (with a 5kΩ load on the DAC output) is: 132µA + (5V/ 5kΩ) = 1.13mA The output voltage for any input code can be calculated as follows: R2 D R1 + R2 V O = VREF • • − VREF • R R 4096 1 1 where D represents the input code in decimal (0 to 4095). With VREF = 5V, R1 = R2 = 10kΩ: 10 •D VO = – 5V 4096 (2) (4) This is an output voltage range of ±5V with 000H corresponding to a –5V output and FFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, ±2.5V output voltage raw can be achieved. The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 285µV for the 1.13mA current drawn from it; this corresponds to a 0.2LSB error. LAYOUT +15 A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. +5V REF02 As the DAC7513 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter. 132µA (IDD + IREF) SYNC 3-Wire Serial Interface (3) VOUT = 0V to 5V DAC7513 SCLK Due to the single ground pin of the DAC7513, all return currents, including digital and analog return currents, must flow through the GND pin, which would, ideally, be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. DIN FIGURE 9. REF02 as Power Supply to the DAC7513. R2 10kΩ VREF +5V R1 10kΩ OPA703 VFB VREF 10µF DAC7513 0.1µF ±5V VOUT –5V 3-Wire Serial Interface FIGURE 10. Bipolar Operation with the DAC7513. DAC7513 SBAS157A www.ti.com 15 The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states; this noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. This is only true for the DAC7513 if the power supply is also opted to be used as the source of reference voltage for the DAC. 16 As with the GND connection, VDD should be connected to a +5V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, the 1µF to 10µF and 0.1µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high-frequency noise. DAC7513 www.ti.com SBAS157A PACKAGE DRAWINGS DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,08 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 DAC7513 SBAS157A www.ti.com 17 PACKAGE DRAWINGS (Cont.) DCN (R-PDSO-G8) PLASTIC SMALL-OUTLINE 0,45 0,28 0,65 1,75 3,00 1,50 2,60 Index Area 1,95 REF 3,00 2,80 1,45 0,90 0°–10° –A– 1,30 0,90 0,15 0,00 0,20 0,09 0,60 0,10 C 4202106/A 03/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Foot length measured reference to flat foot surface parallel to Datum A. D. Package outline exclusive of mold flash, metal burr and dambar protrusion/intrusion. E. Package outline inclusive of solder plating. F. A visual index feature must be located within the cross-hatched area. 18 DAC7513 www.ti.com SBAS157A PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY DAC7513E/250 ACTIVE VSSOP DGK 8 250 DAC7513E/2K5 ACTIVE VSSOP DGK 8 2500 DAC7513N/250 ACTIVE SSOP DCN 8 250 DAC7513N/3K ACTIVE SSOP DCN 8 3000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Applications amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated