2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 8-Bit DAC in a SOT-23 AD5300 FUNCTIONAL BLOCK DIAGRAM Single 8-Bit DAC 6-Lead SOT-23 and 8-Lead MSOP Packages Micropower Operation: 140 μA @ 5 V Power-Down to 200 nA @ 5 V, 50 nA @ 3 V 2.7 V to 5.5 V Power Supply Guaranteed Monotonic by Design Reference Derived from Power Supply Power-On Reset to 0 V 3 Power-Down Functions Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility Qualified for automotive applications VDD GND POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC AD5300 REF (+) REF (–) 8-BIT DAC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC SYNC SCLK DIN VOUT RESISTOR NETWORK 00471-001 FEATURES APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5300 is a single, 8-bit buffered voltage output DAC that operates from a single 2.7 V to 5.5 V supply, consuming 115 μA at 3 V. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5300 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. 1. 2. The reference for the AD53001 is derived from the power supply inputs and thus gives the widest dynamic output range. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The part contains a power-down feature that reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in powerdown mode. The part is put into power-down mode over the serial interface. 4. 5. 3. 6. Available in 6-lead SOT-23 and 8-lead MSOP packages. Low power, single-supply operation. This part operates from a single 2.7 V to 5.5 V supply and typically consumes 0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a slew rate of 1 V/μs. Reference derived from the power supply. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. Power-down capability. When powered down, the DAC typically consumes 50 nA at 3 V and 200 nA at 5 V. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V, reducing to 1 μW in power-down mode. The AD5300 is one of a family of pin-compatible DACs. The AD5310 is the 10-bit version, and the AD5320 is the 12-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. 1 Patent pending; protected by U.S. Patent No. 5684481. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved. (VDD = 2.7 V to 5.5 V; RL = 2 k⍀ to GND; CL = 500 pF to GND; all specifications MIN to TMAX, unless otherwise noted.) AD5300–SPECIFICATIONS T B Version1 Min Typ Max Parameter Unit Conditions/Comments 2 STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time 8 +0.5 –0.5 –20 –5 0 4 Slew Rate Capacitive Load Stability Power-Up Time POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD VDD 6 1 470 1000 20 0.5 1 50 20 2.5 5 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage Pin Capacitance ±1 ± 0.25 +3.5 –3.5 ± 1.25 Bits LSB LSB LSB LSB % of FSR µV/°C ppm of FSR/°C V µs V/µs pF pF nV-s nV-s Ω mA mA µs µs ±1 0.8 0.6 See Figure 2. Guaranteed Monotonic by Design. See Figure 3. All Zeros Loaded to DAC Register. See Figure 6. All Ones Loaded to DAC Register. See Figure 6. 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex). RL = 2 kΩ; 0 pF < CL < 500 pF. See Figure 16. RL = ∞. RL = 2 kΩ. 1 LSB Change Around Major Carry. See Figure 19. VDD = 5 V. VDD = 3 V. Coming Out of Power-Down Mode. V DD = 5 V. Coming Out of Power-Down Mode. V DD = 3 V. 3 µA V V V V pF 5.5 V 140 115 250 200 µA µA DAC Active and Excluding Load Current. VIH = VDD and VIL = GND. VIH = VDD and VIL = GND. 0.2 0.05 1 1 µA µA VIH = VDD and VIL = GND. VIH = VDD and VIL = GND. % ILOAD = 2 mA. VDD = 5 V. 2.4 2.1 2.7 93 VDD = 5 V. VDD = 3 V. VDD = 5 V. VDD = 3 V. NOTES 1 Temperature range as follows: B Version: –40°C to +105°C. 2 Linearity calculated using a reduced code range of 4 to 251. Output unloaded. 3 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. –2– REV. D AD5300 TIMING CHARACTERISTICS1, 2 (V Parameter t1 t2 t3 t4 t5 t6 t7 t8 3 DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments 50 13 22.5 13 5 4.5 0 50 ns min ns min ns min ns min ns min ns min ns min ns min SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time 33 13 13 13 5 4.5 0 33 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2. 2 See Figure 1. 3 Maximum SCLK frequency is 30 MHz at V DD = 3.6 V to 5.5 V and 20 MHz at V DD = 2.7 V to 3.6 V. Specifications subject to change without notice. t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB0 DB15 Figure 1. Serial Write Operation ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150°C SOT-23 Package Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max–TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C MSOP Package Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max–TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3– WARNING! ESD SENSITIVE DEVICE AD5300 PIN CONFIGURATIONS MSOP SOT-23 SYNC VDD 1 8 GND 5 SCLK TOP VIEW VDD 3 (Not to Scale) 4 DIN 2 7 DIN VOUT 1 GND 2 6 AD5300 NC AD5300 TOP VIEW 6 SCLK NC (Not to Scale) 5 SYNC VOUT 4 3 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SOT-23 MSOP Pin No. Pin No. Mnemonic 1 2 3 4 8 1 VOUT GND VDD 4 7 DIN 5 6 SCLK 6 5 SYNC NC 2, 3 NC Function Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be decoupled to GND. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. No Connect. –4– REV. D AD5300 TERMINOLOGY Relative Accuracy Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 2. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking into account all the various errors. A typical TUE vs. code plot can be seen in Figure 4. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 3. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Zero-Code Error Zero-code error is a measure of the output error when zero code (00 Hex) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5300 because the output of the DAC cannot go below 0 V. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in LSBs. A plot of zero-code error vs. temperature can be seen in Figure 6. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital input code is changed by 1 LSB at the major carry transition (7F Hex to 80 Hex). See Figure 19. Full-Scale Error Digital Feedthrough Full-scale error is a measure of the output error when fullscale code (FF Hex) is loaded to the DAC register. Ideally, the output should be VDD – 1 LSB. Full-scale error is expressed in LSBs. A plot of full-scale error vs. temperature can be seen in Figure 6. REV. D Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-secs and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s, and vice versa. –5– AD5300–Typical Performance Characteristics 0.5 1.0 TA = 25ⴗC 1.0 0.4 INL @ 5V 0 –0.5 0.5 0.2 TUE – LSBs DNL ERROR – LSBs INL ERROR – LSBs INL @ 3V 0.5 TUE @ 3V TA = 25ⴗC 0.3 DNL @ 5V 0.1 0 –0.1 DNL @ 3V TUE @ 5V 0 –0.2 –0.5 –0.3 TA = 25ⴗC –0.4 –1.0 –0.5 0 50 100 150 CODE 200 250 0 50 100 150 CODE 200 Figure 3. Typical DNL Plot Figure 2. Typical INL Plot –1.0 250 0 2000 MIN DNL VDD = 3V 1 ZS ERROR FREQUENCY MAX DNL ERROR – LSBs 0.5 0 250 VDD = 5V 2 MAX INL 200 2500 VDD = 5V VDD = 5V ERROR – LSBs 100 150 CODE Figure 4. Typical Total Unadjusted Error Plot 3 1.0 50 0 FS ERROR –1 1500 1000 MIN INL –0.5 500 –2 –1.0 –40 0 40 80 TEMPERATURE – ⴗC 120 Figure 5. INL Error and DNL Error vs. Temperature –3 –40 0 40 80 TEMPERATURE – ⴗC 0 120 IDD – A Figure 7. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 6. Zero-Scale Error and Full-Scale Error vs. Temperature 5 3 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 500 TA = 25ⴗC DAC LOADED WITH FF HEX 4 400 DAC LOADED WITH FF HEX 3 IDD – A VOUT – V VOUT – V 2 TA = 25ⴗC 2 300 200 VDD = 5V 1 DAC LOADED WITH 00 HEX 1 100 VDD = 3V DAC LOADED WITH 00 HEX 0 0 0 5 10 ISOURCE/SINK – mA 15 Figure 8. Source and Sink Current Capability with VDD = 3 V 0 5 10 ISOURCE/SINK – mA 15 Figure 9. Source and Sink Current Capability with VDD = 5 V –6– 0 0 50 100 150 CODE 200 250 Figure 10. Supply Current vs. Code REV. D AD5300 300 300 1.0 THREE–STATE CONDITION 0.9 250 200 200 150 100 0.8 0.7 0.6 IDD – A 250 IDD – A IDD – A VDD = 5V 150 0.5 0.4 100 +105ⴗC 0.3 +25ⴗC –40ⴗC 50 0.2 50 0.1 0 –40 0 40 80 TEMPERATURE – ⴗC 0 2.7 120 Figure 11. Supply Current vs. Temperature 3.2 3.7 4.2 VDD – V 4.7 0 2.7 5.2 Figure 12. Supply Current vs. Supply Voltage 3.2 3.7 4.2 VDD – V 4.7 5.2 Figure 13. Power-Down Current vs. Supply Voltage 800 TA = 25ⴗC CH 2 IDD – A 600 CH 2 CLK CLK 400 VOUT 200 CH1 VDD = 5V VDD = 3V 0 0 2 3 VLOGIC – V 1 4 CH 1 CH1 1V, CH 2 5V, TIME BASE = 1s/DIV 5 Figure 14. Supply Current vs. Logic Input Voltage VOUT VDD = 5V FULL-SCALE CODE CHANGE 00 HEX – FF HEX TA = 25ⴗC OUTPUT LOADED WITH 2k⍀ AND 200pF TO GND Figure 15. Full-Scale Settling Time VDD = 5V HALF-SCALE CODE CHANGE 40 HEX – C0 HEX TA = 25ⴗC OUTPUT LOADED WITH 2k⍀ AND 200pF TO GND CH1 1V, CH2 5V, TIME BASE = 1s/DIV Figure 16. Half-Scale Settling Time 2.54 2k⍀ LOAD TO VDD LOADED WITH 2k⍀ AND 200pF TO GND VDD = 5V CH2 CLK VOUT – V 2.52 VDD CH1 CODE CHANGE: 80 HEX TO 7F HEX 2.50 VOUT VOUT CH2 2.48 CH1 CH1 1V, CH 2 1V, TIME BASE = 20s/DIV CH1 1V, CH 2 5V, TIME BASE = 5s/DIV 2.46 500ns/DIV Figure 17. Power-On Reset to 0 V REV. D Figure 18. Exiting Power-Down (7F Hex Loaded) –7– Figure 19. Digital-to-Analog Glitch Impulse AD5300 GENERAL DESCRIPTION D/A Section The AD5300 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Since there is no reference input pin, the power supply (VDD) acts as the reference. Figure 20 shows a block diagram of the DAC architecture. VDD RESISTOR STRING The AD5300 has a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 1 for a timing diagram of a typical write sequence. VOUT REF (–) OUTPUT AMPLIFIER GND The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5300 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns (VDD = 3.6 V to 5.5 V) or 50 ns (VDD = 2.7 V to 3.6 V) before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2.4 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part. As previously mentioned, however, it must be brought high again just before the next write sequence. Figure 20. DAC Architecture Since the input coding to the DAC is straight binary, the ideal output voltage is given by D V OUT =V DD × 256 where D = decimal equivalent of the binary code that is loaded to the DAC register; D can range from 0 to 255. Resistor String The resistor string section is shown in Figure 21. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Input Shift Register The input shift register is 16 bits wide (see Figure 22). The first two bits are Don’t Cares. The next two are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next eight bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. Finally, the last four bits are Don’t Cares. R R TO OUTPUT AMPLIFIER R The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/µs with a half-scale settling time of 4 µs with the output loaded. SERIAL INTERFACE REF (+) DAC REGISTER Output Amplifier R R Figure 21. Resistor String DB15 (MSB) X DB0 (LSB) X PD1 PD 0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS 0 0 1 1 0 1 0 1 NORMAL OPERATION 1k⍀ TO GND 100k⍀ TO GND POWER-DOWN MODES THREE-STATE Figure 22. Input Register Contents –8– REV. D AD5300 SCLK SYNC DB15 DIN DB0 DB15 DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH FALLING EDGE INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH FALLING EDGE Figure 23. SYNC Interrupt Facility SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid; neither an update of the DAC register contents or a change in the operating mode occurs—see Figure 23. RESISTOR STRING DAC AMPLIFIER POWER-DOWN CIRCUITRY VOUT RESISTOR NETWORK Power-On Reset The AD5300 contains a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. Figure 24. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for VDD = 3 V (see Figure 18). Power-Down Modes The AD5300 contains four separate modes of operation. These modes are software programmable by setting two bits (DB13 and DB12) in the control register. Table I shows how the state of the bits corresponds to the mode of operation of the device. MICROPROCESSOR INTERFACING AD5300 to ADSP-2101/ADSP-2103 Interface Figure 25 shows a serial interface between the AD5300 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Table I. Modes of Operation for the AD5300 DB13 DB12 Operating Mode 0 0 0 1 1 1 0 1 Normal Operation Power-Down Modes 1 kΩ to GND 100 kΩ to GND Three-State ADSP-2101/ ADSP-2103* When both bits are set to 0, the part works normally with its normal power consumption of 140 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has an advantage: the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is illustrated in Figure 24. REV. D AD5300* TFS DT SCLK SYNC DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface –9– AD5300 AD5300 to 68HC11/68L11 Interface Figure 26 shows a serial interface between the AD5300 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5300, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5300, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken high at the end of this procedure. AD5300* 68HC11/68L11* PC7 SCK MOSI SYNC SCLK DIN AD5300* MICROWIRE* CS SYNC SK SCLK SO DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. AD5300 to MICROWIRE Interface APPLICATIONS Using REF19x as a Power Supply for AD5300 Because the supply current required by the AD5300 is extremely low, an alternative option is to use a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) to supply the required voltage to the part—see Figure 29. This is especially useful if your power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x will output a steady supply voltage for the AD5300. If the low dropout REF195 is used, the current it needs to supply to the AD5300 is 140 µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 140 µA + (5 V/5 kΩ) = 1.14 mA *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26. AD5300 to 68HC11/68L11 Interface AD5300 to 80C51/80L51 Interface Figure 27 shows a serial interface between the AD5300 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5300, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5300, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5300 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine takes this into account. AD5300* 80C51/80L51* The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 2.3 ppm (11.5 µV) for the 1.14 mA current drawn from it. This corresponds to a 0.0006 LSB error. 15V 5V REF195 140A 3-WIRE SERIAL INTERFACE SYNC SCLK DIN AD5300 VOUT = 0V TO 5V Figure 29. REF195 as Power Supply to AD5300 Bipolar Operation Using the AD5300 The AD5300 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 30. The circuit in Figure 30 will give an output voltage range of ± 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as P3.3 SYNC TXD SCLK RXD DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 27. AD5300 to 80C51/80L51 Interface D R1 + R2 R2 VO = VDD × × R1 – VDD × R1 256 where D represents the input code in decimal (0 to 255). With VDD = 5 V, R1 = R2 = 10 kΩ, 10 × D VO = – 5V 256 AD5300 to MICROWIRE Interface Figure 28 shows an interface between the AD5300 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5300 on the rising edge of the SK. This is an output voltage range of ±5 V with 00 Hex corresponding to a –5 V output and FF Hex corresponding to a 5 V output. –10– REV. D AD5300 R2 = 10k⍀ 5V REGULATOR +5V +5V 10F POWER 0.1F R1 = 10k⍀ AD820/ OP295 0.1F 10k⍀ VOUT VDD 10F VDD ⴞ5V AD5300 SCLK –5V VDD SCLK VDD AD5300 10k⍀ SYNC 3-WIRE SERIAL INTERFACE 10k⍀ DATA Two 8-Bit AD5300s Together Make One 15-Bit DAC Figure 32. AD5300 with an Opto-Isolated Interface Power Supply Bypassing and Grounding Since the AD5300 works on any supply voltage between 2.5 V and 5.5 V, the output of the first DAC can be anywhere above 2.5 V. For a VDD of 5 V, this allows the first DAC to use half of its output range (2.5 V to 5 V), which gives 7-bit resolution on the output voltage. This output then becomes the supply and reference for the second DAC. The second DAC has 8-bit resolution on the output range, which gives an overall resolution for the system of 15 bits. A level-shifter is required to ensure that the logic input voltages do not exceed the supply voltage of the part. The microcontroller outputs 5 V signals, which need to be level shifted down to 2.5 V in the case of the second DAC having a supply of only 2.5 V. 5V VOUT = 2.5V TO 5V AD5300 DIN MICROCONTROLLER LEVEL SHIFTER SYNC VDD SCLK AD5300 DIN VOUT = 0V TO 5V 15-BIT RESOLUTION Figure 31. 15-Bit DAC Using Two AD5300s Using AD5300 with an Opto-Isolated Interface In process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous commonmode voltages that may occur in the area where the DAC is functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5300 uses a 3-wire serial logic interface, it requires only three opto-isolators to provide the required isolation (see Figure 32). The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5300. REV. D DIN GND By using the configuration in Figure 31, it can be seen that one 15-bit DAC can be made with two 8-bit AD5300s. Because of the low supply current the AD5300 requires, the output of one DAC may be directed into the supply pin of the second DAC. The first DAC has no problem sourcing the required 140 µA of current for the second DAC. VDD VOUT VDD Figure 30. Bipolar Operation with the AD5300 SYNC SCLK SYNC When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5300 should have separate analog and digital sections, each having its own area of the board. If the AD5300 is in a system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5300. The power supply to the AD5300 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be physically as close as possible to the device with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), e.g., common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. –11– AD5300 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 3.00 2.80 2.60 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 0.08 MIN 0.15 MAX 0.05 MIN 10° 4° 0° SEATING PLANE 0.50 MAX 0.30 MIN 0.60 BSC 0.55 0.45 0.35 12-16-2008-A 1.45 MAX 0.95 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 33. 6-Lead Small Outline Transistor Package (SOT-23) (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 34. 8-Lead Mini Small Outline Package (MSOP) (RM-8) Dimensions shown in millimeters Rev. D | Page 12 of 13 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 AD5300 ORDERING GUIDE Model1, 2 AD5300BRM AD5300BRMZ AD5300BRMZ-REEL AD5300BRMZ-REEL7 AD5300BRT-500RL7 AD5300BRT-REEL AD5300BRT-REEL7 AD5300BRTZ-500RL7 AD5300BRTZ-REEL AD5300BRTZ-REEL7 AD5300WBRTZ-RL7 1 2 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 Package Option RM-8 RM-8 RM-8 RM-8 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 Branding D2B D2B D2B D2B D2B D2B D2B D2B D2B D2B DG5 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5300WBRTZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. REVISION HISTORY 12/10—Rev. C to Rev. D Change to Features Section .............................................................. 1 Updated Outline Dimensions ........................................................12 Moved Ordering Guide; Changes to Ordering Guide................13 Added Automotive Products Section ...........................................13 11/03—Rev. B to Rev. C Changes to Ordering Guide ............................................................. 3 Changes to Pin Function Descriptions Section ............................ 4 Updated Outline Dimensions ........................................................12 ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00471-0-12/10(D) Rev. D | Page 13 of 13