Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP AD5063 FEATURES APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM VREF POWER-ON RESET BUF VDD AD5063 RFB INV DAC REGISTER REF(+) VOUT DAC AGND INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC RESISTOR NETWORK 04766-001 Single 16-bit DAC, 1 LSB INL Power-on reset to midscale Guaranteed monotonic by design 3 power-down functions Low power serial interface with Schmitt-triggered inputs 10-lead MSOP, low power Fast settling time of 1 μs maximum (AD5063-1 model) 2.7 V to 5.5 V power supply Low glitch on power-up Unbuffered voltage capable of driving 60 kΩ load SYNC interrupt facility SYNC SCLK DIN DACGND Figure 1. Table 1. Related Devices Part No. AD5061 AD5062 AD5040/AD5060 Description 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSBs INL, SOT-23. 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, SOT-23. 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A, 1 LSB INL, SOT-23. GENERAL DESCRIPTION The AD5063, a member of ADI’s nanoDAC™ family, is a low power, single 16-bit, unbuffered voltage-output DAC that operates from a single 2.7 V to 5 V supply. The part offers a relative accuracy specification of ±1 LSB, and operation is guaranteed monotonic with a ±1 LSB DNL specification. The AD5063 comes with on-board resistors in a 10-lead MSOP, allowing bipolar signals to be generated with an output amplifier. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and that is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5063 is supplied from an external VREF pin. A reference buffer is also provided on-chip. The part incorporates a power-on reset circuit that ensures the DAC output powers up to midscale and remains there until a valid write to the device takes place. The part contains a power-down feature that reduces the current consumption of the device to typically 300 nA at 5 V and provides software-selectable output loads while in power-down mode. The part is put into power-down mode via the serial interface. Total unadjusted error for the part is <1 mV. This part exhibits very low glitch on power-up. PRODUCT HIGHLIGHTS Available in 10-lead MSOP. 16-bit accurate, 1 LSB INL. Low glitch on power-up. High speed serial interface with clock speeds up to 30 MHz. Three power-down modes available to the user. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved. AD5063 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 13 Applications ....................................................................................... 1 Input Shift Register .................................................................... 13 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 13 General Description ......................................................................... 1 Power-On to Midscale ............................................................... 14 Product Highlights ........................................................................... 1 Software Reset ............................................................................. 14 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 14 Specifications..................................................................................... 3 Microprocessor Interfacing ....................................................... 14 Timing Characteristics ................................................................ 5 Applications..................................................................................... 16 Absolute Maximum Ratings............................................................ 6 Choosing a Reference for the AD5063 .................................... 16 ESD Caution .................................................................................. 6 Bipolar Operation Using the AD5063 ..................................... 16 Pin Configuration and Function Descriptions ............................. 7 Using the AD5063 with a Galvanically Isolated Interface Chip ............................ 17 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 DAC Architecture ....................................................................... 13 Power Supply Bypassing and Grounding ................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 Reference Buffer ......................................................................... 13 REVISION HISTORY 8/09—Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Output Voltage Settling Time Parameter, Table 2 ... 3 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 3/06—Rev. A to Rev. B Updated Format .................................................................. Universal Change to Features ........................................................................... 1 Change to Figure 1 ........................................................................... 1 Changes to Specifications ................................................................ 3 Change to Absolute Maximum Ratings......................................... 6 Change to Reference Buffer Section ............................................ 13 Change to Serial Interface Section ............................................... 13 Change to Table 6 ........................................................................... 14 Change to Bipolar Operation Using the AD5063 Section ........ 16 7/05—Rev. 0 to Rev. A Changes to Galvanically Isolated Chip Section .......................... 17 Changes to Figure 38 ...................................................................... 17 4/05—Revision 0: Initial Version Rev. C | Page 2 of 20 AD5063 SPECIFICATIONS VDD = 2.7 V to 5.5 V, VREF = 4.096 V @ VDD = 5.0 V, RL = unloaded, CL = unloaded to GND; TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution Relative Accuracy (INL) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Gain Error Gain Error Temperature Coefficient Zero-Code Error Min Pin Capacitance Bits LSB μV LSB % FSR ppm FSR/°C mV 1 ±8 ±0.5 ±16 0 −VREF ±1 ±800 ±1 ±0.02 ±0.1 ±0.1 ±800 μV/°C mV μV/°C μV ±32 Ω/Ω LSB ppm FSR/°C LSB VREF VREF V V ±16 4 Test Conditions/Comments −40°C to + 85°C, B grade over all codes Guaranteed monotonic TA = −40°C to +85°C All 0s loaded to DAC register, TA = −40°C to +85°C TA = −40°C to +85°C All 1s loaded to DAC register, TA = −40°C to +85°C RFB/RINV, RFB = RINV = 30 kΩ typically Unipolar operation Bipolar operation ¼ scale to ¾ scale code transition to ±1 LSB 4 64 6 μs μs μs nV/√Hz μV p-p 2 0.002 8 nV-s nV-s kΩ Output impedance tolerance ±10% 1 100 kΩ kΩ Output impedance tolerance ±400 Ω Output impedance tolerance ±20 kΩ μA μA MΩ Zero-scale loaded 1 Output Noise Spectral Density Output Voltage Noise Input High Voltage, VIH ±0.5 ±500 ±0.5 ±0.01 1 ±0.05 0.05 ±0.05 0.5 ±500 Output Voltage Settling Time 3 AD5063BRMZ AD5063BRMZ-1 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance (Normal) DC Output Impedance (Power-Down) (Output Connected to 1 kΩ Network) (Output Connected to 10 kΩ Network) REFERENCE INPUT/OUPUT VREF Input Range Input Current (Power-Down) Input Current (Normal) DC Input Impedance LOGIC INPUTS Input Current 4 Input Low Voltage, VIL Unit 16 Zero-Code Error Temperature Coefficient Offset Error Offset Error Temperature Coefficient Full-Scale Error Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Temperature Coefficient Bipolar Gain Error OUTPUT CHARACTERISTICS 2 Output Voltage Range B Version 1 Typ Max 2 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 5.5 V DAC code = midscale, 1 kHz DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 1 LSB change around major carry VDD − 50 mV ±1 ±1 1 ±1 ±2 0.8 0.8 2.0 1.8 μA V V 4 pF Rev. C | Page 3 of 20 Bipolar/unipolar operation VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 2.7 V to 5.5 V VDD = 2.7 V to 3.6 V AD5063 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V Power Supply Rejection Ratio (PSRR) Min B Version 1 Typ Max 2.7 0.65 Unit Test Conditions/Comments 5.5 V 0.7 mA mA All digital inputs at 0 V or VDD DAC active and excluding load current VIN = VDD and VIL = GND, VDD = 5 V, VREF = 4.096 V, code = midscale VIH = VDD and VIL = GND, VDD = 3 V μA μA LSB VIH = VDD and VIL = GND VIH = VDD and VIL = GND ∆VDD ± 10%, VDD = 5 V, unloaded 0.5 1 1 0.5 1 Temperature ranges for the B version: −40°C to +85°C, typical at +25°C, functional to +125°C. Guaranteed by design and characterization, not production tested. 3 See the Ordering Guide. 4 Total current flowing into all pins. 2 Rev. C | Page 4 of 20 AD5063 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Limit 1 33 5 3 10 3 2 0 12 9 Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 2 Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 30 MHz. t4 SCLK t2 t8 t1 t9 t3 t7 SYNC t6 t5 DIN D23 D22 D2 D1 Figure 2. Timing Diagram Rev. C | Page 5 of 20 D0 D23 D22 04766-002 1 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min AD5063 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREF to GND INV to GND RFB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MSOP Package Power Dissipation θJA Thermal Impedance θJc Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature ESD 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V +7 V to −7 V This device is a high performance integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. −40°C to + 85°C 1 −65°C to +150°C 150°C (TJ max − TA)/θJA 206°C/W 44°C/W 260(0/−5)°C 10 sec to 40 sec 1.5 kV Temperature range for this device is −40°C to +85°C; however, the device is still operational at 125°C. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 20 AD5063 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIN 1 9 SYNC 8 DACGND VOUT 4 7 AGND INV 5 6 RFB VREF 3 AD5063 TOP VIEW (Not to Scale) 04766-003 VDD 2 10 SCLK Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic DIN 2 3 4 5 VDD VREF VOUT INV 6 7 8 9 RFB AGND DACGND SYNC 10 SCLK Description Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND. Reference Voltage Input. Analog Output Voltage from DAC. Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amp’s inverting input in bipolar mode. Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit. Ground Reference Point for Analog Circuitry. Ground Input to the DAC. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 30 MHz. Rev. C | Page 7 of 20 AD5063 TYPICAL PERFORMANCE CHARACTERISTICS 1.4 1.0 TA = 25°C 0.8 VDD = 5V VREF = 4.096V TA = 25°C 1.2 VDD = 5V VREF = 4.096V 1.0 0.6 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 0.2 0 –0.2 –0.4 04766-047 –0.8 0 10000 20000 30000 40000 DAC CODE 50000 60000 04766-046 –0.6 –0.6 –1.0 0.4 –0.8 –1.0 70000 0 10000 Figure 4. INL Error vs. DAC Code 1.0 0.06 0.6 0.04 0.4 0.02 0 –0.02 –0.04 –0.06 70000 MAX DNL @ VDD = 5.5V 0.2 0 MAX DNL @ VDD = 2.7V –0.2 MIN DNL @ VDD = 2.7V –0.4 04766-048 0 10000 20000 30000 40000 DAC CODE 50000 60000 MIN DNL @ VDD = 5.5V –0.8 –1.0 –40 70000 –20 Figure 5. TUE Error vs. DAC Code VDD = 5.5V VREF = 4.096V VDD = 2.7V VREF = 2.0V 0.8 1.0 MAX INL @ VDD = 2.7V 0.8 TUE ERROR (LSB) 0.2 MIN INL @ VDD = 5.5V –0.2 –0.4 04766-012 –0.8 0 20 40 60 80 TEMPERATURE (°C) 140 MAX TUE @ 2.7V 100 MAX TUE @ 5.5V 0.2 0 MIN TUE @ 5.5V –0.2 –0.4 MIN TUE @ 2.7V –0.6 MIN INL @ VDD = 2.7V –20 120 120 140 04766-009 –0.6 100 VDD = 5.5V VREF = 4.096V VDD = 2.7V VREF = 2.0V 0.4 0 20 40 60 80 TEMPERATURE (°C) 0.6 0.4 –1.0 –40 0 Figure 8. DNL Error vs. Temperature MAX INL @ VDD = 5.5V 0.6 INL ERROR (LSB) 60000 –0.6 –0.08 1.0 50000 VDD = 5.5V VREF = 4.096V 0.8 VDD = 2.7V VREF = 2.0V DNL ERROR (LSB) TUE ERROR (mV) TA = 25°C 0.08 VDD = 5V VREF = 4.096V 1.2 30000 40000 DAC CODE Figure 7. DNL Error vs. DAC Code 0.10 –0.10 20000 04766-013 INL ERROR (LSB) 0.8 –0.8 –1.0 –40 Figure 6. INL Error vs. Temperature –20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 9. TUE Error vs. Temperature Rev. C | Page 8 of 20 120 140 AD5063 3 0.25 TA = 25°C 0.15 1 0.10 MAX INL @ VDD = 5.5V OFFSET (mV) 0 MIN INL @ VDD = 5.5V –1 0.05 MAX OFFSET @ VDD = 5.5V 0 MAX OFFSET @ VDD = 2.7V –0.05 –0.10 –0.15 04766-004 –2 2 1 3 4 REFERENCE VOLTAGE (V) 5 04766-007 INL ERROR (LSB) 2 –3 VDD = 5.5V VREF = 4.096V VDD = 2.7V VREF = 2.0V 0.20 –0.20 –0.25 –40 6 –20 TA = 25°C 0.8 140 0.8 SUPPLY CURRENT (mA) 0.4 MAX DNL VDD = 5.5V 0.2 0 –0.2 –0.4 0.7 0.5 0.3 0.2 0.1 04766-044 –0.8 2 1 3 4 REFERENCE VOLTAGE (V) VDD = 3V VREF = 2.7V 0.4 MIN DNL VDD = 5.5V –0.6 VDD = 5.5V VREF = 4.096V 0.6 5 0 –40 6 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 14. Supply Current vs. Temperature Figure 11. DNL Error vs. Reference Input Voltage 1.0 0.10 TA = 25°C 0.08 04766-041 DNL ERROR (LSB) 120 0.9 0.6 TA = 25°C 0.9 0.8 0.04 SUPPLY CURRENT (mA) 0.06 MAX TUE @ VDD = 5.5V 0.02 0 –0.02 –0.04 0.7 VDD = 5.5V VREF = 4.096V 0.6 0.5 VDD = 3V VREF = 2.5V 0.4 0.3 0.2 –0.08 MIN TUE @ VDD = 5.5V 1 2 3 4 REFERENCE VOLTAGE (V) 5 0.1 0 6 04766-042 –0.06 04766-005 TUE ERROR (mV) 100 1.0 1.0 –0.10 20 40 60 80 TEMPERATURE (°C) Figure 13. Offset vs. Temperature Figure 10. INL Error vs. Reference Input Voltage –1.0 0 0 10000 20000 30000 40000 50000 DIGITAL INPUT CODE 60000 Figure 15. Supply Current vs. Digital Input Code Figure 12. TUE Error vs. Reference Input Voltage Rev. C | Page 9 of 20 70000 AD5063 1.0 TA = 25°C VREF = 2.7V 0.9 CH3 = SCLK SUPPLY CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 CH2 = VOUT 0.3 04766-043 0.2 0 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 5.7 CH1 = TRIGGER 04766-026 0.1 CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs Figure 16. Supply Current vs. Supply Voltage Figure 19. Exiting Power-Down Time to Midscale 24TH CLOCK FALLING VDD = 3V DAC = FULL SCALE VREF = 2.7V TA = 25°C CH1 = SCLK CH2 50mV/DIV CH1 2V/DIV Y-AXIS = 2µV/DIV X-AXIS = 4sec/DIV TIME BASE 400ns/DIV Figure 20. 0.1 Hz to 10 Hz Noise Plot Figure 17. Digital-to-Analog Glitch Impulse (See Figure 21) VDD = 5V VREF = 4.096V TA = 25°C 10ns/SAMPLE AMPLITUDE (200µV/DIV) 200 150 FULL SCALE 100 MIDSCALE ZERO SCALE 50 0 100 1000 10000 FREQUENCY (Hz) 100000 04766-017 250 VDD = 5V TA = 25°C VREF = 4.096V 04766-011 NOISE SPECTRAL DENSITY (nV/ Hz) 300 04766-018 04766-015 CH2 = VOUT 1000000 0 Figure 18. Output Noise Spectral Density 50 100 150 200 250 300 SAMPLES 350 Figure 21. Glitch Energy Rev. C | Page 10 of 20 400 450 500 AD5063 0.010 0.008 VDD = 5.5V VREF = 4.096V VDD = 2.7V VREF = 2.0V 0.004 CH1 = VDD 0.002 0 GAIN ERROR @ VDD = 5.5V –0.002 –0.004 CH2 = VOUT –0.006 –0.010 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 04766-010 GAIN ERROR @ VDD = 2.7V –0.008 120 VDD = 5V VREF = 4.096V RAMP RATE = 200µs TA = 25°C 140 04766-022 GAIN ERROR (%fsr) 0.006 CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs Figure 22. Gain Error vs. Temperature Figure 25. Hardware Power-Down Glitch 20 18 CH1 = SCLK 16 FREQUENCY 14 CH2 = SYNC 12 10 8 6 04766-049 VDD = 5V VREF = 4.096V TA = 25°C MORE 0.680 0.655 0.640 0.625 0.610 0.595 0.580 0.565 0 0.550 2 CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV TIME BASE 1µs/DIV BIN Figure 26. Exiting Software Power-Down Glitch Figure 23. IDD Histogram @ VDD = 5 V 35 30 20 15 10 0.545 0.535 0.525 0.515 0.505 0.495 0.485 0.475 04766-050 5 0.465 FREQUENCY 25 0 CH4 = TRIGGER BIN Figure 24. IDD Histogram @ VDD = 3 V Rev. C | Page 11 of 20 04766-020 CH3 = VOUT 4 AD5063 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL error vs. code plot is shown in Figure 7. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5063 because the output of the DAC cannot go below 0 V. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error, taking all the various errors into account. A typical TUE vs. code plot is shown in Figure 5. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with a change in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. See Figure 17 and Figure 21. Figure 17 shows the glitch generated following completion of the calibration routine; Figure 21 zooms in on this glitch. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Rev. C | Page 12 of 20 AD5063 THEORY OF OPERATION The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making these parts compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed (that is, a change in the DAC register contents and/or a change in the mode of operation). The AD5063 is a single 16-bit, serial input, voltage-output DAC. It operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5063 in a 24-bit word format via a 3-wire serial interface. The AD5063 incorporates a power-on reset circuit that ensures the DAC output powers up to midscale. The device also has a software power-down mode pin that reduces the typical current consumption to less than 1 μA. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 12 ns before the next write sequence, so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIH = 1.8 V than it does when VIH = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part. As previously indicated, however, it must be brought high again just before the next write sequence. DAC ARCHITECTURE The DAC architecture of the AD5063 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 27. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either the DACGND or VREF buffer output. The remaining 12 bits of the data-word drive Switches S0 to S11 of a 12-bit voltage mode R-2R ladder network. INPUT SHIFT REGISTER VOUT 2R 2R 2R 2R 2R 2R S0 S1 S11 E1 E2 E15 The input shift register is 24 bits wide (see Figure 28). PD1 and PD0 are bits that control the operating mode of the part (normal mode or any one of the three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK. 12-BIT R-2R LADDER 04766-027 VREF FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 27. DAC Ladder Structure REFERENCE BUFFER SYNC INTERRUPT The AD5063 operates with an external reference. The reference input (VREF) has an input range of 2 V to AVDD − 50 mV. This input voltage is used to provide a buffered reference for the DAC core. In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 31). SERIAL INTERFACE The AD5063 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs. (See Figure 2 for a timing diagram of a typical write sequence.) DB15 (MSB) 0 0 0 0 0 0 PD1 PD0 D15 DB0 (LSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 0 1 NORMAL OPERATION 1 0 100kΩ TO GND 1 1 1kΩ TO GND THREE-STATE POWER-DOWN MODES Figure 28. Input Register Contents Rev. C | Page 13 of 20 04766-028 2R AD5063 AD5063 DAC The AD5063 contains a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with the midscale code, and the output voltage is midscale until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. VOUT POWER-DOWN CIRCUITRY RESISTOR NETWORK 04766-029 POWER-ON TO MIDSCALE Figure 29. Output Stage During Power-Down SOFTWARE RESET The device can be put into software reset by setting all bits in the DAC register to 1; this includes writing 1s to Bits D23 to D16, which is not the normal mode of operation. Note that the SYNC interrupt command cannot be performed if a software reset command is started. MICROPROCESSOR INTERFACING The AD5063 contains four separate modes of operation. These modes are software-programmable by setting two bits (DB17 and DB16) in the control register. Table 6 shows how the state of the bits corresponds to the operating mode of the device. Table 6. Modes of Operation for the AD5063 DB16 0 0 1 1 1 0 1 Operating Mode Normal operation Power-down mode: Three-state 100 kΩ to GND 1 kΩ to GND AD5063 to ADSP-2101/ADSP-2103 Interface Figure 30 shows a serial interface between the AD5063 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. ADSP-2101/ ADSP-21031 When both bits are set to 0, the part has normal power consumption. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three options: The output can be connected internally to GND through either a 1 kΩ resistor or a 100 kΩ resistor, or it can be left open-circuited (three-stated). The output stage is illustrated in Figure 29. AD5063 SYNC TFS DIN DT SCLK SCLK 1ADDITIONAL 04766-030 POWER-DOWN MODES DB17 0 The bias generator, DAC core, and other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V (see Figure 19). PINS OMITTED FOR CLARITY Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface SCLK DIN DB23 DB0 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE DB23 DB0 VALID WRITE SEQUENCE: OUTPUT UPDATES ON THE 24TH FALLING EDGE Figure 31. SYNC Interrupt Facility Rev. C | Page 14 of 20 04766-031 SYNC AD5063 AD5063 to 68HC11/68L11 Interface AD5063 to 80C51/80L51 Interface Figure 32 shows a serial interface between the AD5063 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK pin of the AD5063, and the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface require that the 68HC11/68L11 be configured so that its CPOL bit is 0 and its CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 are configured with their CPOL bit set to 0 and their CPHA bit set to 1, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5063, PC7 is left low after the first eight bits are transferred, and then a second serial write operation is performed to the DAC, with PC7 taken high at the end of this procedure. Figure 34 shows a serial interface between the AD5063 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5063, and RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5063, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data in a format that has the LSB first. The AD5063 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. 68HC11/ 68L111 DIN 1ADDITIONAL Figure 32. AD5063 to 68HC11/68L11 Interface DIN PINS OMITTED FOR CLARITY AD5063 to MICROWIRE Interface AD5063 to Blackfin® ADSP-BF53x Interface Figure 33 shows a serial interface between the AD5063 and the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5063, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5063, TSCLK0 drives the SCLK of the part, and TFS0 drives SYNC. Figure 35 shows an interface between the AD5063 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and clocked into the AD5063 on the rising edge of the SK. AD50631 MICROWIRE1 CS SYNC SK SCLK SO DIN AD50631 ADSP-BF53x1 1ADDITIONAL 1ADDITIONAL SCLK RxD Figure 34. AD5063 to 80C51/80L51 Interface PINS OMITTED FOR CLARITY TSCLK0 SCLK TFS0 SYNC PINS OMITTED FOR CLARITY Figure 35. AD5063 to MICROWIRE Interface DIN 04766-033 DT0PRI SYNC TxD PINS OMITTED FOR CLARITY Figure 33. AD5063 to Blackfin ADSP-BF53x Interface Rev. C | Page 15 of 20 04766-035 MOSI SCLK 04766-032 SCK SYNC P3.3 04766-034 AD50631 PC7 1ADDITIONAL AD50631 80C51/80L511 AD5063 APPLICATIONS Table 7. Recommended Precision References for the AD5063 CHOOSING A REFERENCE FOR THE AD5063 To achieve optimum performance of the AD5063, thought should be given to the choice of a precision voltage reference. The AD5063 has one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC; therefore, any error in the reference is reflected in the DAC. There are four possible sources of error when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. Initial accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR423, allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at any point within the operating temperature range to trim out error. Initial Accuracy (mV max) ±2 ±2 ±3 ±3 ±5 Part No. ADR435 ADR425 ADR02 ADR02 ADR395 Temperature Drift (ppm/°C max) 3 (R-8) 3 (R-8) 3 (R-8) 3 (SC-70) 9 (TSOT-23) 0.1 Hz to 10 Hz Noise (μV p-p typ) 8 3.4 10 10 8 BIPOLAR OPERATION USING THE AD5063 The AD5063 has been designed for single-supply operation, but a bipolar output range is also possible by using the circuit shown in Figure 37. This circuit yields an output voltage range of ±4.096 V. Rail-to-rail operation at the amplifier output is achievable using AD8675/AD8031/AD8032 or an OP196. The output voltage for any input code can be calculated as Because the supply current required by the AD5063 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended; it requires less than 100 μA of quiescent current and can, therefore, drive multiple DACs in one system, if required. It also provides very good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range. ⎡ ⎛ D ⎞ ⎛ R1 + R2 ⎞ ⎛ R2 ⎞⎤ VO = ⎢VDD × ⎜ ⎟×⎜ ⎟ − VDD × ⎜ ⎟⎥ ⎝ R1 ⎠⎦ ⎝ 65,536 ⎠ ⎝ R1 ⎠ ⎣ where D represents the input code in decimal (0 to 65,536). With VREF = 5 V, R1 = R2 = 30 kΩ 7V SYNC SCLK AD5063 This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output and 0xFFFF corresponding to a +5 V output. VOUT = 0V TO 5V DIN +4.096V +5V 0.1µF Figure 36. ADR395 as a Reference to AD5063 10µF + 0.1µF RFB Long-term drift is a measure of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the temperature dependence of the DAC output voltage on ambient conditions. SERIAL INTERFACE In high accuracy applications, which have a relatively low tolerance for noise, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references, such as the ADR435, produce low output noise in the 0.1 Hz to 10 Hz region. Examples of some recommended precision references for use as the supply to the AD5063 are shown in Table 7. Rev. C | Page 16 of 20 VDD VREF RFB SYNC RINV DIN SCLK AD5063 DACGND +5V INV BIPOLAR OUTPUT OUT AGND Figure 37. Bipolar Operation –5V EXTERNAL OP AMP 04766-037 3-WIRE SERIAL INTERFACE 10 × D ⎞ VO = ⎛⎜ ⎟−5V ⎝ 65536 ⎠ 5V 04766-036 ADR395 AD5063 POWER SUPPLY BYPASSING AND GROUNDING USING THE AD5063 WITH A GALVANICALLY ISOLATED INTERFACE CHIP In process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous commonmode voltages that may occur in the area where the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. Because the AD5063 uses a 3-wire serial logic interface, the ADuM130x family provides an ideal digital solution for the DAC interface. The ADuM130x isolators provide three independent isolation channels in a variety of channel configurations and data rates. They operate across the full range of 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. Figure 38 shows a typical galvanically isolated configuration using the AD5063. The power supply to the part also needs to be isolated; this is accomplished by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5063. 5V REGULATOR POWER 10µF 0.1µF VDD V1A V0A SCLK AD5063 ADMu1300 SDI V1B V0B SYNC DATA V1C V0C DIN VOUT GND The power supply to the AD5063 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should physically be as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and low effective series inductance (ESI), as do common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents from internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by a digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. 04766-039 SCLK When accuracy is important in a circuit, it is helpful to consider carefully the power supply and ground return layout on the board. The printed circuit board containing the AD5063 should have separate analog and digital sections, each on its own area of the board. If the AD5063 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5063. Figure 38. AD5063 with a Galvanically Isolated Interface Rev. C | Page 17 of 20 AD5063 OUTLINE DIMENSIONS 3.10 3.00 2.90 6 10 3.10 3.00 2.90 1 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD5063BRMZ 1 AD5063BRMZ-REEL71 AD5063BRMZ-11 AD5063BRMZ-1-REEL71 EVAL-AD5063EB 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C INL 1 LSB 1 LSB 1 LSB 1 LSB Settling Time 4 μs typ 4 μs typ 1 μs max 1 μs max Z = RoHS Compliant Part. Rev. C | Page 18 of 20 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 Branding D49 D49 DCG DCG AD5063 NOTES Rev. C | Page 19 of 20 AD5063 NOTES ©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04766-0-8/09(C) Rev. C | Page 20 of 20