TI SN74HC259NSR

 SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
D
D
D
D
D
D
D
10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 14 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
Asynchronous Parallel Clear
Active-High Decoder
Enable Input Simplifies Expansion
Expandable for n-Bit Applications
Four Distinct Functional Modes
SN54HC259 . . . J OR W PACKAGE
SN74HC259 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
S0
S1
S2
Q0
Q1
Q2
Q3
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
CLR
G
D
Q7
Q6
Q5
Q4
SN54HC259 . . . FK PACKAGE
(TOP VIEW)
S1
S0
NC
VCC
CLR
D Wide Operating Voltage Range of 2 V to 6 V
D High-Current Inverting Outputs Drive Up To
S2
Q0
NC
Q1
Q2
description/ordering information
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
G
D
NC
Q7
Q6
Q3
GND
NC
Q4
Q5
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
4
NC − No internal connection
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
TOP-SIDE
MARKING
Tube of 25
SN74HC259N
Tube of 40
SN74HC259D
Reel of 2500
SN74HC259DR
Reel of 250
SN74HC259DT
Reel of 2000
SN74HC259NSR
Reel of 2000
SN74HC259PWR
Reel of 250
SN74HC259PWT
CDIP − J
Tube of 25
SNJ54HC259J
SNJ54HC259J
CFP − W
Tube of 150
SNJ54HC259W
SNJ54HC259W
SOIC − D
−40°C
−40
C to 85
85°C
C
SOP − NS
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
SN74HC259N
HC259
HC259
HC259
LCCC − FK
Tube of 55
SNJ54HC259FK
SNJ54HC259FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
%(#"! "%' /011 '' %$$! $ $!$(
#'$!! *$,!$ $() '' *$ %(#"! %(#"
%"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
POST OFFICE BOX 655303
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1
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all
latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines
are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the
D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.
Function Tables
FUNCTION
INPUTS
CLR
G
OUTPUT OF
ADDRESSED
LATCH
EACH
OTHER
OUTPUT
FUNCTION
Addressable latch
H
L
D
QiO
H
H
QiO
QiO
Memory
L
L
D
L
8-line demultiplexer
L
H
L
L
Clear
LATCH SELECTION
SELECT INPUTS
2
S0
LATCH
ADDRESSED
L
L
0
L
H
1
L
H
L
2
S2
S1
L
L
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram
S0
D
C
1
Q
4
Q0
R
D
C
Q
5
Q1
R
S1
D
C
2
Q
6
Q2
R
D
C
Q
7
Q3
R
S2
3
D
C
Q
9
Q4
R
D
C
Q
10
Q5
R
G
14
D
C
Q
11
Q6
R
D
13
D
C
Q
12
Q7
R
CLR
15
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
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3
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram, each internal latch (positive logic)
C
TG
D
C
Q
C
C
C
C
TG
R
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC259
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
Low-level input voltage
SN74HC259
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
VCC = 4.5 V
VCC = 6 V
VI
VO
Input voltage
0
Output voltage
0
∆t/∆v
Input transition rise/fall time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
UNIT
V
V
4.2
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
0
0
VCC
VCC
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −20 µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
Ci
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC259
MIN
MAX
SN74HC259
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
3
10
10
10
pF
6V
2 V to 6 V
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
CLR low
tw
Pulse duration
G low
tsu
th
Setup time, data or address before G↑
G↑
Hold time, data or address after G
POST OFFICE BOX 655303
TA = 25°C
MIN
MAX
SN54HC259
MIN
MAX
SN74HC259
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
75
115
95
4.5 V
15
23
19
6V
13
20
16
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
• DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
ns
5
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC259
SN74HC259
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
60
150
225
190
tPHL
CLR
Any Q
4.5 V
18
30
45
38
6V
14
26
38
32
Data
tpd
Address
G
Any Q
Any Q
Any Q
tt
Any
MIN
MIN
MAX
MIN
MAX
2V
56
130
195
165
4.5 V
17
26
39
33
6V
13
22
33
28
2V
74
200
300
250
4.5 V
21
40
60
50
6V
17
34
51
43
2V
66
170
255
215
4.5 V
20
34
51
43
6V
16
29
43
37
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance per latch
POST OFFICE BOX 655303
No load
• DALLAS, TEXAS 75265
TYP
33
UNIT
pF
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
50%
10%
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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7
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
85519012A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
8551901EA
ACTIVE
CDIP
J
16
1
None
Call TI
Level-NC-NC-NC
8551901FA
ACTIVE
CFP
W
16
1
None
Call TI
Level-NC-NC-NC
JM38510/65402BEA
ACTIVE
CDIP
J
16
1
None
Call TI
Level-NC-NC-NC
SN54HC259J
ACTIVE
CDIP
J
16
1
None
Call TI
Level-NC-NC-NC
SN74HC259D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC259DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC259DT
ACTIVE
SOIC
D
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC259N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74HC259NSR
ACTIVE
SO
NS
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC259PWLE
OBSOLETE
TSSOP
PW
16
None
Call TI
SN74HC259PWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74HC259PWT
ACTIVE
TSSOP
PW
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SNJ54HC259FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54HC259J
ACTIVE
CDIP
J
16
1
None
Call TI
Level-NC-NC-NC
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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