SLUS274A – JANUARY 1999 – REVISED APRIL 2003 FEATURES D Precision Fault Threshold D Programmable Average Power Limiting D Programmable Linear Current Control D Programmable Overcurrent Limit D Programmable Fault Time D Fault Output Indicator D Shutdown Control D Undervoltage Lockout D 8-Pin SOIC DESCRIPTION APPLICATIONS D –48-V Distributed Power Systems D Central Office Switching D Wireless Base Stations SIMPLIFIED APPLICATION DIAGRAM RVDD R1 DC/DC Converter or Load 3 RPL Power Limiting 1 2 CVDD 8 When the output current is below the fault level, the output device is switched on. When the output current exceeds the fault level, but is less than the maximum sourcing level programmed by the IMAX pin, the output remains switched on, and the fault timer starts charging CT. Once CT charges to 2.5 V, the output device is turned off and performs a retry some time later. When the output current reaches the maximum sourcing current level, the output appears as a current source, limiting the output current to the set value defined by IMAX. M1 Current Control 7 Fault Protection and Timer 6 RS 5 UCC3913 4 R2 CT –VIN The UCCx913 family of negative voltage circuit breakers provides complete power management, hot-swap, and fault handling capability. The device is referenced to the negative input voltage and is driven through an external resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive. The on-board 10-V shunt regulator protects the device from excess voltage and serves as a reference for programming the maximum allowable output sourcing current during a fault. In the event of a constant fault, the internal timer limits the on-time from less than 0.1% to a maximum of 3%. The duty cycle modulates depending on the current into the PL pin, which is a function of the voltage across the FET, and limits average power dissipation in the FET. The fault level is fixed at 50 mV across the current-sense resistor to minimize total dropout. The fault current level is set with an external current sense resistor. The maximum allowable sourcing current is programmed with a voltage divider from VDD to generate a fixed voltage on the IMAX pin. The current level, when the output appears as a current source, is equal to VIMAX/RSENSE. If desired, a controlled current startup can be programmed with a capacitor on the IMAX pin. UDG–03059 Other features of the UCCx913 family include undervoltage lockout, and 8-pin small outline (SOIC) and dual-in-line (DIP) packages. Copyright 1999 – 2003, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!# - '# #!# &, !&"'# # - && $## ( www.ti.com 1 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA –40°C 40°C to 85°C –0°C 0°C to 70°C PACKAGE(1) PART NUMBER PDIP (N) UCC2913N SOIC (D) UCC2913D PDIP (N) UCC3913N SOIC (D) UCC3913D (1) The N and D packaged are also available taped and reeled. Add an R suffix to the device type (i.e., UCC2913NR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Input voltage Input In ut current UCC2923 UCC3913 UNIT IMAX limited to VDD V VDD 50 SHUTDOWN 10 PL mA 10 Operating junction temperature range, TJ –55 to 150 Storage temperature, Tstg –65 to 150 °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS (the most negative voltage). All currents are positive into and negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS Input current, IVDD N PACKAGE (TOP VIEW) D PACKAGE (TOP VIEW) SD/FLT IMAX VDD CT 2 1 8 2 7 3 6 4 5 PL OUT SENSE VSS www.ti.com SD/FLT IMAX VDD CT 1 8 2 7 3 6 4 5 PL OUT SENSE VSS MIN NOM MAX UNIT 2 5 20 mA SLUS274A – JANUARY 1999 – REVISED APRIL 2003 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C for UCC2913, TA = 0°C to 70°C for UCC3913, TJ = TA, IVDD = 2 mA, CT = 4.7 pF, TA = TJ (unless otherwise noted) MIN TYP 1 2 8.5 9.5 10.5 6 7 8 TJ = 25 °C Over temperature 47.5 50.0 53.0 46.0 50.0 53.5 50 500 nA –22 –36 –50 µA Timing capacitance charge current VCT = 1.0 V, IPL = 0 A Overload condition, VSENSE – VIMAX = 300 mV –0.7 –1.2 –1.7 mA Timing capacitance discharge current VCT = 1.0 V, PARAMETER TEST CONDITIONS MAX UNIT INPUT SUPPLY Minimum input current, VDD Regulator voltage 2 mA≤ ISOURCE ≤ 10 mA Undervoltage lockout off-voltage mA V FAULT TIMING Overcurrent threshold voltage Overcurrent input bias mV 0.6 1.0 1.5 µA Timing capacitance fault threshold voltage 2.2 2.4 2.6 V Timing capacitance reset threshold voltage 0.32 0.50 0.62 V 1.7% 2.7% 3.7% 8.5 10 6 8 Output duty cycle Fault condition, IPL = 0 A IPL = 0 A OUTPUT High le el output High-level o tp t voltage oltage Low level output voltage Low-level IOUT = 0 A IOUT = –1 A IOUT = 0 A, VSENSE – VIMAX = 100mV 0.01 IOUT = 2 A, VSENSE – VIMAX = 100mV 0.2 V 0.6 LINEAR AMPLIFIER Sense control voltage VIMAX = 100 mV VIMAX = 400 mV 85 100 115 370 400 430 50 500 nA 1.7 2.0 V µA Input bias mV SHUTDOWN/FAULT Shutdown threshold voltage Input current 1.4 VSD/FLT = 5 V High-level output voltage 15 25 45 6.0 7.5 9.0 Low-level output voltage 0.01 Delay-to-output time 150 V 300 ns V POWER LIMITING PL regulator voltage Duty cycle control IPL = 64 µA IPL = 64 µA 4.35 4.85 5.35 0.6% 1.2% 1.7% IPL = 1 mA 0.045% 0.1% 0.17% 300 500 OVERLOAD Delay-to-output time Output sink current Overload threshold voltage VSENSE – VIMAX = 300mV Relataive to IIMAX www.ti.com 40 100 140 200 ns mA 260 mV 3 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 TERMINAL FUNCTIONS TERMINAL NAME NO. CT 4 IMAX OUT I/O DESCRIPTION I A capacitor is connected to this pin in order to set the maximum fault time. 2 I This pin programs the maximum allowable sourcing current. 7 O Output drive to the MOSFET pass element. PL 8 I This feature ensures that the average MOSFET power dissipation is controlled. SENSE 6 I Input voltage from the current sense resistor. SD/FLT 1 O This pin provides fault output indication and shutdown control. VDD 3 O Current driven with a resistor to a voltage at least 10V more positive than VSS. VSS 5 O Ground reference for the device and the most negative voltage available. DETAILED PIN DESCRIPTIONS CT A capacitor connected to this pin allows setting of the maximum fault time. The maximum fault time must be more than the time to charge external load capacitance. The maximum fault time is defined as: t FAULT + ǒ2 C TǓ I CH (1) where I CH + 36 mA ) I PL (2) and IPL is the current into the power limit pin. Once the fault time is reached the output shuts down for a time given by: t SD + 2 10 6 CT (3) IMAX This pin programs the maximum allowable sourcing current. Since VDD is a regulated voltage, a voltage divider can be derived from VDD to generate the program level for the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin over the current sense resistor. If desired, a controlled current startup can be programmed with a capacitor on the IMAX pin, and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an R-C network. PL This pin’s feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this pin to the drain of the N-channel MOSFET pass element. When the voltage across the N-channel MOSFET exceeds 5 V, current flows into the PL pin which adds to the fault timer charge current, reducing the duty cycle from the 3% level. When IPL is much greater 36 µA, then the average MOSFET power dissipation is given by: P FET(avg) + IMAX 1 10 *6 R PL (4) SENSE Input voltage from the current sense resistor. When there is greater than 50 mV across this pin with respect to VSS, a fault is sensed, and CT starts to charge. 4 www.ti.com SLUS274A – JANUARY 1999 – REVISED APRIL 2003 DETAILED PIN DESCRIPTIONS (continued) SD/FLT This pin provides fault output indication and shutdown control. Interface into and out of this pin is usually performed through level shift transistors. When 20 µA is sourced into this pin, shutdown drives high causing the output to disable the N-channel MOSFET pass device. When opened, and under a non-fault condition, the SD/FLT pin pulls to a low state. When a fault is detected by the fault timer, or undervoltage lockout, this pin drives to a high state, indicating the output MOSFET is off. VDD Current driven with a resistor to a voltage at least 10-V more positive than VSS. Typically a resistor is connected to ground. The 10-V shunt regulator clamps VDD at 10 V above the VSS pin, and is also used as an output reference to program the maximum allowable sourcing current. BLOCK DIAGRAM VDD IMAX 3 2 UVLO LOGIC SUPPLY 5.0V REF 1= UNDERVOLTAGE 9.5-V SHUNT REGULATOR VDD 0.2 V + VDD + + – OVERLOAD COMPARATOR SD/FLT PL 7 OUT 6 SENSE 5 VSS 4 CT VDD – 5.0 V – 8 + LINEAR CURRENT AMPLIFIER 50 DISABLE 1 ON–TIME CONTROL + – + 20 µA SOURCE ONLY 50 mV OVERCURRENT COMPARATOR UDG–99001 www.ti.com 5 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION Typical Fault Mode Figure 1 shows the detailed circuitry for the fault timing function of the UCCx913. This initial discussion of the typical fault mode ignores the overload comparator, and current source I3. Once the voltage across the current sense resistor, RS, exceeds 50 mV, a fault has occurred. This causes the timing capacitor to charge with a combination of 36 µA plus the current from the power limiting amplifier. The PL amplifier is designed to source current into the CT pin only and to begin sourcing current once the voltage across the output FET exceeds 5 V. The current IPL is related to the voltage across the FET with the following expression: I PL + V FET * 5 V R PL (5) where VFET is the voltage across the N-channel MOSFET pass device. (How this feature limits average power dissipation in the pass device is described in further detail in the following sections). Note that under a condition where the output current is more than the fault level, but less than the maximum level, VOUT ≈ VSS (input voltage), IPL = 0, the CT charging current is 36 µA. LOAD RPL OVERLOAD COMPARATOR VDD 8 I1 36 µA – 5.0 V OUTPUT + 6 RS + SENSE 50 mV + – H=CLOSE I2 1 µA 5 0.5 V VSS INPUT VOLTAGE CT IMAX + SENSE TO OUTPUT DRIVE H=OFF 2.5 V H=CLOSE – I3 1mA OVERCURRENT COMPARATOR VSS + 0.2 V PL – + S Q – R Q + FAULT TIMING CIRCUITRY 4 CT VSS Figure 1. Fault Timing Circuitry Including Power Limit and Overload Comparator 6 www.ti.com UDG–99004 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION During a fault, CT charges at a rate determined by the internal charging current and the external timing capacitor. Once CT charges to 2.5 V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with the 1-µA current source, I2, until 0.5 V is reached. Once the voltage at CT reaches 0.5 V, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault comparator closes the charging switch causing the cycle to begin. Under a constant fault, the duty cycle is given by: Duty Cycle + 1 mA I PL ) 36 mA (6) Average power dissipation in the pass element is given by: P FET(avg) + V FET IMAX ǒ Ǔ 1 mA I PL ) 36 mA (7) Where VFET >> 5 V IPL can be approximated as : I PL ^ V FET R PL (8) and where IPL >> 36 µA, the duty cycle can be approximated as : Duty Cycle + 1 mA R PL V FET (9) Therefore, the maximum average power dissipation in the MOSFET can be approximated by: P FET(avg) + V FET IMAX ǒ Ǔ 1 mA R PL + IMAX V FET 1 mA R PL (10) Notice that in the approximation, VFET cancels. therefore, average power dissipation is limited in the N-channel MOSFET pass element. Overload Comparator The linear amplifier in the UCCx913 ensures that the output N-channel MOSFET does not pass more than IMAX (which is VIMAX/RS). In the event the output current exceeds the programmed IMAX by 0.2 V/RS (which can only occur if the output MOSFET is not responding to a command from the device) the CT pin begins charging with I3, 1 mA, and continue to charge to approximately 8 V. This allows a constant fault to show up on the SD/FLT pin, and also since the voltage on CT charges past 2.5 V only in an overload fault mode, it can be used for detection of output FET failure or to build in redundancy in the system. www.ti.com 7 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION Determining External Component Values (See FIgure 2) To set RVDD the following must be achieved: V IN(min) R VDD u 10 V ) 2 mA (R1 ) R2) (11) In order to estimate the minimum timing capacitor, CT, several things must be taken into account. For example, given the schematic below as a possible (and at this point, a standard) application, certain external component values must be known in order to estimate CT(min). Then use the given the values of COUT, Load, RSENSE, VSS, and the resistors determining the voltage on the IMAX pin, to calculate the approximate startup time of the node VOUT. This startup time must be faster than the time it takes for CT to charge to 2.5 V (relative to VSS), and is the basis for estimating the minimum value of CT. In order to determine the value of the sense resistor, RSENSE, assuming the user has determined the fault current, RSENSE can be calculated by: R SENSE + 50 mV I FAULT (12) Next, calculate the variable IMAX. IMAX is the maximum current that the device allows through the transistor, M1, and during startup with an output capacitor the power MOSFET, M1, can be modeled as a constant current source of value IMAX where: I MAX + V IMAX R SENSE (13) where VIMAX = voltage on IMAX pin. RVDD 3 VDD VOUT RPL PL 8 OUT 7 SENSE 6 R1 M1 2 COUT IMAX LOAD RSENSE R2 VSS 5 UCC3913 VSS Note: LOAD = ILOAD For Current Source Load LOAD = ROUT For Resistive Load UDG–03045 Figure 2. External Component Connections 8 www.ti.com SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION TIMING DIAGRAM IOUT Output Current IMAX IFAULT Io(nom) t 0A VCT 2.5V CT Voltage (w/respect to VSS) 0.5V t 0V VOUT 0V Output Voltage (w/respect to GND) VSS TIME t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t DESCRIPTION t0 Safe condition. Output current is nominal, output voltage is at the negative rail, VSS. t1 Fault control reached. Output current reaches the programmed fault value. CT begins to charge at approximately 36-µA. t2 Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 Fault occurs. CT has charged to 2.5V. Fault output goes high. The FET turns off allowing no output current to flow. VOUT floats up to ground. t4 Retry. CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT pulled down to VSS. t5 t5 = t3. Illustrates 3% duty cycle. t6 t6 = t4 t7 Output short circuit. If VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VSS and RPL. t8 Fault occurs. Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t9 t9 = t4. Output short circuit released, still in fault mode. t10 t10 = t0. Fault released. Safe condition. Return to normal operaton of the circuit breaker. www.ti.com 9 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION CVDD R1 R2 VSS RVDD CSS IMAX VDD 3 OUTPUT 2 PL 8 UVLO 5.0 V REF RT 1 = UNDERVOLTAGE 9.5 SHUNT REGULATOR VDD SD/FLT – VDD VDD – + + LOGIC SUPPLY OUT + – + LINEAR CURRENT AMPLIFIER 7 50 Ω DISABLE 1 SENSE + 20 µA + ON–TIME CONTROL SOURCE ONLY – 6 FAULT= 50 mV RS VSS 5 CT 4 CT VSS UDG–99002 Figure 3. Typical Application Diagram To calculate the startup time using the current source load. t START + C OUT |VSS| I MAX * I LOAD (14) To calculate the startup time using the resistive load. t START + C OUT 10 R OUT ln ǒ I MAX R OUT I MAX R OUT * |VSS| www.ti.com Ǔ (15) SLUS274A – JANUARY 1999 – REVISED APRIL 2003 APPLICATION INFORMATION Once tSTART is calculated, the power limit feature of the UCCx913 must be addressed and component values derived. Assuming the designer chooses to limit the maximum allowable average power that is associated with the circuit breaker, the power limiting resistor, RPL, can be easily determined by the following: R PL + P FET(avg) 1 mA I MAX (16) where a minimum RPL exists defined by R PL(min) + |VSS| 10mA (17) Finally, after computing the aforementioned variables, the minimum timing capacitor can be derived for a current source load with the following equation. C T(min) + ǒ98 mA t START R PL ) |VSS| * 10 VǓ 4V R PL (18) The minimum timing capacitor can be derived for a resistive load with the following equation. C T(min) + t START (19) ǒ49 mA R OUTǓ ) R OUT R PL ) |VSS| * 5 V * I MAX 2V C OUT |VSS| R PL AVERAGE POWER DISSIPATION vs MOSFET VOLTAGE 25.0 IMAX = 4 A R3 SHUTDOWN FAULT OUT R4 LOCAL GND LEVEL SHIFT 7 SD/FLT VSS UDG–99003 PAVG – Average Power Dissipation– W LOCAL VDD RPL = ∞ 22.5 UCC2913 UCC3913 20.0 17.5 RPL = 10 MΩ 15.0 12.5 RPL = 500 kΩ RPL = 5 MΩ 10.0 RPL = 200 kΩ 7.5 RPL = 2 MΩ 5.0 RPL = 1 MΩ 2.5 0 0 Figure 4. Possible Level Shift Circuitry Interface www.ti.com 25 50 100 125 150 75 VFET – MOSFET Voltage– V 175 200 Figure 5 11 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 SAFETY RECOMMENDATION Although the UCC3913 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3913 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3913 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. 12 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) UCC2913D ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM UCC2913DTR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM UCC2913DTRG4 PREVIEW SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2913J OBSOLETE CDIP JG 8 UCC2913N ACTIVE PDIP P 8 UCC3913D ACTIVE SOIC D UCC3913DTR ACTIVE SOIC UCC3913N ACTIVE PDIP None Call TI Call TI 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 8 75 None CU NIPDAU Level-1-220C-UNLIM D 8 2500 None CU NIPDAU Level-1-220C-UNLIM P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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