UC1914 UC2914 UC3914 5V to 35V Hot Swap Power Manager FEATURES DESCRIPTION • 5V to 35V Operation The UC3914 family of Hot Swap Power Managers provides complete power management, hot swap and fault handling capability. Integrating this part and a few external components, allows a board to be swapped in or out upon failure or system modification without removing power to the hardware, while maintaining the integrity of the powered system. Complementary output drivers and diodes have been integrated for use with external capacitors as a charge pump to ensure sufficient gate drive to the external NMOS transistor for low RDS(on). All control and housekeeping functions are integrated and externally programmable and include the fault current level, maximum output sourcing current, maximum fault time and average power limiting of the external FET. The UC3914 features a duty ratio current limiting technique, which provides peak load capability while limiting the average power dissipation of the external pass transistor during fault conditions. The fault level is fixed at 50mV with respect to VCC to minimize total dropout. The fault current level is set with an external current sense resistor. The maximum allowable sourcing current is programmed by using a resistor divider from VCC to REF to set the voltage on IMAX. The maximum current level, when the output appears as a current source is (VCC – VIMAX)/RSENSE. • Precision Maximum Current Control • Precision Fault Threshold • Programmable Average Power Limiting • Programmable Overcurrent Limit • Shutdown Control • Charge Pump for Low RDS(on) High-Side Drive • Latch Reset Function Available • Output Drive VGS Clamping • Fault Output Indication • 18 Pin DIL and SOIC Packages (continued) BLOCK DIAGRAM UDG-95134-2 SLUS425A - AUGUST 1999 UC1914 UC2914 UC3914 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM Input Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . 40V Maximum Forced Voltage SD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC LR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Maximum Current FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA PLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Maximum Voltage, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . 40V Reference Output Current . . . . . . . . . . . . . . . Internally Limited Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-18, SOIC-18 (Top View) N or J Package, DW Package Unless otherwise indicated, voltages are referenced to ground. Currents are positive into, negative out of specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. DESCRIPTION (cont.) When the output current is less than the fault level, the external output transistor remains switched on. When the output current exceeds the fault level, but is less than the maximum sourcing level programmed by IMAX, the output remains switched on, and the fault timer starts to charge CT, a timing capacitor. Once CT charges to 2.5V, the output device is turned off and CT is slowly discharged. Once CT is discharged to 0.5V, the IC performs a retry and the output transistor is switched on again. The UC3914 offers two distinct reset modes. In one mode with LR left floating or held low, the IC will repeatedly try to reset itself if a fault occurs as described above. In the second mode with LR held high, once a fault occurs, the output is latched off until either LR is toggled low, the part is shutdown then re-enabled using SD, or the power to the part is turned off and then on again. This part is offered in both 18 pin DW Wide-Body (SOIC) and Dual-In-Line (DIL) packages. ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UC3914, –40°C to 85°C for the UC2914, and –55°C to 125°C for the UC1914. VCC = 12V, VPUMP = VPUMP(max), SD = 5V, CP1 = CP2 = CPUMP = 0.01µF. T A = T J. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VCC Section ICC (Note 2) 8 15 mA VCC = 35V, (Note 2) 12 20 mA Shutdown ICC SD = 0V 500 900 µA UVLO Turn on threshold 4.0 4.4 V 100 200 350 mV TJ = 25°C, with respect to VCC –55 –50 –45 mV Over operating temperature, with respect to VCC –57 –50 –42 mV 1 3 µA µA UVLO Hysteresis Fault Timing Section Overcurrent Threshold IMAX Input Bias CT Charge Current CT = 1V –140 –100 –60 CT Discharge Current CT = 1V 2.0 3.0 4.5 µA CT Charge Current CT = 1V, Overload condition –6.0 –3.0 –1.5 mA CT Fault Threshold 2.25 2.50 2.75 V CT Reset Threshold 0.45 0.50 0.55 V 1.5 3.0 4.5 % Output Duty Cycle Fault condition, IPL = 0 2 UC1914 UC2914 UC3914 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UC3914, –40°C to 85°C for the UC2914, and –55°C to 125°C for the UC1914. VCC = 12V, VPUMP = VPUMP(max), SD = 5V, CP1 = CP2 = CPUMP = 0.01µF. T A = T J. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output Section OUT High Voltage VOUTS = VCC, VPUMP = VPUMP max, with respect to VPUMP –1.5 –1.0 V OUT High Voltage VOUTS = VCC, VPUMP = VPUMP max, IOUT = –2mA, with respect to VPUMP –2.0 –1.5 V OUT Low Voltage IOUT = 0 0.8 IOUT = 5mA IOUT = 25mA, Overload Condition, VOUTS = 0V 11.5 1.3 V 1 2 V 1.2 1.8 V OUT Clamp Voltage VOUTS = 0V 13.0 14.5 V Rise Time COUT = 1nF (Note 1) 750 1250 ns Fall Time COUT = 1nF (Note 1) 250 500 ns Charge Pump Section OSC, OSCB Frequency 60 150 250 kHz 10.0 11.0 11.6 V 0.2 0.5 V OSC, OSCB Output Clamp Voltage VCC = 25 18.5 20.5 22.5 V OSC, OSCB Output Current Limit High Side Only –20 –10 –3 mA Pump Diode Voltage Drop IDIODE = 10mA, Measured from PMP to PMPB, PMPB to VPUMP 0.5 0.9 1.3 V PMP Clamp Voltage VCC = 25 18.5 20.5 22.5 V VPUMP Maximum Voltage VCC = 12, VOUTS = VCC, Voltage Where Charge Pump Disabled 20 22 24 V VCC = 35V, VOUTS = VCC, Voltage Where Charge Pump Disabled 42 45 48 V VCC = 12, VOUTS = VCC, Voltage Where Charge Pump Re-enabled 0.3 0.7 1.4 V VCC = 35V, VOUTS = VCC, Charge Pump Re-enabled 0.25 0.7 1.4 V –15 0 15 mV 20 mV OSC, OSCB Output High IOSC = –5mA OSC, OSCB Output Low IOSC = 5mA VPUMP Hysteresis Linear Current Section Input Offset Voltage Voltage Gain IMAX Control Voltage 60 80 IMAX = OUT, SENSE = VCC, with respect to VCC –20 0 IMAX = OUT, SENSE = REF, with respect to REF –20 dB 0 20 mV 1.5 3.5 µA –2.25 –2.00 –1.75 V 12.5 SENSE Input Bias Reference Section REF Output Voltage With respect to VCC REF Current Limit 20.0 50.0 mA Load Regulation IVREF = 1mA to 5mA 25 60 mV Line Regulation VCC = 5V to 35V 25 100 mV Shutdown Section Shutdown Threshold 1.5 2.0 V Input Current SD = 5V 0.6 150 300 µA Delay to Output (Note 1) 0.5 2.0 µs Fault Output Low IFAULT = 1mA 100 200 mV Fault Output Leakage VFAULT = 35V 10 500 nA Fault Section 3 UC1914 UC2914 UC3914 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UC3914, –40°C to 85°C for the UC2914, and –55°C to 125°C for the UC1914. VCC = 12V, VPUMP = VPUMP(max), SD = 5V, CP1 = CP2 = CPUMP = 0.01µF. T A = T J. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.6 1.4 2.0 V 500 750 µA Latch Section LR Threshold High to Low Input Current LR = 5V Power Limiting Section Duty Cycle Control In Fault, IPLIM = 200µA 0.6 1.3 2.0 % In Fault, IPLIM = 3mA 0.05 0.12 0.20 % 500 1250 ns –250 –200 –150 mV Overload Section Delay to Output (Note 1) Threshold Respect to IMAX Note 1: Guaranteed by design. Not 100% tested in production. Note 2: A mathematical averaging is used to determine this value. See Application Section for more information. PIN DESCRIPTIONS a power-on-reset occurs. Pulling this pin low before the reset time is reached will not clear the fault until the reset time is reached. Floating or holding this pin low will result in the part repeatedly trying to reset itself if a fault occurs. CT: A capacitor is connected to this pin in order to set the maximum fault time. The minimum fault time must be more than the time to charge external load capacitance. The fault time is defined as: T FAULT = 2 • CT ICH OUT: Output drive to the MOSFET pass element. Internal clamping ensures that the maximum VGS drive is 15V. where ICH = 100µA + IPL, where IPL is the current into the power limit pin. Once the fault time is reached the output will shutdown for a time given by: T SD = OSC, OSCB: Complementary output drivers for intermediate charge pump stages. A 0.01µF capacitor should be placed between OSC and PMP, and OSCB and PMPB. 2 • CT I DIS PLIM: This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this pin to VCC. Current will flow into PLIM which adds to the fault timer charge current, reducing the duty cycle from the typical 3% level. When IPL >> 100µA then the average MOSFET power dissipation is given by: –6 PFET_AVG = IMAX • 3 • 10 •RPL. where IDIS is nominally 3µA. FAULT: Open collector output which pulls low upon any of the following conditions: Timer fault, Shutdown, UVLO. This pin MUST be pulled up to VCC or another supply through a suitable impedance. GND: Ground reference for the IC. PMP, PMPB: Complementary pins which couple charge pump capacitors to internal diodes and are used to provide charge to the reservoir capacitor tied to VPUMP. Typical capacitor values used are 0.01µF. IMAX: This pin programs the maximum allowable sourcing current. Since REF is a –2V reference (with respect to VCC), a voltage divider can be derived from VCC to REF in order to generate the program level for the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin, with respect to VCC, divided by the current sense resistor. If desired, a controlled current startup can be programmed with a capacitor on IMAX to VCC. REF: –2V reference with respect to VCC used to program the IMAX pin voltage. A 0.1µF ceramic or tantalum capacitor MUST be tied between this pin and VCC to ensure proper operation of the chip. SD: When this TTL compatible input is brought to a logic low, the output of the linear amplifier is driven low, FAULT is pulled low and the IC is put into a low power mode. The ABSOLUTE maximum voltage that can be placed on this pin is 12V. LR: If this pin is held high and a fault occurs, the timer will be prevented from resetting the fault latch when CT is discharged below the reset comparator threshold. The part will not retry until this pin is brought to a logic low or 4 UC1914 UC2914 UC3914 PIN DESCRIPTIONS (cont.) SENSE: Input voltage from current sense resistor. When there is greater than 50mV across this pin with respect to VCC, a fault is sensed and CT begins to charge. VOUTS: Source connection of external N-channel MOSFET and sensed output voltage of load. VPUMP: Charge pump output voltage. A capacitor should be tied between this pin and VOUTS with a typical value being 0.01µF. VCC: Input voltage to the IC. Typical voltages are 4.5V to 35V. The minimum input voltage required for operation is 4.5V. TYPICAL CHARACTERISTIC CURVES Linear Amp VIO vs. Temperature Fault Threshold vs. Temperature FAULT THRESHOLD (mV) 3.5 VIO (mV) 3 2.5 2 1.5 1 0.5 0 -55 -40 0 25 70 85 TEMPERATURE (°C) 125 -48 -48.5 -49 -49.5 -50 -50.5 -51 -51.5 -52 -55 -40 0 25 70 85 125 TEMPERATURE (°C) CT ICHARGE vs. Temperature VCC - REF vs Temperature IMAX & SENSE Input Bias vs. Temperature CT IDISCHARGE vs. Temperature Figure 1. Typical characteristic curves. 5 UC1914 UC2914 UC3914 APPLICATION INFORMATION The UC3914 is to be used in conjunction with external passive components and an N-channel MOSFET (NMOS) to facilitate hot swap capability of application modules. A typical application set-up is given in Fig. 9. The term hot swap refers to the system requirement that submodules be swapped in or out upon failure or system modification without removing power to the operating hardware. The integrity of the power bus must not be compromised due to the addition of an unpowered module. Significant power bus glitches can occur due to the substantial initial charging current of on-board module bypass capacitance and other load conditions (for more information on hot swapping and power management applications, see Application Note U-151). The UC3914 provides protection by monitoring and controlling the output current of an external NMOS to charge this capacitance and provide load current. The addition of the NMOS, a sense resistor, RSENSE, and two other resistors, R1 and R2, sets the programmed maximum current level the NMOS can source to charge the load in a controlled manner. The equation for this current, IMAX, is: I MAX = VCC − V IMAX R SENSE where VIMAX is the voltage generated at the IMAX pin. Analysis of the application circuit shows that VIMAX (with respect to GND) can be defined as: V IMAX = V REF + (VCC − V REF ) • R1 R1 + R 2 = 2V • R1 + V REF R1 + R 2 where VREF is the voltage on the REF pin and whose internally generated potential is two volts below VCC. The UC3914 also has an internal overcurrent comparator which monitors the voltage between SENSE and VCC. If this voltage exceeds 50mV, the comparator determines that a fault has occurred, and a timing capacitor, CT, will begin to charge. This can be rewritten as a current which causes a fault, IFAULT: I FAULT = 50mV R SENSE Fault Timing Fig. 2 shows the circuitry associated with the fault timing function of the UC3914. A typical fault mode, where the overload comparator and current source I3 do not factor into operation (switch S2 is open), will first be considered. Once the voltage across RSENSE exceeds 50mV, a fault has occurred. This causes the timing capacitor, CT, to charge with a combination of 100µA (I1) plus the current from the power limiting circuitry (IPL). UDG-97052 Figure 2. Fault timing circuitry for the UC3914, including power limit and overcurrent. 6 UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) Fig. 3a shows typical fault timing waveforms for the external NMOS output current, the voltage on the CT pin, and the output load voltage, VOUT, with LR left floating or grounded. The output voltage waveforms have assumed an RC characteristic load and time constants will vary depending upon the component values. Prior to time t0, the load is fully charged to almost VCC and the NMOS is supplying the current, IO, to the load. At t0, the current begins to ramp up due to a change in the load conditions until, at t1, the fault current level, IFAULT, has been reached to cause switch S1 to close. This results in CT being charged with the current sources I1 and IPL. During this time, VOUT is still almost equal to VCC except for small losses from voltage drops across the sense resistor and the NMOS. The output current reaches the programmed maximum level, IMAX, at t2. The CT voltage continues to rise since IMAX is still greater than IFAULT. The load output voltage drops because the current load requirements have become greater than the controlled maximum sourcing current. The CT voltage reaches the upper comparator threshold (Fig. 2) of 2.5V at t3, which promptly shuts off the gate drive to the NMOS (not UDG-97054 t0: Normal conditions - output current is nominal, output voltage is at positive rail, VCC goes low, the FET turns off allowing no output current to flow, VOUT discharge to GND. t1: Fault control reached - output current rises above the programmed fault value, CT begins to charge with ≅ 100µA + IPL. t4: Retry - CT has discharged to 0.5V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT increases. t2: Maximum current reached - output current reaches the programmed maximum level and becomes a constant current with value IMAX. t5 = t3: Illustrates <3% duty cycle depending upon RPL selected. t3: Fault occurs - CT has charged to 2.5V, fault output Figure 3a: Typical timing diagram. 7 t6 = t4 t7 = t0: Fault released, normal condition - return to normal operation of the hot swap power manager. UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) source to charge CT. VCC – VOUTS represents the voltage across the NMOS pass device. shown but can be inferred from the fact that no output current is provided to the load), latches in the fault and opens switch S1 disconnecting the charging currents I1 and IPL from CT. Since no output current is supplied, the load voltage decays at a rate determined by the load characteristics and the capacitance. The 3µA current source, I2, discharges CT to the 0.5V reset comparator threshold. This time is significantly longer than the charging time and is the basis for the duty cycle current limiting technique. When the CT voltage reaches 0.5V at t4, the part performs a retry, allowing the NMOS to again source current to the load and cause VOUT to rise. In this particular example, IMAX is still sourced by the NMOS at each attempted retry and the fault timing sequence is repeated until time t7 when the load requirements change to IO. Since IO is less than the fault current level at this time, switch S1 is opened, I2 discharges CT and VOUT rises to almost VCC. Later it will be shown how this feature will limit average power dissipation in the pass device. Note that under a fault condition where the output current is just above the fault level, but less than the maximum level, VOUTS ~ VCC, IPL = 0 and the CT charging current is 100µA. During a fault, the CT pin will charge at a rate determined by the internal charging current and the external timing capacitor, CT. Once CT charges to 2.5V, the fault comparator trips and sets the fault latch. When this occurs, OUT is pulled down to VOUTS, causing the external NMOS to shut off and the charging switch, S1, to open. CT will be discharged with I2 until the CT potential reaches 0.5V. Once this occurs, the fault latch will reset (unless LR is being held high, whereby a fault can only be cleared by pulling this pin low or going through a power-on-reset cycle), which re-enables the output of the linear amplifier and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the overcurrent comparator will close the charging switch causing the cycle to repeat. Under a constant fault the duty cycle is given by: Fig. 3b shows fault timing waveforms similar to those depicted in Fig. 3a except that the latch reset (LR) function is utilized. Operation is the same as described above until t4 when the voltage on CT reaches the reset threshold. Holding LR high prevents the latch from being reset, preventing the IC from performing a retry (sourcing current to the load). The UC3914 is latched off until either LR is pulled to a logic low, or the chip is forced into an under voltage lockout (UVLO) condition and back out of UVLO causing the latch to automatically perform a power on reset. Fig. 3b illustrates LR being toggled low at t5, causing the part to perform a retry. Time t6 again illustrates what happens when a fault is detected. The LR pin is toggled low and back high at time t7, prior to the voltage on the CT pin hitting the reset threshold. This information tells the UC3914 to allow the part to perform a retry when the lower reset threshold is reached, which occurs at t8. Time t9 corresponds to when load conditions change to where a fault is not present as described for Fig. 3a. Duty Cycle = Average power dissipation can be limited using the PLIM pin. Average power dissipation in the pass element is given by: PFETavg = (VCC − VOUTS ) • I MAX • Duty Cycle = (VCC − VOUTS ) • I MAX • I PL 3 µA + 100 µA VCC – VOUTS is the drain to source voltage across the FET. When IPL >> 100µA, the duty cycle equation given above can be rewritten as: Power Limiting Duty Cycle = The power limiting circuitry is designed to only source current into the CT pin. To implement this feature, a resistor, RPL, should be placed between VCC and PLIM. The current, IPL (show in Fig. 2) is given by the following expression: I PL = 3 µA I PL + 100 µA RPL • 3µA (VCC − VOUTS ) and the average power dissipation of the MOSFET is given by: PFETavg = (VCC − VOUTS ) • IMAX • VCC − VOUTS , for VOUTS > 1V + VCT R PL RPL • 3µA (VCC − VOUTS ) = IMAX • RPL • 3µA where VCT is the voltage on the CT pin. For VOUTS < 1V + VCT the common mode range of the power limiting circuitry causes IPL = 0 leaving only the 100µA current The average power is limited by the programmed IMAX current and the appropriate value for RPL. 8 UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) UDG-97055 t0: Normal conditions - output current is nominal, output voltage is at positive rail, VCC t4: Reset comparator threshold reached but no retry since LR pin held high. t1: Fault control reached - output current rises above the programmed fault value, CT begins to charge with ≅ 100µA + IPL. t5: LR toggled low, NMOS turned on and sources current to load. t2: Maximum current reached - output current reaches the programmed maximum level and becomes a constant current with value IMAX. t7: LR toggled low before VCT reaches reset comparator threshold, causing retry. t6 = t3 t8: Since LR toggled low during present cycle, NMOS turned on and sources current to load. t3: Fault occurs - CT has charged to 2.5V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharge to GND. t9 = t0: Fault released, normal condition - return to normal operation of the hot swap power manager. Figure 3b. Typical timing diagram utilizing LR (Latch Reset) function. 9 UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) capacitor, M1 can be modeled as a constant current source of value IMAX where: Overload Comparator The linear amplifier in the UC3914 ensures that the external NMOS does not source more than the current IMAX, defined above as: I MAX = I MAX = VCC − V IMAX R SENSE VCC − V IMAX R SENSE Given this information, calculation of startup time is now possible via the following: Current Source Load: In the event that output current exceeds the programmed IMAX by more than 200mV/RSENSE, the output of the linear amplifier will immediately be pulled low (with respect to VOUTS) providing no gate drive to the NMOS, and preventing current from being delivered to the load. This situation could occur if the external NMOS is not responding to a command from the IC or output load conditions change quickly to cause an overload condition before the linear amplifier can respond. For example, if the NMOS is sourcing current into a load and the load suddenly becomes short circuited, an overload condition may occur. The short circuit will cause the VGS of the NMOS to immediately increase, resulting in increased load current and voltage drop across RSENSE. If this drop exceeds the overload comparator threshold, the amplifier output will be quickly pulled low. It will also cause the CT pin to begin charging with I3, a 3mA current source (refer to Fig. 2) and continue to charge until approximately one volt below VCC, where it is clamped. This allows a constant fault to show up on FAULT and since the voltage on CT will only charge past 2.5V in an overload fault condition, it can be used for detection of output NMOS failure or to build redundancy into the system. T START = C LOAD • VCC I MAX – I LOAD Resistive Load: VCC T START = −R LOAD • C LOAD • ln 1 − I MAX • R LOAD The only remaining external component which may affect the minimum timing capacitor is the optional power limiting resistor, RPL. If the addition of RPL is desirable, its value can be determined from the “Fault Timing” section above. The minimum timing capacitor values are now given by Current Source Load: CT min = T START VCC −4 10 • R PL + 2 • 2 • R PL Estimating Minimum Timing Capacitance The startup time of the IC may not exceed the fault time for the application. Since the timing capacitor, CT, determines the fault time, its minimum value can be determined by calculating the startup time of the IC. The startup time is dependent upon several external components. A load capacitor, CLOAD, should be tied between VOUTS and GND. Its value should be greater than that of CPUMP, the reservoir capacitor tied from VPUMP to VOUTS (see Fig. 4). Given values of CLOAD, Load, RSENSE, VCC and the resistors determining the voltage on IMAX, the user can calculate the approximate startup time of the node VOUT. This time must be less than the time it takes for CT to charge to 2.5V. Assuming the user has determined the fault current, RSENSE can be calculated by: R SENSE = 50mV I FAULT UDG-97056 IMAX is the maximum current the UC3914 will allow through the transistor M1. During startup with an output Figure 4. Estimating minimum timing capacitor. 10 UC1914 UC2914 APPLICATION INFORMATION (cont.) Resistive Load: CT min = (10 + −4 current of the MOSFET will be controlled via soft start as long as the soft start time constant (τSS) is much greater than the charge pump time constant τCP, given by ) • R PL + VCC − (I MAX • R LOAD ) • T START 2 • R PL τ SS = (R1 R 2) • C SS Minimizing Total Dropout Under Low Voltage Operation VCC • R LOAD • C LOAD 2R PL In a typical application, the UC3914 will be used to control the output current of an external NMOS during hot swapping situations. Once the load has been fully charged, the desired output voltage on the load, VOUT, will be required to be as close to VCC as possible to minimize total dropout. For a resistive load, RLOAD, the output voltage is given by: Output Current Softstart The external MOSFET output current can be increased at a user-defined rate to ensure that the output voltage comes up in a controlled fashion by adding capacitor CSS, as shown in Fig. 5. The chip does place one constraint on the soft start time and that is that the charge pump time constant has to be much less than the softstart time constant to ensure proper soft start operation. The time constant determining the startup time of the charge pump is given by: VOUT = RSENSE was picked to set the fault current, IFAULT. RDS(on), the on-resistance of the NMOS, should be made as small as possible to ensure VOUT is as close to VCC as possible. For a given NMOS, the manufacturer will specify the RDS(on) for a certain VGS (maybe 7V to 10V). The source potential of the NMOS is VOUT. In order to ensure sufficient VGS, this requires the gate of the NMOS, which is the output of the linear amplifier, to be many volts higher than VCC. The UC3914 provides the capability to generate this voltage through the addition of 3 capacitors, CP1, CP2 and CPUMP as shown in Fig. 6. These capacitors should be used in conjunction with the complementary output drivers and internal diodes included on-chip to create a charge pump or voltage tripler. The circuit boosts VCC by utilizing capacitors CP1, CP2 and CPUMP in such a way that the voltage at VPUMP approximately equals (3 • VCC ) – (5 • VDIODE), almost tripling the input supply voltage to the chip. τCP = ROUT • C PUMP ROUT is the output impedance of the charge pump given by: ROUT = R LOAD R LOAD • VCC + R SENSE + R DS (on ) 1 fPUMP • CP where fPUMP is the charge pump frequency (125kHz) and CP = CP1 = CP2 are the charge pump flying capacitors. For typical values of CP1, CP2 and CPUMP (0.01µF) and a switching frequency of 125kHz, the output impedance is 800Ω and the charge pump time constant is 8µs. The charge pump should be close to being fully charged in 3 time constants or 24µs. By placing a capacitor from VCC to IMAX, the voltage at IMAX, which sets the maximum output current of the FET, will exponentially decay from VCC to the desired value set by R1 and R2. The output C1 CSS R1 R2 18 16 2 REF IMAX VCC M1 6 OSC OUT 11 9 PMP VOUTS 12 8 OSCB 5 PMPB CP1 VOUT CPUMP CP2 VPUMP L O A D CLOAD 7 UDG-97058 UDG-98160 Figure 5. MOSFET soft start diagram. Figure 6. Charge pump block diagram. 11 UC1914 APPLICATION INFORMATION (cont.) On each complete cycle, CP1 is charged to approximately VCC – VDIODE (unless VCC is greater than 15V causing internal clamping to limit this charging voltage to about 13V) when the output Q of the toggle flip flop is low. When Q is transitioned low (and Q correspondingly is brought high), the negative side of CP2 is pulled to ground, and CP1 charges CP2 up to about (2 • VCC – 3 • VDIODE). When Q is toggled high, the negative side of CP2 is brought to (VCC –VDIODE). Since the voltage across a capacitor cannot change instantaneously with time, the positive side of the capacitor swings up to (3 • VCC – 4 • VDIODE). This charges CPUMP up to (3 • VCC – 5 • VDIODE). Fig. 8 shows a way to use the existing drivers with external diodes (or Schottky diodes for even higher pump voltages but with additional cost) and capacitors to make a voltage quadrupler. The additional charge pump stage will provide a sufficient pump voltage (VPUMP = 4 • VCC – 7 • VDIODE) to generate the maximum VGS. Operation is similar to the case described above. This additional circuitry is not necessary for higher input voltages because the UC3914 has internal clamping which only allows VPUMP to be 10V greater than VOUTS. Input Voltage (VCC) 4.5 5 5.5 6 6.5 7 9 10 The maximum output voltage of the linear amplifier is actually less than this because of the ability of the amplifier to swing to within approximately 1V of VPUMP. Due to inefficiencies of the charge pump, the UC3914 may not have sufficient gate drive to fully enhance a standard power MOSFET when operating at input voltages below 7V. Logic Level MOSFETs could be used depending on the application but are limited by their lower current capability. For applications requiring operation below 7V there are two ways to increase the charge pump output voltage. Fig. 7 shows the typical tripler of Fig. 6 enhanced with three external schottky diodes. Placing the schottky diodes in parallel with the internal charge pump diodes decreases the voltage drop across each diode thereby increasing the overall efficiency and output voltage of the charge pump. Internal Diodes (VGS) 4.57 5.8 6.6 7.6 8.7 8.8 9.2 9.3 External Quadrupler Schottky Diodes (VGS) (VGS) 6.8 8.7 7.9 8.8 8.6 8.9 8.8 9 8.8 9 9 9 9.4 9.1 9.4 9.3 Table 1. UC3914 charge pump characteristics. Table 1 characterizes the UC3914 charge pump in its standard configuration, with external schottky diodes, and configured as a voltage quadrupler. Please note: The voltage quadrupler is unnecessary for input voltages above 7.0V due the internal clamping action. ICC Specification PMP 9 CP1 VCC 2 The ICC operating measurement is actually a mathematical calculation. The charge pump voltage is constantly being monitored with respect to both VCC and VOUTS to determine whether the pump requires servicing. If there is insufficient voltage on this pin, the charge pump drivers are alternately switched to raise the voltage of the pump (see Fig. 9). Once the voltage on the pump is high enough, the drivers and other charge pump related circuitry are shutdown to conserve current. The pump voltage will decay due to internal loading until it reaches a low enough level to turn the drivers back on. The chip requires significantly different amounts of current during these two modes of operation and the following mathematical calculation is used to figure out the average current: OSC 6 D1 D2 PMPB 8 D3 CP2 TOGGLE FLIP FLOP Q OSCB 5 QT 7 VPUMP 250kHz OSCILLATOR ICC = CPUMP TO VOUT UDG-98204 Figure 7. Enhanced charge pump block diagram. 12 ICC DRIVERS (on ) • TON + ICC DRIVERS (off ) • TOFF TON + TOFF UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) Since the charge pump does not always require servicing, the user may think that the charge pump frequency is much less than the datasheet specification. This is not the case as the free-running frequency is guaranteed to be within the datasheet limits. The charge pump servicing frequency can make it appear as though the drivers are operating at a much lower frequency. UDG-97059 Figure 8. Low voltage operation to produce higher pump voltage. PUMP UPPER LEVEL PUMP PUMP LOWER LEVEL "PUMP" SERVICING FREQUENCY OSCILLATOR FREQUENCY OSC OSCB TON TOFF TIME Figure 9. Charge pump waveforms. 13 UDG-98144 UC1914 UC2914 UC3914 APPLICATION INFORMATION (cont.) C1 R1 PMP OSC 9 REF 6 18 VCC PMPB 5 VPUMP 7 CPUMP VOUT +10V (45VMAX) – – TO LINEAR AMPLIFIER RFAULT Q Q TO VCC GND C2 103mA VPUMP FAULT LATCH S R FAULT TIMING CIRCUITRY 1 + – LINEAR – AMPLIFIER + 3m A 0.5V RSENSE 17 H=CLOSE 2.5V – FAULT= 50mV VCC 2 – 3mA H=CLOSE 10 200mV OVERCURRENT COMPARATOR 50mV + SD 4 FAULT + TOGGLE + UNDERVOLTAGE LOCKOUT 4.0V / 3.8V TO VOUT OVERLOAD COMPARATOR + CP2 250kHz OSCILLATOR T VCC IMAX 16 VCC – 2V REFERENCE 8 OSCB R2 + CP1 11 1.4V OUT 15V 12 + SENSE 14 VOUTS RPL PLIM – + 13 15 LR CT CT VOUT UDG-98194 Figure 10. Typical application. SAFETY RECOMMENDATIONS Although the UC3914 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UC3914 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UC3914 will prevent the fuse from blowing in virtually all fault conditions, increasing system reliability and reducing maintainence cost, in addition to providing the hot swap benefits of the device. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 14