SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
D
D
D
D
D
D
D
D
D
D
D
D
D
Meets IEEE Standard 488-1978 (GPIB)
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
Designed to Implement Control Bus
Interface
SN75161B Designed for Single Controller
SN75162B Designed for Multiple
Controllers
High-Speed, Low-Power Schottky Circuitry
Low Power Dissipation . . . 72 mW Max Per
Channel
Fast Propagation Times . . . 22 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis . . . 650 mV Typ
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (VCC = 0)
SN75161B . . . DW OR N PACKAGE
(TOP VIEW)
GPIB
I/O Ports
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
Terminal
I/O Ports
(TOP VIEW)
The SN75161B and SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B octal
bus transceiver, the SN75161B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
The SN75161B and SN75162B feature eight
driver-receiver pairs connected in a front-to-back
configuration to form input/output (I/O) ports at
both the bus and terminal sides. A powerup/-down disable circuit is included on all bus and
receiver outputs. This provides glitch-free operation during VCC power up and power down.
1
SN75162B . . . DW PACKAGE
GPIB
I/O Ports
description
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
DC
Terminal
I/O Ports
SN75162B . . . N PACKAGE
(TOP VIEW)
GPIB
I/O Ports
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
2
22 VCC
21 NC
3
20 REN
4
19 IFC
5
18 NDAC
6
17 NRFD
7
16 DAV
8
15 EOI
9
14 ATN
10
13 SRQ
11
12 DC
1
Terminal
I/O Ports
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
description (continued)
The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B)
enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161B and SN75162B are characterized for operation from 0°C to 70°C.
Function Tables
SN75161B RECEIVE/TRANSMIT
CONTROLS
BUS-MANAGEMENT CHANNELS
DC
TE
ATN†
H
H
H
H
H
L
L
L
H
L
L
L
H
L
X
L
H
X
ATN†
SRQ
REN
IFC
DATA-TRANSFER CHANNELS
EOI
DAV
NDAC
(Controlled by DC)
NRFD
(Controlled by TE)
T
R
T
R
R
T
R
T
T
R
T
R
R
R
R
T
T
T
R
T
T
T
T
R
R
R
R
T
T
R
R
R
T
T
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
† ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75162B RECEIVE/TRANSMIT
CONTROLS
SC
BUS-MANAGEMENT CHANNELS
ATN†
DATA-TRANSFER CHANNELS
DC
TE
ATN†
H
H
H
H
H
L
L
L
H
L
L
L
H
L
X
R
T
R
R
T
T
L
H
X
T
R
T
T
R
R
SRQ
(Controlled by DC)
R
T
T
R
REN
IFC
EOI
DAV
(Controlled by SC)
R
R
T
T
T
L
R
R
NRFD
(Controlled by TE)
T
H
NDAC
T
R
R
R
T
T
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
† ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
2
POST OFFICE BOX 655303
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SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
CHANNEL-IDENTIFICATION TABLE
NAME
IDENTITY
Direction Control
TE
Talk Enable
SC
System Control (SN75162B only)
ATN
Attention
SRQ
Service Request
REN
Remote Enable
Bus
IFC
Interface Clear
Management
EOI
End of Identity
DAV
Data Valid
NDAC
Not Data Accepted
Data
NRFD
Not Ready for Data
Transfer
Control
SN75161B logic symbol†
DC
TE
11
1
13
SN75161B logic diagram (positive logic)
EN1/G4
DC
EN2/G5
1
5
ATN
TE
EN3
8
SRQ
REN
IFC
DAV
NDAC
NRFD
14
1
19
3
7
1
1
1
1
9
2
1
18
1
1
3
1
15
1
1
6
2
17
2
1
2
1
4
2
16
5
2
2
ATN
ATN
1
3
12
11
1
4
1
EOI
CLASS
DC
13
8
14
7
12
9
19
2
18
3
15
6
17
4
16
5
ATN
EOI
SRQ
EOI
EOI
REN
SRQ
SRQ
IFC
DAV
REN
REN
NDAC
NRFD
IFC
IFC
1
{ This symbol is in accordance with IEEE Std 91-1984 and
DAV
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
NDAC
NRFD
POST OFFICE BOX 655303
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DAV
NDAC
NRFD
3
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
SN75162B logic symbol†
DC
TE
SC
12
2
1
EN1/G4
14
DC
EN2/G5
EN3
TE
≥1
5
ATN
SN75162B logic diagram (positive logic)
EN3
SC
4
1
EOI
SRQ
REN
IFC
DAV
NDAC
NRFD
15
13
20
19
16
18
17
1
1
6
6
1
1
1
3
1
3
3
1
2
2
1
2
2
1
2
1
8
ATN
ATN
EOI
EOI
1
3
9
2
10
3
4
7
5
6
12
2
1
14
9
15
8
13
10
20
3
19
4
16
7
18
5
17
6
EOI
SRQ
REN
SRQ
SRQ
IFC
REN
REN
DAV
NDAC
IFC
IFC
NRFD
{This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
DAV
NDAC
NRFD
Pin numbers shown are for the N package.
4
ATN
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DAV
NDAC
NRFD
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
VCC
TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
VCC
10 kΩ
NOM
1.7 kΩ
NOM
9 kΩ
NOM
Input
4 kΩ
NOM
GND
GND
Input/Output Port
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
VCC
R(eq)
4 kΩ
NOM
1.7 kΩ
NOM
10 kΩ
NOM
4 kΩ
NOM
GND
Input/Output Port
Driver output R(eq) = 30 Ω NOM
Receiver output R(eq) = 110 Ω NOM
Circuit inside dashed lines is on the driver outputs only.
R(eq) = equivalent resistor
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
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5
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW (20 pin)
1125 mW
9.0 mW/°C
720 mW
DW (24 pin)
1350 mW
10.8 mW/°C
864 mW
N (20 pin)
1150 mW
9.2 mW/°C
736 mW
N (22 pin)
1700 mW
13.6 mW/°C
1088 mW
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High level output current,
High-level
current IOH
Low level output current,
Low-level
current IOL
V
Bus ports with 3-state outputs
– 5.2
mA
Terminal ports
– 800
µA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
6
V
0.8
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
mA
°C
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
Vhys
Hysteresis voltage
(VIT + – VIT –)
VOH‡
High level output voltage
High-level
VOL
Low level output voltage
Low-level
II
Input current at maximum
input voltage
IIH
IIL
VI/O(b
I/O(bus))
High-level input current
Low-level input current
TEST CONDITIONS
II = – 18 mA
MAX
UNIT
– 0.8
– 1.5
V
See Figure 7
0.4
0.65
Terminal
IOH = – 800 µA
IOH = – 5.2 mA
2.7
3.5
2.5
3.3
Bus
Terminal
Bus
IOL = 16 mA
IOL = 48 mA
Terminal
Terminal and
control inputs
Voltage at bus port
Current into bus port
TYP†
Bus
0.5
0.5
VI = 5
5.5
5V
02
0.2
100
µA
VI = 2.7 V
VI = 0.5 V
0.1
20
µA
– 10
– 100
µA
3.0
3.7
II(bus) = 0
II(bus) = – 12 mA
Driver disabled
VCC = 0,
2.5
– 1.5
0
2.5
– 3.2
0
0.7
2.5
– 40
– 15
– 35
– 75
Bus
– 25
– 50
– 125
ICC
Supply current
No load,
CI/O(bus)
I/O(b )
Bus port capacitance
Bus-port
VCC = 5 V to 0,
VI/O = 0 to 2 V, f = 1 MHz
mA
2.5
Terminal
Short circuit output current
Short-circuit
V
– 3.2
VI(bus) = 0 V to 2.5 V
IOS
V
– 1.3
VI(b
2.5
5 V to 3
3.7
7V
I(bus)) = 2
VI(bus) = 3.7 V to 5 V
VI(bus) = 5 V to 5.5 V
Power off
V
0.3
Driver disabled
Power on
V
0.35
VI(bus) = – 1.5 V to 0.4 V
VI(bus) = 0.4 V to 2.5 V
II/O(bus)
(
)
MIN
TE, DE, and SC low
110
16
µA
mA
mA
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ VOH applies for 3-state outputs only.
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7
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time,
low- to high-level output
tPHL
Propagation delay time,
high- to low-level output
tPLH
Propagation delay time,
low- to high-level output
tPLH
Propagation delay time,
low- to high-level output
tPHL
TO
(OUTPUT)
TEST
CONDITIONS
Terminal
Bus
CL = 30 pF,
See Figure 1
Terminal
Bus
(SRQ, NDAC,
NRFD)
CL = 30 pF,
See Figure 1
Bus
Terminal
CL = 30 pF,
See Figure 2
Propagation delay time,
high- to low-level output
tPZH
tPHZ
Output enable time to high level
tPZL
tPLZ
Output enable time to low level
tPZH
tPHZ
Output enable time to high level
tPZL
tPLZ
Output enable time to low level
8
FROM
(INPUT)
Output disable time from high level
TE,DC,
or
SC
Output disable time from low level
Output disable time from high level
Bus (ATN,
(ATN
EOI,, REN,,
IFC, and
DAV)
MIN
TYP
MAX
14
20
14
20
29
35
10
20
15
22
UNIT
ns
ns
ns
60
See Figure 3
45
60
ns
55
55
TE,DC,
or
SC
Terminal
See Figure 4
Output disable time from low level
50
45
55
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ns
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
5V
200 Ω
From (Bus)
Output Under
Test
Test Point
CL = 30 pF
(see Note A)
480 Ω
LOAD CIRCUIT
3V
Terminal
Input
1.5 V
1.5 V
See Note B
tPHL
tPLH
0V
VOH
2.2 V
Bus
Output
1.0 V
VOH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
4.3 V
240 Ω
From (Terminal)
Output Under
Test
Test Point
CL = 30 pF
(see Note A)
3 kΩ
LOAD CIRCUIT
3V
Bus
Input
1.5 V
1.5 V
See Note B
0V
tPHL
tPLH
VOH
Terminal
Output
1.5 V
1.5 V
VOLTAGE WAVEFORMS
VOL
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
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9
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
S1
5V
200 Ω
From (Bus)
Output Under
Test
Test Point
CL = 15 pF
(see Note A)
480 Ω
LOAD CIRCUIT
3V
Control
Input
1.5 V
1.5 V
See Note B
0V
tPHZ
tPZH
Bus
Output
S1 Open
90%
VOH
2V
0V
tPZL
tPLZ
3.5 V
Bus
Output
S1 Closed
1V
0.5 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms
10
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SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
S1
4.3 V
240 Ω
From (Terminal)
Output Under
Test
Test Point
CL = 15 pF
(see Note A)
3 kΩ
LOAD CIRCUIT
3V
Control
Input
1.5 V
1.5 V
See Note B
tPZH
Output
Terminal
S1 Open
0V
tPHZ
90%
VOH
1.5 V
0V
tPLZ
tPZL
4V
Terminal
Output
S1 Closed
1V
0.7 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms
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SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
TERMINAL I/O PORTS
TERMINAL I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
3.5
VOL
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VOH
4
3
2.5
2
1.5
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0.5
0
0
0
–5
– 10
– 15
– 20
– 25
– 30
– 35
10
0
– 40
20
Figure 5
Figure 6
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
VCC = 5 V
No Load
TA = 25°C
VO
VO – Output Voltage – V
3.5
3
2.5
2
VIT–
VIT+
1.5
1
0.5
0
0
40
50
IOL – Low-Level Output Current – mA
IOH – High-Level Output Current – mA
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
VI – Bus Input Voltage – V
Figure 7
12
30
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2
60
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
GPIB I/O PORTS
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0
0.6
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 5 V
TA = 25°C
3
2
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
– 10
– 20
– 40
– 30
– 50
IOH – High-Level Output Current – mA
0
0
– 60
10
20 30 40 50 60 70 80 90 100
IOL – Low-Level Output Current – mA
Figure 8
4
Figure 9
GPIB I/O PORTS
GPIB I/O PORTS
OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
CURRENT
vs
VOLTAGE
VCC = 5 V
No Load
TA = 25°C
VCC = 5 V
TA = 25°C
2
0
I I/O – Current – mA
V
VO
O – Output Voltage – V
1
3
2
–1
–2
–3
–4
1
–5
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
–6
0
0.9
–7
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
–2
–1
0
1
2
3
4
5
6
VI/O – Voltage – V
VI – Input Voltage – V
Figure 11
Figure 10
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