SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
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DW OR N PACKAGE
(TOP VIEW)
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
High-Speed Low-Power Schottky Circuitry
Low Power Dissipation . . . 66 mW Max Per
Channel
High-impedance PNP Inputs
Receiver Hysteresis . . . 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (VCC = 0)
TE
B1
B2
B3
B4
B5
B6
B7
B8
GND
GPIB
I/O Ports
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
D1
D2
D3
D4
D5
D6
D7
D8
PE
Terminal
I/O Ports
description
The SN75163B octal general-purpose interface
NOT RECOMMENDED FOR NEW DESIGN
bus transceiver is a monolithic, high-speed, lowpower Schottky device. It is designed for two-way
data communications over single-ended transmission lines. The transceiver features driver outputs that can be
operated in either the open-collector or 3-state modes. If talk enable (TE) is high, these outputs have the
characteristics of open-collector outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.
Taking TE low places the outputs in the high-impedance state. The driver outputs are designed to handle loads
of up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and 400 mV
of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when VCC = 0.
The SN75163B is characterized for operation from 0°C to 70°C.
Function Tables
EACH DRIVER
INPUTS
EACH RECEIVER
D
TE
PE
OUTPUT
B
H
L
H
L
X
H
H
X
H
L
H
H
L
L
X
H
L
Z
L
Z
H = high level,
L = low level,
X = irrelevant,
INPUTS
B
TE
PE
OUTPUT
D
L
H
X
L
L
H
X
X
X
L
H
Z
Z = high-impedance state
Copyright 1993, Texas Instruments Incorporated
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2−1
SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
logic symbol†
logic diagram (positive logic)
PE
PE
M1 (3S)
TE 1
19
D1
M2 (0C)
TE
11
11
1
EN3 (XMT)
EN4 (RCV)
D1
D2
19
2
3(1 /2
4
D2
D3
D4
D5
D6
D7
D8
)
18
3
17
4
16
5
15
6
14
7
13
8
12
9
B3
B4
D4
B5
B7
3
B2
4
B3
D3 17
B2
B6
B1
18
B1
1
2
16
5 B4
Terminal
I/O Ports
D5
B8
{ This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates open-collector outputs
GPIB
I/O
Ports
15
6
B5
7
B6
D6 14
D7 13
8
D8
B7
12
9
B8
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
VCC
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
Req
9 kΩ
NOM
VCC
10 kΩ
NOM
Input
4 kΩ
NOM
GND
GND
Input/Output Port
Driver output Req = 30 Ω NOM
Receiver output Req = 110 Ω NOM
2−2
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SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW
1125 mW
9.0 mW/°C
720 mW
N
1150 mW
9.2 mW/°C
736 mW
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
Bus ports with pullups active
High-level output current, IOH
High-level output current, IOL
Terminal ports
V
0.8
V
−10
mA
−800
µA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
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70
mA
°C
2−3
SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Vhys
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
High-level output current
(open-collector mode)
IOZ
II
Hysteresis (VT + − VT −)
TEST CONDITIONS
MIN
II = − 18 mA
See Figure 8
Bus
TYP†
MAX
UNIT
−0.8
−1.5
V
0.4
0.65
V
IOH = − 800 µA,
IOH = − 10 mA,
TE at 0.8 V
2.7
3.5
PE and TE at 2 V
2.5
3.3
IOL = 16 mA,
IOL = 48 mA,
TE at 0.8 V
0.3
0.5
PE and TE at 2 V
0.4
0.5
Bus
VO = 5.5 V,
D and TE at 2 V
PE at 0.8 V,
Off-state output current
(3-state mode)
Bus
PE at 2 V,
TE at 0.8 V
VO = 2.7 V
VO = 0.4 V
Input current at maximum
input voltage
Terminal
VI = 5.5 V
0.2
IIH
IIL
High-level input current
Terminal
Low-level input current
Terminal
VI = 2.7 V
VI = 0.5 V
IOS
Short-circuit output current
IIL
Supply current
Terminal
Bus
Terminal
Bus
V
100
20
−20
0.1
20
µA
−10
−100
µA
−15
−35
−75
−25
−50
−125
Receivers low and enabled
VI/O = 0 to 2 V,
mA
80
Drivers low and enabled
VCC = 5 V to 0,
A
µA
µA
Bus
CI/O(bus) Bus-port capacitance
† All typical values are at VCC = 5, TA = 25°C.
µA
A
100
Terminal
No load
V
100
f = 1 MHz
30
mA
pF
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
Terminal
Bus
Bus
Terminal
MIN
TYP
MAX
CL = 30 pF,
See Figure 1
14
20
14
20
CL = 30 pF,
See Figure 2
10
20
15
22
tPLH
tPHL
Propagation delay time, low-to-high-level output
tPLH
tPHL
Propagation delay time, low-to-high-level output
tPZH
tPHZ
Output enable time to high level
25
35
Output disable time from high level
13
22
tPZL
tPLZ
Output enable time to low level
22
35
Output disable time from low level
22
32
tPZH
tPHZ
Output enable time to high level
20
30
Output disable time from high level
12
20
tPZL
tPLZ
Output enable time to low level
23
32
Output disable time from low level
19
30
ten
tdis
Output pullup enable time
15
22
13
20
2−4
Propagation delay time, high-to-low-level output
Propagation delay time, high-to-low-level output
Output pullup disable time
TE
Bus
TE
Terminal
PE
Terminal
•
See Figure 3
See Figure 4
See Figure 5
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•
UNIT
ns
ns
ns
ns
ns
SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
PE
3V
3V
200 Ω
Output
Generator
(see Note A)
D Input
B
D
1.5 V
tPLH
B Output
480 Ω
50 Ω
1.5 V
0V
tPHL
VOH
2.2 V
1.0 V
CL = 30 pF
(see Note B)
TE
3V
TEST CIRCUIT
VOH
VOLTAGE WAVEFORMS
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
TE
3V
4.3 V
Output
240 Ω
Generator
(see Note A)
B
1.5 V
1.5 V
0V
tPLH
D
tPHL
VOH
D Output
3 kΩ
CL = 30 pF
(see Note B)
50 Ω
B Input
1.5 V
1.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
5V
3V
200 Ω
PE
3V
TE Input
Output
S1 D
B
S2
B Output
S1 to 3 V
S2 Open
480 Ω
1.5 V
B Output
S1 to GND
S2 Closed
TE
0V
tPZH tPHZ
90%
VOH
2V
0.8 V
tPZL
CL = 15 pF
(see Note B)
Generator
(see Note A)
1.5 V
tPLZ
1.0 V
3.5 V
0.5 V
VOL
50 Ω
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
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2−5
SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4.3 V
TE
Generator
(see Note A)
3V
S2
3 kΩ
S1
B
1.5 V
90%
VOH
1.5 V
0V
tPLZ
D Output
S1 to GND
S2 Closed
CL = 15 pF
(see Note B)
0V
tPHZ
D Output
S1 to 3 V
S2 Open
tPZL
D
3V
TE Input
tPZH
Output
240 Ω
50 Ω
1.5 V
4V
1.0 V
0.7 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms
Generator
(see Note A)
PE
3V
PE Input
1.5 V
D
B
50 Ω
Output
ten
1.5 V
0V
tdis
RL = 480 Ω
90%
B Output
VOH
2V
VOL = 0.8 V
CL = 15 pF
(see Note B)
3V
TE
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. PE-to-Bus Pullup Test Circuit and Voltage Waveforms
NOTES: C. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
D. CL includes probe and jig capacitance.
2−6
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SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
3.5
VOL
VOL − Low-Level Output Voltage − V
VCC = 5 V
TA = 25°C
3
2.5
2
1.5
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0.5
0
0
0
−5 −10 −15 −20 −25 −30 −35
IOH − High-Level Output Current − mA
0
−40
10
20
30
40
50
IOL − Low-Level Output Current − mA
Figure 6
60
Figure 7
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
VCC = 5 V
No Load
TA = 25°C
3.5
VO
VO − Output Voltage − V
V
VOH
OH − High-Level Output Voltage − V
4
3
2.5
2
VT−
VT+
1.5
1
0.5
0
0
0.2
0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
VI − Input Voltage − V
2
Figure 8
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SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
VOL − Low-Level Output Voltage − V
VOL
V
VOH
OH − High-Level Output Voltage − V
0
3
2
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
0
−10
−20
−30
−40
−50
0
−60
10
20
30
Figure 9
4
V
VO
O − Output Voltage − V
50
60
Figure 10
BUS OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
VCC = 5 V
No Load
TA = 25°C
3
2
1
0
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
VI − Input Voltage − V
Figure 11
2−8
40
70
80
90 100
IOL − Low-Level Output Current − mA
IOH − High-Level Output Current − mA
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1.7
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