TI TPS75801KTTT

TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT VOLTAGE REGULATORS
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
3-A Low-Dropout Voltage Regulator
Available in 1.5-V, 1.8-V, 2.5-V, and 3.3-V
Fixed-Output and Adjustable Versions
Dropout Voltage Typically 150 mV at 3 A
(TPS75833)
Low 125 µA Typical Quiescent Current
Fast Transient Response
3% Tolerance Over Specified Conditions for
Fixed-Output Versions
Available in 5-Pin TO-220 and TO-263
Surface-Mount Packages
Thermal Shutdown Protection
The TPS758xx family of 3-A low dropout (LDO)
regulators contains four fixed voltage option regulators and an adjustable voltage option regulator.
These devices are capable of supplying 3 A of output
current with a dropout of 150 mV (TPS75833).
Therefore, the device is capable of performing a
3.3-V to 2.5-V conversion.
Quiescent current is 125 µA at full load and drops
down to less than 1 µA when the device is disabled.
The TPS758xx is designed to have fast transient
response for large load current changes.
TO–263 (KTT) PACKAGE
(TOP VIEW)
TO–220 (KC) PACKAGE
(TOP VIEW)
EN
IN
GND
OUTPUT
FB/NC
1
2
3
4
5
1
2
3
4
5
EN
IN
GND
OUTPUT
FB/NC
TPS75833
IO = 3 A
VO = 3.3 V
200
150
100
50
0
–40 –25 –10 5
20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
LOAD TRANSIENT RESPONSE
150
VO = 1.5 V
Co = 100 µF
100
50
0
–50
di
0.75 A
s
dt
–100
3
–150
0
20
0
40 60 80 100 120 140 160 180 200
t – Time – µs
IO – Output Current – A
VDO– Dropout Voltage – mV
250
TPS75815
∆VO– Change in Output Voltage – mV
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2004, Texas Instruments Incorporated
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 150 mV at
an output current of 3 A for the TPS75833) and is directly proportional to the output current. Additionally, since
the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output
loading (typically 125 µA over the full range of output current). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when EN (enable) is connected to a high voltage level (>2 V). Applying a low voltage level
(<0.7 V) to EN shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = 25°C.
The TPS758xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over
line, load, and temperature ranges. The TPS758xx family is available in a 5-pin TO-220 (KC) and TO-263 (KTT)
packages.
AVAILABLE OPTIONS
TJ
40°C to 125°C
(1)
OUTPUT VOLTAGE (TYP)
TO-220 (KC)
TO-263(KTT) (1)
3.3 V
TPS75833KC
TPS75833KTT
2.5 V
TPS75825KC
TPS75825KTT
1.8 V
TPS75818KC
TPS75818KTT
1.5 V
TPS75815KC
TPS75815KTT
Adjustable 1.22 V to 5 V
TPS75801KC
TPS75801KTT
The TPS75801 is programmable using an external resistor divider (see application information). The
KTT package is available taped and reeled. Add T for KTT devices in 50-piece reel. Add R for KTT
devices in 500-piece reel.
VI
2
IN
NC
OUT
1 µF
5
4
VO
1
EN
+
GND
Co(1)
47 µF
3
(1) See application information section for capacitor selection details.
Figure 1. Typical Application Configuration (For Fixed Output Options)
2
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
VOUT
VIN
Current
Sense
UVLO
SHUTDOWN
ILIM
_
GND
R1
+
FB
EN
UVLO
R2
Thermal
Shutdown
External to
the Device
Bandgap
Reference
VIN
Vref = 1.22 V
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
VOUT
VIN
UVLO
Current
Sense
SHUTDOWN
ILIM
_
R1
+
GND
UVLO
EN
R2
Thermal
Shutdown
Vref = 1.22 V
Bandgap
Reference
VIN
TERMINAL FUNCTIONS (TPS758xx)
TERMINAL
I/O
DESCRIPTION
1
I
Enable input
5
I
Feedback input voltage for adjustable device/no connection for fixed options
NAME
NO.
EN
FB/NC
GND
3
IN
2
I
Input voltage
OUTPUT
4
O
Regulated output voltage
Regulator ground
3
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
DETAILED DESCRIPTION
The TPS758xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an
adjustable regulator, the TPS75801 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.
Pin Functions
Enable (EN)
The EN terminal is an input which enables or shuts down the device. If EN is a low voltage level (<0.7 V), the
device will be in shutdown or sleep mode. When EN goes to a high voltage level (>2 V), the device will be
enabled.
Feedback (FB)
FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either
directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor
divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in
such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is
not recommended because it may cause the regulator to oscillate.
Input Voltage (IN)
The VIN terminal is an input to the regulator.
Output Voltage (OUTPUT)
The VOUTPUT terminal is an output from the regulator.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted) (1) (2)
UNIT
Input voltage range, VI
-0.3 V to 6 V
Voltage range at EN
-0.3 V to 6 V
Peak output current
Internally limited
Continuous total power dissipation
See Dissipation Rating Table
Output voltage, VO (OUTPUT, FB)
5.5 V
Operating junction temperature range, TJ
-40°C to 150°C
Storage temperature range, Tstg
-65°C to 150°C
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE
(1)
(2)
(3)
4
PACKAGE
RΘJC(°C/W)
RΘJA(°C/W) (1)
TO-220
2
58.7 (2)
TO-263
2
38.7 (3)
For both packages, the RΘJAvalues were computed using JEDEC high K board (2S2P) with 1 ounce internal copper plane and ground
plane. There was no air flow across the packages.
RΘJA was computed assuming a vertical, free standing TO-220 package with pins soldered to the board. There is no heatsink attached
to the package.
RΘJA was computed assuming a horizontally mounted TO-263 package with pins soldered to the board. There is no copper pad
underneath the package.
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI (1)
Output voltage range, VO
UNIT
5.5
V
1.22
5
V
Output current, IO
Operating virtual junction temperature, TJ
(1)
MAX
2.8
0
3
A
-40
125
°C
To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min)= VO(max)+ VDO(max
load).
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (TJ = -40°C to 125°C), VI= VO(typ) + 1 V, IO = 1 mA, EN = VI, Co =
100 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Adjustable
voltage
1.5 V Output
Output voltage (1)
1.8 V Output
2.5 V Output
3.3 V Output
Quiescent current (GND current) (2), (3)
Output voltage line regulation (∆VO/VO) (3)
Load regulation
1.22 V ≤ VO≤ 5.5 V
MIN
1.22 V ≤ VO≤ 5.5 V
TJ = 25°C
TJ = 25°C
2.8 V < VI < 5.5 V
1.8
3.5 V < VI < 5.5 V
2.425
4.3 V < VI < 5.5 V
4.3 V ≤ VI≤ 5.5 V
3.3
3.201
TJ = 25°C
200
VO + 1 V ≤ VI≤ 5.5 V,
TJ = 25°C
0.04
VO + 1 V ≤ VI < 5.5 V
0.1
BW = 300 Hz to 50 kHz, TJ = 25°C, VI = 2.8 V
VO = 0 V
EN = 0,
Standby current
5.5
TJ = 25°C
10
TPS75801
FB = 1.5 V
f = 100 Hz, TJ = 25°C
-1
EN = 0 V
-1
High level EN input voltage
Low level EN input voltage
V
V
V
V
µA
%/V
µVrms
14
A
°C
0.1
µA
3
µA
1
µA
1
µA
1
µA
62
EN = VI
V
150
-1
VI = 2.8 V, IO = 3 A
V
%/V
35
EN = 0
Power supply ripple rejection TPS75815
(1)
(2)
(3)
3.399
125
Thermal shutdown junction temperature
Input current (EN)
2.575
0.35
TPS75815
Output current limit
FB input current
1.854
2.5
(2)
Output noise voltage
1.545
1.746
3.5 V ≤ VI≤ 5 V
TJ = 25°C
1.03 VO
1.5
1.455
2.8 V ≤ VI≤ 5.5 V
UNIT
1.03 VO
0.97 VO
2.8 V < VI < 5.5 V
2.8 V ≤ VI≤ 5.5 V
MAX
VO
0.97 VO
1.22 V ≤ VO≤ 5.5 V, TJ = 0 to 125°C (1)
TJ = 25°C
TYP
TJ = 25°C
0
dB
2
V
0.7
V
The adjustable option operates with a 2% tolerance over TJ = 0 to 125°C.
IO = 1 mA to 3 A
If VO < 2.5 V then VImin = 2.8 V, VImax = 5.5 V:
VOVImax 2.8V
Line regulator (mV) (%V) 1000
100
If VO≥ 2.5 V then VImin = VO + 1 V, VImax = 5.5 V:
VOVImax VO 1V
Line regulator (mV) (%V) 1000
100
5
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range (TJ = -40°C to 125°C), VI= VO(typ) + 1 V, IO = 1 mA, EN = VI, Co =
100 µF (unless otherwise noted)
PARAMETER
VO
VI
(4)
TEST CONDITIONS
MIN
TYP
IO = 3 A,
VI = 3.2 V
IO = 3 A,
VI = 3.2 V
Discharge transistor
current
VO = 1.5 V
TJ = 25°C
10
UVLO
TJ = 25°C
VI rising
2.2
UVLO hysteresis
TJ = 25°C
VI falling
Dropout voltage,
(3.3 V output) (4)
TJ = 25°C
MAX
UNIT
150
300
25
mA
2.75
100
IN voltage equals VO(typ) - 100 mV; TPS75815, TPS75818, and TPS75825 dropout voltage limited by input voltage range limitations
(i.e., TPS75833 input voltage is set to 3.2 V for the purpose of this test).
Table of Graphs
FIGURE
vs Output current
2, 3
vs Junction temperature
4, 5
Ground current
vs Junction temperature
6
Power supply ripple rejection
vs Frequency
7
Output spectral noise density
vs Frequency
8
zo
Output impedance
vs Frequency
9
VDO
Dropout voltage
vs Input voltage
10
vs Junction temperature
11
VI
Minimum required input voltage
vs Output voltage
12
Output voltage
Line transient response
13, 15
Load transient response
VO
6
V
mV
TYPICAL CHARACTERISTICS
VO
mV
14, 16
Output voltage and enable voltage
vs Time (start-up)
17
Equivalent series resistance
vs Output current
19, 20
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
TPS75833
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS75815
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.345
1.545
VI = 2.8 V
TJ = 25°C
VI = 4.3 V
TJ = 25°C
1.530
VO − Output Voltage − V
VO − Output Voltage − V
3.330
3.315
3.3
3.285
1.515
1.5
1.485
1.470
3.270
3.255
0
2
1
1.455
3
0
1
IO − Output Current − A
Figure 2.
Figure 3.
TPS75833
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
TPS75815
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.345
3
1.545
VI = 4.3 V
VI = 2.8 V
3.33
1.530
VO − Output Voltage − V
VO − Output Voltage − V
2
IO − Output Current − A
3.315
3.3
3.285
1.5
1.485
1.470
3.270
3.255
−40 −25
1.515
10
5
20
35
50
65 80
95 110 125
TJ − Junction Temperature − °C
Figure 4.
1.455
−40 −25 −10
5
20
35
50 65
80
95 110 125
TJ − Junction Temperature − °C
Figure 5.
7
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
TPS758xx
GROUND CURRENT
vs
JUNCTION TEMPERATURE
TPS75833
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
150
90
PSRR − Power Supply Ripple Rejection − dB
Ground Current − µ A
VI = 5 V
IO = 3 A
125
100
75
−40 −25 −10
5
20
35 50
65
80
95 110 125
IO = 1 mA
60
50
40
30
20
IO = 3 A
10
0
10
100
1k
10k
100k
f − Frequency − Hz
Figure 6.
Figure 7.
TPS75833
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
TPS75833
OUTPUT IMPEDANCE
vs
FREQUENCY
1M
10M
1M
10M
100
VI = 4.3 V
VO = 3.3 V
Co = 100 µF
TJ = 25°C
2
10
z o − Output Impedance − Ω
Hz
Output Spectral Noise Density − µ V/
70
TJ − Junction Temperature − °C
2.5
1.5
IO = 3 A
IO = 1 mA
1
VI = 4.3 V
Co = 100 µF
IO = 1 mA
TJ = 25°C
IO = 1 mA
1
0.1
0.01
IO = 3 A
0.001
0.5
0.0001
0
10
100
1k
f − Frequency − Hz
Figure 8.
8
VI = 4.3 V
Co = 100 µF
TJ = 25°C
80
10k
100k
0.00001
10
100
1k
10k
100k
f − Frequency − Hz
Figure 9.
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
TPS75801
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
TPS75833
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
250
250
IO = 3 A
VO= 3.3 V
IO = 3 A
VDO − Dropout Voltage − mV
TJ = 25°C
150
TJ = −40°C
100
200
150
100
50
50
0
2.5
3
3.5
4
VI − Input Voltage − V
4.5
Figure 11.
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
TPS75815
LINE TRANSIENT RESPONSE
∆ VO − Change in Output Voltage − mV
Figure 10.
4
IO = 3 A
VI− Minimum Required Input Voltage − V
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
5
TJ = 125°C
TJ = 25°C
TJ = −40°C
3
VO = 1.5 V
IO = 3 A
Co = 100 µF
50
0
−50
−100
2.8
3.8
2.8
2
1.5
1.75
2
3
2.25 2.5 2.75
VO − Output Voltage − V
Figure 12.
3.25
3.5
0
50
VI − Input Voltage − V
VDO − Dropout Voltage − mV
TJ = 125°C
200
100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 13.
9
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
150
VO = 1.5 V
Co = 100 µF
50
0
−50
di 0.75 A
s
dt
3
0
20
40
60
80 100 120 140 160 180 200
t − Time − µs
50
100 150 200 250 300 350 400 450 500
t − Time − µs
TPS75833
LOAD TRANSIENT RESPONSE
TPS75833
OUTPUT VOLTAGE AND ENABLE VOLTAGE
TIME (START-UP)
di 0.75 A
s
dt
−100
4
2
0
40
60
80 100 120 140 160 180 200
t − Time − µs
Figure 16.
10
4.3
Figure 15.
0
20
5.3
Figure 14.
100
0
−50
0
VO = 3.3 V
Co = 100 µF
200
0
VO − Output Voltage − V
∆ VO − Change in Output Voltage − mV
0
50
VI = 4.3 V
IO = 10 mA
TJ = 25°C
3.3
0
4.3
0
0
0.2
0.4
0.6
t − Time (Start-Up) − ms
Figure 17.
0.8
1
VI − Input Voltage − V
−150
VO = 3.3 V
IO = 3 A
Co = 100 µF
−100
I O − Output Current − A
−100
100
Enable Voltage − V
100
∆ VO − Change in Output Voltage − mV
TPS75833
LINE TRANSIENT RESPONSE
I O − Output Current − A
∆ VO − Change in Output Voltage − mV
TPS75815
LOAD TRANSIENT RESPONSE
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
To Load
IN
VI
OUT
+
EN
RL
Co
GND
ESR
Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options)
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(A)
vs
OUTPUT CURRENT
10
Co = 680 µF
TJ = 25°C
ESR − Equivalent Series Resistance − Ω
ESR − Equivalent Series Resistance − Ω
10
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(A)
vs
OUTPUT CURRENT
1
Region of Stability
0.1
Co = 47 µF
TJ = 25°C
1
Region of Stability
0.2
Region of Instability
0.015
Region of Instability
0.01
0.01
0
1
2
3
0
1
2
IO − Output Current − A
IO − Output Current − A
Figure 19.
Figure 20.
3
A. Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any
series resistance added externally, and PWB trace resistance to CO.
11
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)
above which normal operation is not assured. A system designer must design the operating environment so that
the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two
main environmental variables that a designer can use to improve thermal performance are air flow and external
heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment
for a linear regulator that is operating at a specific power level.
In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
P max V
V
I
V
xI
D
I(avg)
O(avg)
O(avg)
I(avg) (Q)
(1)
Where:
•
•
•
•
VI(avg) is the average input voltage.
VO(avg) is the average output voltage.
IO(avg) is the average output current.
I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the
ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case (RΘJC), the case to heatsink (RΘCS), and the heatsink to ambient
(RΘSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object's thermal resistance.
Figure 21 illustrates these thermal resistances for (a) a TO-220 package attached to a heatsink, and (b) a
TO-263 package mounted on a JEDEC High-K board.
C
B
A
TJ
RθJC
A
B
A
B
TC
RθCS
C
RθSA
TA
TO–220 Package
(a)
Figure 21. Thermal Resistances
12
TO–263 Package
(b)
C
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
Equation 2 summarizes the computation:
T
J
T PDmax x R
R
R
A
θJC
θCS
θSA
(2)
The RΘJC is specific to each regulator as determined by its package, lead frame, and die size provided in the
regulator's data sheet. The RΘSA is a function of the type and size of heatsink. For example, black body radiator
type heatsinks, like the one attached to the TO-220 package in Figure 21(a), can have RΘCS values ranging from
5 °C/W for very large heatsinks to 50 °C/W for very small heatsinks. The RΘCS is a function of how the package is
attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a TO-220 package,
RΘCSof 1°C/W is reasonable.
Even if no external black body radiator type heatsink is attached to the package, the board on which the
regulator is mounted will provide some heatsinking through the pin solder connections. Some packages, like the
TO-263 and TI's TSSOP PowerPAD™ packages, use a copper plane underneath the package or the circuit
board's ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal
modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in
different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks,
different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal
resistance between junction and ambient (RΘJA). This RΘJA is valid only for the specific operating environment
used in the computer model.
Equation 2 simplifies into Equation 3:
T T PDmax x R
J
A
θJA
Rearranging Equation 3 gives Equation 4:
T –T
R
J A
θJA
P max
D
(3)
(4)
Using Equation 3 and the computer model generated curves shown in Figure 22 and Figure 25, a designer can
quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power
dissipation, and operating environment.
TO-220 Power Dissipation
The TO-220 package provides an effective means of managing power dissipation in through-hole applications.
The TO-220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A
heatsink can be used with the TO-220 package to effectively lower the junction-to-ambient thermal resistance.
To illustrate, the TPS75825 in a TO-220 package was chosen. For this example, the average input voltage is 3.3
V, the average output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air
flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent
current, the maximum average power is:
P Dmax (3.3 – 2.5) V x 3 A 2.4 W
(5)
Substituting TJmax for TJ into Equation 4 gives Equation 6:
R
max (125 – 55)°C2.4 W 29°CW
θJA
(6)
From Figure 22, RΘJA vs Heatsink Thermal Resistance, a heatsink with RΘSA = 22°C/W is required to dissipate
2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a
standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package
pins were soldered to the board, 450 mm2 of the board was modeled as a heatsink. Figure 23 shows the side
view of the operating environment used in the computer model.
13
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
65
Rθ JA − Thermal Resistance −
° C/W
Natural Convection
55
Air Flow = 150 LFM
45
Air Flow = 250 LFM
Air Flow = 500 LFM
35
25
15
No Heatsink
5
25
20
15
10
5
RθSA − Heatsink Thermal Resistance − °C/W
0
Figure 22. Thermal Resistance vs Heatsink Thermal Resistance
0.21 mm
0.21 mm
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
Figure 23.
From the data in Figure 22 and rearranging Equation 4, the maximum power dissipation for a different heatsink
RΘSA and a specific ambient temperature can be computed (see Figure 24).
14
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
10
PD − Power Dissipation Limit − W
TA = 55°C
Air Flow = 500 LFM
Air Flow = 250 LFM
Air Flow = 150 LFM
Natural Convection
No Heatsink
1
20
10
RθSA − Heatsink Thermal Resistance − °C/W
0
Figure 24. Power Dissipation vs Heatsink Thermal Resistance
TO-263 Power Dissipation
The TO-263 package provides an effective means of managing power dissipation in surface-mount applications.
The TO-263 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the TO-263 package enhances the thermal performance of the
package.
To illustrate, the TPS75825 in a TO-263 package was chosen. For this example, the average input voltage is 3.3
V, the average output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air
flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent
current, the maximum average power is:
P Dmax (3.3 – 2.5) V x 3 A 2.4 W
(7)
Substituting TJmax for TJ into Equation 4 gives Equation 8:
R
max (125 – 55)°C2.4 W 29°CW
θJA
(8)
2
From Figure 25, RΘJA vs Copper Heatsink Area, the ground plane needs to be 2 cm for the part to dissipate 2.4
W. The model operating environment used in the computer model to construct Figure 25 consisted of a standard
JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a
2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows the side view
of the operating environment used in the computer model.
15
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
40
Rθ JA − Thermal Resistance −
° C/W
No Air Flow
35
150 LFM
30
250 LFM
25
20
15
0
0.01
0.1
1
10
Copper Heatsink Area − cm2
100
Figure 25. Thermal Resistance vs Copper Heatsink Area
2 oz. Copper Solder Pad
With 25 Thermal Vias
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
Thermal Vias, 0.3 mm
Diameter, 1.5 mm Pitch
Figure 26.
From the data in Figure 25 and rearranging Equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed (see Figure 27).
16
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
5
PD − Maximum Power Dissipation − W
TA = 55°C
250 LFM
4
150 LFM
3
No Air Flow
2
1
0
0.01
0.1
1
10
Copper Heatsink Area − cm2
100
Figure 27. Maximum Power Dissipation vs Copper Heatsink Area
17
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
APPLICATION INFORMATION
Programming the TPS75801 Adjustable LDO Regulator
The output voltage of the TPS75801 adjustable regulator is programmed using an external resistor divider as
shown in Figure 28. The output voltage is calculated using:
V
O
V
ref
1 R1
R2
Where:
Vref = 1.224 V typ (the internal reference voltage)
(9)
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ
to set the divider current at 40 µA and then calculate R1 using:
R1 V
V
O 1
ref
R2
(10)
TPS75801
VI
IN
1 µF
OUTPUT
VOLTAGE
EN
≤ 0.7 V
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUT
≥2V
VO
R1
FB
GND
Co
R1
R2
UNIT
2.5 V
31.6
30.1
kΩ
3.3 V
51
30.1
kΩ
3.6 V
58.3
30.1
kΩ
R2
Figure 28. TPS75801 Adjustable LDO Regulator Programming
Regulator Protection
The TPS758xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS758xx also features internal current limiting and thermal protection. During normal operation, the
TPS758xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the
device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C
(typ), regulator operation resumes.
Input Capacitor
For a typical application, a ceramic input bypass capacitor (0.22 µF - 1 µF) is recommended to ensure device
stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply,
large transient currents will cause the input voltage to droop. If this droop causes the input voltage to drop below
the UVLO threshold, the device will turn off. Therefore, it is recommended that a larger capacitor be placed in
parallel with the ceramic bypass capacitor at the regulator's input. The size of this capacitor depends on the
output current, response time of the main power supply, and the main power supply's distance to the regulator.
At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum
UVLO threshold voltage during normal operating conditions.
18
TPS75801, TPS75815
TPS75818, TPS75825
TPS75833
www.ti.com
SLVS330D – JUNE 2001 – REVISED MARCH 2004
APPLICATION INFORMATION (continued)
Output Capacitor
As with most LDO regulators, the TPS758xx requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance value is 47 µF with an ESR
(equivalent series resistance) of at least 200 mΩ. As shown in Figure 29, most capacitor and ESR combinations
with a product of 47e-6 x 0.2 = 9.4e-6 or larger will be stable, provided the capacitor value is at least 47 µF. Solid
tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided they meet the requirements
described in this section. Larger capacitors provide a wider range of stability and better load transient response.
This information along with the ESR graphs, Figure 19, Figure 20, and Figure 29, is included to assist in
selection of suitable capacitance for the user's application. When necessary to achieve low height requirements
along with high output current and/or high load capacitance, several higher ESR capacitors can be used in
parallel to meet these guidelines.
1000
Output Capacitance − µ F
Region of Stability
ESR min x Co = Constant
100
47
Region xofCInstability
Y = ESRmin
o
10
0.01
0.1
ESR − Equivalent Series Resistance − Ω
0.2
Figure 29. Output Capacitance vs Equivalent Series Resistance
19
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS75801KC
ACTIVE
TO-220
KC
5
TPS75801KTT
OBSOLETE
DDPAK/
TO-263
KTT
5
TPS75801KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
TPS75801KTTT
ACTIVE
DDPAK/
TO-263
KTT
TPS75815KC
ACTIVE
TO-220
TPS75815KTT
OBSOLETE
TPS75815KTTR
50
Lead/Ball Finish
MSL Peak Temp (3)
None
CU SN
Level-NA-NA-NA
None
Call TI
Call TI
500
None
CU SN
Level-2-220C-1 YEAR
5
50
None
CU SN
Level-2-220C-1 YEAR
KC
5
1000
None
CU SN
Level-NA-NA-NA
DDPAK/
TO-263
KTT
5
None
Call TI
Call TI
ACTIVE
DDPAK/
TO-263
KTT
5
500
None
CU SN
Level-2-220C-1 YEAR
TPS75815KTTT
ACTIVE
DDPAK/
TO-263
KTT
5
50
None
CU SN
Level-2-220C-1 YEAR
TPS75818KC
ACTIVE
TO-220
KC
5
1000
None
CU SN
Level-NA-NA-NA
TPS75818KTT
OBSOLETE
DDPAK/
TO-263
KTT
5
None
Call TI
Call TI
TPS75818KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
500
None
CU SN
Level-2-220C-1 YEAR
TPS75818KTTT
ACTIVE
DDPAK/
TO-263
KTT
5
50
None
CU SN
Level-2-220C-1 YEAR
TPS75825KC
ACTIVE
TO-220
KC
5
1000
None
CU SN
Level-NA-NA-NA
TPS75825KTT
OBSOLETE
DDPAK/
TO-263
KTT
5
None
Call TI
Call TI
TPS75825KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
500
None
CU SN
Level-2-220C-1 YEAR
TPS75825KTTT
ACTIVE
DDPAK/
TO-263
KTT
5
50
None
CU SN
Level-2-220C-1 YEAR
TPS75833KC
ACTIVE
TO-220
KC
5
50
None
CU SN
Level-NA-NA-NA
TPS75833KTT
OBSOLETE
DDPAK/
TO-263
KTT
5
None
Call TI
Call TI
TPS75833KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
500
None
CU SN
Level-2-220C-1 YEAR
TPS75833KTTT
ACTIVE
DDPAK/
TO-263
KTT
5
50
None
CU SN
Level-2-220C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSOT008B – JANUARY 1995 – REVISED SEPTEMBER 2000
KC (R-PSFM-T5)
PLASTIC FLANGE-MOUNT
0.113 (2,87)
0.103 (2,62)
0.420 (10,67)
0.380 (9,65)
0.156 (3,96)
DIA
0.146 (3,71)
0.185 (4,70)
0.175 (4,46)
0.055 (1,40)
0.045 (1,14)
0.147 (3,73)
0.137 (3,48)
0.340 (8,64)
0.330 (8,38)
1.037 (26,34)
0.997 (25,32)
0.125 (3,18)
(see Note C)
1
0.040 (1,02)
0.030 (0,76)
0.010 (0,25) M
5
0.067 (1,70)
0.268 (6,81)
0.122 (3,10)
0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
4040208/E 09/00
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Lead dimensions are not controlled within this area.
All lead dimensions apply before solder dip.
The center lead is in electrical contact with the mounting tab.
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1
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