NB7HQ14M 2.5V 7GHz / 10Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer w/ Selectable http://onsemi.com Input Equalizer MARKING DIAGRAM* Multi−Level Inputs w/ Internal Termination 16 Description The NB7HQ14M is a high performance differential 1:4 CML fanout buffer with a selectable Equalizer receiver. When placed in series with a Clock /Data path operating up to 7 GHz or 10 Gb/s, respectively, the NB7HQ14M inputs will compensate the degraded signal transmitted across a FR4 PCB backplane or cable interconnect and output four identical CML copies of the input signal. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at start−up is LOW. As such, NB7HQ14M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7HQ14M to accept various logic level standards, such as LVPECL, CML or LVDS. The outputs have the flexibility of being powered by either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized for low output skew applications. The NB7HQ14M is a member of the GigaComm™ family of high performance clock products. 1 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7H Q14M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SIMPLIFIED BLOCK DIAGRAM EQ Features • • • • • • • • • • • • • Input Data Rate > 10 Gb/s Input Clock Frequency > 7 GHz 150 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times < 15 ps Maximum Output Skew < 0.8 ps Maximum RMS Clock Jitter < 10 ps pp of Data Dependent Jitter Differential CML Outputs, 400 mV Peak−to−Peak, Typical Selectable Input Equalization Operating Range: VCC = 2.375 V to 2.625 V, VCCO = 1.71 V to 2.625 V Internal Input Termination Resistors, 50 W −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 0 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Publication Order Number: NB7HQ14M/D NB7HQ14M CML Outputs Multi−Level Inputs LVPECL, LVDS, CML IN VCC0 Q0 Q0 50 W VT IN 0 50 W 2:1 MUX VREFAC VCC EQ 1 GND EQEN (Equalizer Enable) Q1 Q1 Q2 Q2 Q3 Q3 75 kW Figure 1. Detailed Block Diagram of NB7HQ14M http://onsemi.com 2 NB7HQ14M GND Q0 16 IN 1 VT 2 Q0 VCC Exposed Pad (EP) 14 13 15 EQEN 12 Q1 Function 0 IN / IN Inputs By−pass the Equalizer section 1 Inputs flow through the Equalizer 11 Q1 NB7HQ14M VREFAC 3 IN Table 1. EQUALIZER ENABLE FUNCTION 10 Q2 4 9 5 6 7 EQEN Q3 Q2 8 Q3 VCCO Figure 2. QFN−16 Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IN LVPECL, CML, LVDS Input 2 VT 3 VREFAC 4 IN LVPECL, CML, LVDS Input Inverted Differential Input. Note 1. 5 EQEN LVCMOS Input Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor) 6 Q3 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 7 Q3 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 8 VCCO − Non−inverted Differential Input. Note 1. Internal 100 W Center−tapped Termination Pin for IN / IN Output Voltage Reference for Capacitor−Coupled Inputs, only 1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs 9 Q2 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 10 Q2 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 11 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 12 Q1 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 13 VCC − 14 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 15 Q0 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 16 GND − Negative Supply Voltage − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 2.5 V Positive Supply Voltage for the core 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN / IN input, then, the device will be susceptible to self−oscillation. 2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 3 NB7HQ14M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model RPD − EQEN Input Pulldown Resistor > 2 kV > 200V 75 kW Moisture Sensitivity (Note 3) 16−QFN Flammability Rating Oxygen Index: 28 to 34 Transistor Count Level 1 UL 94 V−0 @ 0.125 in 290 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply − Core GND = 0 V 3.0 V VCCO Positive Power Supply − Outputs GND = 0 V 3.0 V VIO Positive Input/Output Voltage GND = 0 V −0.5 to VCC + 0.5 V VINPP Differential Input Voltage |IN − IN| 1.89 V IIN Input Current Through RT (50 W Resistor) $40 mA IOUT Output Current Through RT (50 W Resistor) $40 mA IVFREFAC VREFAC Sink/Source Current $1.5 mA TA Operating Temperature Range Tstg Storage Temperature Range θJA Thermal Resistance (Junction−to−Ambient) (Note 4) θJC Thermal Resistance (Junction−to−Case) (Note 4) Tsol Wave Solder 16 QFN 0 lfpm 500 lfpm Pb−Free −40 to +85 °C −65 to +150 °C 16 QFN 16 QFN 42 35 °C/W °C/W 16 QFN 4 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB7HQ14M Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 5) Characteristic Symbol Min Typ Max Unit 2.375 2.375 1.71 2.5 2.5 1.8 2.625 2.625 1.89 V 95 65 135 85 mA POWER SUPPLY / CURRENT VCC VCCO Power Supply Voltage VCC = 2.5 V VCCO = 2.5 V VCCO = 1.8 V ICC ICCO Power Supply Current for VCC (Inputs and Outputs Open) Power Supply Current for VCCO (Inputs and Outputs Open) CML OUTPUTS (Note 6) VOH Output HIGH Voltage VOL Output LOW Voltage VCCO = 2.5 V VCCO = 1.8 V VCCO – 30 2470 1770 VCCO – 10 2490 1790 VCCO 2500 1800 mV VCCO = 2.5 V VCCO = 1.8 V VCCO – 550 1950 1250 VCCO – 400 2100 1400 VCCO – 300 2200 1500 mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7) VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth −100 mV Vth Input Threshold Reference Voltage Range (Note 8) 1100 VCC − 100 mV VISE Single−ended Input Voltage Amplitude (VIH − VIL) 200 2800 mV VCC – 925 mV VREFAC VREFAC Output Reference Voltage @100 mA for capacitor− coupled inputs, only VCC – 1325 VCC – 1125 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 100 mV VID Differential Input Voltage (VIHD − VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration) (Note 10) (Figure 9) 1050 VCC − 50 mV IIH Input HIGH Current IN / IN, (VT Open) −150 150 uA IIL Input LOW Current IN / IN, (VT Open) −150 150 uA CONTROL INPUTS (EQEN) VIH Input HIGH Voltage for Control Pins VCC x 0.65 VCC V VIL Input LOW Voltage for Control Pins GND VCC x 0.35 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Output parameters vary 1:1 with VCCO. 6. CML outputs loaded with 50 W to VCCO for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the crosspoint side of the differential input signal. http://onsemi.com 5 NB7HQ14M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11) Symbol Characteristic fMAX Maximum Input Clock Frequency; fDATAMAX Maximum Operating Data Rate (PRBS23) VOUTPP Output Voltage Amplitude, EQEN = 0 or 1 (Note 15) (See Figure 10) tPLH, tPHL Propagation Delay tSKEW Duty Cycle Skew (Note 12) Output – Output Within Device Skew Device to Device Skew tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) FN Phase Noise, fin = 1 GHz tŐFN Integrated Phase Jitter fin = 1 GHz, 12 kHz − 20 MHz Offset (RMS) tJITTER RMS Random Clock Jitter (Note 13) Min Typ 7 10 GHz 10 12 Gbps fin ≤ 7GHz 200 400 mV IN to Q 120 170 225 ps 3 15 15 50 ps 50 60 % VOUT w 200 mV fin v 7GHz 40 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz fin v 7 GHz Peak−to−Peak Data Dependent Jitter (Note 14) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) tr tf Output Rise/Fall Times @ 1.0 GHz (20% − 80%) dBc 50 fs 0.2 100 15 Unit −135 −137 −149 −150 −150 −151 fin v 10 Gb/s EQEN = 0 (v 3” FR4) EQEN = 1 (12” FR4) Qx, Qx Max 30 0.8 ps rms 10 10 ps pk−pk ps pk−pk 1200 mV 45 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured by forcing VINPP 400mV from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCCO. Input edge rates 40 ps (20% − 80%). 12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swings are single−ended measurements operating in a differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 600 500 Q AMP (mV) 400 300 200 100 0 0 1 2 3 4 5 6 7 8 fin, CLOCK INPUT FREQUENCY (GHz) 9 10 Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 6 NB7HQ14M VCC IN 50 W VT 50 W IN Figure 4. Input Structure IN VIH IN Vth VIL IN IN Vth Figure 5. Differential Input Driven Single−Ended VCC Vthmax Figure 6. Differential Inputs Driven Differentially VIHmax VILmax Vth IN Vthmin GND VIH Vth VIL IN IN VCMRmax VILmin VIHD(MAX) Figure 8. Differential Inputs Driven Differentially INx VILD(MAX) VINPP = VIH(IN) − VIL(IN) INx VCMR VIHD VID = VIHD − VILD Q VILD VCMRmin GND VILD VIHmin Figure 7. Vth Diagram VCC VID = |VIHD(IN) − VILD(IN)| VIHD VOUTPP = VOH(Q) − VOL(Q) Q VIHD(MIN) tPHL tPLH VILD(MIN) Figure 9. VCMR Diagram Figure 10. AC Reference Measurement http://onsemi.com 7 NB7HQ14M VCC VCC VCC NB7HQ14M ZO = 50 W LVPECL Driver VCC ZO = 50 W IN 50 W VT = VCC − 2 V ZO = 50 W LVDS Driver 50 W 50 W 50 W IN GND/VEE GND GND GND Figure 11. LVPECL Interface Figure 12. LVDS Interface VCC CML Driver IN VT = Open ZO = 50 W IN VCC VCC VCC NB7HQ14M ZO = 50 W NB7HQ14M ZO = 50 W IN 50 W VT = VCC ZO = 50 W Differential Driver 50 W IN NB7HQ14M IN 50 W VT = VREFAC* ZO = 50 W 50 W IN GND GND GND GND Figure 14. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) Figure 13. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor VCC VCC ZO = 50 W Differential Driver NB7HQ14M IN 50 W VT = VREFAC* 50 W IN GND Figure 15. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) http://onsemi.com 8 GND NB7HQ14M NB7HQ14M Receiver VCCO VCCO = VCC (Receiver) 50 W 50 W VCC (Receiver) 50 W 50 W 16 mA GND Figure 16. Typical CML Output Structure and Termination VCC VT Driver FR4 − 12 Inch Backplane Q NB7HQ14M EQualizer EQEN = 1 IN IN Q DJ1 DJ2 DJ3 Figure 17. Typical NB7HQ14M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1 ORDERING INFORMATION Package Shipping† NB7HQ14MMNG QFN−16 (Pb−Free) 123 Units / Rail NB7HQ14MMNHTBG QFN−16 (Pb−Free) 100 / Tape & Reel NB7HQ14MMNTXG QFN−16 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB7HQ14M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D ÇÇÇ ÇÇÇ L1 DETAIL A PIN 1 LOCATION ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.15 C TOP VIEW 0.15 C ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DIM A A1 A3 b D D2 E E2 e K L L1 DETAIL B (A3) DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG L L A B ALTERNATE CONSTRUCTIONS A 16 X SEATING PLANE 0.08 C SIDE VIEW 16X L A1 5 8 4 e 0.575 0.022 EXPOSED PAD 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 K 12 1 16 16X e 1.50 0.059 3.25 0.128 13 b 0.10 C A B 0.05 C SOLDERING FOOTPRINT* D2 DETAIL A NOTE 5 16X C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 BOTTOM VIEW NOTE 3 0.50 0.02 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7L14M/D