TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 100−W STEREO DIGITAL AMPLIFIER POWER STAGE CONTROLLER D Power Amplifiers D Home Theater D Subwoofer Driver FEATURES D D D D Stereo H-Bridge Controller Efficiency > 95%† 2x100 W (RMS) at 6 Ω (BTL)† DESCRIPTION THD+N < 0.15% (Typical at 100 W at 6 Ω, 1 kHz)‡ D Half-Bridge Independent Control D Glueless Interface to TAS50XX Digital Audio PWM Processors D 3.3-V Digital Interface D Fault Detection - Overcurrent - Overtemperature - Undervoltage Protection for External MOSFETs D Low Profile 56-Terminal TSSOP SMD Package The TAS5182 device is a high-performance, stereo digital amplifier power stage controller. It is designed to drive two discrete bridge-tied-load (BTL) MOSFET output stages at up to 100 W per channel at 6 Ω. The TAS5182 device, incorporating Texas Instrument’s PurePatht technology, is used in conjunction with a digital audio PWM processor (TAS50XX) and two discrete MOSFET H-bridges (4 MOSFETs per H-Bridge) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 95%, reducing the size of both the power supplies and heat sinks needed. The TAS5182 device accepts a stereo PWM 3.3-V input, and it controls the switching of the discrete H-bridges. Overcurrent, overtemperature, and undervoltage protections are built into the TAS5182 device, safeguarding the H-bridge and speakers against output short-circuit conditions, overtemperature conditions, and other fault conditions that could damage the system. APPLICATIONS D AV Receivers D High Power DVD Receivers Typical Stereo Audio System Using TAS5182 H-Bridge Driver Digital Audio • TI DAP • TI DSP • TI SPD IF • TI 1394 Texas Instruments Digital Audio Solutions Left LOAD Right LOAD L L TAS5182 TAS50XX R R PWM Modulator H-Bridge Driver Discrete MOSFET H-Bridges † When using appropriate MOSFETs. ‡ When using recommended design. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath and PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 ORDERING INFORMATION TA PACKAGE 0°C to 70°C TAS5182DCA -40°C to 85°C TAS5182IDCA These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (TA) unless otherwise noted(1) TAS5182 Supply voltage range GVDD to GVSS -0.3 V to 15 V DVDD to DVSS -0.3 V to 3.6 V AP, AM, BP, BM, CP, CM, DP, DM -0.3 V to DVDD + 0.3 V RESET, SHUTDOWN -0.3 V to DVDD + 0.3 V BST_A, BST_B, BST_C, BST_D to GVSS for pulse width <100 ns 63 V Switching frequency 1500 kHz Operating junction temperature range, TJ 150°C Storage temperature range, Tstg (1) -65°C to 150°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage range MIN NOM MAX UNIT GVDD to GVSS 9 12 12.6 V DVDD to DVSS 3 3.3 3.6 V High-side bootstrap supply voltage range BST_A, BST_B, BST_C, BST_D 50 52.6 V High-side drain connection voltage range DHS_A, DHS_B, DHS_C, DHS_D 40 42 V High-side source connection voltage range SHS_A, SHS_B, SHS_C, SHS_D 40 42 V 2 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 ELECTRICAL CHARACTERISTICS TC = 25°C, DVDD = 3.3 V, GVDD = 12 V, Frequency = 384 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT TERMINALS: AM, AP, BM, BP, CM, CP, DM, DP VIH High input voltage 2 VIL Low input voltage RI Input resistance Rdtp Dead time resistor range V 0.8 50 0 V kΩ 100 kΩ INPUT TERMINAL: RESET_X VIH(RESET) High input voltage VIL(RESET) Low input voltage 2 V 0.8 V GATE DRIVE OUTPUT: GHS_A, GHS_B, GHS_C, GHS_D, GLS_A, GLS_B, GLS_C, GLS_D Ioso Source current, peak VO = 2 V -1.2 A Iosi Sink current, peak VO = 8 V 1.6 A Forward current voltage drop Id = 100 mA 2 V BST DIODE Vd SUPPLY CURRENTS IDVDD Operating supply current No load on gate drive output 3 mA IDVDDQ Quiescent supply current No switching 3 mA IGVDD Operating supply current No load on gate drive output 15 mA IGVDDQ Quiescent supply current No switching 2 mA VOLTAGE PROTECTION Vuvp,G Undervoltage protection limit, GVDD 8.3 V SWITCHING CHARACTERISTICS TC = 25°C, DVDD = 3.3 V, GVDD = 12 V PARAMETER TEST CONDITIONS MIN NOM MAX UNIT 1500 kHz TIMING, OUTPUT TERMINALS fop Operating frequency tpd(if-O) Positive input falling to GHS_x falling CL = 1 nF 45 tpd(ir-O) Positive input rising to GLS_x falling CL = 1 nF 45 tdtp Dead time programming range(1) Rdfp = 100 kΩ tr(GD) Rise time, gate drive output (0.5 to 3 V) CL = 1 nF 4.5 ns tf(GD) Fall time, gate drive output (9 to 3 V) CL = 1 nF 7 ns ns ns 110 ns TIMING, PROTECTION, AND CONTROL tpd(R-SD) Delay, RESET low to SHUTDOWN high 40 ns tpd(R-LH) Delay, RESET low to GLS_x high 44 ns tpd(R-OP) Delay, RESET high to operation state 50 ns tpd(E-L) Delay, error event to all gates low 180 ns tpd(E-SD) Delay, error event to SHUTDOWN low 170 ns (1) Dead time programming definition: Adjustable delay from AP (BP, CP, or DP) rising edge to GHS_A (GHS_B, GHS_C, or GHS_D) rising edge, and AM (BM, CM, or DM) rising edge to GLS_A (GLS_B, GLS_C, or GLS_D) rising edge. 3 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 PIN ASSIGNMENTS DCA PACKAGE (TOP VIEW) NC NC DVDD DVSS NC DTC_HS DTC_LS OC_HIGH VRFILT AP AM RESET_AB BM BP CP CM RESET_CD DM DP SHUTDOWN ERR0 ERR1 LOW/HIZ DVSS NC NC OC_LOW TEMP 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GVSS GVDD GLS_A SLS_A SHS_A GHS_A BST_A DHS_A GLS_B SLS_B SHS_B GHS_B BST_B DHS_B GLS_C SLS_C SHS_C GHS_C BST_C DHS_C GLS_D SLS_D SHS_D GHS_D BST_D DHS_D GVDD GVSS NC - No internal connection Exposed pad size is 106 x 204 mils Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AM 11 I PWM input signal (negative), half-bridge A AP 10 I PWM input signal (positive), half-bridge A BM 13 I PWM input signal (negative), half-bridge B BP 14 I PWM input signal (positive), half-bridge B BST_A 50 I High-side bootstrap supply (BST), external capacitor to SHS_A required BST_B 44 I High-side bootstrap supply (BST), external capacitor to SHS_B required BST_C 38 I High-side bootstrap supply (BST), external capacitor to SHS_C required BST_D 32 I High-side bootstrap supply (BST), external capacitor to SHS_D required CM 16 I PWM input signal (negative), half-bridge C CP 15 I PWM input signal (positive), half-bridge C DM 18 I PWM input signal (negative), half-bridge D DP 19 I PWM input signal (positive), half-bridge D 4 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION DHS_A 49 I High-side drain connection, used for high-side VDS sensing DHS_B 43 I High-side drain connection, used for high-side VDS sensing DHS_C 37 I High-side drain connection, used for high-side VDS sensing DHS_D 31 I High-side drain connection, used for high-side VDS sensing DTC_HS 6 I High-side dead-time programming, external resistor to DVSS required DTC_LS 7 I Low-side dead-time programming, external resistor to DVSS required DVDD 3 P Logic supply voltage DVSS 4, 24 P Digital ground, reference for input signals ERR0 21 O Logic output, signals chip operation mode/state. This output is open drain with internal pullup resistor. ERR1 22 O Logic output, signals chip operation mode/state. This output is open drain with internal pullup resistor. GHS_A 51 O Gate drive output for high-side MOSFET, half-bridge A GHS_B 45 O Gate drive output for high-side MOSFET, half-bridge B GHS_C 39 O Gate drive output for high-side MOSFET, half-bridge C GHS_D 33 O Gate drive output for high-side MOSFET, half-bridge D GLS_A 54 O Gate drive output for low-side MOSFET, half-bridge A GLS_B 48 O Gate drive output for low-side MOSFET, half-bridge B GLS_C 42 O Gate drive output for low-side MOSFET, half-bridge C GLS_D 36 O Gate drive output for low-side MOSFET, half-bridge D GVDD 30, 55 P Gate drive voltage supply terminal GVSS 29, 56 P Gate drive voltage supply ground return 23 I Logic signal that determines the drive output state during a reset. When RESET_AB or RESET_CD is low, LOW/HIZ = 1 indicates that the outputs are low impedance LOW/HIZ = 0 indicates that the outputs are high impedance LOW/HIZ NC 1, 2, 5, 25, 26 Not connected. Terminals 1, 2, 5, 25, and 26 may be connected to DVSS. OC_HIGH 8 I High-side overcurrent trip value programming. OC configuration circuit (see Figure 5) is required. OC_LOW 27 I Low-side overcurrent trip value programming. OC configuration circuit (see Figure 5) is required. RESET_AB 12 I Reset signal half-bridge A and B, active low RESET_CD 17 I Reset signal half-bridge C and D, active low SHUTDOWN 20 O Error/warning report indicator. This output is open drain with internal pull-up resistor. SHS_A 52 I High-side source connection, used as BST floating ground (and high-side VDS sensing) SHS_B 46 I High-side source connection, used as BST floating ground (and high-side VDS sensing) SHS_C 40 I High-side source connection, used as BST floating ground (and high-side VDS sensing) SHS_D 34 I High-side source connection, used as BST floating ground (and high-side VDS sensing) SLS_A 53 I Source connection low-side MOSFET, ground return terminal, half-bridge A SLS_B 47 I Source connection low-side MOSFET, ground return terminal, half-bridge B SLS_C 41 I Source connection low-side MOSFET, ground return terminal, half-bridge C SLS_D 35 I Source connection low-side MOSFET, ground return terminal, half-bridge D TEMP 28 I External temperature sensing connection VRFILT 9 I Bandgap reference = 1.8 V. Capacitor must be connected from VRFILT to DVSS. 5 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 FUNCTIONAL BLOCK DIAGRAM LOW/HIZ OC_HIGH OC_LOW TEMP VRFILT Protection Circuitry Bandgap Reference A - Half-Bridge Driver GVDD BST_A DTC_HS DTC_LS AP AM RESET_AB SHUTDOWN ERR0 ERR1 Status PWM Receiver Timing and Control HS Gate Drive DHS_A GHS_A SHS_A LS Gate Drive GVDD B - Half-Bridge Driver GLS_A SLS_A GVDD BST_B BP BM PWM Receiver Timing and Control HS Gate Drive LS Gate Drive C - Half-Bridge Driver DHS_B GHS_B SHS_B GVDD GLS_B SLS_B GVDD BST_C CP CM RESET_CD PWM Receiver Timing and Control HS Gate Drive DHS_C GHS_C SHS_C LS Gate Drive GLS_C SLS_C D - Half-Bridge Driver GVDD GVDD BST_D DP DM DVDD DVSS 6 PWM Receiver Timing and Control HS Gate Drive DHS_D GHS_D SHS_D LS Gate Drive GVDD GLS_D SLS_D GVSS TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 TIMING DIAGRAMS 1/fop AP AM tdtp tpd(if-O) GHS_A GLS_A tdtp tpd(ir-O) Figure 1. PWM Input to Gate Drive Output Timing (Same for A, B, C, and D Half-Bridge Drivers) RESET tpd(R-SD) SHUTDOWN Figure 2. RESET to SHUTDOWN Propagation Delay RESET tpd(R-OP) GHS_A GLS_A Figure 3. RESET to Gate Drive Output Propagation Delay (Same for Half-Bridge A, B, C, and D) 7 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 SIMPLIFIED APPLICATION CONNECTION DIAGRAM (BRIDGE-TIED-LOAD CONFIGURATION) Gate Drive Supply 55 30 56 29 10 PWM_AP_L 11 PWM_AM_L 12 VALID_L 13 PWM_BP_L 14 PWM_BM_L GVDD DHS_A GVDD GHS_A GVSS SHS_A GVSS GLS_A AP AM BST_A SLS_A RESET_AB 15 PWM_AP_R 16 PWM_AM_R 17 VALID_R 18 PWM_BP_R 19 PWM_BM_R 20 RESET 21 To UP 22 23 6 7 CP TAS5182 BST_B RESET_CD GLS_B DM DP SHUTDOWN SHS_B 27 H-Bridge Supply ERR1 LOW/HIZ DHS_C GHS_C SHS_C DTC_HS 28 GLS_C 47 + 44 H-Bridge Supply 48 46 37 39 40 42 38 LOAD VRFILT BST_D OC_LOW GLS_D 35 32 36 DVDD TEMP H-Bridge + Supply 41 OC_HIGH 34 33 GHS_D 31 DHS_D 1 NC 2 NC 5 NC 25 NC 26 NC NTC NOTE: Recommended power MOSFETs International Rectifier IRFIZ24N (8 places) For complete reference schematics contact Texas Instruments. 8 53 H-Bridge Supply DTC_LS 4 DV SS 24 DV SS 3 + ERR0 SHS_D Digital Supply 50 45 GHS_B 43 DHS_B SLS_D 9 54 CM SLS_C 8 52 LOAD BST_C H-Bridge Supply 51 BM BP SLS_B TAS50XX 49 + H-Bridge Supply TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 FUNCTIONAL DESCRIPTION Channel Reset Power Stage Protection The reset function enables operation after power up, re-enables operation after an error event, and disables the MOSFET output stage switching during power down and mute. The falling edge of RESET_AB (left audio channel) or RESET_CD (right audio channel) causes the TAS5182 device to reset. The rising edge of RESET_AB or RESET_CD causes the TAS5182 device to clear the error latch and resume normal operation. The TAS5182 device provides overcurrent, overtemperature, and undervoltage protection for the MOSFET power stage. Overcurrent Protection (OCP) To protect the power stage from damage due to high currents, a VDS sensing system is implemented in the TAS5182 device. Based on RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated which, when exceeded, triggers the protection latch, causing the SHUTDOWN terminal to go low. This voltage threshold is resistor programmable. See the Calculation of Overcurrent Resistor Values section for more details. Overtemperature Protection (OTP) The TAS5182 device has a temperature protection system that uses an external negative temperature coefficient (NTC) resistor as a temperature sensor. See the Overtemperature Programming Circuit section for implementation details. Undervoltage Protection (UVP) To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the TAS5182 device provides power stage undervoltage protection by driving its outputs low whenever GVDD is under 7 V. With the TAS5182 outputs driven low, the MOSFETs go to a high-impedance state. Control Terminals The TAS5182 device provides input control terminals to reset each audio channel and also to control the electrical characteristics of the MOSFET output power stage. MOSFET Output Reset Control The LOW/HIZ control terminal selects whether the MOSFET output stage goes into a high-impedance (HI-Z) state or LOW-LOW state when RESET_AB or RESET_CD is enabled. In the high-impedance state, the low-side and high-side MOSFETs are turned off causing no current flow through the MOSFETs. This effectively disconnects the load from the power supply rail. In the LOW-LOW state, the low-side MOSFETs are turned on, while the high-side MOSFETs are turned off. This causes a low or ground signal to be output to the load. Status Terminals The TAS5182 device provides output status terminals to report overcurrent, overtemperature, and undervoltage warnings and errors. Shutdown Indicator The SHUTDOWN terminal indicates an error event has occurred such as overcurrent, overtemperature, or undervoltage. The SHUTDOWN terminal is pulled high when RESET_AB or RESET_CD is asserted. ERR0 and ERR1 terminals along with the SHUTDOWN terminal indicate the type of warnings and errors. Note that SHUTDOWN is an open-drain signal. See Table 1 for a functional description of these signals. Table 1. TAS5182 Status Signals ERR0 ERR1 SHUTDOWN DESCRIPTION 0 0 0 Multiple errors (TAS5182 gate outputs low, MOSFET outputs HI-Z) 0 0 1 Not valid 0 1 0 Overtemperature error (TAS5182 gate outputs low, MOSFET outputs HI-Z) 0 1 1 Overtemperature warning (normal operation) 1 0 0 Overcurrent error (TAS5182 gate outputs low, MOSFET outputs HI-Z) 1 0 1 Not valid 1 1 0 GVDD undervoltage error (TAS5182 gate outputs low, MOSFET outputs HI-Z) 1 1 1 Normal operation 9 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 TAS5182 Power Up and Reset After power up, all gate drive outputs are held low (i.e., the error latch is set). Normal operation can be initiated by toggling RESET_AB and/or RESET_CD from a low state to a high state. If no errors are present, then the TAS5182 device is ready to accept audio inputs. TAS5182 Reset and Error Timing The TAS5182 device provides two output control configurations for reset and error situations. In a BTL system configuration, the MOSFET outputs must be grounded before resuming normal operation. This enables the bootstrap capacitors to charge. Reset and Error Timing (BTL System) When using this device in the BTL configuration, it is advisable to bring the MOSFET outputs to a high impedance state when reset (RESET_AB or RESET_CD) is asserted. Figure 4 shows the timing that occurs in this configuration. This feature is enabled by connecting the LOW/HIZ terminal to DVSS. When an error event occurs (see Table 1) and following propagation delay tpd(E-SD), the TAS5182 device pulls the SHUTDOWN signal low. The falling edge of SHUTDOWN forces the MOSFET outputs into a high-impedance state. The SHUTDOWN signal is usually connected to the RESET terminal of the TAS50XX PWM controller. After some delay, the controller then asserts the TAS5182 RESET_AB and RESET_CD terminals low. The falling edge of RESET forces the MOSFET outputs to ground potential (this event also brings the SHUTDOWN signal high). This allows the bootstrap capacitors to charge through the grounded MOSFET outputs. When RESET is pulled high, the system resumes normal operation. Error Event tpd(E-SD) SHUTDOWN tpd(R-SD) RESET tpd(E-L) tpd(R-OP) tpd(R-LH) LOW/HIZ = LOW TAS5182 Outputs Normal Operation All Gate Outputs Low MOSFET Outputs Normal Operation HI-Z All Gate Outputs Low HI-Z Normal Operation Normal Operation Figure 4. Reset and Error Timing (BTL System) Overcurrent Configuration From Circuit Table 2. OCL and OCH Reference Voltages (Overcurrent Configuration Circuit) The output current flows through internal resistance RDS(on) of the external MOSFETs, which creates voltage drop VDS. The overcurrent detector senses this voltage to trigger an error event. The exact current limit depends on parasitics from the PCB layout, resistance of the MOSFET at the operation temperature, and the configuration of the H-bridge output stage. See Table 2 for the OCL and OCH reference voltages. Figure 5 shows the recommended overcurrent configuration circuit. 10 VOLTAGE OUTPUT INDUCTOR SHUTDOWN CURRENT RANGE(1) OCL 0.7 V (terminal 27) 12-19 A OCH 1.17 V (terminal 8) 14-24 A (1) Measured on Texas Instruments reference board TAS5182C6REF. TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 Board configuration: D D D D 1R0 resistors on SHS and GLS connections GVDD = 12 V, PVDD = 40 V 10BQ060 voltage clamp on output node TT snubbers: L = 75 nH, C = 10 nF, R = 5.4 Ω 220 kW DVDD. OT error occurs when the voltage at the TEMP terminal is approximately 23% of DVDD. OT warning is decoded when ERR0 = 0, ERR1 = 1, and SHUTDOWN = 1. OT error is decoded when ERR0 = 0, ERR1 = 1, and SHUTDOWN = 0. The user for a particular application determines the values of R1 and RNTC. Typical values are R1 = 16 kΩ and RNTC = 47 kΩ. 1 MW V-HBRIDGE V-HBRIDGE TAS5182 220 kW THERMAL INFORMATION 1 MW 9 22 kW VRFILT = 1.8 V 22 kW 8 VOC 27 10 kW OC_HIGH OC_LOW 10 kW Figure 5. Overcurrent Configuration Circuit Overtemperature Programming Circuit The TAS5182 device features a temperature protection system that uses an external negative temperature coefficient (NTC) resistor as a temperature sensor. Figure 6 shows a typical application. DVDD Supply TAS5182 3 DVDD R1 16 kW 28 R(NTC) 47 kW 4 TEMP DVSS Figure 6. Temperature Sensing Circuit The temperature protection system has two trigger limits: OT warning and OT error. OT warning occurs when the voltage at the TEMP terminal is approximately 36% of The thermally enhanced DCA package is based on the 56-pin HTSSOP, but includes a thermal pad (see Figure 7) to provide an effective thermal contact between the IC and the PCB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220 type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, have two shortcomings: they do not address the low profile requirements (< 2 mm) of many of today’s advanced systems and they do not offer a terminal count high enough to accommodate increasing integration. However, traditional low-power, surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits The PowerPADt package (thermally enhanced HTSSOP) combines fine-pitch, surface-mount technology with thermal performance comparable to much larger power packages. The PowerPAD package is designed to optimize the heat transfer to the PCB. Because of the small size and limited mass of a HTSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a patented lead-frame design and manufacturing technique to provide a direct connection to the heat-generating IC. When this pad is soldered to the PCB, good power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. See Reference 4 for recommended soldering procedure. THERMAL DATA PARAMETER MIN TYP Commercial Industrial Thermal resistance, θjc Pad with solder (1) Thermal resistance, θja Thermal resistance, θjc Thermal resistance, θja Pad without solder (1) UNIT 150 _C 0 25 70 _C -40 25 85 _C Junction temperature, TJ(SD) Operating p g temperature, p , TC MAX 0.27 _C/W 21.17 _C/W 0.27 _C/W 36.42 _C/W 11 TAS5182 www.ti.com SLES045E - JUNE 2002 - REVISED MAY 2004 (1) Values taken from Table 6 Thermal Characteristics for Different Package and PCB Configurations of the PowerPAD Thermally Enhanced Package application note (SLMA002). See pages 32 and 33 for a description of the printed circuit board (PCB) used for these measurements. Note that the PCB used for these measurements is not the recommended PCB for TAS5182 applications but is cited here for reference only. Power Dissipation The equation for TAS5182 power dissipation using N external MOSFETs is: Pd = Vgd x Qg x f x N Note: Lab measurements yield a power dissipation of 0.8 W (PVDD = 40 V). where: REFERENCES Vgd = GVDD (typically 12 V) 1. TAS5000 Digital Audio PWM Process data manual, Qg = MOSFET gate charge Texas Instruments Literature Number SLAS270 f = operating frequency 2. System Design Considerations for True Digital Audio N = number of external MOSFETs driven (eight for two-channel operation) Example power dissipation calculation: Given a TAS5182 system with eight external IRFIZ24N MOSFETs and GVDD = 12 V. The power dissipation is: Pd = Vgd x Qg x f x N = 12V x 22.5nC x 384 kHz x 8 = 0.8 W Thermal Pad Bottom View DCA Figure 7. Views of a Thermally Enhanced DCA Package 12 Power Amplifiers, Texas Instruments Literature Number SLAA117 3. Digital Audio Measurements, Texas Instruments Literature Number SLAA114 4. PowerPAD Thermally Enhanced Package, Texas Instruments Literature Number SLMA002 5 4 3 2 1 TAS5182 OUTPUT STAGE TAS5182 SECTION H-BRIDGE SECTION DE-MODULATION FILTER CHANNEL 1 L240 OC CONFIGURATION 1 2 CH1-OUT+ 7uH D 2 2 RESET_AB GHS_B 45 PWM-BM-CH1 13 BM BST_B 44 PWM-BP-CH1 14 BP DHS_B 43 PWM-AP-CH2 15 CP GLS_C 42 PWM-AM-CH2 16 CM SLS_C 41 /VALID-CH2 17 RESET_CD SHS_C 40 PWM-BM-CH2 18 DM GHS_C 39 PWM-BP-CH2 19 DP BST_C 38 20 SHUTDOWN DHS_C 37 /ERR0 21 ERR0 GLS_D 36 /ERR1 22 ERR1 SLS_D 35 23 LOW/HIZ SHS_D 34 24 DVSS GHS_D 33 25 NC BST_D 32 DHS_D 31 OC_LOW GVDD 30 TEMP GVSS 29 TAS5182 2 1 DVDD 22nF 10nF Q225 IRFIZ24N 1 R229 2 1 PVDD-D 1 1 2 2 1 1 1 2 2 2 1 C265 1nF R261 3.30R 75nH 2 1 C263 10nF C261 1000uF L263 R231 2.70R C209 2 1.00R 1 22nF R213 1 2 R230 1 2 1.00R GVDD Q226 IRFIZ24N 1 1R C211 1uF D262 10BQ060 R232 2.70R B GND R265 1 GND 2 V-HBRIDGE 2.70R C268 100nF DE-MODULATION FILTER CHANNEL 2 GND GND 16k 2 C223 L280 1 R208 47k 2 CH2-OUT+ 2 12 3 2 2 2.70R C269 100nF 2 2 GND V-HBRIDGE L281 1 R283 4.70k R281 4.7R R285 4.70k A 2 A 2 2 1 C281 470nF GND C286 680pF 1 R266 2 2 3 GND D263 10BQ060 R236 2.70R 1 Q228 IRFIZ24N 1 1 R234 1.00R R284 4.70k V-HBRIDGE 2 1.00R 2 R282 4.70k C285 680pF R235 2.70R 2 1 C280 470nF 10nF R233 1 1 C224 Q227 IRFIZ24N 1 2 2 1 2 GND 1 R280 4.7R PVDD-D 1 1 7uH 2 1 GND 2 1 1 1 PVDD-C C208 2 2 R207 GND 2 2 C212 100nF 1 C213 100nF V-HBRIDGE 75nH 1 28 L262 1 PVDD-C 1 27 R260 3.30R 2 NC C264 1nF GND 1 22nF 2 0R 26 C207 2 2 OC-LOW 2 GND R211 1 2 C262 10nF C260 1000uF 1 /SHUTDOWN GND 2 75nH 2 12 L261 1 PVDD-B 1 SHS_B /VALID-CH1 V-HBRIDGE 2.70R C267 100nF 2 AM 46 3 PWM-AM-CH1 11 2 1 47 2 SLS_B R264 1 1 AP 10 1.00R D261 10BQ060 R228 2.70R 2 48 Q224 IRFIZ24N 1 1 GLS_B 2 2 VRFILT R226 1 1 9 1.00R 1 22nF 2 DHS_A C206 2 1 OC_HIGH 49 2 100nF PWM-AP-CH1 50 8 1 2 51 BST_A C 2 2 1 GHS_A DTC_LS 2 75nH 1 VR-FILT DTC_HS 7 1 L260 1 PVDD-A 2 100nF C202 6 R227 2.70R 2 0R 2 SHS_A R225 1 C214 1 2 NC 52 2 1 OC-HIGH 5 2 R210 1 21 53 2 54 SLS_A 1 GLS_A DVSS POWER SUPPLY FILTER 10nF 2 DVDD 4 CH1-OUT- 1 3 Q223 IRFIZ24N 12 55 2 GVDD 1 PVDD-B C222 3 NC R241 4.7R R245 4.70k 7uH 2 1uF 2 2 GND 3 56 2 GVSS 1 C201 100nF NC L241 R243 4.70k 2 2.70R C266 100nF GND 3 0R 1 2 2 V-HBRIDGE 1 2 C241 470nF 1 2 2 1 R205 1 DVDD R212 1R C205 1 1 B To/From Texas Instruments TAS5036 PWM Modulator C GND GVDD U201 1 2 1 GND C246 680pF 1 R263 2 1.00R GND D260 10BQ060 R224 2.70R 1 2 Q222 IRFIZ24N 1 2 2 GND 2 C245 680pF R244 4.70k 2 R222 1 R242 4.70k V-HBRIDGE 1 R128 10k GND 12 2 2 1.00R 2 R124 10k OC-LOW 3 1 OC-HIGH R221 1 2 22k C240 470nF R223 2.70R 3 R126 1M 2 C221 10nF 1 1 VR-FILT 2 22k R127 1 1 VR-FILT R121 220k 2 Q221 IRFIZ24N 1 12 12 R123 1 R240 4.7R PVDD-A R125 1M 1 V-HBRIDGE R120 220k 1 V-HBRIDGE 1 1 D 1 CH2-OUT- 7uH GND DIGITAL AUDIO & VIDEO DIVISION TI Patents pending in circuitry design and layout (WO99/59241 & WO99/59242). This circuitry may only be used together with the integrated circuit TAS5100/TAS5110/TAS5111/TAS5112/TAS5182 from Texas Instruments Incorporated. 5 4 3 2 ALL RIGHTS RESERVED - PATENTS PENDING TEXAS INSTRUMENTS INCORPORATED Project: TAS5182C6REF Rev: 6.00 Page Title: CHANNEL 1 & CHANNEL 2 Size: File Name: Engineer: Date: Page: 1 of MECHANICAL DATA MPDS044 – JANUARY 1998 DCA (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 Thermal Pad (See Note D) 8,30 7,90 6,20 6,00 0,15 NOM Gage Plane 1 24 0,25 A 0°– 8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4073259/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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