SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 FEATURES D Industry-Standard Pin-Out D High Current Drive Capability of ±4 A at the D D D D D D D D D Miller Plateau Region Efficient Constant Current Sourcing Using a Unique BiPolar & CMOS Output Stage TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times with 1.8-nF Load Typical Propagation Delay Times of 25 ns with Input Falling and 35 ns with Input Rising 4-V to 15-V Supply Voltage Supply Current of 0.3 mA Dual Outputs Can Be Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPADTM Package with 4.7°C/W θjc Rated From –40°C to 85°C APPLICATIONS D Switch Mode Power Supplies D DC/DC Converters D Motor Controllers D Line Drivers DESCRIPTION The UCC37323/4/5 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads.Three standard logic options are offered – dual-inverting, dual-noninverting and one-inverting and one-noninverting driver. The thermally enhanced 8-pin PowerPADTM MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. Using a design that inherently minimizes shoot-through current, these drivers deliver 4-A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. BLOCK DIAGRAM INVERTING N/C 1 INA 2 8 N/C 7 OUTA NON–INVERTING GND 3 INVERTING INB 4 6 VDD 5 OUTB NON–INVERTING UDG–01063 PowerPADt is a trademark of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '! !"# %! &*)' '$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. www.ti.com 1 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 ORDERING INFORMATION OUTPUT CONFIGURATION TEMPERATURE RANGE TA = TJ SOIC-8 (D) PDIP-8 (P) –40°C to +85°C UCC27323D UCC27323DGN UCC27323P 0°C to +70°C UCC37323D UCC37323DGN UCC37323P –40°C to +85°C UCC27324D UCC27324DGN UCC27324P 0°C to +70°C UCC37324D UCC37324DGN UCC37324P –40°C to +85°C UCC27325D UCC27325DGN UCC27325P Dual inverting D al nonIn Dual nonInverting erting One inverting, one noninverting PACKAGED DEVICES MSOP-8 PowerPAD (DGN)} 0°C to +70°C UCC37325D UCC37325DGN UCC37325P † D (SOIC–8) and DGN (PowerPAD–MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27323DR, UCC27324DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package. ‡ The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) N/A 1 8 N/A N/A 1 8 N/A N/A 1 8 N/A INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD INB 4 5 OUTB INB 4 5 OUTB INB 4 5 OUTB (DUAL INVERTING) (ONE INVERTING, ONE NONINVERTING) (DUAL NONINVERTING) power dissipation rating table PACKAGE SUFFIX Θjc (°C/W) Θja (°C/W) Power Rating (mW) TA = 70°C See Note 1 Derating Factor Above 70°C (mW/ C) See Note 1 SOIC-8 D 42 84 – 160} 344–655 See Note 2 6.25 – 11.9 See Note 2 PDIP-8 P 49 110 500 9 MSOP PowerPAD-8 See Note 3 DGN 4.7 50 – 59} 1370 17.1 Notes: 1. 125°C operating junction temperature is used for power rating calculations 2. The range of values indicates the effect of pc–board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc–board where possible in order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made Easy, Texas Instruments Literature No. SLMA004. 3. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. Table 1. Input/Output Table INPUTS (VIN_L, VIN_H) 2 UCC37323 UCC37324 UCC37325 INA INB OUTA OUTB OUTA OUTB OUTA OUTB L L H H L L H L L H H L L H H H H L L H H L L L H H L L H H L H www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V Output current (OUTA, OUTB) DC, IOUT_DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 A Pulsed, (0.5 µs), IOUT_PULSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A . . . Power dissipation at TA = 25°C (DGN package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W (D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW (P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mW Junction operating temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature (soldering, 10 sec.), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. electrical characteristics, VDD = 4.5 V to 15 V, TA = TJ, (unless otherwise noted) input (INA, INB) PARAMETER TEST CONDITION MIN VIN_H, logic 1 input threshold TYP 0 V <= VIN <= VDD UNITS V VIN_L, logic 0 input threshold Input current MAX 2 1 V –10 0 10 µA MIN TYP MAX UNITS 300 450 mV 22 40 mV 30 35 Ω 42 Ω 2.5 Ω 4.0 Ω output (OUTA, OUTB) PARAMETER Output current VOH, high-level output voltage VOL, low-level output level Output resistance high Output resistance low Latch-up protection TEST CONDITION VDD = 14 V, See Note 1, VOH = VDD – VOUT, See Note 2 4 IOUT = –10 mA IOUT = 10 mA TA = 25°C, See Note 3 IOUT = –10 mA, VDD = 14 V, 25 TA = full range, See Note 3 IOUT = –10 mA, VDD = 14 V, 18 TA = 25°C, See Note 3 IOUT = 10 mA, VDD = 14 V, 1.9 TA = full range See Note 3 IOUT = 10 mA, VDD = 14 V, 1.2 See Note 1 500 2.2 A mA NOTES: 1. Ensured by design. Not tested in production. 2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. 3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. www.ti.com 3 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 electrical characteristics, VDD = 4.5 V to 15 V, TA = TJ, (unless otherwise noted) switching time TYP MAX UNITS tR, rise time (OUTA, OUTB) PARAMETER CLOAD = 1.8 nF, TEST CONDITION See Figure 1 MIN 20 40 ns tF, fall time (OUTA, OUTB) CLOAD = 1.8 nF, See Figure 1 15 40 ns tD1, delay, IN rising (IN to OUT) CLOAD = 1.8 nF, See Figure 1 25 40 ns tD2, delay, IN falling (IN to OUT) CLOAD = 1.8 nF, See Figure 1 35 50 ns UNITS overall PARAMETER TEST CONDITION TYP MAX INB = 0 V 300 450 INA = 0 V, INB = HIGH 300 450 INA = HIGH, INB = 0 V 300 450 INA = HIGH, INB = HIGH 300 450 INA = 0 V, INB = 0 V INA = 0 V, INA = HIGH, INA = 0 V, UCCx7323 IDD, static operating current c rrent UCC 7324 UCCx7324 UCC 7325 UCCx7325 MIN 2 50 INB = HIGH 300 450 INB = 0 V 300 450 INA = HIGH, INB = HIGH 600 750 INA = 0 V, INB = 0 V 150 300 INA = 0 V, INB = HIGH 450 600 INA = HIGH, INB = 0 V 150 300 INA = HIGH, INB = HIGH 450 600 µA A NOTES: 1. Ensured by design. Not production. 2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. 3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. (a) (b) +5V 90% 90% INPUT INPUT 10% 10% 0V tD1 tf tD2 tF 90% 90% tF tF 16V tD1 OUTPUT 90% tD2 OUTPUT 10% 10% 0V Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 4 www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 Terminal Functions TERMINAL FUNCTION NO. NAME I/O 1 N/C – No connection. Should be grounded. 2 INA I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. 3 GND – Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. 4 INB I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. 5 OUTB O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. 6 VDD I Supply. Supply voltage and the power input connection for this device. 7 OUTA O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. 8 N/C – No Connection. Should be grounded. APPLICATION INFORMATION general information High frequency power supplies often require high-speed, high-current drivers such as the UCC37323/4/5 family. A leading application is the need to provide a high power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC37323/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. www.ti.com 5 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION input stage The inputs of UCC37323/4/5 family of drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the IC package, as discussed in the section on Thermal Considerations. output stage Inverting outputs of the UCC37323 and OUTA of the UCC37325 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC37324 and OUTB of the UCC37325 are intended to drive external N-channel MOSFETs. Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. The UCC37323 family delivers 4-A of gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages. 6 www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION source/sink capabilities during Miller plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC37323/4/5 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver IC. [1] Two circuits are used to test the current capabilities of the UCC37323 driver. In each case external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC37323 is found to sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V. VDD UCC37323 INPUT 1 2 8 INA 3 GND 4 INB OUTA DSCHOTTKY C2 1 µF VDD 6 OUTB 10 Ω 7 5 C3 + 100 µ F VSUPPLY 5.5 V VSNS 1 µF CER 100µF AL EL RSNS 0.1Ω UDG–01065 Figure 2. www.ti.com 7 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC37323 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V. VDD UCC37323 1 INPUT 2 8 OUTA INA 3 GND 4 DSCHOTTKY C2 1 µF VDD 6 INB OUTB 10Ω 7 5 C3 100 µF DADJ 4.5 V VSNS 1 µF CER RSNS 0.1Ω 100µF AL EL UDG–01066 Figure 3. It should be noted that the current sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON. parallel outputs The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 4. VDD = 12 V UCC37323 INPUT 1 2 8 INA 3 GND 4 INB OUTA 7 VDD 6 OUTB 5 CLOAD 0.1 µF CER 2.2 µF UDG–01067 Figure 4. 8 www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION operational waveforms and circuit layout Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load. The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. Figure 5. In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections should also be made with a small enclosed loop area to minimize the inductance. VDD Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg x f, where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. www.ti.com 9 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION drive current and power requirements The UCC37323/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers. When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E + 1 CV 2, where C is the load capacitor and V is the bias voltage feeding the driver. 2 There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P+2 1 CV 2f, where f is the switching frequency. 2 This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as: P = 10 nF x (12)2 x (300 kHz) = 0.432 W With a 12-V supply, this would equate to a current of: I + P + 0.432 W + 0.036 A V 12 V The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the IDD current that is due to the IC internal consumption should be considered. With no load the IC current draw is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to that expected. 10 www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for power: P+C V2 f + Qg f This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. THERMAL INFORMATION The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC37323/4/5 family of drivers is available in three different packages to cover a range of application requirements. As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages. The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference 2, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the IC package, reducing the Θjc down to 4.7°C/W. Data is presented in Reference 2 to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference 3. This allows a significant improvement in heatsinking over that available in the D or P packages, and is shown to more than double the power capability of the D and P packages. references 1. Power Supply Seminar SEM–1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, by Bill Andreycak, Texas Instruments Literature No. SLUA105 3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 4. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004 www.ti.com 11 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 www.ti.com SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 MECHANICAL DATA DGN (MSOP) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note F) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°–ā6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 04/98 NOTES: A. B. C. D. E. F. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. Falls within JEDEC MO-187 The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The exposed pad dimension is 1.3 mm x 1.7 mm. However, the tolerances can be +1.05/–0.05 mm (+ 41 / –2 mils) due to position and mold flow variation. G. For additional information on the PowerPADt package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com. PowerPADt is a trademark of Texas Instruments Incorporated. www.ti.com 13 SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002 MECHANICAL DATA P (PDIP) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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