Ordering number : ENA1337 CMOS LSI LC01700PW FM tuner IC for VICS Overview LC01700PW is an FM tuner IC for vehicle-mounted VICS incorporating FM FE, IF, OP AMP, PLL. VICS tuner can be developed by one chip. This IC can make up a small FM tuner module mounted for navigation. Features • Dedicated FM tuner IC for VICS in Japan and RDS in Europe. • Variable gain LNA incorporated. • A pulse counter detection method employed in the FM detection circuit. No adjustment necessary. • Less number of external parts. • BUS control tuner IC enabling control with I2C BUS. • OP AMP provided to adjust the composite frequency level appropriate to VICS and RDS. • 6Bit-ADC incorporated to enable digital output of S meter. Functions • FM-FE+IF+OP AMP+PLL Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max 6 V Maximum input voltage VDD H 6 V Maximum output voltage VDD L 6 Allowable power dissipation Pd max Operating temperature Topr -40 to +85 °C Storage temperature Tstg -50 to +150 °C Ta ≤ 85°C 400 V mW Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. O1508 MS PC 20080924-S00001 No.A1337-1/18 LC01700PW Operating supply voltage range at Ta = 25°C Parameter Symbol Recommended supply voltage VDD Supply voltage range VDD Conditions Ratings Not to exceed the absolute maximum rating Serial interface voltage level Parameter Unit 4.5 to 5.5 V 5.0 V VDD : Communications bus voltage Symbol Ratings Conditions min typ Unit max High level input voltage VIH 2.4 VDD V Low level input voltage VIL 0.0 0.7 V High level output voltage VOH VDD* V 0.2VDD V (open⋅drain) Low level output voltage VOL 0.0 (open·drain) * High level output voltage causes the open drain to become the high-impedance state. Since the drain is pulled up to VDD, the voltage is equal to VDD. Electrical Characteristics at Ta = 25°C, unless otherwise specified. fc = 83MHz, Vin = 60dBµVEMF, fm = 1kHz, Audio filter : HPF =100Hz, LPF = 15kHz Sample application circuit (Sample application circuit) look-up Register map <writing> look-up Parameter Symbol Ratings Conditions min S/N 30dB sensitivity SN30 22.5kHz dev, fm = 1kHz, S/N = 30dB input level S/N 10dB sensitivity *1 SN10 7.5kHz dev, fm = 76kHz, S/N = 10dB input level *2 Seek sensitivity (LO) Seek 22.5kHz dev, Vin = 40dBµVEMF typ Unit max 15 20 dBµVEMF 29 dBµVEMF 25 15 22 50 60 dBµVEMF Vsm = 2.0V adjustment Pin 18 (STDO) Lo → Hi input level S/N ratio 1 SN_1 22.5kHz dev, fm = 1kHz S/N ratio 2 SN_2 7.5kHz dev, fm = 76kHz *2 35 Total harmonic distortion 1 THD_1 22.5kHz dev, fm = 1kHz 0.1 1 % Total harmonic distortion 2 THD_2 75.0kHz dev, fm = 1kHz 0.2 1 % Total harmonic distortion 3 THD_3 22.5kHz dev, fm = 1kHz, Vin = 120dBµVEMF 0.1 1 Image removal ratio Image 22.5kHz dev, fm = 1kHz 40 50 dB AM suppression ratio AMR AM 30% mod 45 55 dB 170 270 430 mVrms 16 25 40 mVrms 30 45 mA Audio output level 1 Vo_1 75.0kHz dev, fm = 1kHz Audio output level 2 Vo_2 7.5kHz dev, fm = 76kHz *2 Current drain IDD Input at no signal dB dB % *1 S/N = 10dB at BER = 1% *2 Audio filter : HPF = 100Hz, LPF = OFF No.A1337-2/18 LC01700PW Package Dimensions unit : mm (typ) 3163B 36 0.5 9.0 7.0 25 24 48 13 7.0 9.0 37 1 12 0.5 0.18 0.15 (1.5) 0.1 1.7max (0.75) SANYO : SQFP48(7X7) No.A1337-3/18 LC01700PW 36 35 34 33 32 REG 10µF COMPOUT R3(*5) 3300pF GND_IF 10µF 0.1µF R2( 4) C( 6) * * 18pF 82pF 0.1µF 47kΩ 500kΩ 1µF 0.1µF SMETER Sample Application Circuit (Block Diagram) 31 30 29 28 27 26 0.1µF 25 24 OPAMP 3V REG 21 20 1shot 1.8V REF POR BUFF 1.5V 38 8pF X(*7) 8pF IOBUS SMUTE Demod IF CNT IRSSI 22 37 0.1µF VDD_IO 23 VSS 19 18 39 SCL 1kΩ SDA 1kΩ STDO 10kΩ 40 Lock Det. 0.1µF 15 5.6kΩ 1µF 14 13 SVC720 48 16 N-AGC 47 W-AGC RF AGC 1µF Keyed-AGC 1µF 45 VDD_AGC 46 0.1µF 17 Charge Pump Phase Det. Prog. Counter 44 SMUT E CNT 43 AGC COMP 0.1µF 42 SD COMP VDD_IF Level Shift 1µF Ref. Counter ADC 41 I/F CF(*3) 180nH 3pF 220Ω T2(*1) 12 1µF T1(*1) 0.1µF 0.1µF 33Ω 11 VDD - LO 100kΩ 10 GND - LO 9 22pF 2pF 22pF 100kΩ 1000pF 110nH 8 R1(*2) SVC720 110nH 7 VDD - RF 5 6 0.1µF 10pF 0.1µF 0.1µF CF(*3) 3 4 100pF 2 100pF 1 SVC720 GND - RF 180nH 100kΩ 1000pF 1SV249 12pF 100nH 56pF 22pF RF - IN (*1) T1 -TOKO : 5CCE #A638AN -1840YFZ T2 -TOKO : 5CCL ##613BG -0581WN (*2) R1 -TAIYO YUDEN: BK1608HS102 -T (*4) R2 -fm = 1kHz : NM fm = 76kHz : 6.8kΩ (*6) C -fm = 1kHz : NM fm = 76kHz : 680pF (*3) CF -MURATA : SFELL15M0GQQTS01 -B0 3dB Bandwidth 230 50kHz (*5) R3 -fm = 1kHz : 0Ω m = 76kHz : 6.8kΩ (*7) X -NIHON DENPA KOGYO CO.,LTD : AT41 14.55MHz No.A1337-4/18 LC01700PW Pin Description Pin No. Pin Name Type Description 1 MIX_ON OUT 2 MIX_OP OUT 3 MIX_IP IN 1stMIX signal input (+) 4 MIX_IN IN 1stMIX signal input (-) 5 LNA_ON OUT LNA signal output (-) 6 LNA_OP OUT 7 VDD_RF POWER 8 FM_IP IN 9 FM_IN IN 10 GND_RF GND RF block GND 11 GND_LO GND LO block GND 12 VDD_LO POWER LO block power 13 LOSC2 IN/OUT VCO resonant load pin 2 14 LOSC1 IN/OUT VCO resonant load pin 1 OUT 1stMIX signal output (-) 1stMIX signal output (+) LNA signal output (+) RF block power FM signal input (+) FM signal input (-) 15 VT 16 NC1 NC NC 17 NC2 NC NC 18 STDO 19 SDA IN/OUT 20 SCL IN Serial clock input (I2C) 21 XOSC2 IN/OUT Crystal oscillator pin 2 22 XOSC1 IN/OUT 23 VSS 24 VDD_IO 25 VDD OUT Digital block power (built-in regulator output) 26 GND_IF GND IF block GND 27 COMPOUT OUT Composite signal output OUT GND POWER Charge pump output Monitor output/reset detection output Serial data I/O (I2C) Crystal oscillator pin 1 Digital block GND 5V power for interface 28 DETREF IN/OUT 29 DETADJ OUT FM detection signal amplifier reference voltage 30 DETINP IN FM detection signal amplifier input (+) IN FM detection signal amplifier input (-) FM detection signal amplitude adjustment 31 DETINN 32 FDO 33 SMETER 34 CRSSI IN/OUT Connection of smoothing capacitor for S-meter/S-meter output voltage adjustment 35 LIM2 IN/OUT Limiter offset canceling capacitor connection 2 36 LIM1 IN/OUT Limiter offset canceling capacitor connection 1 37 NC3 NC NC 38 NC4 NC NC 39 IF2nd_IN IN 2ndMIX signal input (-) 2ndMIX signal input (+) OUT IN/OUT FM detection circuit output S meter output 40 IF2nd_IP IN 41 IF1stOUT OUT 42 VDD_IF POWER 43 IF1st_IN IN 1st IF amplifier signal input (-) IN 1st IF amplifier signal input (+) 44 IF1st_IP 45 VDD_AGC 46 FMAGC POWER OUT 1st IF amplifier signal output IF block power Pin diode AGC circuit power FM pin diode driver output 47 CAGC IN/OUT AGC circuit smoothing capacitor connection 2 48 LNAAGC IN/OUT AGC circuit smoothing capacitor connection 1 No.A1337-5/18 LC01700PW Communications Specifications Communications specifications are shown below : Serial Interface(I2C-bus) ; Serial interface (I2C-bus) Send/receive is made via I2C-bus that consists of two bus lines, each being a serial • data • line (SDA) and serial • clock • line (SCL). This bus enables 8-bit bi-directional serial data transmission at maximum 400kbit/s (fast mode). This is not compatible with the Hs mode. 1. Terms used in I2C The following terms are used in I2C. Terms Transmitter Receiver Description Device to send data to the bus Device to receive data from the bus Master Device to start data transmission, to generate the clock signal, and to end data transmission Slave Device whose address is designated by the master 2. "Start" and "Stop" conditions "Start" condition must be satisfied at start of data communications and "Stop" condition must be satisfied at end of communications. The condition in which the SDA line changes from "H" to "L" with SCL at "H" is called the "Start" line. The condition in which the SDA line changes from "L" to "H" with SCL at "H" is called the "Stop" condition. SDA SDA SCL SCL S P START condition STOP condition No.A1337-6/18 LC01700PW 3. Data transmission The length of each byte output to the SDA line is always 8 bits. An acknowledge bit is always necessary after each byte, Data is transmitted sequentially from the most significant bit (MSB). During data transfer, the slave address is transmitted after the "Start" condition (S). Data transfer is always ended by the "Stop" condition (P) generated by the master. ACK ; acknowledgement ACK signal from slsave ACK signal from receiver P SDA D7 D6 D1 D0 Mostsignificant bit of MSB Sr byte complete, interrupt within slave clock line held low while interrupts are serviced SCL S or Sr 1 2 START or repeated START condition 7 8 9 1 clock pulse for ACK 2 3-8 9 clock pulse for ACK Sr or P STOP or repeated START condition 4. Acknowledge (Confirmation of reception) When the master generates the acknowledge clock pulse, the transmitter opens the SDA line (SDA line entering the "H" state). When the acknowledge clock pulse is in the "H" state, the receiver sets the SDA line to "L" each time it receives one byte (eight bits) of data. When the master functions as receiver, the master informs the end of data to the slave by omitting acknowledgement at the end of data sent from the slave. Release the SDA line(HIGH) Dataoutput by Transmitter NACK(master is reciever) Dataoutput by Receiver ACK(master is transmitter) SCL from Master 1 2 8 9 S START condition ACK ; acknowledgement NACK ; not acknowledgement clock pulse for ACK No.A1337-7/18 LC01700PW 5. Software reset After power ON, enter the signal as follows to avoid malfunction. If the communication is interrupted (microcomputer reset, etc.), entry of the following signal enables normal operation. SDA SCL S 1 2 7 8 START condition 9 Sr P reperted START condition STOP condition 6. Electrical Specification and Timing for I/O Stages t2 t1 SDA t4 t2 t7 t9 t1 SCL t10 t5 t6 t3 t8 START condition STOP condition Bus line characteristics For FAST-MODE Parameter Symbol unit SCL = 100kHz min max fSCL - 400 kHz 100 SDA, SCL fall time t1 20+0.1Cb 300 ns - SDA, SCL rise time t2 20+0.1Cb 300 ns - SCL "H" time t3 0.6 - µs 3 SCL clock frequency (Example) SCL "L" time t4 1.3 - µs 7 "Start" condition hold time t5 0.6 - µs 10 Data hold time For I2C bus device t6 0.3 - µs - Data setup time t7 0.1 - µs 3 "Stop" condition setup time t8 0.6 - µs 10 "Stop"-"Start" bus free time t9 1.3 - µs 20 "Start" condition setup time t10 0.6 - µs - Bus line capacitive load Cb - 400 pF - No.A1337-8/18 LC01700PW 7. Definition of each bit in one byte 7-1. Slave address The slave address consists of a fixed seven-bit address "1110010" uniqueto the chip and the eighth bit or a data direction bit (R/W) : Send (Write) when this bit is "0" and Receive (Read) when this bit is "1". LSB MSB 1 1 1 0 0 1 0 R/W Fixed address R/W BIT READ 1 WRITE 0 7-2. Register address Since the total number of internal registers is 16, 4-bit data set on the MSB side becomes invalid. LSB MSB 0 0 0 0 A3 Invalid address A2 A1 A0 Valid address 7-3. Register data Each register data consists of eight bits. LSB MSB D7 D6 D5 D4 D3 D2 D1 D0 No.A1337-9/18 LC01700PW 8. Command Format 8-1. Individual register • data writing Write S SDA 1 1 1 START condition 0 0 1 0 Invalid address 0 Slave address 0 0 0 ACK 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Register data 0 0 0 1/0 1/0 1/0 1/0 Register address 0 ACK P ACK STOP condition From master to slave From slave to master 8-2. Individual register • data reading Write SDA S 1 1 START condition 1 0 0 1 0 0 Slave address Invalid address 0 0 0 0 0 1/0 1/0 1/0 1/0 0 ACK Register address ACK 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1 ACK Register address Read Sr 1 1 Repeated START condition 1 0 0 1 Slave address From master to slave 0 1 P NACK STOP condition From slave to master No.A1337-10/18 LC01700PW 8-3. Consecutive register • data writing Write SDA S 1 1 1 START condition 0 0 1 0 0 Slave address Invalid address 0 0 0 ACK 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Register data (of Register address) 0 0 0 1/0 1/0 1/0 1/0 0 Register address 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 ACK 0 ACK Register data (of Register address+1) ACK 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 P Register data (of Register address+2) ACK Register data (of Register address+n) ACK STOP condition From master to slave From slave to master Continuous data transmission after transmission of initially-set address data of register • data writing sequence enables writing of data in the consecutive register • data area. In this case, the register • address increases by one address from the initially-set address of the sequence and continues increasing till the "Stop" condition (P) is generated. 8-4. Consecutive register • data reading Invalid address Write SDA S 1 1 START condition 1 0 0 1 0 0 Slave address 0 0 0 0 0 1/0 1/0 1/0 1/0 0 ACK Register address ACK 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 Slave address ACK Register data (of Register address) ACK 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 Read Sr 1 1 Repeated START condition 0 1 0 0 1 0 1 1 P ACK Register data (of Register address+1) ACK Register data (of Register address+n) NACK STOP condition From master to slave From slave to master When the master returns ACK (0 data) after reading of the initial register • address • data of read sequence, the register • address increases by one address, enabling consecutive reading of data corresponding to each register address. If the master does not return ACK (0 data), the register address does not increase. No.A1337-11/18 LC01700PW Register Map <writing> Register address 0 Bit Name 7 PE 6 SWSTD 5 * Register value : Decimal notation Functions Power enable (all blocks) 0:OFF LOBIAS Selection of digital signal monitor pin output 0:RSTDET 4:IFCNT_CLK 5:RSSI_CLK 6:PROCNTR 7:REFCNTR Oscillation level adjustment value 1:ON /reset detection output 4 3 Default Bit operation 1:SD 2:LDO 1 3:KAGC 1 0 0:Oscillation level small 2 1 0 1 7 15:Oscillation level large SDREG LO/DX changeover (seek determination level 25 15:10dBµV adjustment) 6 5 *1dB STEP 4 3 55:50dBµV 2 2 (As for value reference value) 1 CTE 2ndIF count measurement start control 0:OFF 1:ON (automatically OFF) 0 0 RSTDET Initial register writing for reset detection 0:Reset 1:Normal 1 7 PCNT PLL synthesizer program data 0:LSB 6 5 4 3 2 PCNT = Receiver frequency + 1stl frequency (upperlocal setting) 50kHz PCNT = Receiver frequency + 1stl frequency (lowerlocal setting) 50kHz 1 0 3 7 6 5 4 3 2 1 0 4 7 GT 2ndIF count time selection 6 0:4ms 1:8ms 2:32ms 3:64ms 0:10.95MHz 1:11.25MHz 4 2:14.55MHz 3:14.75MHz 3 4:21.15MHz 5:21.45MHz 5 2 CSEL FSEL PLL master clock signal selection PLL comparative frequency setting 0:50kHz 0 2 0 1 0 5 7 RSEL PLL REF reference frequency selection 0:50kHz 0 6 ADCLK RSSIADC clock frequency changeover 0:800kHz 0 5 DZSEL Dead zone adjustment 0:0ns 1:2ns 2:10ns 3:20ns 4 3 2 CI ChargePump output current setting 0:0µA 0 1 *10µA STEP 1 0 15:150µA Continued on next page. No.A1337-12/18 LC01700PW Continued from preceding page. Register address 6 Bit * Register value : Decimal notation Name Functions 7 value 0:Fixing 0 6 PEVCO Power enable (VCO) 0:OFF 1:ON 1 5 BGRTEST BGR (RFAGC circuit) inspection mode changeover 0:OFF 1:ON 0 SMTREG Softmute start point adjustment 4 3 2 0:Fixing 0 0:Softmute function OFF 10 1:-4dBµV 1 7 (As for value reference value) RSSIGAIN RSSI detection sensitivity adjustment 6 0:31mV/dB *RSSI output gradient *1mV/dB STEP 4 7:38mV/dB 5 4 *2dB STEP 15:24dBµV 0 7 Default Bit operation (As for value reference value) RSSITMP 3 RSSI detection temperature characteristics adjustment 0:4dB *Front-end circuit temperature characteristics compensation 3 *0.5dB STEP 7:7.5dB 2 (As for value reference value) 1 0:Fixing 0 0 8 7 WAGC W_AGC sensitivity adjustment 0:Sensitivity low *1.1dB STEP 15 6 5 4 3 15:Sensitivity high NAGC N_AGC sensitivity adjustment 0:Sensitivity low KAGC Keyed-AGC judgment level adjustment 0:-3dBµV 6 *1.1dB STEP 2 1 0 9 7 15:Sensitivity high 6 5 15:27dBµV 4 10 (As for value reference value) 3 WAGCSW W_AGC_ON/OFF 0:OFF 1:ON 1 2 NAGCSW N_AGC_ON/OFF 0:OFF 1:ON 1 1 ATTAGCSW ATT_AGC_ON/OFF 0:OFF 1:ON 1 0 LNAAGCSW LNA_AGC_ON/OFF 0:OFF 1:ON 1 7 KAGCSW Keyed-AGC_ON/OFF 0:OFF 1:ON 0 6 WKAGCSW Keyed-W_AGC sensitivity changeover 0:No sensitivity change 1:-10dB sensitivity change 0 5 LNAG LNA gain adjustment 0:17dB 1:19dB 3 2:21dB 3:23dB 4 3 MIXG 1stMIX gain adjustment 3 0:-0.2dB 1:2.8dB 2:4.5dB 3:5.4dB 0:7dB 1:10dB 0 2:13dB 3:16dB 7 0:Fixing 0 0:oscillation allowance, small 0 2 1 11 6 *2dB STEP IFAG 1stIFA gain adjustment 3 6 5 4 XOSCADJ Crystal oscillation level adjustment 3 2 7:oscillation allowance, large 1 0:Fixing 0 0 0:Fixing 0 Continued on next page. No.A1337-13/18 LC01700PW Continued from preceding page. Register address 12 * Register value : Decimal notation Bit Name Functions 7 RMXG Composite output level adjustment DEMODR Detection output level adjustment Default Bit operation value 0:3.1dB 1:3.7dB 2:4.4dB 3:5.2dB 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 0 6 5 4 3 0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 2 13 14 7 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms (As for value reference value) 1 PERF Power enable (RF block) 0:OFF 1:ON 1 0 PEIF Power enable (IF block) 0:OFF 1:ON 1 7 PEDEM Power enable (LIM/DEMOD) 0:OFF 1:ON 1 6 PEAMP Power enable (audio amplifier) 0:OFF 1:ON 1 5 PEXOSC Power enable (XOSC) 0:OFF 1:ON 1 4 PELNA Power enable (LNA) 0:OFF 1:ON 1 3 PELO1 Power enable (LO block_VCOetc) 0:OFF 1:ON 1 2 PELO2 Power enable (LO block_LOBUFetc) 0:OFF 1:ON 1 1 PEREFCNT Power enable (REF counter) 0:OFF 1:ON 1 0 PERFAGC Power enable (RFAGC block) 0:OFF 1:ON 1 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 No.A1337-14/18 LC01700PW Register Map <reading> Register address 0 Bit Name 7 PE 6 SWSTD 5 * Register value : Decimal notation Functions Power enable (all blocks) 0:OFF LOBIAS Selection of digital signal monitor pin output 0:RSTDET 4:IFCNT_CLK 5:RSSI_CLK 6:PROCNTR 7:REFCNTR GM adjustment of the oscillation circuit core block value 1:ON /reset detection output 4 3 Default Bit operation 1:SD 2:LDO 1 3:KAGC 1 0 0:Oscillation level small 2 1 0 1 7 15:Oscillation level large SDREG LO/DX changeover (seek determination level 25 15:10dBµV adjustment) 6 5 *1dB STEP 4 3 55:50dBµV 2 2 (As for value reference value) 1 CTE 2ndIF count measurement start control 0:OFF 1:ON (automatically OFF) 0 0 RSTDET Initial register writing for reset detection 0:Reset 1:Normal 1 7 IFCOUT 2ndIF count value output 0:LSB 6 5 4 3 2ndIF frequency = 2 1 IFCOUT value (2ndIF count value) GT 0 3 7 6 5 4 3 2 1 0 4 7 GT 2ndIF count time selection 6 0:4ms 1:8ms 2:32ms 3:64ms 0:10.95MHz 1:11.25MHz 4 2:14.55MHz 3:14.75MHz 3 4:21.15MHz 5:21.45MHz 5 2 CSEL FSEL PLL master clock signal selection PLL comparative frequency setting 0:50kHz 0 2 0 1 0 5 7 RSEL PLL REF reference frequency selection 0:50kHz 0 6 ADCLK RSSIADC clock frequency changeover 0:800kHz 0 5 DZSEL Dead zone adjustment 0:0ns 1:2ns 2:10ns 3:20ns 4 3 2 CI ChargePump output current setting 0:0µA 0 1 *10µA STEP 1 0 15:150µA Continued on next page. No.A1337-15/18 LC01700PW Continued from preceding page. Register address 6 Bit * Register value : Decimal notation Name Functions 7 value 0:Fixing 0 6 PEVCO Power enable (VCO) 0:OFF 1:ON 1 5 BGRTEST BGR(RFAGC circuit) inspection mode changeover 0:OFF 1:ON 0 SMTREG Softmute start point adjustment 4 3 2 0:Fixing 0 0:Softmute function OFF 10 1:-4dBµV 1 7 (As for value reference value) RSSIGAIN RSSI detection sensitivity adjustment 6 0:31mV/dB *RSSI output gradient *1mV/dB STEP 4 7:38mV/dB 5 4 *2dB STEP 15:24dBµV 0 7 Default Bit operation (As for value reference value) RSSITMP 3 RSSI detection temperature characteristics adjustment 0:4dB *Front-end circuit temperature characteristics compensation 3 *0.5dB STEP 7:7.5dB 2 (As for value reference value) 1 0:Fixing 0 0 8 7 WAGC W_AGC sensitivity adjustment 0:Sensitivity low *1.1dB STEP 15 6 5 4 3 15:Sensitivity high NAGC N_AGC sensitivity adjustment 0:Sensitivity low KAGC Keyed-AGC judgment level adjustment 0:-3dBµV 6 *1.1dB STEP 2 1 0 9 7 15:Sensitivity high 6 5 15:27dBµV 4 10 (As for value reference value) 3 WAGCSW W_AGC_ON/OFF 0:OFF 1:ON 1 2 NAGCSW N_AGC_ON/OFF 0:OFF 1:ON 1 1 ATTAGCSW ATT_AGC_ON/OFF 0:OFF 1:ON 1 0 LNAAGCSW LNA_AGC_ON/OFF 0:OFF 1:ON 1 7 KAGCSW Keyed-AGC_ON/OFF 0:OFF 1:ON 0 6 WKAGCSW Keyed-W_AGC sensitivity changeover 0:No sensitivity change 1:-10dB sensitivity change 0 5 LNAG LNA gain adjustment 0:17dB 1:19dB 3 2:21dB 3:23dB 4 3 MIXG 1stMIX gain adjustment 3 0:0dB 1:2dB 2:4dB 3:6dB 0:7dB 1:10dB 0 2:13dB 3:16dB 7 0:Fixing 0 0:oscillation allowance, small 0 2 1 11 6 *2dB STEP IFAG 1stIFA gain adjustment 3 6 5 4 XOSCADJ Crystal oscillation level adjustment 3 2 7:Oscillation allowance, larg 1 0:Fixing 0 0 0:Fixing 0 Continued on next page. No.A1337-16/18 LC01700PW Continued from preceding page. Register address 12 * Register value : Decimal notation Bit Name Functions 7 RMXG Composite output level adjustment DEMODR Detection output level adjustment Default Bit operation value 0:3.1dB 1:3.7dB 2:4.4dB 3:5.2dB 4:6.0dB 5:6.9dB 6:8.0dB 9:9.1dB 0 6 5 4 3 0:106mVrm 1:119mVrms 2:151mVrms 3:167mVrms 2 13 14 7 4:212mVrm 5:230mVrms 6:276mVrms 7:297mVrms (As for value reference value) 1 PERF Power enable (RF block) 0:OFF 1:ON 1 0 PEIF Power enable (IF block) 0:OFF 1:ON 1 7 PEDEM Power enable (LIM/DEMOD) 0:OFF 1:ON 1 6 PEAMP Power enable (audio amplifier) 0:OFF 1:ON 1 5 PEXOSC Power enable (XOSC) 0:OFF 1:ON 1 4 PELNA Power enable (LNA) 0:OFF 1:ON 1 3 PELO1 Power enable (LO block_VCOetc) 0:OFF 1:ON 1 2 PELO2 Power enable (LO block_LOBUFetc) 0:OFF 1:ON 1 1 PEREFCNT Power enable (REF counter) 0:OFF 1:ON 1 0 PERFAGC Power enable (RFAGC block) 0:OFF 1:ON 1 7 WAGCOUT W_AGC output 0:LSB Soft mute changeover control signal output 0:LSB RSSI digital output 0:LSB 6 5 4 3 SMTSWOUT 2 1 0 15 7 RSSIOUT 6 5 4 3 2 1 0 No.A1337-17/18 LC01700PW SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2008. Specifications and information herein are subject to change without notice. PS No.A1337-18/18