DATA SHEET PRELIMINARY DATA SHEET BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT µPB1005K REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER DESCRIPTION The µPB1005K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip. The µPB1005K features 36-pin plastic QFN, fixed prescaler and supply voltage. The 36-pin plastic QFN package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the µPB1005K can make RF block fewer components and lower power consumption. This IC is manufactured using NEC’s 20 GHz fT NESATTMIII silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability. FEATURES • Double conversion : fREFin = 16.368 MHz, f2ndIFout = 4.092 MHz • Integrated RF block : RF/IF frequency down-converter + PLL frequency synthesizer • High-density surface mountable : 36-pin plastic QFN (6.0 × 6.0 × 0.95 mm) • Needless to input counter data : fixed division internal prescaler • VCO side division : ÷ 200 (÷ 25, ÷ 8 serial prescaler) • Reference division : ÷2 : VCC = 2.7 to 3.3 V • Supply voltage • Low current consumption : ICC = 45.0 mA TYP.@VCC = 3.0 V • Gain adjustable externally : Gain control voltage pin (control voltage up vs. gain down) APPLICATION • Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz ORDERING INFORMATION Part Number µPB1005K-E1 Remark Package 36-pin plastic QFN Supplying Form Embossed tape 12 mm wide. Pin 1 is in pull-out direction. Qty 2.5 kp/reel. To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: µPB1005K) Caution Electro-static sensitive device The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P14016EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan © 1999 µPB1005K GND (2ndIF-AMP) 2ndIFin1 2ndIFin2 2ndIFbypass VCC (2ndIF-AMP) 2ndIFout N.C. REFout VCC (reference block) PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 27 26 25 24 23 22 21 20 19 IF-MIXout 28 18 N.C. N.C. 29 17 REFin VGC (IF-MIX) 30 ÷2 16 N.C. GND 15 (divider block) VCC (IF-MIX) 31 ÷8 N.C. 32 14 LOout ÷25 IF-MIXin 33 VCC 13 (divider block) PD GND 12 (Phase detector) GND 34 (IF-MIX) 2 3 4 5 6 7 8 9 GND (1stLO-OSC) VCC (phase detector) N.C. PD-Vout3 2 1stLO-OSC2 1 1stLO-OSC1 10 PD-Vout2 VCC (1stLO-OSC) VCC 36 (RF-MIX) GND (RF-MIXin) 11 PD-Vout1 RF-MIXin RF-MIXout 35 Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K PRODUCT LINE-UP (TA = +25 °C, VCC = 3.0 V) Type Functions (Frequency unit: MHz) Part Number General Purpose Wideband Separate IC µPC2756T VCC (V) RF down-converter with osc. Tr 2.7 to 3.3 ICC (mA) CG (dB) 6.0 14 Package Status Available 6-pin minimold µPC2756TB 6-pin super minimold µPC2753GR IF down-converter with gain control amplifier 2.7 to 3.3 6.5 60 to 79 20-pin plastic SSOP (225 mil) Clock µPB1003GS Frequency Specific 1 chip IC RF/IF down-converter + PLL synthesizer REF = 18.414 1stIF = 28.644/2ndIF = 1.023 2.7 to 3.3 37.5 72 to 92 30-pin plastic SSOP (300 mil) µPB1004GS RF/IF down-converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 37.5 72 to 92 2.7 to 3.3 45.0 72 to 92 µPB1005GS µPB1005K Notice Discontinued Available 36-pin plastic QFN Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. To know the associated products, please refer to their latest data sheets. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram • f0 = 1.023 MHz in the diagram. 60f0 RF-MIXout 1575.42 MHz from Antenna LNA 1540f0 • µ PB1005K is in 40f0 BPF IF-MIXin LPF IF-MIXout VGC 2ndlF-Amp IF-MIX RF-MIX 4.092 MHz 4f0 1540f0 e.g. µ PC2749TB . 2ndlFin1 2ndlFin2 2ndlFbypass Buff to Demodulator BPF 64f0 8f0 1/25 1/8 PD 16f0 1/2 1600f0 16.368 MHz Buff to Demodulator REF OSC LOOP 8f0 AMP 1stLO-OSC1 1stLO-OSC2 16f0 LOOUT VCC TCXO 16.368 MHz Caution This diagram schematically shows only the µPB1005K’s internal functions on the system. This diagram does not present the actual application circuits. Preliminary Data Sheet P14016EJ1V0DS00 3 µPB1005K ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating Unit Supply Voltage VCC TA = +25 °C 3.6 V Total Circuit Current ICC TA = +25 °C 120 mA Power Dissipation PD Mounted on double-sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB (TA = +85 °C) 430 mW Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −55 to +150 °C RECOMMENDED OPERATING RANGE Parameter 4 Symbol MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA −40 +25 +85 °C RF Input Frequency fRFin 1575.42 MHz 1st LO Oscillating Frequency f1stLOin 1616.80 1636.80 1656.80 MHz 1st IF Input Frequency f1stIFin 61.38 MHz 2nd LO Input Frequency f2ndLOin 65.472 MHz 2nd IF Input/output Frequency f2ndIFin f2ndIFout 4.092 MHz Reference Input/output Frequency fREFin fREFout 16.368 MHz LO Output Frequency fLOout 8.184 MHz Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 °C, VCC = 3.0 V) Parameter Total Circuit Current Symbol ICCtotal Conditions ICC1 + ICC2 + ICC3 + ICC4 MIN. TYP. MAX. Unit 32.0 45.0 60.0 mA RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = −10 dBm, ZS = ZL = 50 Ω) Circuit Current 1 ICC1 No Signals 6.0 10.0 14.0 mA RF Conversion Gain CGRF PRFin = −40 dBm 12.5 15.5 18.5 dB RF-SSB Noise Figure NFRF PRFin = −40 dBm 7.0 10.0 13.0 dB PO(sat)RF PRFin = −10 dBm −5.5 −2.5 +0.5 dBm Maximum IF Output IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 Ω, ZL = 2 kΩ) Circuit Current 2 IF Conversion Voltage Gain IF-SSB Noise Figure Maximum 2ndIF Output ICC2 No Signals 3.4 5.3 7.2 mA CG(GV)IF at Maximum Gain, P1stIFin = −50 dBm 38 41 44 dB NFIF at Maximum Gain, P1stIFin = −50 dBm 8.5 11.5 14.5 dB PO(sat)IF at Maximum Gain, P1stIFin = −20 dBm −9.5 −6.5 −3.5 dBm Gain Control Voltage VGC Voltage at Maximum Gain CGIF 1.0 V Gain Control Range DGC P1stIFin = −50 dBm 20 dB 1.55 2.40 3.25 mA 2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 Ω, ZL = 2 kΩ) Circuit Current 3 ICC3 No Signals Voltage Gain GV P2ndIFin = −60 dBm 37 40 43 dB Output Power P2ndIFout P2ndIFin = −30 dBm −14.5 −11.5 −8.5 dBm PLL All Block Operating 18.5 28.5 38.5 mA PLL Loop 8.0 8.184 8.4 MHz 200 mVP-P 2.8 V 0.4 V 1.0 VP-P PLL Synthesizer Block Circuit Current 4 Phase Comparing Frequency ICC4 fPD Reference Input Minimum Level VREFin Loop Filter Output Level (H) VLP(H) Loop Filter Output Level (L) VLP(L) Reference Output Swing VREFout ZL = 10 kΩ//20 pF ZL = 10 kΩ//2 pF Note Note Note Impedance of measurement equipment Preliminary Data Sheet P14016EJ1V0DS00 5 µPB1005K STANDARD CHARACTERISTICS (Unless otherwise specified TA = +25 °C, VCC = 3.0 V) Parameter Symbol Conditions Reference Unit RF Down-converter Block (P1stLOin = −10 dBm, ZS = ZL = 50 Ω) LO Leakage to IF Pin LOif f1stLOin = 1 636.80 MHz −30 dBm LO Leakage to RF Pin LOrf f1stLOin = 1 636.80 MHz −30 dBm fRFin1 = 1 600 MHz, fRFin2 = 1605 MHz f1stLOin = 1 660 MHz −13 dBm Input 3rd Order Intercept Point IIP3RF IF Down-converter Block (1st LO oscillating, ZS = 50 Ω, ZL = 2 kΩ) LO Leakage to 2nd IF LO2ndif f2ndLOin = 65.472 MHz −20 dBm LO Leakage to 1st IF LO1stif f2ndLOin = 65.472 MHz −40 dBm Input 3rd Order Intercept Point IIP3IF f1stIFin1 = 61.38 MHz, f1stIFIn2 = 61.48 MHz f2ndLOin = 65.472 MHz −34 dBm PLL Loop, ∆1kHz of VCO wave −78 dBc/Hz VCO Block Phase Noise 6 C/N Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K PIN EXPLANATION Pin No. 35 36 1 Pin Name RX-MIXout VCC (RF-MIX) RF-MIXin Applied Voltage (V) Pin Voltage (V) 1.68 2.7 to 3.3 Function and Application Output pin of RF mixer. 1st IF filter must be inserted between pin 33 & 35. Supply voltage pin of RF mixer block. This pin must be decoupled with capacitor (example: 1 000 pF). 1.20 Ground pin RF mixer. VCC (1stLO-OSC) 2.7 to 3.3 Supply voltage pin of differential amplifier for 1st LO oscillator circuit. 4 1stLO-OSC1 1.88 5 1stLO-OSC2 1.88 6 GND (1stLO-OSC) 0 GND (RF-MIX) 3 7 VCC (phase Pin 4 & 5 are each base pin of differential amplifier for 1st LO oscillator. These pins should be equipped with LC and varactor to oscillate on 1 636.80 MHz as VCO. Ground pin of differential amplifier for 1st LO oscillator circuit. 2.7 to 3.3 Supply voltage pin of phase detector and active loop filter. Non connection Pins of active loop filter for tuning voltage output. The active transistors configured with darlington pair are built on chip. Pin 11 should be pulled down with external resistor. Pin 9 to 10 should be equipped with external RC in order to adjust dumping factor and cutoff frequency. This tuning voltage output must be connected to varactor diode of 1st LO-OSC. detector) 8 N.C. 9 PD-Vout3 10 PD-Vout2 11 12 PD-Vout1 GND (phase detector) Pull-up with resistor Pull-up with resistor 0 Output in accordance with phase difference 36 1stLO -OSC 35 1 Input pin of RF mixer. 1 575.42 MHz band pass filter can be inserted between pin 1 and external LNA. 0 2 Internal Equivalent Circuit 2 3 VCC RF-MIX or Prescaler input 4 5 6 7 10 PD 12 9 11 Ground pin of phase detector + active loop filter. Preliminary Data Sheet P14016EJ1V0DS00 7 µPB1005K Pin No. 13 Pin Name VCC (divider block) Applied Voltage (V) Pin Voltage (V) 2.7 to 3.3 Function and Application Supply voltage pin of prescalers. 13 Monitor pin of comparison frequency at phase detector. 1st LO OSC 15 14 LOout 2.08 15 GND (divider block) 0 Ground pin of prescalers + LOout amplifier Non connection 16 N.C. 17 REFin 1.96 18 19 N.C. VCC (reference block) Internal Equivalent Circuit Input pin of reference frequency. This pin should be equipped with external 16.368 MHz oscillator (example: TCXO). Non connection 2.7 to 3.3 Supply voltage pin of input/output amplifiers in reference block. IF MIX ÷25 PD ÷8 PD 14 ÷2 Ref. 19 20 17 PD 20 REFout 1.65 21 N.C. 22 2ndIFout 1.56 Output pin of reference frequency. The frequency from pin 17 can be took out as 1 VP-P swing. 15 Non connection Output pin of 2nd IF amplifier. This pin output 4.092 MHz clipped sinewave. This pin should be equipped with external inverter to adjust level to next stage on user’s system. 23 VCC (2ndIF-AMP) 2.7 to 3.3 24 2ndIF bypass 2.30 Bypass pin of 2nd IF amplifier input 1. This pin should be grounded through capacitor. 25 2ndIFin2 2.35 Pin of 2nd IF amplifier input 2. This pin should be grounded through capacitor. 26 2ndIFin1 2.35 Pin of 2nd IF amplifier input 1. 2nd IF filter can be inserted between pin 26 & 28. 27 GND (2ndIF-AMP) 0 Ground pin of 2nd IF amplifier. Supply voltage pin of 2nd IF amplifier. 23 24 26 8 Preliminary Data Sheet P14016EJ1V0DS00 25 27 22 µPB1005K Pin No. 28 Pin Name IF-MIXout 29 N.C. 30 VGC (IF-MIX) Applied Voltage (V) Pin Voltage (V) 1.15 Function and Application Output pin from IF mixer. IF mixer output signal goes through gain control amplifier before this emitter follower output port. Non connection 0 to 3.3 Gain control voltage pin of IF mixer output amplifier. This voltage performs forward control (VGC up → Gain down). 2.7 to 3.3 Supply voltage pin of IF mixer, gain control amplifier and emitter follower transistor. N.C. Non connection 33 IF-MIXin 2.00 34 GND (IF-MIX) 0 31 VCC (IF-MIX) 32 Caution Internal Equivalent Circuit 30 31 33 2nd LO 28 34 Input pin of IF mixer. Ground pin of IF mixer. Ground pattern on the board must be formed as wide as possible to minimize ground impedance. Preliminary Data Sheet P14016EJ1V0DS00 9 µPB1005K TEST CIRCUIT 50 Ω Spectrum Analyzer VCC C17 Signal Generator C20 27 Osilloscope VCC C19 26 R5 C16 C15 C18 25 24 23 22 21 C14 20 19 R6 C21 Spectrum Analyzer To get maximum gain. Apply 1.0V MAX. VCC C22 28 18 29 17 ÷2 30 15 ÷8 32 33 Osilloscope 14 C12 ÷25 C1 50 Ω Signal Generator 16 31 C23 50 Ω C13 13 C11 VCC PD Signal Generator Spectrum Analyzer 34 12 35 11 36 10 C2 VCC C3 1 50 Ω 2 3 C4 4 5 C6 6 V-Di C7 C8 L R2 7 8 9 R3 VCC C10 R4 Signal Generator VCC C5 R1 C9 Spectrum Analyzer : measure frequency Oscilloscope : measure output voltage swing Component List Form Chip capacitor Chip resistor Varactor Diode Chip Inductor 10 Symbol Value C1 to C5, C8, C11 to C15, C17, C18, C22 1 000 pF C6, C7 24 pF (UJ) C9 1800 pF C10 33 nF C19 10 000 pF C23 1 µF C16, C20 0.1 µF C21 0.01 µF R1, R2 4.7 kΩ R3 6.2 kΩ R4 1.2 kΩ R5, R6 1.95 kΩ V-Di 1SV285 L 3.9 nH Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K PACKAGE DIMENSIONS 36 PIN PLASTIC QFN (UNIT: mm) 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2 6.2±0.2 6.0±0.2 4–C0.5 Pin36 Pin1 6.2±0.2 6.0±0.2 0.6±0.1 1.0MAX 0.22±0.05 0.5±0.025 Bottom View Preliminary Data Sheet P14016EJ1V0DS00 11 µPB1005K NOTE ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor (example: 1 000 pF) to the VCC pin. (5) Frequency signal input/output pins must be each coupled with external capacitor for DC cut. RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared Reflow Package peak temperature: 235 °C or below Time: 30 seconds or less (at 210 °C) Note Count: 2, Exposure limit : None IR35-00-2 Partial Heating Pin temperature: 300 °C Time: 3 seconds or less (per side of device) Note Exposure limit : None – Note After opening the dry pack, keep it in a place below 25 °C and 65 % RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 12 Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K [MEMO] Preliminary Data Sheet P14016EJ1V0DS00 13 µPB1005K [MEMO] 14 Preliminary Data Sheet P14016EJ1V0DS00 µPB1005K [MEMO] Preliminary Data Sheet P14016EJ1V0DS00 15 µPB1005K ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8