Edge629 1 GHz Timing Deskew and Quad Fanout Element TEST AND MEASUREMENT PRODUCTS Description Featur es The Edge629 is a monolithic timing delay and signal fanout solution manufactured in a high-performance bipolar process. In Automatic Test Equipment (ATE) applications, the Edge629 buffers, distributes, and aligns timing signals across multiple channels (typically found inside Memory Test Systems). It is also suitable for per pin deskew in Logic Testers. • • • • • • • Fmax ≥ 1 GHz Independent Falling Edge Adjust Small Footprint (10 mm x 10 mm) Excellent Timing Accuracy Very Stable Timing Delays 5 ps Resolution ECL, CMOS Compatible Inputs The Edge629 supports: • Minimum pulse width = 330 ps with Falling Edge Adjust disabled, 500 ps with Falling Edge Adjust enabled • Net usable delay span ≥ 4.0 ns • Falling Edge Adjust ± 250 ps • On Board DACs to generate 5 ps resolution With a maximum operating frequency of 1 GHz, the Edge629 is optimized for extremely high speed, high accuracy testers, particularly those aimed to test memory devices. Functional Block Diagram The Edge629 solves several difficult problems associated with aligning multiple timing signals because it can: • delay very narrow pulses over a long timing span • adjust the falling edge independently from the overall propagation delay • maintain extreme timing accuracy for very narrow (sub-ns) pulses • maintain tight timing accuracy over changes in frequency, duty cycle, and pattern. IN0 / IN0* ∆T– ∆T ∆T Coarse Fine ∆T ∆T Coarse Fine ∆T ∆T Coarse Fine ∆T ∆T Coarse Fine OUT0 / OUT0* IN / IN* IN1/ IN1* ∆T– OUT1 / OUT1* IN2 / IN2* ∆T– Applications • • • IN3 / IN3* Memory Test Equipment – Data Fanout – Channel Deskew Logic Testers – Per Pin Deskew Clock / Signal Fanout Revision 3 / August 1, 2005 OUT2 / OUT2* ∆T– OUT3 / OUT3* SEL / SEL* 1 www .semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS PIN Description Pin Name Pin # Description IN/IN* 9, 8 Differential input signal used for 1:4 signal fanout. IN0, IN0* IN1/IN1* IN2/IN2* IN3/IN3* 15, 16 11, 12 6, 5 2, 1 Differential input signals used for 1:1 signal fanout. OUT0/OUT0* OUT1/OUT1* OUT2/OUT2* OUT3/OUT3* 33, 34 37, 38 44, 43 48, 47 Differential output signals. SEL/SEL* 22, 23 Differential input signals used to select the input signal source. SDI 58 Serial data input. CK 56 Clock used to latch in SDI. CS 59 Chip select. UPDATE 57 Digital input which loads the delay registers. CATHODE, ANODE 24, 25 Terminals of an on-chip thermal diode string. COMP0-3 20, 19, 62, 61 External op amp compensation pins. DAC_FALL_(0-3) 27, 29, 52, 54 Falling edge adjust DAC outputs. For test purposes only; nothing should be connected to these pins. DAC_FINE_(0-3) 28, 30, 51, 53 Fine delay DAC outputs. For test purposes only; nothing should be connected to these pins. VCC 3, 4, 13, 14, 26, Positive power supply. 31, 35, 36, 40, 45, 46, 50, 55 VEE 7, 10, 17, 18, 21, Negative power supply. 32, 39, 41, 42, 49, 60, 63, 64 2005 Semtech Corp. Rev. 3, 8/1/05 2 www.semtech.com Edge629 VEE3 VEE5 COMP2 COMP3 VEE5 CS SDI UPDATE CK VCC5 DAC_FALL_3 DAC_FINE_3 DAC_FALL_2 DAC_FINE_2 VCC5 VEE3 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) 64 IN3* IN3 VCC3 VCC2 IN2* IN2 VEE2 IN* IN VEE1 IN1 IN1* 49 1 OUT3 OUT3* VCC3 VCC2 OUT2 OUT2* VEE2 VEE4 VCC4 VEE1 OUT1* OUT1 E629AXF 64 Pin 10 mm x 10 mm TQFP Top View VCC1 VCC0 IN0 VCC1 VCC0 OUT0* IN0* 33 OUT0 VEE0 VEE6 COMP1 COMP0 VEE6 SEL SEL* CATHODE ANODE VCC6 DAC_FALL_0 DAC_FINE_0 DAC_FALL_1 DAC_FINE_1 VCC6 VEE0 17 2005 Semtech Corp. Rev. 3, 8/1/05 3 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description Introduction Coarse Delay The Edge629 is a quad channel delay element with 2 basic operating modes: 1) Fanout – 1 signal in, 4 signals out 2) Pass Through – 4 signals in, 4 signals out Coarse propagation delay adjustment is accomplished using a series of gate delays and multiplexers (see Figure 1). Coarse delay provides a total delay span of: 1 Coarse LSB = 90 ps 2 Coarse LSB = 180 ps 4 Coarse LSB = 360 ps 8 Coarse LSB = 720 ps 16 Coarse LSB = 1.44 ns 32 Coarse LSB = 2.88 ns 0 ns ≤ Coarse Delay Range ≤ 5.67 ns In all modes, each channel supports 3 delay functions: 1) Coarse timing delay 2) Fine timing delay 3) Falling edge adjust All 3 delay functions are independent of each other, and independent for each channel. The programming of the delay functions is done using a 16 bit register, loaded serially, which contains both a delay and an address value. Each channel has its own unique coarse delay setting and may be programmed independently from all other channels. The coarse delay of any channel will not affect the fine delay of that channel, nor will it affect the overall delay of any other channel. The propagation delay of a rising edge and falling edge will track each other over the entire coarse delay span. (Adding or subtracting coarse delay does not cause pulse width distortion.) Delay Code 000000 Minimum Delay 0.0 ns 111111 Maximum Delay 5.67 ns 90 ps 180 ps 360 ps 720 ps 1.44 ns 2.88 ns Coarse Delay Register 5 4 3 2 MSB 1 0 LSB 16 Bit Serial Register Figure 1. Coarse Delay Architecture 2005 Semtech Corp. Rev. 3, 8/1/05 4 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Fine Delay Fine Delay Select Fine delay is accomplished using an analog delay cell and an on-chip 6 bit DAC (see Figure 2). The fine delay range is designed to be ~2X the coarse delay resolution. The fine delay section may be selected or bypassed by a multiplexer (see Figure 2). If SFD (Select Fine Delay) is high, Fine Delay will be used. If SFD is low, Fine Delay will be bypassed. Fine delay provides a total delay span of: LSB 1 Fine LSB = 2.5 ps (see note) 2 Fine LSB = 5 ps 4 Fine LSB = 10 ps 8 Fine LSB = 20 ps 16 Fine LSB = 40 ps MSP 32 Fine LSB = 80 ps 0 ns ≤ Fine Delay Range ≤ 157.5 ps. Note: Because the transfer function is non-linear, some LSB steps could be as large as 5 ps. Each channel has its own unique delay setting and may be programmed independently from all other channels. The fine delay of any channel will not affect the coarse delay of that channel, nor will it affect the overall delay of any other channel. DAC Code SFD Delay XXXXXX 0 Fine Delay Bypassed 000000 1 Minimum Delay (0.0 ns) 111111 1 Maximum Delay (157 ps) Fine Delay DAC Outputs DAC_FINE_(0–3) are analog voltage outputs from the onboard DACs which program the fine delay elements of each channel. DAC_FINE_(0-3) pins are for test purposes only. Nothing should be connected to these pins. The propagation delay of a rising and falling edge will track each other over the entire span of fine delay. (Adding or subtracting fine delay will not cause pulse width distortion.) 6 Bit DAC ∆T SFD Figure 2. Fine Delay Architecture 2005 Semtech Corp. Rev. 3, 8/1/05 5 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Falling Edge Adjustment There is a limitation on FEA range vs. pulse width. The falling edge of a signal may be adjusted to compensate for any system level pulse width distortion that may occur. Falling edge adjust (FEA) is accomplished using an analog delay cell and an on-chip 7 bit DAC (see Figure 3). FEA may be bypassed completely by a multiplexer. Also, FEA affects only the propagation delay of the falling edge. It has no effect on the propagation delay of a rising edge. Each channel has its own unique FEA setting and may be programmed independently from all other channels. The FEA of any channel will not affect the propagation delay of any other channel, nor will FEA affect the propagation delay of a rising edge. SFE DAC Code Falling Edge Delay Resolution 0 XXXXXXX FEA Bypassed N/A 1 1 0000000 1111111 –250 ps +250 ps 2.5 ps 2.5 ps Input Pulse Width FEA Range 1.0 ns ±250 ps 900 ps ±250 ps 800 ps ±250 ps 700 ps ±250 ps 600 ps ±200 ps 500 ps ±100 ps Falling Edge Adjust DAC Outputs DAC_FALL_(0–3) are analog voltage outputs from the onboard DACs which program the falling edge delay elements of each channel. DAC_FALL_(0-3) pins are for test purposes only. Nothing should be connected to these pins. Thermal Monitor The Edge629 features a thermal diode string consisting of 5 diodes as shown in Figure 4 below. This string allows accurate die temperature measurements. 7 Bit DAC ANODE Bias Current ∆T Temperature Coefficient = –7.8 mV/˚C CATHODE SFE Figure 4. Thermal Diode String Figure 3. Falling Edge Adjust Architecture 2005 Semtech Corp. Rev. 3, 8/1/05 When an external bias current of up to 100 µA is injected through the string, the voltage measured across the ANODE and CATHODE pins maps directly to the Edge629 junction temperature (see Figure 5). 6 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Programming The Edge629 is programmed serially with 3 control lines: SDI – serial data input CS – chip select UPDATE – register update which are all synchronous with CK. With CS valid (high), rising edge of CK will load SDI into the 16 bit shift register. Bit 15 14 13 12 11 Addr LA A3 A2 A1 A0 0 0 0 0 0 0 X Channel 0, Coarse Delay 1 0 0 0 0 1 1 Channel 0, Fine Delay 2 0 0 0 1 0 1 Channel 0, Falling Edge Adjust 3 0 0 0 1 1 X Not Used 4 0 0 1 0 0 X Channel 1, Coarse Delay 5 0 0 1 0 1 1 Channel 1, Fine Delay 6 0 0 1 1 0 1 Channel 1, Falling Edge Adjust 7 0 0 1 1 1 X Not Used 8 0 1 0 0 0 X Channel 2, Coarse Delay 9 0 1 0 0 1 1 Channel 2, Fine Delay A 0 1 0 1 0 1 Channel 2, Falling Edge Adjust B 0 1 0 1 1 X Not Used C 0 1 1 0 0 X Channel 3, Coarse Delay D 0 1 1 0 1 1 Channel 3, Fine Delay E 0 1 1 1 0 1 Channel 3, Falling Edge Adjust F 0 1 1 1 1 X Not Used X 1 X X X X 0 All Channels, Coarse Delay X 1 X X X X 1 All Channels, All Functions With CS valid and UPDATE valid (high), CK high will make the selected latch go transparent. The falling edge of CK will then latch the data (see Figures 6 and 7). Data and address information are combined in the 16 bit word. Bits 0–6 are used for data, bits 11–15 for address. Bits 11–14 select 1 of 16 destinations, bit 15, if high, selects all 16 locations to be loaded simultaneously (useful for preloading all registers to a default state). 10 Delay Function V = Vanode – Vcathode; Vcathode = VEE 4.20 4.00 3.80 V = Vanode – Vcathode [V] 3.60 3.40 : : : 3.20 IFORCE = 100µ/Anode IFORCE = 10µ/Anode IFORCE = 1µ/Anode 3.00 2.80 2.60 2.40 2.20 0.00 50.0 100 150 Temp (˚C) Figure 5. Voltage vs. Temperature for Thermal Diode String 2005 Semtech Corp. Rev. 3, 8/1/05 7 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) 629 Digital Interface Timing 16 Bit Loads CK0 CK SDI CK15 ... ... CD0 CD1 CD2 CD3 CD4 A0 CD5 A1 A2 A3 LA Coarse Delay Update Load All SDI FD0 FD1 FD2 FD3 FD4 SFD FD5 A0 A1 A2 A3 Fine Delay Update LA Load All SDI FE0 FE1 FE2 FE3 FE4 FE5 SFE FE6 A0 A1 A2 A3 LA Falling Edge Adjust Update Load All CS UPDATE Update Selected Delay Register Figure 6. Synchronous Loading 2005 Semtech Corp. Rev. 3, 8/1/05 8 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Coarse Delay MSB 0 5 LSB 4 3 2 1 0 Fine Delay SFD 1 Channel 0 MSB 10 5 LSB 4 3 2 1 0 Falling Edge Adjust 2 MSB SFE 10 Channel 1 Channel 2 .. . .. . .. . .. . 6 5 LSB 4 3 2 1 0 .. . .. . Coarse Delay MSB C 5 LSB 4 3 2 1 0 Fine Delay Channel 3 SFD D MSB 10 5 LSB 4 3 2 1 0 Falling Edge Adjust E SFE 10 MSB 6 5 LSB 4 3 2 1 0 UPDATE CS LA A3 A2 A1 A0 CK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDI Address Figure 7. Data Interface 2005 Semtech Corp. Rev. 3, 8/1/05 9 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Timing Inputs Data Interface Digital Inputs IN/IN* and IN0/IN0* – IN3/IN3* are high speed differential inputs which require >300 mV of differential input voltage for reliable switching. All data digital inputs are standard, single ended ECL inputs with Vbb = –1.3V relative to VCC. However, all digital inputs may receive input signals anywhere between VCC and VEE. This wide input voltage compliance allows CMOS signals to program the Edge629 without causing saturation problems. These inputs may receive differential input signals with amplitudes up to 3.3V. This wide range input voltage compliance allows CMOS signals to drive the Edge629 directly. The inputs may go all the way up to VCC and still not cause any saturation. The Edge629 will operate at full performance under these input conditions. Do not leave any differential inputs floating as they will be in an indeterminate state. All unused inputs must be tied to either a high or low level. Connecting unused timing inputs to VCC is an acceptable method to make an input high. However, to make an input low, it must be connected to VEE +2.0V or higher. All digital interface inputs are "3.3V rail to rail" CMOS compatible provided VCC = +3.3V and VEE = –2V. CK, SDI, and UPDATE all have an internal pull-down resistor network to establish a default condition of a logical 0 when left floating. CS has a large (~50 KΩ) internal pullup resistor to VCC to establish a default condition of a logical 1 when left floating. For optimal performance, all data interface digital inputs should be static when the Edge 629 is actively delaying signals. (However, it is acceptable if CK continues to run.) Input Mux Select VCC VCC Each delay channel can select its input from one of two sources. If Mux Select is high (SEL > SEL*), IN/IN* will be selected for all four channels. If Mux Select is low (SEL < SEL*), IN0/IN0* – IN3/IN3* will be selected for each channel. 50KΩ CK, SDI, UPDATE 50KΩ CS 50KΩ VEE SEL/SEL* Input Source Mode 0 IN0/IN0* – IN3/IN3* Pass Through 1 IN/IN* Fanout Timing Outputs OUT0/OUT0* – OUT3/OUT3* are standard differential ECL open emitter outputs. SEL/SEL* have internal pull-up/pull-down resistors which, when left floating, place the chip in fanout mode. VCC Compensation Pins COMP0, COMP1, COMP2, and COMP3 are op amp compensation pins requiring external 100 pF capacitors to VEE. VCC 50KΩ SEL SEL* 50KΩ VEE 2005 Semtech Corp. Rev. 3, 8/1/05 10 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Package Information 64-Pin TQFP 10 mm x 10 mm x 1.4 mm D PIN Descriptions ˚ 12 TYP. D1 N A2 1 EXPOSED HEATSINK 3.56 ± .50 DIA. A A1 –B– –A– E1 ˚ E 12 TYP. –D– Top View Dims. Tolerance Value A MAX. 1.60 .20 RAD. TYP. A1 20 RAD. TYP. .05 min. / .15 max A2 ±.05 1.40 D ±.20 12.00 D1 ±.10 10.00 E ±.20 12.00 E1 ±.10 10.00 L +.15 / –.10 .60 e BASIC .50 b ±.05 .22 6˚±4˚ STANDOFF A A1 .25 SEATING PLANE .17 MAX θ b –C– LEAD COMPLANARITY ddd M C A–B S D S ccc C L Notes: 1. All dimensions in millimeters. 2. Dimensions shown are nominal with tolerances as indicated. 3. L/F: EFTEC 64T copper or equivalent, 0.127mm (.005”) or 0.15mm (.006”) thick. 4. Foot length “L” is measured at gage plane, at 0.25 above the seating plane. 2005 Semtech Corp. Rev. 3, 8/1/05 θ ddd MAX. .08 ccc MAX. .08 Package Thickness Footprint 11 0˚ - 7˚ 1.40 Body + 2 mm www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions Parameter Total Power Supply Symbol Min Typ Max Units VCC – VEE 4.2 5.2 +5.5 V TJ 0 +100 ˚C Junction Temperature Absolute Maximum Ratings Parameter Max Units 0 7.0 V Voltage on any Digital Input Pin VEE – 0.5 VCC + 0.5 V Voltage on any Analog Input Pin VEE – 0.5 VCC + 0.5 V Power Supply Symbol Min VCC – VEE Output Current –50 Storage Temperature TS Junction Temperature Soldering Temperature (5 seconds, .25" from the pin) Typ mA –65 +150 ˚C TJ +150 ˚C TSOL +260 ˚C θJC (to top of case) θJ C 1.5 ˚C θJ A (@ still air) θJ A 28 ˚C θJ A (@ 400 LFPM) θJ A 21 ˚C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2005 Semtech Corp. Rev. 3, 8/1/05 12 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS DC Characteristics Parameter Symbol Min Differential Input Voltage |IN – IN*| Input High Voltage Range Typ Max Units .3 VCC – VEE V VIH VEE + 2.0 VCC V Input Low Voltage Range VIL VEE + 2.0 VIH – .3 V Input High Current IIH –100 +100 µA Input Low Current IIL –100 +100 µA Input High Voltage SEL – SEL* .3 VCC – VEE V Input Low Voltage SEL* – SEL .3 VCC – VEE V Input High Common Mode Range VIH VEE + 2.0 VCC V Input Low Common Mode Range VIL VEE + 2.0 VIH – .3 V Input High Current IIH 250 µA Input Low Current IIL 250 µA Timing Inputs (IN/IN*, IN0/IN0* – IN3/IN3*) Select Input (SEL/SEL*) Programming Inputs (CK, UPDATE, CS, SDI) Input High Voltage VIH VCC – 1.1 VCC V Input Low Voltage VIL VEE + 2.0 VCC – 1.5 V Input High Current IIH 250 µA Input Low Current IIL 250 µA Digital Outputs Digital Output High Voltage OUT – OUT* 600 690 mV Digital Output Low Voltage OUT* – OUT 600 690 mV Output Common Mode Range OUT + OUT* 2 VCC – 1.5 VCC – 1.3 Output Current Iout VCC – 1.1 V 30 mA Power Supply Current VCC – VEE = 4.2V IEE 561 900 mA VCC – VEE = 5.2V IEE 604 900 mA VCC – VEE = 5.5V IEE 613 900 mA 2005 Semtech Corp. Rev. 3, 8/1/05 13 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS AC Characteristics Parameter Symbol Min Typ Max Units Tpd Min Tpd Min ∆Tpd ∆Tpd 1.282 1.406 1.357 1.481 320 950 1.432 1.556 ns ns ps ps 3 10 ps 10 15 45 50 ps ps Timing Inputs/Outputs Minimum Propagation Delay (Note 2) IN to OUT (0,3) IN0, 3 to OUT (0,3) ∆Tpd, FD Disabled to FD=0 ∆Tpd, FEA Disabled to FEA=0 Rising Edge/Falling Edge Propagation Delay Difference (FEA disabled) Channel-to-Channel Skew (Note 2) IN to OUT (0,3) (Fanout Mode) IN (0,3) to OUT (0,3) Programmable Delay (Note 2) Coarse Delay Fine Delay |Tpd+ – Tpd–| Tskew1 Tskew2 Tspan_Coarse Tspan_Fine 5.5 110 6.0 150 6.5 180 ns ps Falling Edge Adjust (SFE = 1) (Note 1) FEA ±200 ±250 ±300 ps Programmable Delay Step Size (Note 3) Coarse Delay Fine Delay Falling Edge Adjust Tstep_Coarse Tstep_Fine Tstep_FEA 1.0 1.0 1.0 95 5 5 110 7 7 ps ps ps Maximum Operating Frequency (FEA Enabled) Fmax 1.0 GHz Maximum Operating Frequency (FEA Disabled) Fmax 1.3 GHz PW min 350 ps Minimum Pulse Width (at outputs) Output Rise and Fall Times (20% - 80%) Temperature Coefficient (vs. Die Temp) CD = Min, FD & FEA Disabled CD = Max, FD & FEA Disabled CD & FD = Min, FEA Disabled CD & FD = Max, FEA Disabled CD, FD, & FEA = Min CD, FD, & FEA = Max Tr/Tf 110 150 ps 2.4 13.3 3.3 15.1 5.2 18.8 ps/˚C ps/˚C ps/˚C ps/˚C ps/˚C ps/˚C 10 ps ps 1 5 ps ps ∆Tpd/∆T Total Timing Error ∆Tpd vs. Frequency Channel-to-Channel Crosstalk ∆Tpd vs. Duty Cycle Jitter @ Minimum Delay Jitter @ Maximum Delay 20 2 20 Test Conditions (unless otherwise specified): "Recommended Operating Conditions." 2005 Semtech Corp. Rev. 3, 8/1/05 14 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Test Conditions (unless otherwise specified): "Recommended Operating Conditions." Note 1: Tested with an input pulse = 50 ns. This parameter is guaranteed by characterization for input pulse widths ≥ 700 ps. Note 2: Coarse Delay = 0, Fine Delay and Falling Edge Adjust disabled. Case Temperature = 50˚C. Note 3: Coarse Delay is monotonic. Fine Delay is Monotonic. Since the fine delay spans close to 2 LSBs of coarse delay, the summation of digital codes for coarse and fine delays is not monotonic. Proper binary searching using both the coarse and fine delays is achieved first with the coarse (with SFD=1), and then with the fine delays as separate searches. Parameter Symbol Min Typ Max Units Set Up Time SDI to CK ↑ CS to CK ↑ UPDATE to CK ↓ Tsu Tsu Tsu 10 10 20 ns ns ns Hold Time CK ↑ to SDI CK ↑ to CS CK ↓ to UPDATE Th Th Th 4 4 4 ns ns ns T 13 13 30 ns ns ns Data Interface Minimum Pulse Widths CK High CK Low CK Period DAC Settling Time 1 µs Test Conditions (unless otherwise specified): "Recommended Operating Conditions." AC Characteristics are guaranteed by design and characterization. Not production tested. 2005 Semtech Corp. Rev. 3, 8/1/05 15 www.semtech.com Edge629 TEST AND MEASUREMENT PRODUCTS Ordering Infor mation Model Number Package E629AXF 10 x 10 x 1.4mm TQFP w/Exposed Heatsink on Top EVM629AXF Edge629 Evaluation Board Contact Infor mation Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 2005 Semtech Corp. Rev. 3, 8/1/05 16 www.semtech.com