Edge6435/6436 Per-Pin Electronics Companion DAC TEST AND MEASUREMENT PRODUCTS Description The Edge6435/6436 is a low-cost, 40-channel, monolithic ATE level DAC solution manufactured in a wide-voltage bi-CMOS process. The Edge6435/6436 features 2 ranks of input latches into each DAC, whereby all DAC values may be updated at one time. The Edge6435/6436 features independent buffered voltage and current outputs that are serially programmed and can be used to provide all of the reference levels required for up to 8 channels of pin electronics in an ATE system. For Automated Test Equipment, the Edge6435/6436 can support Pin Electronics and Parametric Measurement Units whose outputs are in the range of –3.25V to +13V, and Driver Super Voltages to +13V after calibration. It provides 10 or 5 per pin levels for 4 or 8 channels respectively. The Edge6435/6436 is designed such that DACs may be shared for various levels whereby minimizing the total number of DACs required in a specific application. Designated Voltage Output DACs – Wide Voltage Range (16.75V) – Adjustable Full-Scale Range – Adjustable Minimum Offset Voltage – 13-bit Resolution – 11-bit Accuracy (E6436) – 10-bit Accuracy (E6435) Features • 40 DACs Partitioned into 4 Groups for 4 or 8 Pin Channels • Wide Voltage Output Range (16.75V Range) • 24 Voltage DACs per Package • 8 Voltage / Current DACs per Package • 8 Current DACs per Package • Adjustable Full-Scale Range and Offset per Group • DUT GND or Analog GND Reference per Group • Self-Calibrating DACs via Internal Offset, Gain Registers • Two Offset, Gain Registers to Support Sharing of DACs • DAC Programming per Channel or Set of Channels • Readback of DAC Input Data and Output Value • Small 100-Pin MQFP Package • Low-Cost, Highly Integrated Multi-DAC Solution Selectable Voltage/Current Output DACs – Wide Voltage/Current Range (16.75V/2 mA) – Adjustable Full-Scale Range – Adjustable Minimum Offset – Configurable as either Voltage or Current Output – 13-bit Resolution – 11-bit Accuracy (E6436) – 10-bit Accuracy (E6435) Designated Current Output DACs – 1.6 mA Range – Adjustable Full-Scale Range – 6-bit Resolution On-chip, digital storage of offset and gain calibration coefficients allow the E6435/6436 output levels to be programmed using “Ideal Code”, helping to reduce some of the complexity and time normally associated with programming level DACs in ATE systems. Applications • Automated Test Equipment (ATE) • Cost Sensitive applications requiring multiple programmable voltage and currents PINCAST allows the Edge6435/6436 to further reduce this complexity and time by allowing channels across multiple Edge6435/6436 devices to be digitally assigned to up to 8 distinct sets that can be addressed and programmed with a limited number of instructions. Revision 3 / August 25, 2006 1 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Functional Block Diagram SDIN CLKIN 4 DAC 0 2 2 2 DACEN 2 Channel 0 VOUTA VOUTB VOUTC IOUTC IOUTD UPDATE 4 2 2 STORE 2 2 Channel 1 VOUTA VOUTB VOUTC IOUTC IOUTD LOAD 4 RANK 2 2 RESET* 2 2 TESTMODE 4 2 2 2 SHIFTOUT* 2 DAC 39 SDOUT LDOUT 2006 Semtech Corp. / Rev. 3, 8/25/06 2 Channel 2 VOUTA VOUTB VOUTC IOUTC IOUTD Channel 3 VOUTA VOUTB VOUTC IOUTC IOUTD DACOUT www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS PIN Description Pin Name Pin # Description Power Supplies AVCC 29, 58, 76 Positive Analog Supply Pins (Output Buffer Supply) AVEE 2, 3, 22, 27, 28, 57, 61, 73, 77 AVDD 21, 26, 60, 74, 96 Positive Analog Supply Pins (Core DAC Supply) AGND 20, 25, 59, 75, 99 Analog Supply Ground Pins DVDD 65, 67 Digital Supply Input Pins DGND 64, 68 Digital Supply Ground Pins VREF 4, 63, 69 Negative Analog Supply Pins Reference Voltage Input Digital I/O Pins CLKIN 14 Clock input pin. SDIN 12 Serial data input pin that is used to read 24-bit words into the E6435 input shift register. LOAD 15 Digital input pin that triggers the transfer of data from the serial data input shift register to the central DAC register at up to 33 MHz. STORE 10 Digital input pin that is used to update the rank A latches. UPDATE 9 Digital input pin that is used to update the rank B latches. RANK 66 Digital input pin that selects either data in the rank A or rank B latches as the DAC input. FORMAT 11 Digital input pin used to select between "4-channel" or "8-channel" decoding schemes. RESET* 7 Digital input pin that is used to initialize the E6435 by placing it into a known state. DACEN 6 Digital input pin that is used to set all DAC outputs ~0V (Voltage output DACs) or ~0mA (Current output DACs). SDOUT 17 Serial data output pin. TEST_MODE 16 Digital input pin that is used to enable/disable the DAC_OUT and LD_OUT functions. DAC_OUT 54 High impedance analog voltage output pin that displays the output level of a selected DAC (used for system level diagnostics) when enabled using the TEST_MODE pin. SHIFTOUT* 8 Digital input pin that is used to begin the transmission of serial data through the LD_OUT pin. LD_OUT 13 Serial data output pin used to display the binary value stored in a selected rank A or rank B latch. Diagnostic Pins 2006 Semtech Corp. / Rev. 3, 8/25/06 3 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) Pin Name Pin # Description 13-Bit Voltage Output DACs VOUTA_0 VOUTA_1 VOUTA_2 VOUTA_3 VOUTA_4 VOUTA_5 VOUTA_6 VOUTA_7 VOUTA_8 VOUTA_9 VOUTA_10 VOUTA_11 VOUTA_12 VOUTA_13 VOUTA_14 VOUTA_15 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 Group A Voltage DAC Output Pins. VOUTB_0 VOUTB_1 VOUTB_2 VOUTB_3 VOUTB_4 VOUTB_5 VOUTB_6 VOUTB_7 30 31 32 33 34 35 36 37 Group B Voltage DAC Output Pins. 13_Bit Selectable Voltage/Current Output DACs VOUTC_0 VOUTC_1 VOUTC_2 VOUTC_3 VOUTC_4 VOUTC_5 VOUTC_6 VOUTC_7 38 41 42 45 46 49 50 53 Group C Voltage DAC Output Pins. IOUTC_0 IOUTC_1 IOUTC_2 IOUTC_3 IOUTC_4 IOUTC_5 IOUTC_6 IOUTC_7 39 40 43 44 47 48 51 52 Group C Current DAC Output Pins. 18 19 1 100 98 97 95 94 Group D Current DAC Output Pins. 6-Bit Current Output DACs IOUTD_0 IOUTD_1 IOUTD_2 IOUTD_3 IOUTD_4 IOUTD_5 IOUTD_6 IOUTD_7 2006 Semtech Corp. / Rev. 3, 8/25/06 4 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) Pin Name Pin # Description Resistor Connections R_MASTER 70 External resistor connection used in combination with R_VGAIN_A, R_VGAIN_B, and R_VGAIN_C to set the maximum output range for the Group A, B, and C voltage output DACs. R_VGAIN_A 71 External Resistor connection used in combination with R_MASTER to set the maximum range for the group A voltage DAC outputs. R_VGAIN_B 24 External Resistor connection used in combination with R_MASTER to set the maximum range for the group B voltage DAC outputs. R_VGAIN_C 56 External Resistor connection used in combination with R_MASTER to set the maximum range for the group C voltage DAC outputs. R_OFFSET_A 72 External resistor connection used to set the base offset voltage for group A voltage DAC outputs. R_OFFSET_B 23 External resistor connection used to set the base offset voltage for group B voltage DAC outputs. R_OFFSET_C 55 External resistor connection used to set the base offset voltage for group C voltage DAC outputs. R_IGAIN_C 62 External resistor connection used to set the maximum range for the group C current DAC outputs. R_IGAIN_D 5 External resistor connection used to set the maximum range for the group D current DAC outputs. 2006 Semtech Corp. / Rev. 3, 8/25/06 5 www.semtech.com Edge6435/6436 AGND IOUTD_4 IOUTD_5 AVDD IOUTD_6 IOUTD_7 VOUTA_0 VOUTA_1 VOUTA_2 VOUTA_3 VOUTA_4 VOUTA_5 VOUTA_6 VOUTA_7 VOUTA_8 VOUTA_9 VOUTA_10 VOUTA_11 VOUTA_12 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 IOUTD_3 100 99 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) IOUTD_2 1 80 VOUTA_13 AVEE 2 79 VOUTA_14 AVEE 3 78 VOUTA_15 VREF 4 77 AVEE R_IGAIN_D 5 76 AVCC DACEN 6 75 AGND RESET* 7 74 AVDD SHIFTOUT* 8 73 AVEE UPDATE 9 72 R_OFFSET_A STORE 10 71 R_VGAIN_A FORMAT 11 70 R_MASTER SDIN 12 69 VREF LD_OUT 13 68 DGND CLKIN 14 67 DVDD LOAD 15 66 RANK TEST_MODE 16 65 DVDD SDOUT 17 64 DGND IOUTD_0 18 63 VREF IOUTD_1 19 62 R_IGAIN_C AGND 20 61 AVEE AVDD 21 60 AVDD AVEE 22 59 AGND R_OFFSET_B 23 58 AVCC R_VGAIN_B 24 57 AVEE AGND 25 56 R_VGAIN_C AVDD 26 55 R_OFFSET_C AVEE 27 54 DAC_OUT AVEE 28 53 VOUTC_7 AVCC 29 52 IOUTC_7 VOUTB_0 30 51 IOUTC_6 Edge6435AHF 100 Lead - 14 x 20 MQFP with Internal Heat Spreader 44 45 46 47 48 49 50 IOUTC_3 VOUTC_3 VOUTC_4 IOUTC_4 IOUTC_5 VOUTC_5 VOUTC_6 IOUTC_0 43 39 VOUTC_0 IOUTC_2 38 VOUTB_7 VOUTC_2 37 VOUTB_6 42 36 VOUTB_5 41 35 VOUTB_4 VOUTC_1 34 VOUTB_3 40 33 VOUTB_2 2006 Semtech Corp. / Rev. 3, 8/25/06 IOUTC_1 31 32 VOUTB_1 (Top View) 6 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description Chip Overview Grouping of DACs The Edge6435/6436 provides 40 output levels. These outputs can easily be configured to generate the specific analog voltage and current requirements for 4 or 8 channels of ATE pin electronics including: – 3 level driver – Window comparator – Active load – Per pin PMU or PTU without requiring any scaling or shifting via external components. DACs are separated into 4 or 8 channels of 4 distinct functional groups. Groups are defined by: Selection of 4 or 8 channel format is via the FORMAT input. Group C DACs have both voltage and current output pins. Programming of the chip is done using a 6 wire digital interface comprised of: – Serial Data In – Clock In – Load – – – – Type (voltage or current output) Resolution (# of bits) Output range Output compliance. Table 1 defines the DACs on a per group and channel basis. Group C DACs can be individually configured via the serial interface to be either a voltage or current DAC (but not both at the same time). Tables 3 and 4 identify the code needed to configure Group C DACs. Please note that 24 clock cycles are required to load the configuration code for each channel. Group A Group B Group C Group D 4 CH Format 4 per channel 2 per channel 2 per channel 2 per channel 8 CH Format 2 per channel 1 per channel 1 per channel 1 per channel Type V V V/I I Resolution (# of bits) 13 13 13 6 16.75V –3.5V to –0.75V 16.75V –3.5V to –0.75V 16.75V –3.5V to –0.75V or 2.05 mA (Note 2) yes yes yes for Vout no for Iout no ±200 µA ±200 µA ±200 µA(V) –0.2 to +3V(I) –0.2 to +3V Attribute Total # of DACs in Group Output Range: Max DAC Range (Note 1) Offset Range Adjustable Output Offset Compliance Note 1: Note 2: 1.6 mA The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details. Group C has both voltage and current outputs. Table 1. DAC Grouping 2006 Semtech Corp. / Rev. 3, 8/25/06 7 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Voltage Outputs DACs (Groups A, B, C) Minimum / Maximum Output Voltages The output voltage of each E6435/6436 VOUT DAC is a function of external resistor values (R_MASTER, R_VGAIN and R_OFFSET), a reference voltage level (VREF), contents of digital offset and gain registers, and the programmed input code (DATA). The general equation that describes the output voltage as a function of these variables is presented below as Equation 1: See Table 2 for the minimum and maximum possible voltages of a voltage output, where: VOUT_[A:C] = 8 * VREF * R_VGAIN_[A:C] R_MASTER * CODE 8192 * R_VGAIN_[A:C] R_MASTER * 8191 8192 + VOFFSET_[A:C] Equation 3. Resolution where: VOUT[A:C] is the output voltage of a Group A, B, or C Voltage DAC. VREF is an externally applied 2.5V reference voltage R_VGAIN[A:C] is the value of an external resistor used to set the range for Group A, B, or C DACs R_MASTER is the value of an external resistor that sets the bias point/range for the voltage DACs CODE is the base-10 value of the binary code (DATA) loaded into the DAC shift register (see Figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibration registers as shown in Figure 2. VOFFSET[A:C] is the raw DAC offset voltage that is programmed using an external resistor per group, R_OFFSET[A:C] as follows: R_OFFSET_[A:C] R_MASTER Equation 2. As can be seen from Equation 1, the accuracy of the DAC output voltage after calibration is dependent upon the temperature coefficients of VREF and the external resistors. 2006 Semtech Corp. / Rev. 3, 8/25/06 = 8 * VREF VMAX_[A:C] + VOFFSET_[A:C] Equation 1. VOFFSET_[A:C] = – VREF VOFFSET[A:C] is defined in equation 2, and 8 The resolution of the DACs in Groups A, B and C is: VRANGE_[A:C] / (213 – 1) where VRANGE_[A:C] is defined in Equation 4. Range The range of the DACs in Groups A, B and C is: VRANGE_[A:C] = 8 * VREF * R_VGAIN_[A:C] * R_MASTER 8191 8192 Equation 4. External Resistors Typically computed for R_MASTER = 100kΩ. DAC Setting MSB ... LSB VOUT_[A:C] (V) 0000H VOFFSET_[A:C] 1FFFH VMAX_[A:C] Table 2. Minimum/Maximum Output Voltages www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Current Output DACs (Groups C, D) Group C DACs The output current of each Group C Current DAC is a function of an external resistor value (R_IGAIN_C), a reference voltage level (VREF), contents of digital offset and gain registers, and the input code (DATA). The general equation that describes the output current as a function of these variables is presented below as Equation 5: 50 x VREF R_IGAIN_C IOUT_C = CODE * 8192 Equation 5. where: IOUT_C is the output current of the Group C Current DAC R_IGAIN_D is the value of an external resistor that sets the output current range for Group D DACs (78.12KΩ ≤ R_IGAIN_D ≤ 156.25KΩ) DATA is the base-10 value of the binary code loaded into the DAC shift register (see Figures 4 and 5). Functional Description Figure 1 provides a Functional Block Diagram. Figures 2 and 3 show details of the data latches and logic for the DACs. The Edge6435/6436 features a serial data input to program a channel or set of channel’s DACs and functions. The Edge6435/6436 also features selfcalibrating DAC outputs via internal offset and gain registers (Figure 2). Figures 4 and 5 show the format of the Serial Input Data for 4 pin channel and 8 pin channel formats. VREF is an externally applied 2.5V reference voltage Figure 6 shows the Serial Data Programming Sequence R_IGAIN_C is the value of an external resistor that sets the output current range for Group C DACs (60.97KΩ ≤ R_IGAIN_C ≤ 250KΩ) CODE is the base-10 value of the binary code (DATA) loaded into the DAC shift register (see Figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibraiotn registers as shown in Figure 2. Tables 3 and 4 provide the Address Maps for 4 pin channel and 8 pin channel formats. FORMAT FORMAT Low selects the 4 pin channel format. FORMAT High selects the 8 pin channel format. Group D DACs The output current of each group D DAC is a function of an external resistor value (R_IGAIN_D), a reference voltage level (VREF) and the input code (DATA). The general equation that describes the output current as a function of these variables is presented below as Equation 6: IOUT_D = DATA 64 * 50 x VREF R_IGAIN_D Equation 6. where: IOUT_D is the output current of the Group D DAC VREF is an externally applied 2.5V reference voltage 2006 Semtech Corp. / Rev. 3, 8/25/06 9 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) RESET* UPDATE RESET* low resets the input shift register (no CLKIN required), the central register, and input registers. With RESET* high, the following leading edge of CLKIN will cause reset condition to be removed (see Figure 21). Two clock cycles are required after RESET* is set to logic “high” for the DAC outputs to be enabled. Following the STORE of multiple DAC values into Rank A DAC latches, Rank B latches may be updated in parallel with the values of their Rank A DAC latches by a CLKIN with UPDATE high. There must be at least 16 clock cycles between when STORE is set to logic “low” and UPDATE is latched to logic “high” in order to latch the latest data (see Figure 21). Programming Sequence RANK Selection The DACs are programmed serially (see Figures 1 and 6). On each rising edge of CLKIN, SDIN is loaded into a shift register. It requires 24 Clocks to fully load the shift register. Referring to Figures 1, 2 and 3: RANK low selects Rank A latches to the DACs (no CLKIN required). LOAD Following the serial input of a new DAC value, then LOAD high for the leading edge of CLKIN loads the new DAC value and its address into the Central Register. Following the loading of the Central Register, LOAD needs to go low followed by a leading edge of CLKIN so as to enable the address decoder (see Figure 6). STORE Following the LOAD of the Central Register and the enabling of the address docoder, the channel or set of channels addressed DACs input register or channel function is “stored” by a CLKIN with STORE high. Only upon the STORE of a DAC or set of DAC’s “value latch” (Figure 2) does the Edge6435/6436 compute the input to DAC’s Latch A (of Rank A). There needs to be at least one clock edge after LOAD is set to logic “low” before STORE is set to logic “high” (see Figure 21). RANK high selects Rank B latches to the DACs (no CLKIN required). DACEN DACEN low forces all DAC voltage outputs to ~0V and all current outputs to ~0 mA (no CLKIN required). With DACEN high, then a following leading edge of CLKIN will cause DACs to be enabled (see Figure 23). TEST MODE/SHIFTOUT* TEST_MODE is used to enable the LDOUT and DACOUT channels. Once enabled (TESTMODE = 1), SHIFTOUT* can be used to begin transmission of serial data through the LDOUT pin, or DAC outputs can be monitored at the DACOUT pin (see Figure 24) (TEST_MODE functionality does not depend on CLKIN)). When addressing DAC channels that have been assigned to a PinCast “set”, TEST-MODE is internally disabled in order to prevent multiple DAC outputs from being connected in parallel and possibly damaging the E6435/ 6436. 2006 Semtech Corp. / Rev. 3, 8/25/06 10 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Serial Programming The Edge6435/6436 is programmed with 24-bit serial data (Figure 6) in either a 4 channel (Figure 4) or 8 Channel (Figure 5) format. Following the input of serial data, it is loaded into a central register by LOAD (Figure 1). The central register’s contents are stored in the “addressed” latch by the STORE input. Tables 3 and 4 show the “Address Maps” for the 4 and 8 channel formats. Referring to Table 3 for 4 channel format, a channel’s DACs Set Register or Function may be addressed and the “stored” value changed. For each DAC, there are associated multiple latches (Figures 2 and 3). For the 13-bit DACs (Figure 2) the DAC’s output is a function of the contents of its value, gain and offset latches. The Edge6435/6436 features two gain and offset latches per DAC whereby a DAC’s output may be shared. For example, in ATE a DAC’s value may be shared between a pin driver’s high level and a pin’s parametric unit’s high limit level, where each application requires different offset and gain factors to calibrate each path correctly. Gains and offsets are computed externally to the Edge6435/6436 in the process of pin channel level calibration in the ATE. Gains and offsets are stored in the Edge6435/6436 in the same manner as other latches. Selection of what is stored is determined by the “register selection” bits in the 24-bit input data (Figures 2 and 4). Upon storing a 13-bit DAC’s Value, the resultant DAC’s ((Value x Gain) + Offset + 4096 Value) is updated by UPDATEA (Figure 2) into the DAC’s output latch of RANKA. The contents of all RANKA latches may be transferred to RANKB latches, in parallel, across multiple Edge6435/6436’s by the UPDATE input into the Edge6435/6436. The RANK input into the Edge6435/ 6436 selects either RANKA or RANKB latches for all DACs. For the 6-bit DACs (Figure 3) the DAC’s output is selected from four “value latches”. belong to none, one, or any combination of up to 8 distinct sets. The address maps show that a channel’s DAC (or Function) may be addressed individually, or a DAC (or Function) of multiple channels belonging to the same set may be programmed in parallel. Figure 11 shows an example of addressing channels by sets. Referring to Table 3, a Channel’s function is programmed as indicated in Figure 9 (offset and gain selection as well as Group C DAC V/I output selection, see below). Channel’s Functions (for 13 bit DACs only), with R2 = R1 = R0 = 0, then: D0 = 0: D0 = 1: D1 = 0: D1 = 1: Selects 1st Offset/Gain Registers Selects 2nd Offset/Gain Registers Selects Voltage Output on Group C DACs Selects Current Output on Group C DACs Referring to Table 4 for 8 channel format, and Figures 2, 3, 5, 8 and 10, a channel’s DACs, Set Registers and Function, etc. are programmed and operate similar to the 4 channel format described above. NOTE: The STORE of a DAC’s offset or gain does not result in a DAC output change. Only upon the STORE of a DAC or set of DAC’s “value” does the Edge6435/6436 compute the input to DAC’s “A” latches. In a tester having multiple Edge6435/6436s, DACs or channel functions may be programmed individually or as a set (1 of 8) of channels across all channels. If multiple E6435/6436s are programmed in parallel, individual DAC or Function programming requires the STORE input to the associated Edge6435/6436 to be applied where all STORE inputs to other Edge6435/6436s are to be inhibited (externally). Programming a DAC or Function of a Set of Channels requires STORE input to be applied to all Edge6435/6436s. Edge6435/6436’s DACs may be “updated” in parallel following the programming of DACs as individual DACs or sets of DACs. Referring to Table 3, a channels Set Register may also be programmed. This is an independent 8-bit register per channel which determines the “sets” to which the channel belongs. Figure 7 shows details of programming a channel’s Set Register, which is stored in the Edge6435/6436 by the STORE input. A channel may 2006 Semtech Corp. / Rev. 3, 8/25/06 11 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) STORE UPDATE RANK DACEN Decode and Individual DAC Update R C C R C R S A D DACSEL0 D D D D DAC0 VOUTA_0 DAC1 VOUTA_1 DAC39 IOUTD_3 B SR4-SR0 UPDATEA A D DACSEL1 B UPDATEB UPDATEA A ADDRESS AND SET DECODERS FORMAT D7-D0 D D UPDATEA DISABLE R R R R 13 D12-D0 R A3-A0 C1-C0 M1-M0 R2-R0 11 C B D CENTRAL REGISTER LOAD LCLK (24 Bits) LDOUT RESET CLKIN 24-BIT SHIFT REGISTER SDOUT SDIN RESET* S RESET DACOUT Programming Logic NOTE: VOUT, IOUT names shown for 4 Channel Format. NOTE: Not shown is the function of the Latched Data Readback (via LDOUT) and the DAC Value Readback (via DACOUT). Details of the 'Store' Latches are shown on the following pages. Figure 1. DAC Functional Block Diagram 2006 Semtech Corp. / Rev. 3, 8/25/06 12 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) D[12:0] UPDATEA SEQUENCE GENERATOR STORE UPDATEA UPDATE RANK 13 D 13 V DACSEL SR0 A 13 + D[9:0] ÷4096 13 + 13 D B D D V G SR1 10 10 A 10 D[9:0] R SEL R B D V G SR2 D[9:0] D O SR3 10 A D[9:0] 10 10 SEL B D O SR4 CALSEL R KEY: V: Value Latch that contains DATA programmed to a DAC (see Figures 4 & 5). O: Offset Latches that are used to store offset calibration coefficients (two offset latches per DAC allow the DAC to be shared in a system). Function G: Gain Latches that are used to store gain calibration coefficients (two gain latches per DAC allow the DAC to be shared in a system). NOTE: CALSEL common to all DACs assigned to a Channel DAC Output (CODE): CODE = V * (G + 4096) 4096 +O Register Selection R2 R1 R0 Select DAC Data 0 0 0 SR0 Gain Register A 0 0 1 SR1 Gain Register B 0 1 0 SR2 Offset Register A 0 1 1 SR3 Offset Register B 1 0 0 SR4 Figure 2. Details of DAC Data Latches for 13 Bit DACs (Groups A, B, and C) 2006 Semtech Corp. / Rev. 3, 8/25/06 13 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) UPDATEB D[12:7] D 6 VA DACSEL RANK STORE A SR0 A 6 B D D 6 B VB V SR1 M U X D R 6 C VC V SR2 D 6 D VD SR3 D[8:7] D 2 VS SR4 R KEY: VA, VB, VC, VD: Value Latches A, B, C, D VS: Value Selection Latch Value Selection (VS) D8 D7 Select 0 0 A 0 1 B 1 0 C 1 1 D Figure 3. Details of DAC Data Latches for 6 Bit DACs (Group D) 2006 Semtech Corp. / Rev. 3, 8/25/06 14 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) DATA R2 R1 R0 D12 D11 D10 D9 D8 D7 D6 ADDRESS D5 D4 D3 D2 D1 D0 MSB M1 M0 C1 C0 A3 LSB REGISTER A2 A1 MSB MODE A0 LSB CHANNEL Figure 4. Format of Address and Data in Shift Register (4 Channel Format) DATA R2 R1 R0 D12 D11 D10 D9 D8 D7 D6 ADDRESS D5 D4 D3 D2 MSB D1 D0 M1 M0 LSB REGISTER C1 C0 A3 A2 MSB MODE A1 A0 LSB LSB CHANNEL A1 M0 M1 D0 D1 CLKIN ≈ ≈ A0 LSB Data ≈ SDIN MSB Addr. Next Set of Data MSB Data R1 A0 R2 A1 ≈ LSB Addr. ≈ ≈ Figure 5. Format of Address and Data in Shift Register (8 Channel Format) CK24 CK1 TCK SDOUT A0 Previous Data A1 ≈ ≈ LOAD Corresponds to A0 loaded at CK1 Figure 6. Serial Data Programming Sequence 2006 Semtech Corp. / Rev. 3, 8/25/06 15 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) DATA X X X X X X X X D7 D6 ADDRESS D5 D4 D3 D2 D1 MSB D0 0 0 C1 C0 1 LSB 1 0 0 MSB REGISTER MODE LSB CHANNEL Figure 7. Format of Address and Data for Programming to SET REGISTER (4 Channel Format) DATA X X X X X X X X D7 D6 ADDRESS D5 D4 D3 D2 D1 MSB D0 0 0 LSB REGISTER C1 C0 MSB 1 1 MSB MODE 0 A0 LSB LSB CHANNEL Figure 8. Format of Address and Data for Programming to SET REGISTER (8 Channel Format) DATA 0 0 0 X X X X X X X ADDRESS X X X X D1 MSB D0 0 0 C1 C0 LSB REGISTER 1 1 1 MSB MODE 0 LSB CHANNEL Figure 9. Format of Address and Data for Programming a Channel’s Function (4 Channel Format) DATA 0 0 0 X X X X X X X ADDRESS X X MSB X X D1 D0 0 0 LSB REGISTER C1 MSB MODE C0 1 MSB 1 1 A0 LSB LSB CHANNEL Figure 10. Format of Address and Data for Programming a Channel’s Function (8 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 16 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) DATA X X X X X X X X D7 D6 ADDRESS D5 D4 D3 D2 D1 D0 0 0 C1 C0 MSB 1 1 0 MSB REGISTER MODE 0 LSB CHANNEL STORE 0 1 0 1 0 0 0 0 CHANNEL'S SET REGISTER (Channel belongs to Sets 4 and 6) COM PAR E 1 of 8 Selection DATA R2 R1 R0 D12 D11 D10 D9 D8 D7 D6 ADDRESS D5 D4 D3 D2 MSB D1 D0 M1 LSB LSB 1 C1 MSB C0 A3 MSB A2 A1 A0 LSB Channel Set Selection If Set 4 is selected, then channel’s DAC value or Function will be ‘stored’. If Set 3 is selected, then the channel will not be ‘addressed’. Figure 11. Example of Channel’s Set Selection (4 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 17 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) FORMAT = 0 Bit # Hex Multiplier Binary Position Item Group A 13-bit V Reserved CHANNEL 0 Group B 13-bit V Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved Group A 13-bit V Reserved CHANNEL 1 Group B 13-bit V Group C 13-bit V/I Group D 6-bit I (Note 1) CHANNEL FUNCTIONS PINCAST Register 1 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved Group A 13-bit V Reserved CHANNEL 2 Group B 13-bit V Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 2 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved CHANNEL 3 Reserved Group D 6-bit I (Note 1) PINCAST Register 3 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved 23 22 21 20 19-16 0x10 0000 0x01 0000 8 4 2 1 8 - 1 DAC Output Pin Name Register R2 X X X X X X X X R1 X X X X X X X X VOUTC_1, IOUTC_1 X X X X X IOUTD_0 IOUTD_1 N/A N/A N/A VOUTA_4 VOUTA_5 VOUTA_6 VOUTA_7 N/A VOUTB_2 VOUTB_3 VOUTC_2, IOUTC_2 X X X X 0 0 0 0 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X VOUTC_3, IOUTC_3 X X X X IOUTD_2 IOUTD_3 N/A N/A N/A VOUTA_8 VOUTA_9 VOUTA_10 VOUTA_11 N/A VOUTB_4 VOUTB_5 VOUTC_4, IOUTC_4 X X X X 0 0 0 0 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X VOUTC_5, IOUTC_5 X X X IOUTD_4 IOUTD_5 N/A N/A X X X X 0 0 0 0 X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X 0 0 0 0 X X X X X X X N/A N/A N/A VOUTA_12 VOUTA_13 VOUTA_14 VOUTA_15 N/A VOUTB_6 11 10 9 0x0100 4 2 8 8 7 6 5 4 3 2 1 0 1 8 4 2 1 8 4 2 1 M1 0 0 0 0 0 0 0 0 M0 0 0 0 0 0 0 0 0 C1 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 Data VOUTA_0 VOUTA_1 VOUTA_2 VOUTA_3 N/A VOUTB_0 VOUTB_1 VOUTC_0, IOUTC_0 N/A 15-12 0x1000 8 - 1 R0 D12 D11 - D8 X X X X X X X X X X X X X X X X X X X X X X X X D7 - D4 X X X X X X X X D3 X X X X X X X X D2 X X X X X X X X D1 X X X X X X X X D0 X X X X X X X X X X X X X 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X 0 1 X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X 0 1 X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 A2 0 0 0 0 0 0 0 0 N/A 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 0 N/A N/A N/A N/A N/A N/A N/A N/A VOUTB_7 X X X X X X X X X X 0 0 1 1 0 1 1 1 X X X X X X X X X X 0 0 1 1 1 0 0 0 VOUTC_7, IOUTC_7 X X X X X X X X X X 0 0 1 1 1 0 0 1 IOUTD_6 IOUTD_7 N/A N/A X X X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 (continued next page) N/A N/A VOUTC_6, IOUTC_6 N/A N/A N/A N/A N/A N/A Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. Table 3. Address Map (4 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 18 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Bit # Hex Multiplier Binary Position FORMAT = 0 GROUP B DACs GROUP D DACs GROUP C DACs PINCAST SET FUNCTIONS GROUP A DACs All DACs 23 22 21 20 0x10 0000 8 4 2 1 19-16 0x01 0000 8 - 1 15-12 0x1000 8 - 1 Register 11 8 10 9 0x0100 4 2 8 7 1 8 DAC Output Pin Name Data Parallel Load of All DACs All DAC Output Pins Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTA_0 VOUTA_4 VOUTA_8 VOUTA_12 X X X X X X X VOUTA_1 VOUTA_5 VOUTA_9 VOUTA_13 X X X X X X Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTA_2 VOUTA_6 VOUTA_10 VOUTA_14 X X X X X Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTA_3 VOUTA_7 VOUTA_11 VOUTA_15 X X X X D7 - D4 X 4 3 1 8 Mode Item R2 R1 R0 D12 D11 - D8 X X X X X 6 5 0x0010 4 2 D3 D2 X X D1 X D0 X M1 1 M0 0 X X X PS0 1 X X X X PS0 X X X X X X X X X X 2 1 0 4 2 1 Address C1 0 A3 0 A2 0 A1 0 A0 0 PS2 PS1 0 0 0 0 1 PS2 PS1 0 0 0 1 PS0 1 PS2 PS1 0 0 1 0 X PS0 1 PS2 PS1 0 0 1 1 Reserved N/A X X X X X X X X X X X X Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTB_0 VOUTB_2 VOUTB_4 VOUTB_6 X X X X X X X X X X PS0 1 PS2 PS1 0 1 1 0 Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTB_1 VOUTB_3 VOUTB_5 VOUTB_7 X X X X X X X X X X PS0 1 PS2 PS1 0 1 1 1 Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTC_0 VOUTC_2 VOUTC_4 VOUTC_6 or IOUTC_0 IOUTC_2 IOUTC_4 IOUTC_6 X X X X X X X X X X PS0 1 PS2 PS1 1 0 0 0 Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTC_1 VOUTC_3 VOUTC_5 VOUTC_7 or IOUTC_1 IOUTC_3 IOUTC_5 IOUTC_7 X X X X X X X X X X PS0 1 PS2 PS1 1 0 0 1 Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). IOUTD_0 IOUTD_2 IOUTD_4 IOUTD_6 X X X X X X X X X X PS0 1 PS2 PS1 1 0 1 0 Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). IOUTD_1 IOUTD_3 IOUTD_5 IOUTD_7 X X X X X X X X X X PS0 1 PS2 PS1 1 0 1 1 N/A X X X X X X X X X X X X Reserved X C0 0 X X X Table 3. Address Map (4 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/06 19 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) FORMAT = 1 Item CHANNEL 0 CHANNEL 1 Register 15-12 0x1000 8- 1 11 8 10 9 0x0100 4 2 8 7 6 5 4 3 2 1 0 1 8 4 2 1 8 4 2 1 C1 0 0 0 C0 0 0 0 A3 A2 A1 A0 0 0 0 0 0 0 1 0 0 1 0 0 Data Reserved R1 X X X R0 X X X D3 X X X D2 X X X D1 X X X D0 X X X Group B 13-bit V VOUTB_0 X X X X X X X X X X 0 0 0 0 0 1 1 0 Group C 13-bit V/I VOUTC_0, IOUTC_0 X X X X X X X X X X 0 0 0 0 1 0 0 0 D12 D11 - D8 X X X X X X Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_0 N/A Reserved VOUTA_1 VOUTA_3 N/A X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X 0 0 0 0 X X X Group B 13-bit V VOUTB_1 X X Group C 13-bit V/I VOUTC_1, IOUTC_1 X Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_1 N/A D7 - D4 X X X M1 M0 0 0 0 0 0 0 (16.75V Max Swing) I : 0.5mA to 2.05mA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0.8mA to 1.6mA N/A X X X X X X X X 0 0 0 0 0 1 1 1 X X X X X X X X X 0 0 0 0 1 0 0 1 (16.75V Max Swing) I : 0.5mA to 2.05mA Reserved X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0.8mA to 1.6mA N/A VOUTA_4 VOUTA_6 N/A X X 0 0 0 0 X X X Group B 13-bit V VOUTB_2 X X X X X X X X X X 0 0 0 1 0 1 1 0 Group C 13-bit V/I VOUTC_2, IOUTC_2 X X X X X X X X X X 0 0 0 1 1 0 0 0 (16.75V Max Swing) I : 0.5mA to 2.05mA Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_02 N/A Reserved X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0.8mA to 1.6mA N/A VOUTA_5 VOUTA_7 N/A X X 0 0 0 0 X X X Group B 13-bit V VOUTB_3 X X X X X X X X X X 0 0 0 1 0 1 1 1 Group C 13-bit V/I VOUTC_3, IOUTC_3 X X X X X X X X X X 0 0 0 1 1 0 0 1 (16.75V Max Swing) I : 0.5mA to 2.05mA Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_3 N/A X X 0 0 0 0 X X 0 0 0 0 X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X 0 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0.8mA to 1.6mA N/A N/A -3.5V to +13.75V (16.75V Max Swing) V: -3.5V to +13.75V N/A N/A -3.5V to +13.75V (16.75V Max Swing) V: -3.5V to +13.75V Group A 13-bit V CHANNEL 2 DAC Output Pin Name R2 X X X Group A 13-bit V N/A -3.5V to +13.75V (16.75V Max Swing) N/A -3.5V to +13.75V (16.75V Max Swing) V: -3.5V to +13.75V Group A 13-bit V CHANNEL 3 22 21 20 19-16 0x01 0000 0x10 0000 8 4 2 1 8- 1 VOUTA_0 VOUTA_2 N/A Group A 13-bit V CHANNEL FUNCTIONS (Channels 0 to 3) 23 Bit # Hex Multiplier Binary Position N/A N/A -3.5V to +13.75V (16.75V Max Swing) V: -3.5V to +13.75V N/A (continued next page) Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. Table 4. Address Map (8 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 20 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) FORMAT = 1 Item CHANNEL 4 CHANNEL 5 Register R2 X X X R1 X X X 15-12 0x1000 8 - 1 11 8 10 9 0x0100 4 2 8 7 6 5 4 3 2 1 0 1 8 4 2 1 8 4 2 1 C1 1 1 1 C0 0 0 0 A3 0 0 0 Data R0 D12 D11 - D8 X X X X X X X X X D7 - D4 X X X D3 X X X D2 X X X D1 X X X D0 X X X M1 M0 0 0 0 0 0 0 A2 A1 A0 0 0 0 0 1 0 1 0 0 Reserved VOUTB_4 X X X X X X X X X X 0 0 1 0 0 1 1 0 Group C 13-bit V/I VOUTC_4, IOUTC_4 X X X X X X X X X X 0 0 1 0 1 0 0 0 Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_4 N/A Reserved VOUTA_9 VOUTA_11 N/A X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 0 Group B 13-bit V VOUTB_5 X X X X X X X X X X 0 0 1 0 0 1 1 1 Group C 13-bit V/I VOUTC_5, IOUTC_5 X X X X X X X X X X 0 0 1 0 1 0 0 1 Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_5 N/A Reserved VOUTA_12 VOUTA_14 N/A X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X 0 1 X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 Group B 13-bit V VOUTB_6 X X X X X X X X X X 0 0 1 1 0 1 1 0 Group C 13-bit V/I VOUTC_6, IOUTC_6 X X X X X X X X X X 0 0 1 1 1 0 0 0 Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_6 N/A X X 0 0 0 0 X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X 0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 0 1 Group A 13-bit V CHANNEL 6 DAC Output Pin Name 19-16 0x01 0000 8 - 1 Group B 13-bit V Group A 13-bit V N/A N/A VOUTA_13 VOUTA_15 X X 0 0 0 0 X X Reserved N/A X X X X X X X X X X 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 Group B 13-bit V VOUTB_7 X X X X X X X X X X 0 0 1 1 0 1 1 1 Group C 13-bit V/I VOUTC_7, IOUTC_7 X X X X X X X X X X 0 0 1 1 1 0 0 1 Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout IOUTD_7 N/A X X 0 0 0 0 X X 0 0 0 0 X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X 0 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 Group A 13-bit V CHANNEL 7 22 21 20 0x10 0000 8 4 2 1 VOUTA_8 VOUTA_10 N/A Group A 13-bit V CHANNEL FUNCTIONS (Channels 4 to 7) 23 Bit # Hex Multiplier Binary Position N/A N/A N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I : 0.5mA to 2.05mA 0.8mA to 1.6mA N/A N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I : 0.5mA to 2.05mA 0.8mA to 1.6mA N/A -3.5 to +13.75V (16.75V Max Swing) N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I : 0.5mA to 2.05mA 0.8mA to 1.6mA N/A N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I : 0.5mA to 2.05mA 0.8mA to 1.6mA N/A (continued next page) Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. Table 4. Address Map (8 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/06 21 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) FORMAT = 1 GROUP B DACs GROUP D DACs GROUP C DACs PINCAST SET FUNCTIONS GROUP A DACs All DACs 23 22 21 20 0x10 0000 8 4 2 1 Bit # Hex Multiplier Binary Position Item DAC Output Pin Name Parallel Load of All DACs All DAC Output Pins 19-16 0x01 0000 8 - 1 Register R2 X 15-12 0x1000 8 - 1 11 8 10 9 0x0100 4 2 8 7 6 5 4 3 2 1 0 1 8 4 2 1 8 4 2 1 C1 0 C0 0 A3 0 A2 0 A1 0 A0 X Data R1 R0 X X D12 D11 - D8 X X D7 - D4 X D3 X D2 X D1 X D0 X M1 1 M0 0 Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTA_0 VOUTA_1 VOUTA_4 VOUTA_5 VOUTA_8 VOUTA_9 VOUTA_12 VOUTA_13 X X X X X X X X X X PS0 1 PS2 PS1 0 0 0 X Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTA_2 VOUTA_3 VOUTA_6 VOUTA_7 VOUTA_10 VOUTA_11 VOUTA_14 VOUTA_15 X X X X X X X X X X PS0 1 PS2 PS1 0 0 1 X Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB) across multiple E6435 devices. VOUTB_0 VOUTB_1 VOUTB_2 VOUTB_3 VOUTB_4 VOUTB_5 VOUTB_6 VOUTB_7 X X X X X X X X X X PS0 1 PS2 PS1 0 1 1 X Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). VOUTC_0 VOUTC_1 VOUTC_2 VOUTC_3 VOUTC_4 VOUTC_5 VOUTC_6 VOUTC_7 or IOUTC_0 IOUTC_1 IOUTC_2 IOUTC_3 IOUTC_4 IOUTC_5 IOUTC_6 IOUTC_7 X X X X X X X X X X PS0 1 PS2 PS1 1 0 0 X Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). IOUTD_0 IOUTD_1 IOUTD_2 IOUTD_3 IOUTD_4 IOUTD_5 IOUTD_6 IOUTD_7 X X X X X X X X X X PS0 1 PS2 PS1 1 0 1 X Table 4. Address Map (8 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/06 22 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Digital Inputs DAC Value Readback via DAC_OUT All digital inputs are LV_TTL compatible inputs. Voltage Outputs Digital Outputs Each voltage output of the Edge6435/6436 has high impedance FET(s) connected from the outputs to a common analog line, DAC_OUT, that provides readback of each DAC’s value. The primary purpose of this feature is to provide means for diagnostics of correct DAC functionality in an application that can monitor DAC_OUT, and is not intended for DAC calibration. SDOUT and LDOUT are CMOS outputs that switch between DGND and DVDD. Power Supply Sequence Power supplies must be controlled such that they maintain correct polarity with respect to each other and ground at all times during power-up and power-down. The following sequence is recommended: 1. 2. 3. 4. The feature utilizes the normal address decoding, as shown in Tables 3 and 4, as well as a "high" level on the TEST_MODE pin (see truth table below). AVEE AVCC AVDD, VREF DVDD TEST_MODE DAC_OUT 0 Off 1 On NOTE: A CLK input is not required to change the state of the DAC_OUT pin when TEST_MODE is toggled. VOUT_CH0_1 VOUT_CH0_2 TEST_MODE VOUT_CH0_3 Address Decoder To test an output, a DAC should be loaded as described above. At this point, the DAC_OUT pin, which is an analog output, will reflect the voltage at the addressed DAC's output pin. Note that DAC_OUT is switched off when the parallel load is selected (address 64). This prevents a parallel connection of all the DAC outputs when the scan feature is used. DAC_OUT Figure 12. DAC Voltage Output via DAC_OUT 2006 Semtech Corp. / Rev. 3, 8/25/06 23 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Current Outputs The TEST_MODE and DAC_OUT pins on the Edge6435/ 6436 are used in the same way as for voltage outputs. The scan circuits for current outputs are shown in Figure 13. The voltage measured at the DAC_OUT pin, using the configuration in Figure 13, for Group C and D current outputs are as follows: VDAC_OUT_C = (RSENSE_C + RPAD) * IOUT_C where: RSENSE_C = 160Ω ± 30% RPAD = 30Ω ± 30% The typical "ON" resistance of the FET switch is 2 kΩ, but can vary from 900Ω to 3 kΩ as a function of process and output voltage. Notes when Using DAC_OUT Feature with Multiple Chips When multiple 6435/6436s are used on a board, and it is desired to gang the DAC_OUT pins of these 6435/6436s, or gang the TEST_MODE inputs to one point, it is required to protect the 6435/6436s against damage that the following rules be followed: 1) and VDAC_OUT_D = (RSENSE_D + RPAD) * IOUT_D 2) where: If TEST_MODE inputs are ganged together, DAC_OUT cannot be ganged, or invalid results will be observed at the DAC_OUT pin and damage could occur to the device. Hence, each DAC_OUT pin on a 6435/6436 will have to be measured separately. If DAC_OUT is ganged, the TEST_MODE is used to select only one DAC at a time. RSENSE_D = 160Ω ± 30% RPAD = 30Ω ± 30% + R SENSE R PAD IOUT_CH0_0 CONNECT TO VIRTUAL GROUND – IDAC TEST_MODE + R SENSE R PAD IOUT_CH0_1 CONNECT TO VIRTUAL GROUND – IDAC + ADDRESS DECODER IDAC – R SENSE R PAD IOUT_CH0_2 CONNECT TO VIRTUAL GROUND DAC_OUT NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED. Figure 13. DAC Current Output vs DAC_OUT 2006 Semtech Corp. / Rev. 3, 8/25/06 24 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Latched Data readback via LD_OUT A DACs Rank A or Rank B latches are selcted by the RANK input for subsequent readback. Figure 14 provides a Functional Block Diagram of the means to readback, via LD_OUT, the status of latch’s input into a selected DAC. A DAC’s latches are addressed for readback in the same way they are addressed to be written via the serial input, SDIN. TESTMODE Readback is enabled internally by TESTMODE high whereupon the selected DAC’s Rank A or Rank B latch outputs are loaded into the READBACK REGISTER by a leading edge of CLKIN while SHIFTOUT* is high. With SHIFTOUT* low, subsequent clocks into CLKIN will shift out, via LD_OUT, the status of the selected DAC’s latches of Rank A or Rank B. RANK A SEL B 13 D D DAC DACSEL R R 13 READBACK REGISTER D C SHIFTOUT* C 1 LD_OUT R Figure 14. Latched Data Readback Functional Block Diagram 2006 Semtech Corp. / Rev. 3, 8/25/06 25 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Application Information Typical Supplies 0V +10.0V +5V –5V 0V +3.3V ± 2.5V 0V AGND SGND AVCC AVDD DVDD AGND AVEE DGND VREF VOUT . . . RANK 10 KΩ DAC Voltage Outputs . . . DACEN VOUT Edge6435 10 KΩ IOUT . . . RESET* DAC Current Outputs . . . IOUT GND For Group A DACs Gain and Offset Control For Group B DACs Gain and Offset Control The Selection of R_MASTER Establishes IREF IREF IREF R_IGAIN_D IREF R_IGAIN_C IREF R_OFFSET_C IREF R_VGAIN_C IREF R_OFFSET_B IREF R_VGAIN_B R_VGAIN_A GND connect to the same ground as AGND pins or may be connected to DUT GND (via switchable buffer) on a per group basis. IREF R_MASTER IREF R_OFFSET_A 10 KΩ For Group C DACs Gain and Offset Control (Voltage) NOTE: Pull-down resistors required on RANK, DACEN, and RESET* to ensure they are low upon power-up. Such resistors may be common to multiple Edge6435s. NOTE: Power Supply inputs AVCC, AVDD, DVDD and AVEE need bypass capacitors located at the inputs to the chip of 10 µF (tant.) and 0.1 µF (ceramic). Figure 15. Required External Components 2006 Semtech Corp. / Rev. 3, 8/25/06 26 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Application Information (continued) The E6435/E6436 can be configured to provide all of the DAC levels required for 4 fully-featured high-speed pin channels or 8 fully-featured low-speed pin channels when used with other Semtech pin electronics components. Channel 0 E7725 Channel 1 Since each E6435/E6436 DAC channel includes 2 sets of calibration registers, DAC channels can be shared across two distinct functions in an application to minimize the overall number of level DACs required in a system. Tables 5 and 6 show the recommended shorting scheme for a couple of possible pin electronics solutions. E6435/ E6436 E42X7 E42X7 Channel 2 E7725 High-Speed Pin Electronics Solution: Channel 3 1 – E6435/E6436 per 4 Channels 2 – E7725 Dual Channel, High Speed Pin Driver + Comparator + Load + Signal Clamp devices per 4 Channels 2 – E42X7 Dual-Channel, Parametric Measurement Unit + Clamps per 4 Channels E6435/6436 Group V/I A V A E7725 Function E42X7 Symbol Function Symbol Driver "High" Level DVH Not used N/A V Driver "Low Level DVL Not used N/A A V Upper Voltage Clamp VCH Upper Voltage Clamp HLV A V Lower Voltage Clamp VCL Lower Voltage Clamp LLV B V Comparator Threshold CVA, CVC Lower Comparator Threshold IVMIN B V Comparator Threshold CVB Upper Comparator Threshold IVMAX C V Termination Voltage C V Not used N/A Voltage/Current Programming C I Load Source Current ISC Not used N/A C I Load Sink Current ISK Not used N/A D I Driver "+" Slew Rate Adjust RADJ Not used N/A D I Driver "–" Slew Rate Adjust FADJ Not used N/A DVT, VCM Not used N/A VINP Table 5. E6435/E6436 Per-Channel DAC Connectivity for High-Speed Pin Driver, Comparator, Clamp and Load Solution Featuring Differential Capability and Fast Settling PMU Per Pin 2006 Semtech Corp. / Rev. 3, 8/25/06 27 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Application Information (continued) Channel 0 Low-Speed Pin Electronics Solution: Channel 1 E7804 Channel 2 1 – E6435/E6436 per 8 Channels 2 – E7804 Quad Channel, Driver + Comparator + CTC per 8 Channels devices per 4 Channels 4 – E42X7 Dual-Channel, Parametric Measurement Unit + Clamps per 8 Channels Channel 3 E42X7 E42X7 E42X7 E42X7 E6435/ E6436 Channel 4 Channel 5 E7804 Channel 6 Channel 7 E6435/6436 E7804 E42X7 Group V/I Interconnect Circuit Function Symbol Function Symbol A V None required Driver "High" Level DVH Voltage/Current Programming VINP A V None required Driver "Low" Level DVL Comparator Threshold IVMIN B V None required Comparator Threshold CVA Comparator Threshold IVMAX C V None required Comparator Threshold CVB Upper Voltage Clamp HLV D(0)* I I to V Converter Continuity Test Circuit CTCFIV Lower Voltage Clamp LLV D(1)* I I to V Converter Continuity Test Voltage CTCLV Not used N/A D(2)* I I to V Converter Pull-up Voltage PVP Not used N/A D(3-7)* I None required Not used N/A Not used N/A *D(0), D(1), D(n) correspond to DAC channels that are used for common continuity test voltage/current programming values across multiple E7804 devices and are shared with the lower voltage clamp threshold on the E42X7. Table 6. E6435/E6436 Per-Channel DAC Connectivity for Low-Speed Pin Driver, Comparator, Continuity Test Circuit, and Per-Pin PMU Solution 2006 Semtech Corp. / Rev. 3, 8/25/06 28 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Package Information Figure 16. 14 x 20 x 2.0 mm, 100-Pin MQFP (with Internal Heat Spreader, Requires Heat Sink) N PIN Descriptions .30 RAD. TYP. 1 .20 RAD. TYP. θ1 –A– –B– D1 D STANDOFF A A1 .25 SEATING PLANE θ .17 MAX L –C– b LEAD COPLANARITY ddd M C A–B S D S ccc C –D– BODY + 3.2mm FOOTPRINT, 2.0mm THICK E1 E DIMS. ˚ 10 Typ. A A2 e TOLS. A Max. 2.35 A1 Max. .25 A2 ±.10 2.00 D ±.20 23.20 D1 ±.10 20.00 E ±.20 17.20 E1 ±.10 14.00 L ±0.15 .88 e Basic .65 A1 ˚ 10 Typ. Notes: 1. All dimensions in millimeters (mm). 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length “L” is measured at gage plane 0.25mm above the seating plane. 4. Use MS-022 variation GA-1 for body dimensions. 5. Use MO-112 variation CA-1 for body dimensions. 6. Use variation GA-1 for lead form options and BB for body dime. 7. Use variation GB-1 for lead form options and BB for body dime. 8. Use variation GC-1 for lead form options and BB for body dime. 9. Use MS-022 variation BB for body dimensions. 10. N.J.R. means no single JEDEC reference putline or standard. 2006 Semtech Corp. / Rev. 3, 8/25/06 b 0.24~0.38 θ 0˚ – 7˚ θ1 ±.4˚ 6˚ ddd Nom. .12 ccc Max .10 JEDEC Ref. Dwg. Variation Designator 29 Note 8 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions Parameter Symbol Min Typ Max Units Positive Analog Power Supply AVCC +8.0 +10.0 +15.0 V Positive Analog Power Supply 2 AVDD +4.75 +5.0 +5.25 V Negative Power Supply 1 AVEE –5.25 –5.0 –4.75 V Reference Voltage VREF 2.499 2.501 V Total Analog Supply 1 AVCC – AVEE 12.75 20.25 V Digital Power Supply DVDD – DGND 3.0 +5.25 V DGND –0.5 +0.5 V Digital Ground Thermal Resistance of Package Junction to Case Junction to Ambient Still Air 100 lfpm 400 lfpm Case Temperature θJC θJA TCASE 25 0 12.4 ˚C/W 28 25.2 22.1 ˚C/W ˚C/W ˚C/W 65 ˚C NOTE: All supplies are referenced to AGND unless otherwise noted. 2006 Semtech Corp. / Rev. 3, 8/25/06 30 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Absolute Maximum Ratings Parameter Symbol Min Max Units Positive Analog Supply Positive Analog Supply 2 Negative Analog Supply AVCC AVDD AVEE –0.5 –5.5 +16 +5.5 +0.5 V V V Digital Power Supply DVDD –0.5 +5.5 V AVCC – AVEE AVCC –AVDD AGND AGND AGND VREF –0.5 –0.5 –0.5 –5.5 –0.5 AGND – 0.5 +21.5 +16.0 +5.5 +0.5 +0.5 AVDD + 0.5 V V V V V V SDIN, CLKIN, LOAD, STORE, UPDATE, SELVIC, RANK, RESET* DGND – 0.5 DGND – 0.5 DVDD + 0.5 +5.5 V V VREF[1:4], VMASTER, VOFFSET_[A:C], VGAIN_[A:C] AGND – 0.5 AVDD + 0.5 V IGAIN_[C:D] IMASTER –100 –100 +100 +100 µA µA Analog Output Voltages Groups A, B, C VOUT_[A:C] AVEE – 0.5 AVCC + 0.5 V Analog Output Currents Groups A, B, C Continuous DC Current IOUT_[A:C] –300 +300 µA TA TS TJ TSOL 0 –65 +125 +150 +125 +260 ˚C ˚C ˚C ˚C Total Power Supply Digital Input Voltages DVDD < 5.0V DVDD > 5.0V Analog Input Voltages Analog Input Currents Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin) NOTE: All supplies are referenced to AGND unless otherwise noted. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2006 Semtech Corp. / Rev. 3, 8/25/06 31 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS DC Characteristics Parameter Symbol Digital Inputs (SDIN, CLKIN, LOAD, STORE, UPDATE, RANK, RESET*, TESTMODE, DACEN, FORMAT) Input Low Voltage Input High Voltage 3.0V ≤ DVDD ≤ 3.3V 3.3V < DVDD ≤ 5.25V Input Current VIL VIH IIL, IIH Digital Outputs (SDOUT, LDOUT) Output Low Voltage Output High Voltage Output Current Low Output Current High VOL VOH IOL IOH Min Typ 2.0 2.6 –1 Max Units 0.8 V 1 V V µA 0.4 DVDD 1.6 –0.4 V V mA mA 13 Bits 2.4 DAC Voltage Outputs Groups A, B, and C (Voltage Outputs) Resolution Output Voltage Range VOUT_RANGE AVEE + 1.25 AVCC – 1.25 V Output Voltage Span VOUT_SPAN 8.0 16.75 V Output Offset Range VOFFSET –3.5 –0.75 V ICOMPLIANCE –200 +200 µA Range Error (Figure 17) FS_ERROR –215 +215 mV Offset Error (Figure 17) VOS –35 +35 mV –4 –8 +4 +8 LSB LSB –4 –8 +4 +8 LSB LSB Output Current Compliance Integral Linearity Error following 2-Point Calibration 20% - 80% Calibration Points (Figure 18) E6436 DACs E6435 DACs Endpoint Calibration Points (Figure 19) E6436 DACs E6435 DACs Integral Linearity Error following 7-Point Calibration (Calibration Points: 0, 1365, 2730, 4095, 5460, 6825, 8191) INL –2 2 LSB Differential Linearity Error (Figure 19) DNL –1 +1 LSB Gain TempCo 250 µV/˚C Offset Error TempCo 250 µV/˚C DAC Disabled Output Voltage (DACEN = 0) DAC Interaction (DC Channel-to-Channel Crosstalk) 2006 Semtech Corp. / Rev. 3, 8/25/06 32 –100 +100 mV –1 +1 mV www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Parameter Symbol Min Group C (Current Outputs) Resolution Output Current Range IOUT Integral Linearity Error following Calibration (Figure 18) 20% - 80% Calibration Points (Figure 18) Endpoint Calibration Points (Figure 19) INL Diffrential Linearity Error (Figure 19) DNL Range Error (Figure 17) IOS DAC Disabled Output Current mA –0.2 3.0 V –7 –7 +7 +7 LSB LSB –1 1 LSB –70 +70 µA –20 + 20 –20 Group D (Current Outputs) Resolution Bits 2.05 Offset Error TempCo µA –130 pA/˚C 30 pA/˚C 0 +20 µA 6 IOUT Output Voltage Compliance Integral Linearity Error following Calibration (Figure 18) 20% - 80% Calibration Points (Figure 18) Endpoint Calibration Points (Figure 19) INL Differential Linearity Error (Figure 20) DNL Range Error (Figure 17) Offset Error (Figure 17) Units 0.5 Gain TempCo Output Current Range Max 13 Output Voltage Compliance Offset Error (Figure 17) Typ IOS Bits 0.8 1.6 mA –0.2 3.0 V –0.075 –0.075 +0.075 +0.075 LSB LSB –0.025 +0.025 LSB –70 +70 µA 20 µA –20 0 Gain TempCo 50 pA/˚C Offset Error TempCo 30 pA/˚C DAC Disabled Output Current 2006 Semtech Corp. / Rev. 3, 8/25/06 –20 33 0 +20 µA www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) DAC Output (Voltage or Current) Maximum Range Range Error = Deviation of Real DAC Output from Ideal DAC Output at Max Code ID EA L Real Transfer Characteristic is somewhere between "dotted" lines Min Code Max Code DAC Code Minimum Range Offset Error = Deviation of Real DAC from Ideal DAC at Min Code Range error and offset error are due to E6435/6436 only. External resistor tolerances and VREF tolerance not included. Figure 17. Representation of DAC Offset Error and Range Error for 13-Bit DACs (6-bit DACs similar) DAC Output (Voltage or Current) Maximum Range Min Code St ra igh tl in e th ro ug h2 0 % an d 80 % Po in ts Measured DAC output at 80% of Max Code Max Code DAC Code DAC Integral Non-Linearity (INL) Measured DAC Output at 20% of Max Code Minimum Range Figure 18. Representation of 2-Point DAC Integral Non-Linearity (INL) 2006 Semtech Corp. / Rev. 3, 8/25/06 34 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) DAC Output (Voltage or Current) Maximum Range nt s Measured DAC output at Max Code St ra i gh tl in e th ro u gh En d Po i DAC Integral Non-Linearity (INL) Min Code Max Code DAC Code Minimum Range Measured DAC Output at Min Code Figure 19. Representation of 2-Point DAC Integral Non-Linearity (INL) DAC Output (LSB) 14 Measured DAC output must not change by more than ± DNL specification limits between adjacent DAC codes across the entire DAC range 13 12 11 10 9 8 7 6 5 4 3 2 1 n+14 n+13 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+2 n n+1 DAC Code Figure 20. Representation of Differential Non-Linearity (DNL) 2006 Semtech Corp. / Rev. 3, 8/25/06 35 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Power Supplies Parameter Symbol Min Typ Max Units Power Supply Consumption (Note 1) Positive Analog Supply (AVCC) ICC 15 20 mA Positive Analog Supply (AVDD) IADD 20 30 mA Digital Supply (DVDD) 3.0V ≤ DVDD ≤ 3.3V 3.3V < DVDD ≤ 5.25V IDDD 250 500 800 µA µA Negative Power Supply (AVEE) IEE –50 Reference Supply IREF –0.2 Note 1: –30 mA +0.2 µA CLKIN Low, quiescent. Parameter Power Supply Rejection Ratio Symbol Min Max Units PSRR AVCC to any DAC Output DC 100 kHz 500 kHz 1 MHz –88 AVEE to any DAC Output DC 100 kHz 500 kHz 1 MHz –27 –20 –18 dB dB dB dB –8 –5 –13 dB dB dB dB –3 –18 –26 dB dB dB dB –66 AVDD to any DAC Output DC 100 kHz 500 kHz 1 MHz 2006 Semtech Corp. / Rev. 3, 8/25/06 Typ –62 36 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS AC Characteristics Parameter Symbol Min Typ Max Units TSU_SDI TSU_LD TSU_STR TSU_UPD TSU_RST TSU_DEN TSU_SOUT 2 2 2 2 2 2 2 ns ns ns ns ns ns ns SDIN (to CLKIN rising edge) THLD_SDI 2 ns LOAD STORE THLD_LD 2 2 ns ns 2 ns 2 ns Digital Inputs Set Up Times (to CLKIN rising edge) SDIN LOAD STORE UPDATE RESET* DACEN SHIFTOUT* Hold Times UPDATE SHIFTOUT* Output Times (to CLKIN Rising Edge) SDOUT LDOUT CLKIN Fmax DVDD = 3.0V to 3.3V DVDD = 4.75V to 5.25V THLD_STR THLD_UPD THLD_SOUT TO_SDOUT TO_LDOUT 18 18 ns ns 60 80 MHz MHz Fmax Clock Spacing Clock Width CS_CK CW_CK 5 5 ns ns RESET Pulse Width PWRESET 3 ns DAC Output Settling Time (Note 2) Full-Scale Step (DAC Code 0 to 8191) Voltage DACs (Groups A, B, C) 16V Range Settling to Specified Linearity Error Settling to ±0.5% FSR 8V Range Settling to Specified Linearity Error Settling to ±0.5% FSR Vsettle Current DACs Grroup C Settling to Specified Linearity Error Settling to ±0.5% FSR Grroup D (Full-Scale Step, DAC Code 0 to 63) Settling to Specified Linearity Error Settling to ±0.5% FSR DAC_OUT Readback Time (Note 1) 2.3 65 50 µs µs 30 30 µs µs 45 35 µs µs 40 30 µs µs 5 µs Voltage DAC Output Enable Time (Note 4) Vtoe 4 µs Voltage DAC Output Disable Time (Note 5) Vtz 18 µs Current DAC Output Enable Time (Note 4) Itoe 1.5 µs Current DAC Output Disable Time (Note 6) Itz 7 µs Trank 1.5 µs Rank Transition Time (Note 3) 2006 Semtech Corp. / Rev. 3, 8/25/06 37 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: DAC_OUT Readback Time is the amount of time required for DAC_OUT to display a valid voltage for a selected (and fully settled) DAC channel and only includes channel-to-channel switching time. Measured from CLKIN using edge of update to specified accuracy. Rank Transition Time is a measurement of the time required to change between Rank A and Rank B latches and does not include DAC Output Settling time. DAC Output Enable Time is measured after DACEN is transitioned from 0 to 1 from the rising edge of the clock signal applied to CLKIN as the time required for the DAC output to change by 10%. Voltage DAC output disable time is measured from the falling edge of DACEN as the amount of time required for the DAC output to change from positive full-scale to 0.5V. Current DAC Output Disable Time is measured from the falling edge of DACEN as the amount of time required for the DAC output to change by 10%. C CK24 CLKIN TSU_LD THLD_LD LOAD 3C 16C TSU_STR 2C THLD_STR STORE TSU_STR UPDATEA (Internal) TSU_UPD THLD_UPD UPDATE _ _ _ _ _ _ _ TSU_UPD RANK _ _ _ _ _ _ _ _ TSU_RNK THLD_RNK TSU_RNK THLD_RNK Valid Data A0 SDIN ≈ ≈ Figure 21. Individual DAC Storing and DAC Updating (RESET* high) TSU_SDI TSU_SDI THLD_SDI ≈ THLD_SDI CKIN Valid Data R2 CK24 CK1 TO_SDOUT Previous A0 SDOUT A1 Figure 22. Shift Register Loading Timing Diagram 2006 Semtech Corp. / Rev. 3, 8/25/06 38 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) CLKIN TSU_RST TSU_DEN RESET* DACEN Figure 23. RESET* and DACEN Timing STORE or UPDATE ≥1C RANK, TESTMODE > 0 ns LOAD ≥1C CLKIN TSU_SOUT THLD_SOUT TSU_SOUT SHIFTOUT* TO_LDOUT D0 LDOUT D1 Figure 24. SHIFTOUT*, LDOUT Timing 2006 Semtech Corp. / Rev. 3, 8/25/06 39 www.semtech.com Edge6435/6436 TEST AND MEASUREMENT PRODUCTS Ordering Information Model Number Package E6435BHFT 14 x 20 x 2 mm, 100 Pin MQFP (with Internal Heat Spreader) EVM6435 Edge6435 Evaluation Board E6436BHFT 14 x 20 x 2 mm, 100 Pin MQFP (with Internal Heat Spreader) EVM6436 Edge6436 Evaluation Board Pb This product is lead-free. Contact Information Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 2006 Semtech Corp. / Rev. 3, 8/25/06 40 www.semtech.com