MICROCHIP PIC12F510

PIC12F510/16F506
Data Sheet
8/14-Pin, 8-Bit Flash Microcontrollers
© 2007 Microchip Technology Inc.
DS41268D
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•
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•
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•
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•
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In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
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© 2007, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41268D-page ii
© 2007 Microchip Technology Inc.
PIC12F510/16F506
8/14-Pin, 8-Bit Flash Microcontroller
Devices Included In This Data Sheet:
• PIC16F506
• PIC12F510
High-Performance RISC CPU:
• Only 33 Single-Word Instructions to Learn
• All Single-Cycle Instructions except for Program
Branches, which are Two-Cycle
• 12-Bit Wide Instructions
• Two-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
• 8-Bit Wide Data Path
• 10 Special Function Hardware Registers
(PIC12F510)
• 13 Special Function Hardware Registers
(PIC16F506)
• Operating Speed:
- DC – 8 MHz Crystal Oscillator (PIC12F510)
- DC – 500 ns instruction cycle (PIC12F510)
- DC – 20 MHz Crystal Oscillator (PIC16F506)
- DC – 200 ns instruction cycle (PIC16F506)
Special Microcontroller Features:
• 4 or 8 MHz Selectable Precision Internal
Oscillator:
- Factory calibrated to ±1%
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) Support
• Power-on Reset (POR)
• Device Reset Timer (DRT):
- Short DRT (1.125 ms, typical) for INTOSC,
EXTRC and EC
- DRT (18 ms, typical) for HS, XT and LP
• Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
• Programmable Code Protection
• Multiplexed MCLR Input Pin
• Selectable Internal Weak Pull-Ups on I/O Pins
• Power-Saving Sleep mode
• Wake-up from Sleep on Pin Change
• Wake-up from Sleep on Comparator Change
© 2007 Microchip Technology Inc.
• Selectable Oscillator Options:
- INTOSC: 4/8 MHz precision Internal
oscillator
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- LP: Power-saving, low-frequency crystal
- HS: High-speed crystal/resonator
(PIC16F506 only)
- EC: High-speed external clock input
(PIC16F506 only)
• Analog-to-Digital (A/D) Converter:
- 8-bit resolution
- 4-input channels (1 channel is dedicated to
conversion of the internal 0.6V absolute
voltage reference)
• High Current Sink/Source for Direct LED Drive
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
Low-Power Features/CMOS Technology:
• Operating Current:
- < 175 μA @ 2V, 4 MHz, typical
• Standby Current:
- 100 nA @ 2V, typical
• Low-Power, High-Speed Flash Technology:
- 100,000 cycle Flash endurance
- > 40-year retention
• Fully Static Design
• Wide Operating Voltage Range: 2.0V to 5.5V
• Wide Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Peripheral Features (PIC12F510):
• 6 I/O Pins:
- 5 I/O pins with individual direction control
- 1 input only pin
• 1 Analog Comparator with Absolute Reference
Peripheral Features (PIC16F506):
• 12 I/O Pins:
- 11 I/O pins with individual direction control
- 1 input only pin
• 2 Analog Comparators with Absolute Reference
and Programmable Reference
DS41268D-page 1
PIC12F510/16F506
Program Memory
Data Memory
Flash (words)
SRAM (bytes)
PIC16F506
1024
PIC12F510
1024
Device
I/O
Timers
8-bit
67
12
1
38
6
1
Pin Diagrams
PDIP, SOIC and TSSOP
VSS
12
RB1/AN1/C1IN-/ICSPCLK
11
RB2/AN2/C1OUT
10
RC0/C2IN+
9
RC1/C2IN-
7
8
RC2/CVREF
VDD
1
GP4/OSC2
2
3
8
7
VSS
GP5/OSC1/CLKIN
6
GP1/AN1/C1IN-/ICSPCLK
GP3/MCLR/VPP
4
5
GP2/AN2/T0CKI/C1OUT
1
2
RB4/OSC2/CLKOUT
3
RB3/MCLR/VPP
RC5/T0CKI
4
5
RC4/C2OUT
6
RC3
PIC16F506
14
13
VDD
RB5/OSC1/CLKIN
RB0/AN0/C1IN+/ICSPDAT
PIC12F510
PDIP, SOIC, MSOP
GP0/AN0/C1IN+/ICSPDAT
DS41268D-page 2
VDD
1
GP5/OSC1/CLKIN
2
GP4/OSC2
3
GP3/MCLR/VPP
4
PIC12F510
DFN
8
VSS
7
GP0/AN0/C1IN+/ICSPDAT
6
GP1/AN1/C1IN-/ICSPCLK
5
GP2/AN2/T0CKI/C1OUTI
© 2007 Microchip Technology Inc.
PIC12F510/16F506
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC12F510/16F506 Device Varieties .......................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 15
5.0 I/O Port ....................................................................................................................................................................................... 27
6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 39
7.0 Comparator(s) ............................................................................................................................................................................ 43
8.0 Comparator Voltage Reference Module (PIC16F506 only)........................................................................................................ 49
9.0 Analog-to-Digital (A/D) Converter............................................................................................................................................... 51
10.0 Special Features Of The CPU.................................................................................................................................................... 55
11.0 Instruction Set Summary ............................................................................................................................................................ 71
12.0 Development Support................................................................................................................................................................. 79
13.0 Electrical Characteristics ............................................................................................................................................................ 83
14.0 DC and AC Characteristics Graphs and Charts ......................................................................................................................... 97
15.0 Packaging................................................................................................................................................................................. 105
Index .................................................................................................................................................................................................. 117
The Microchip Web Site ..................................................................................................................................................................... 119
Customer Change Notification Service .............................................................................................................................................. 119
Customer Support .............................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
Product Identification System ............................................................................................................................................................ 121
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© 2007 Microchip Technology Inc.
DS41268D-page 3
PIC12F510/16F506
NOTES:
DS41268D-page 4
© 2007 Microchip Technology Inc.
PIC12F510/16F506
1.0
GENERAL DESCRIPTION
The PIC12F510/16F506 devices from Microchip
Technology are low-cost, high-performance, 8-bit, fullystatic, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are singlecycle except for program branches, which take two
cycles. The PIC12F510/16F506 devices deliver
performance in an order of magnitude higher than their
competitors in the same price category. The 12-bit wide
instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy-to-use and easyto-remember instruction set reduces development time
significantly.
1.1
Applications
The PIC12F510/16F506 devices fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or
surface mounting, make these microcontrollers perfect
for applications with space limitations. Low-cost, lowpower, high-performance, ease-of-use and I/O flexibility make the PIC12F510/16F506 devices very versatile, even in areas where no microcontroller use has
been considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
The PIC12F510/16F506 products are equipped with
special features that reduce system cost and power
requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for
external Reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F506),
including INTOSC Internal Oscillator mode and the
Power-Saving LP (Low-power) Oscillator mode.
Power-Saving Sleep mode, Watchdog Timer and
code protection features improve system cost, power
and reliability.
The PIC12F510/16F506 devices allow the customer to
take full advantage of Microchip’s price leadership in
Flash programmable microcontrollers, while benefiting
from the Flash programmable flexibility.
The PIC12F510/16F506 products are supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a ‘C’ compiler, a low-cost
development programmer and a full featured programmer. All the tools are supported on IBM® PC and
compatible machines.
TABLE 1-1:
PIC12F510/16F506 DEVICES
PIC16F506
Clock
Maximum Frequency of Operation (MHz)
Memory
Flash Program Memory (words)
Data Memory (bytes)
Peripherals
Timer Module(s)
Wake-up from Sleep on Pin Change
Features
I/O Pins
Input Only Pin
PIC12F510
20
8
1024
1024
67
38
TMR0
TMR0
Yes
Yes
11
5
1
1
Internal Pull-ups
Yes
Yes
In-Circuit Serial Programming
Yes
Yes
Number of Instructions
33
33
14-pin PDIP, SOIC,
TSSOP
8-pin PDIP, SOIC, MSOP,
DFN
Packages
The PIC12F510/16F506 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC12F510/16F506 devices use serial programming with data pin RB0/GP0 and clock pin RB1/GP1.
© 2007 Microchip Technology Inc.
DS41268D.-page 5
PIC12F510/16F506
NOTES:
DS41268D.-page 6
© 2007 Microchip Technology Inc.
PIC12F510/16F506
2.0
PIC12F510/16F506 DEVICE
VARIETIES
A variety of packaging options are available. Depending on application and production requirements, the
proper device option can be selected using the
information in this section. When placing orders, please
use the PIC12F510/16F506 Product Identification
System at the back of this data sheet to specify the
correct part number.
2.1
Quick Turn Programming (QTP)
Devices
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices, but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
© 2007 Microchip Technology Inc.
DS41268D-page 7
PIC12F510/16F506
NOTES:
DS41268D-page 8
© 2007 Microchip Technology Inc.
PIC12F510/16F506
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12F510/16F506
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors.
The PIC12F510/16F506 devices use a Harvard architecture in which program and data are accessed on
separate buses. This improves bandwidth over traditional von Neumann architectures where program and
data are fetched on the same bus. Separating program
and data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have all
single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single
cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33)
execute in a single cycle (200 ns @ 20 MHz, 1 μs @
4 MHz) except for program branches.
Table 3-1 lists program memory (Flash) and data
memory (RAM) for the PIC12F510/16F506 devices.
TABLE 3-1:
Device
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single-operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1 for
PIC12F510 with the corresponding device pins
described in Table 3-2. A simplified block diagram for
PIC16F506 is shown in Figure 3-2 with the
corresponding device pins described in Table 3-3.
PIC12F510/16F506 MEMORY
Memory
Program
Data
PIC12F510
1024 x 12
38 x 8
PIC16F506
1024 x 12
67 x 8
The PIC12F510/16F506 devices can directly or indirectly address its register files and data memory. All
Special Function Registers (SFRs), including the PC,
are mapped in the data memory. The PIC12F510/
16F506 devices have a highly orthogonal (symmetrical) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of “special
optimal situations” make programming with the
PIC12F510/16F506 devices simple, yet efficient. In
addition, the learning curve is reduced significantly.
The PIC12F510/16F506 devices contain an 8-bit ALU
and working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
© 2007 Microchip Technology Inc.
DS41268D-page 9
PIC12F510/16F506
FIGURE 3-1:
PIC12F510 SERIES BLOCK DIAGRAM
10-11
Flash
8
Data Bus
Program Counter
GPIO
GP0/ICSPDAT
GP1/ICSPCLK
GP2
GP3
GP4
GP5
1K x 12
Program
Bus
RAM
STACK 1
Program
Memory
38 bytes
STACK 2
File
Registers
12
RAM Addr
9
Addr MUX
Instruction Reg
Direct Addr
5
5-7
Indirect
Addr
FSR Reg
STATUS Reg
8
3
Device Reset
Timer
OSC1/CLKIN
OSC2
Instruction
Decode &
Control
Power-on
Reset
Timing
Generation
Watchdog
Timer
Internal RC
Clock
MUX
ALU
8
W Reg
Timer0
MCLR
Comparator
VDD, VSS
C1IN+
C1INC1OUT
CVREF
8-bit ADC
AN0
AN1
AN2
T0CKI
DS41268D-page 10
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 3-2:
PIN DESCRIPTIONS – PIC12F510
Name
I/O/P Type
Input Type
Output
Type
GP0/AN0/C1IN+/ICSPDAT
GP0
TTL
CMOS
Description
Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
AN0
AN
—
ADC channel input.
C1IN+
AN
—
Comparator input.
ICSPDAT
ST
CMOS
In-Circuit Serial Programming data pin.
GP1
TTL
CMOS
Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
GP1/AN1/C1IN-/ICSPCLK
AN1
AN
—
ADC channel input.
C1IN-
AN
—
Comparator input.
ICSPCLK
ST
—
In-Circuit Serial Programming clock pin.
GP2
TTL
CMOS
AN2
AN
—
ADC channel input.
T0CKI
ST
—
Timer0 clock input.
C1OUT
—
CMOS
Comparator output.
GP3
TTL
—
Standard TTL input. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
MCLR
ST
—
MCLR input – weak pull-up always enabled in
this mode.
VPP
HV
—
Programming Voltage input.
GP4
TTL
CMOS
Bidirectional I/O port.
OSC2
—
XTAL
XTAL oscillator output pin.
GP2/AN2/T0CKI/C1OUT
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
GP5
TTL
CMOS
OSC1
XTAL
—
Bidirectional I/O port.
Bidirectional I/O port.
XTAL oscillator input pin.
CLKIN
ST
—
EXTRC Schmitt Trigger input.
VDD
VDD
P
—
Positive supply for logic and I/O pins.
VSS
VSS
P
—
Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input, AN = Analog Voltage, HV = High Voltage
© 2007 Microchip Technology Inc.
DS41268D-page 11
PIC12F510/16F506
FIGURE 3-2:
PIC16F506 SERIES BLOCK DIAGRAM
10
Flash
1K x 12
Program
Memory
PORTB
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RB3
RB4
RB5
RAM
67 bytes
File
Registers
STACK 1
STACK 2
Program
Bus
8
Data Bus
Program Counter
10
RAM Addr
9
PORTC
Addr MUX
Instruction Reg
Direct Addr
5
5-7
RC0
RC1
RC2
RC3
RC4
RC5
Indirect
Addr
FSR Reg
STATUS Reg
8
3
Device Reset
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decode &
Control
Power-on
Reset
Timing
Generation
Watchdog
Timer
Internal RC
Clock
Comparator 1
MUX
C1IN+
C1INC1OUT
0.6V Reference
C2IN+
ALU
Comparator 2
8
C2INC2OUT
W Reg
CVREF
CVREF
CVREF
Timer0
AN0
MCLR
VDD, VSS
8-bit ADC
AN1
AN2
T0CKI
DS41268D-page 12
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 3-3:
PIN DESCRIPTIONS – PIC16F506
Name
Function
Input Type
Output
Type
RB0/AN0/C1IN+/ICSPDAT
RB0
TTL
CMOS
Description
Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
AN0
AN
—
ADC channel input.
C1IN+
AN
—
Comparator 1 input.
ICSPDAT
ST
CMOS
In-Circuit Serial Programming data pin.
RB1
TTL
CMOS
Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
RB1/AN1/C1IN-/ICSPCLK
AN1
AN
—
ADC channel input.
C1IN-
AN
—
Comparator 1 input.
ICSPCLK
ST
—
In-Circuit Serial Programming clock pin.
RB2/AN2/C1OUT
RB2
TTL
CMOS
AN2
AN
—
C1OUT
—
CMOS
RB3
TTL
—
Standard TTL input. Can be software programmed
for internal weak pull-up and wake-up from Sleep
on pin change.
MCLR
ST
—
MCLR input – weak pull-up always enabled in this
mode.
Programming voltage input.
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
Bidirectional I/O port.
ADC channel input.
Comparator 1 output.
VPP
HV
—
RB4
TTL
CMOS
Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up
from Sleep on pin change.
OSC2
—
XTAL
XTAL oscillator output pin.
CLKOUT
—
CMOS
EXTRC/INTOSC CLKOUT pin (FOSC/4).
RB5
TTL
CMOS
Bidirectional I/O port.
OSC1
XTAL
—
RB5/OSC1/CLKIN
RC0/C2IN+
RC1/C2INRC2/CVREF
XTAL oscillator input pin.
CLKIN
ST
—
RC0
TTL
CMOS
Bidirectional I/O port.
EXTRC/EC Schmitt Trigger input.
C2IN+
AN
—
Comparator 2 input.
RC1
TTL
CMOS
Bidirectional I/O port.
C2IN-
AN
—
Comparator 2 input.
RC2
TTL
CMOS
Bidirectional I/O port.
CVREF
—
AN
RC3
RC3
TTL
CMOS
Bidirectional I/O port.
RC4/C2OUT
RC4
TTL
CMOS
Bidirectional I/O port.
C2OUT
—
CMOS
Comparator 2 output.
RC5
TTL
CMOS
Bidirectional I/O port.
T0CKI
ST
—
Timer0 clock input.
VDD
VDD
P
—
Positive supply for logic and I/O pins.
VSS
VSS
P
—
Ground reference for logic and I/O pins.
RC5/T0CKI
Programmable Voltage Reference output.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input, AN = Analog Voltage, HV = High Voltage
© 2007 Microchip Technology Inc.
DS41268D-page 13
PIC12F510/16F506
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 1
Fetch INST (PC)
Execute INST (PC – 1)
EXAMPLE 3-1:
PC + 2
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTB, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41268D-page 14
© 2007 Microchip Technology Inc.
PIC12F510/16F506
MEMORY ORGANIZATION
The PIC12F510/16F506 memories are organized into
program memory and data memory. For devices with
more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using STATUS register bit PA0. For the PIC12F510 and
PIC16F506, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
4.1
FIGURE 4-1:
PC<11:0>
Only the first 1K x 12 (0000h-03FFh) are physically
implemented (see Figure 4-1). Accessing a location
above these boundaries will cause a wraparound
within the 1K x 12 space. The effective Reset vector
is a 0000h (see Figure 4-1). Location 03FFh contains
the internal clock oscillator calibration value. This
value should never be overwritten.
10
Stack Level 1
Stack Level 2
Reset Vector(1)
Program Memory Organization for
the PIC12F510/16F506
The PIC12F510/16F506 devices have a 10-bit
Program Counter (PC) capable of addressing a 2K x 12
program memory space.
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F510/16F506
CALL, RETLW
0000h
On-chip Program
Memory
User Memory
Space
4.0
512 Word
01FFh
0200h
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
Note 1:
© 2007 Microchip Technology Inc.
Address 0000h becomes the effective
Reset vector. Location 03FFh contains
the MOVLW XX internal oscillator
calibration value.
DS41268D-page 15
PIC12F510/16F506
4.2
Data Memory Organization
FIGURE 4-2:
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFRs)
and General Purpose Registers (GPRs).
FSR<5>
0
1
File Address
The Special Function Registers include the TMR0
register, the Program Counter (PCL), the STATUS
register, the I/O registers (ports) and the File Select
Register (FSR). In addition, Special Function Registers
are used to control the I/O port configuration and
prescaler options.
The General Purpose Registers are used for data and
control information under command of the instructions.
For the PIC12F510, the register file is composed of 10
Special Function Registers, 6 General Purpose
Registers and 32 General Purpose Registers accessed
by banking (see Figure 4-2).
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
07h
CM1CON0
08h
ADCON0
09h
ADRES
0Ah
General
Purpose
Registers
0Fh
For the PIC16F506, the register file is composed of 13
Special Function Registers, 3 General Purpose
Registers and 64 General Purpose Registers,
accessed by banking (see Figure 4-3).
4.2.1
PIC12F510 REGISTER
FILE MAP
20h
Addresses
map back to
addresses in
Bank 0.
2Fh
30h
10h
General
Purpose
Registers
General
Purpose
Registers
GENERAL PURPOSE REGISTER
FILE
1Fh
The General Purpose Register file is accessed either
directly or indirectly through the File Select Register
(FSR). See Section 4.8 “Indirect Data Addressing:
INDF and FSR Registers”.
FIGURE 4-3:
3Fh
Bank 0
Bank 1
Note 1: Not a physical register.
PIC16F506 REGISTER FILE MAP
FSR<6:5>
00
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
PORTB
07h
PORTC
08h
CM1CON0
09h
ADCON0
0Ah
ADRES
0Bh
CM2CON0
0Ch
VRCON
0Dh
General
Purpose
Registers
0Fh
10h
General
Purpose
Registers
1Fh
01
20h
40h
11
60h
Addresses map back to
addresses in Bank 0.
2Fh
30h
3Fh
Bank 0
10
4Fh
General
Purpose
Registers
Bank 1
50h
6Fh
General
Purpose
Registers
5Fh
70h
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Note 1: Not a physical register.
DS41268D-page 16
© 2007 Microchip Technology Inc.
PIC12F510/16F506
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (see Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY – PIC12F510
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
N/A
TRIS
I/O Control Registers (TRISGPIO)
--11 1111
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT Prescaler
1111 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
01h
TMR0
Timer0 Module Register
xxxx xxxx
02h(1)
PCL
Low Order 8 bits of PC
1111 1111
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
GPWUF
CWUF
PA0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
0001 1xxx
110x xxxx
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
1111 111-
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
1111 1100
07h
CM1CON0
08h
ADCON0
09h
ADRES
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused.
The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of
how to access these bits.
ADC Conversion Result
© 2007 Microchip Technology Inc.
xxxx xxxx
DS41268D-page 17
PIC12F510/16F506
TABLE 4-2:
Address
N/A
SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
TRIS
I/O Control Registers (TRISB, TRISC)
--11 1111
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT Prescaler
1111 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
01h
TMR0
Timer0 Module Register
xxxx xxxx
02h(1)
PCL
Low Order 8 bits of PC
03h
STATUS
04h
FSR
05h
OSCCAL
06h
07h
TO
PD
Z
DC
C
0001 1xxx
CAL3
CAL2
CAL1
CAL0
—
1111 111-
Indirect Data Memory Address Pointer
—
—
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
PORTC
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
1111 1100
CM1CON0
0Ah
ADRES
0Bh
CM2CON0
0Ch
VRCON
CAL4
100x xxxx
PORTB
ADCON0
4.3
1111 1111
PA0
CAL5
08h
2:
CWUF
CAL6
09h
Legend:
Note 1:
RBWUF
ADC Conversion Result
xxxx xxxx
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
VREN
VROE
VRR
—(2)
VR3
VR2
VR1
VR0
0011 1111
x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused.
The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of
how to access these bits.
Unimplemented bit VRCON<4> read as ‘1’.
STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 11.0 “Instruction
Set Summary”.
DS41268D-page 18
© 2007 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 4-1:
STATUS: STATUS REGISTER (PIC12F510)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
GPWUF
CWUF
PA0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GPWUF: GPIO Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6
CWUF: Comparator Reset bit
1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset
bit 5
PA0: Program Page Preselect bit
1 = Page 1 (200h-3FFh)
0 = Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is
not recommended, since this may affect upward compatibility with future products.
bit 4
TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
SUBWF:
RRF or RLF:
ADDWF:
1 = A carry occurred
1 = A borrow did not occur
Load bit with LSb or MSb, respectively
0 = A carry did not occur
0 = A borrow occurred
© 2007 Microchip Technology Inc.
DS41268D-page 19
PIC12F510/16F506
REGISTER 4-2:
STATUS: STATUS REGISTER (PIC16F506)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RBWUF
CWUF
PA0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RBWUF: PORTB Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6
CWUF: Comparator Reset bit
1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset
bit 5
PA0: Program Page Preselect bit
1 = Page 1 (200h-3FFh)
0 = Page 0 (000h-1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is
not recommended, since this may affect upward compatibility with future products.
bit 4
TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF:
SUBWF:
RRF or RLF:
1 = A carry occurred
1 = A borrow did not occur
Load bit with LSb or MSb, respectively
0 = A carry did not occur
0 = A borrow occurred
DS41268D-page 20
© 2007 Microchip Technology Inc.
PIC12F510/16F506
4.4
OPTION Register
The OPTION register is a 8-bit wide, write-only register,
that contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A Reset sets the OPTION<7:0> bits.
Note 1: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are
disabled for that pin (i.e., note that TRIS
overrides Option control of GPPU/RBPU
and GPWU/RBWU).
2: If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-3:
OPTION_REG: OPTION REGISTER (PIC12F510)
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6
GPPU: Enable Weak Pull-Ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
© 2007 Microchip Technology Inc.
x = Bit is unknown
DS41268D-page 21
PIC12F510/16F506
REGISTER 4-4:
OPTION_REG: OPTION REGISTER (PIC16F506)
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 6
RBPU: Enable Weak Pull-Ups bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0
PS<2:0>: Prescaler Rate Select bits
DS41268D-page 22
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC12F510/16F506
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4/8 MHz oscillator. It
contains seven bits for calibration.
Note:
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not change
the value. See Section 10.2.5 “Internal 4/8 MHz RC
Oscillator”.
REGISTER 4-5:
OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
x = Bit is unknown
DS41268D-page 23
PIC12F510/16F506
4.6
Program Counter
4.6.1
EFFECTS OF RESET
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS
register provides page information to bit 9 of the PC
(Figure 4-4).
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is preselected.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-4).
Instructions where the PCL is the destination or modify
PCL instructions include MOVWF PC, ADDWF PC and
BSF PC, 5.
Note:
Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
FIGURE 4-4:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
9 8 7
PC
0
PCL
7
4.7
Stack
The PIC12F510/16F506 devices have a two-deep,
12-bit wide hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of
Stack 1 into Stack 2 and then PUSH the current PC
value, incremented by one, into Stack Level 1. If more
than two sequential CALLs are executed, only the
most recent two return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2.
Note 1: The W register will be loaded with the literal value specified in the instruction. This
is particularly useful for the implementation of data look-up tables within the
program memory.
2: There are no Status bits to indicate stack
overflows or stack underflow conditions.
Instruction Word
PA0
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
3: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
0
STATUS
CALL or Modify PCL Instruction
9 8 7
PC
7
0
PCL
Instruction Word
Reset to ‘0’
PA0
0
STATUS
DS41268D-page 24
© 2007 Microchip Technology Inc.
PIC12F510/16F506
4.8
Indirect Data Addressing: INDF
and FSR Registers
EXAMPLE 4-1:
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
4.8.1
INDIRECT ADDRESSING EXAMPLE
•
•
•
•
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSC
GOTO
CONTINUE
:
:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
;YES, continue
The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
PIC16F506 – Uses FSR<6:5>. Selects from Bank 0 to
Bank 3. FSR<7> is unimplemented, read as ‘1’.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
PIC12F510 – Uses FSR<5>. Selects from Bank 0 to
Bank 1. FSR<7:6> are unimplemented, read as ‘11’.
FIGURE 4-5:
DIRECT/INDIRECT ADDRESSING (PIC12F510)
Direct Addressing
(FSR)
(opcode)
6
5
Bank Select
4
3
2
1
Indirect Addressing
(FSR)
0
6
4
Bank
Select
Location Select
00
5
01
3
2
1
0
Location Select
00h
Addresses map back to
addresses in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
3Fh
Bank 0
Note 1:
2:
Bank 1
For register map detail, see Figure 4-2.
Grey boxes are unimplemented and read as ‘1’.
© 2007 Microchip Technology Inc.
DS41268D-page 25
PIC12F510/16F506
FIGURE 4-6:
DIRECT/INDIRECT ADDRESSING (PIC16F506)
Direct Addressing
Indirect Addressing
(FSR)
6 5
(opcode)
4 3 2 1 0
Bank Select
Location Select
6
00
01
10
00h
Data
Memory(1)
Bank
0
Location Select
Addresses
map back to
addresses
in Bank 0.
0Fh
10h
1Fh
Bank 0
Note 1:
11
(FSR)
5 4 3 2 1
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 3
For register map detail, see Figure 4-3.
DS41268D-page 26
© 2007 Microchip Technology Inc.
PIC12F510/16F506
5.0
I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
Note:
5.1
On the PIC12F510, I/O PORTB is referenced as GPIO. On the PIC16F506, I/O
PORTB is referenced as PORTB.
PORTB/GPIO
PORTB/GPIO is an 8-bit I/O register. Only the loworder 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are
unimplemented and read as ‘0’s. Please note that RB3/
GP3 is an input only pin. The Configuration Word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during a port
read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4
(PIC16F506 only) can be configured with weak pull-up
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin selectable. If RB3/GP3/MCLR is configured as MCLR, weak
pull-up is always on and wake-up on change for this pin
is not enabled.
5.2
5.4
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except RB3/GP3 which is
input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input
instruction (e.g., MOVF PORTB, W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0).
For use as an input, the corresponding TRIS bit must
be set. Any I/O pin (except RB3/GP3) can be
programmed individually as input or output.
FIGURE 5-1:
Data
Bus
Data
Bus
Interface
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The exception
is RB3/GP3, which are input only, and the T0CKI pin,
which may be controlled by the OPTION register. See
Register 4-3.
Note:
A read of the port reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Note:
The TRIS registers are write-only and are
set (output drivers disabled) upon Reset.
© 2007 Microchip Technology Inc.
(1)
N
D
I/O
pin
Q
VSS
PORTC (PIC16F506 Only)
TRIS Registers
VDD VDD
P
CK
PORTC is an 8-bit I/O register. Only the low-order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
5.3
PIC12F510/16F506
EQUIVALENT CIRCUIT
FOR PIN DRIVE(2)
VSS
Q
Reset
Note 1:
2:
GP3/RB3 has protection diode to VSS only.
For pin specific information, see Figure 5-2
through Figure 5-13.
DS41268D-page 27
PIC12F510/16F506
FIGURE 5-2:
BLOCK DIAGRAM OF
GP0/RB0 AND GP1/RB1
FIGURE 5-3:
BLOCK DIAGRAM OF
GP3/RB3 (With Weak
Pull-up And Wake-up On
Change)
GPPU
RBPU
GPPU
RBPU
Data
Bus
MCLRE
D
Q
Data
Latch
WR
Port
CK
I/O Pin(1)
Q
Reset
W
Reg
D
I/O Pin(1)
Q
TRIS
Latch
TRIS ‘f’
CK
Q
Data Bus
Reset
RD Port
ADC pin Ebl
Q
COMP pin Ebl
D
CK
RD Port
Mismatch
Q
D
CK
Mismatch
ADC
COMP
Note 1:
I/O pins have protection diodes to VDD and
VSS.
DS41268D-page 28
Note 1:
GP3/MCLR pin has a protection diode to VSS
only.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-4:
BLOCK DIAGRAM OF GP2
C1OUT
Data
Bus
D
Q
0
1
C1OUT
Data
Bus
WR
Port
Q
CK
D
D
Q
TRIS ‘f’
TRIS ‘f’
Q
CK
I/O Pin(1)
1
Q
CK
C1OUTEN
W
Reg
TRIS
Latch
Q
0
Data
Latch
C1OUTEN
W
Reg
BLOCK DIAGRAM OF RB2
I/O Pin(1)
Data
Latch
WR
Port
FIGURE 5-5:
Reset
D
Q
TRIS
Latch
Q
CK
Reset
T0CS
C1T0CS
ADC Pin Enable
ADC Pin Enable
RD Port
T0CKI
RD Port
ADC
ADC
Note 1:
I/O pins have protection diodes to VDD and
VSS.
© 2007 Microchip Technology Inc.
Note 1:
I/O pins have protection diodes to VDD and
VSS.
DS41268D-page 29
PIC12F510/16F506
FIGURE 5-6:
BLOCK DIAGRAM OF RB4
FIGURE 5-7:
BLOCK DIAGRAM OF GP4
RBPU
Data
Bus
Data
Bus
D
WR
Port
Q
0
D
Q
Data
Latch
I/O
pin(1)
Q
CK
Data
Latch
WR
Port
Q
CK
I/O
pin(1)
1
W
Reg
FOSC/4
W
Reg
D
TRIS ‘f’
Q
D
Q
TRIS
Latch
Q
CK
TRIS
Latch
TRIS ‘f’
Reset
Q
CK
INTOSC/RC
Reset
INTOSC/RC/EC
CLKOUT Enable
(Note 2)
RD Port
OSC1
Oscillator
Circuit
RD Port
OSC1
Note 1:
2:
Oscillator
Circuit
I/O pins have protection diodes to VDD and VSS.
Input mode is disabled when pin is used for
oscillator.
DS41268D-page 30
Note 1:
I/O pins have protection diodes to VDD and
VSS.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-8:
Data
Bus
BLOCK DIAGRAM OF
RB5/GP5
D
Data
Bus
Q
Data
Latch
WR
Port
I/O
pin(1)
Q
CK
W
Reg
FIGURE 5-9:
D
W
Reg
Q
TRIS
Latch
TRIS ‘f’
Q
CK
WR
Port
TRIS ‘f’
BLOCK DIAGRAM OF
RC0/RC1
D
Q
Data
Latch
I/O
pin(1)
Q
CK
D
Q
TRIS
Latch
Q
CK
Reset
Reset
(Note 2)
Comp Pin Enable
RD Port
OSC2
Oscillator
Circuit
RD Port
COMP2
Note 1:
I/O pins have protection diodes to VDD and
VSS.
2: Input mode is disabled when pin is used for
oscillator.
© 2007 Microchip Technology Inc.
Note 1:
I/O pins have protection diodes to VDD and
VSS.
DS41268D-page 31
PIC12F510/16F506
FIGURE 5-10:
BLOCK DIAGRAM OF RC2
FIGURE 5-11:
BLOCK DIAGRAM OF RC3
VROE
Data
Bus
CVREF
Data
Bus
WR
Port
D
Q
1 I/O PIN(1)
WR
Port
W
Reg
Q
TRIS ‘f’
W
Reg
TRIS ‘f’
D
D
Q
Data
Latch
Q
CK
0
Data
Latch
CK
I/O Pin(1)
Q
D
Q
TRIS
Latch
Q
CK
Reset
TRIS
Latch
Q
CK
Reset
RD Port
RD Port
COMP2
Note 1:
I/O pins have protection diodes to VDD and
VSS.
DS41268D-page 32
Note 1:
I/O pins have protection diodes to VDD and
VSS.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 5-12:
BLOCK DIAGRAM OF RC4
C2OUT
Data
Bus
WR
Port
D
Q
0
BLOCK DIAGRAM OF RC5
I/O Pin(1)
1
Data
Latch
Q
CK
FIGURE 5-13:
Data
Bus
WR
Port
I/O Pin(1)
D
Q
Data
Latch
Q
CK
C2OUTEN
W
Reg
TRIS ‘f’
D
Q
TRIS
Latch
Q
CK
W
Reg
TRIS ‘f’
Reset
D
Q
TRIS
Latch
Q
CK
T0CS
Reset
RD Port
RD Port
Note 1:
I/O pins have protection diodes to VDD and
VSS.
© 2007 Microchip Technology Inc.
T0CKI
Note 1:
I/O pins have protection diodes to VDD and
VSS.
DS41268D-page 33
PIC12F510/16F506
TABLE 5-1:
Address
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
TRISGPIO(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
—
—
I/O Control Register
--11 1111
--11 1111
N/A
(2)
TRISB
—
—
I/O Control Register
--11 1111
--11 1111
N/A
TRISC(2)
—
—
I/O Control Register
--11 1111
--11 1111
N/A
OPTION
(1)
GPWU
GPPU
T0CS
TOSE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
OPTION(2)
RBWU
RBPU
T0CS
TOSE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
03h
STATUS(1)
GPWUF
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
qq0q quuu(3)
03h
STATUS
(2)
RBWUF
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
qq0q quuu(3)
06h
GPIO(1)
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
PORTB(2)
—
—
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
07h
(2)
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
N/A
PORTC
Legend:
Note 1:
2:
3:
– = unimplemented read as ‘0’, x = unknown, u = unchanged, q = depends on condition.
PIC12F510 only.
PIC16F506 only.
If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 5-2:
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
Priority
RB0
RB1
RB2
RB3
RB4
RB5
1
AN0/C1IN+
AN1/C1IN-
AN2
Input/MCLR
OSC2/CLKOUT
OSC1/CLKIN
2
TRISB
TRISB
C1OUT
—
TRISB
TRISB
3
—
—
TRISB
—
—
—
TABLE 5-3:
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
Priority
RC0
RC1
RC2
RC3
RC4
RC5
1
C2IN+
C2IN-
CVREF
TRISC
C2OUT
T0CKI
2
TRISC
TRISC
TRISC
—
TRISC
TRISC
TABLE 5-4:
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC12F510)
Priority
GP0
GP1
GP2
GP3
GP4
GP5
1
AN0/C1IN+
AN1/C1IN-
AN2
Input/MCLR
OSC2
OSC1/CLKIN
2
TRISIO
TRISIO
C1OUT
—
TRISIO
TRISIO
3
—
—
T0CKI
—
—
—
4
—
—
TRISIO
—
—
—
DS41268D-page 34
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 5-5:
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510)
GP0
GP0
GP1
GP1
GP2
GP2
GP3
GP4
GP5
C1ON
0
1
0
1
0
1
—
—
—
C1PREF
—
0
—
1
—
—
—
—
—
C1NREF
—
—
—
0
—
—
—
—
—
C1T0CS
—
—
—
—
—
1
—
—
—
C1OUTEN
—
—
—
—
—
1
—
—
—
C2ON
—
—
—
—
—
—
—
—
—
C2PREF1
—
—
—
—
—
—
—
—
—
C2PREF2
—
—
—
—
—
—
—
—
—
C2NREF
—
—
—
—
—
—
—
—
—
C2OUTEN
—
—
—
—
—
—
—
—
—
VROE
—
—
—
—
—
—
—
—
—
VREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
00, 01
00, 01
00
00
—
—
—
MCLRE
—
—
—
—
—
—
—
—
—
INTOSC
—
—
—
—
—
—
—
—
—
LP
—
—
—
—
—
—
—
Disabled
Disabled
EXTRC
—
—
—
—
—
—
—
—
Disabled
—
—
—
—
—
—
—
Disabled
Disabled
CM1CON0
CM2CON0
VRCON0
OPTION
T0CS
ADCON0
ANS<1:0>
00, 01, 10 00, 01, 10
CONFIG
XT
Note 1:
2:
Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
Shaded cells indicate the bit status does not affect the pins digital functionality.
© 2007 Microchip Technology Inc.
DS41268D-page 35
PIC12F510/16F506
TABLE 5-6:
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTB)(1), (2)
RB0
RB0
RB0
RB1
RB1
RB2
RB2
RB3
RB4
RB5
CM1CON0
C1ON
—
0
1
0
1
0
1
—
—
—
C1PREF
—
—
0
—
—
—
—
—
—
—
C1NREF
—
—
—
—
0
—
—
—
—
—
C1T0CS
—
—
—
—
—
—
—
—
—
—
C1OUTEN
—
—
—
—
—
—
1
—
—
—
C2ON
1
—
—
—
—
—
—
—
—
—
C2PREF1
0
—
—
—
—
—
—
—
—
—
C2PREF2
1
—
—
—
—
—
—
—
—
—
C2NREF
—
—
—
—
—
—
—
—
—
—
C2OUTEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
00
00
—
—
—
—
—
—
—
CM2CON0
OPTION
T0CS
ADCON0
ANS<1:0>
00, 01 00, 01
00, 01 00, 01, 10 00, 01, 10
CONFIG
MCLRE
—
—
—
—
—
—
—
0
INTOSC
—
—
—
—
—
—
—
—
LP
—
—
—
—
—
—
—
—
EXTRC
—
—
—
—
—
—
—
—
XT
—
—
—
—
—
—
—
—
EC
—
—
—
—
—
—
—
—
HS
—
—
—
—
—
—
—
—
Disabled Disabled
INTOSC CLKOUT
—
—
—
—
—
—
—
—
Disabled Disabled
EXTRC CLOCKOUT
—
—
—
—
—
—
—
—
Disabled Disabled
Note 1:
2:
Disabled Disabled
—
Disabled
Disabled Disabled
—
Disabled
Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
Shaded cells indicate the bit status does not affect the pins digital functionality.
TABLE 5-7:
CM2CON0
C2ON
C2PREF1
C2PREF2
C2NREF
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTC)(1), (2)
RC0
RC0
RC1
RC1
RC2
RC3
RC4
RC4
RC5
RC5
0
—
—
—
1
0
0
—
0
—
—
—
1
—
—
0
—
—
—
—
—
—
—
—
0
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
C2OUTEN
VRCON0
VROE
—
—
—
—
0
—
—
—
—
—
OPTION
T0CS
—
—
—
—
—
—
—
—
0
—
Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for
the pin.
2: Shaded cells indicate the bit status does not affect the pins digital functionality.
DS41268D-page 36
© 2007 Microchip Technology Inc.
PIC12F510/16F506
5.5
I/O Programming Considerations
5.5.1
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. For example, the BCF and BSF
instructions read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of PORTB/GPIO will
cause all eight bits of PORTB/GPIO to be read into the
CPU, bit 5 to be set and the PORTB/GPIO value to be
written to the output latches. If another bit of PORTB/
GPIO is used as a bidirectional I/O pin (say bit ‘0’) and
it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the
Input mode, no problem occurs. However, if bit ‘0’ is
switched into Output mode later on, the content of the
data latch may now be unknown.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
FIGURE 5-14:
;Initial PORTB Settings
;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
;
PORTB latch
;
---------BCF
PORTB, 5 ;--01 -ppp
BCF
PORTB, 4 ;--10 -ppp
MOVLW 007h;
TRIS
PORTB
;--10 -ppp
;
Note:
5.5.2
PORTB pins
-----------11 pppp
--11 pppp
--11 pppp
The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCF caused RB5 to
be latched as the pin value (High).
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle. Whereas for reading, the data must
be valid at the beginning of the instruction cycle
(Figure 5-14). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction causes the file to be read
into the CPU. Otherwise, the previous state of that pin
may be read into the CPU rather than the new state.
When in doubt, it is better to separate these
instructions with a NOP or another instruction not
accessing this I/O port.
PC
PC + 1
MOVWF PORTB
MOVF PORTB, W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB followed by a
read from PORTB.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle
RB<5:0>
TPD = propagation delay
Port pin
written here
Instruction
Executed
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT (e.g., PIC16F506)
SUCCESSIVE I/O OPERATION (PIC16F506)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
EXAMPLE 5-1:
MOVWF PORTB
(Write to PORTB)
© 2007 Microchip Technology Inc.
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Port pin
sampled here
MOVF PORTB,W
(Read PORTB)
NOP
DS41268D-page 37
PIC12F510/16F506
NOTES:
DS41268D-page 38
© 2007 Microchip Technology Inc.
PIC12F510/16F506
6.0
TMR0 MODULE AND TMR0
REGISTER
The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in two
different ways. The first way is selected by setting the
T0CS bit (OPTION<5>), and clearing the C1T0CS bit
(CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does not
affect this mode of operation). This enables an internal
connection between the comparator and the Timer0.
The Timer0 module has the following features:
•
•
•
•
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
- External clock from either the T0CKI pin or
from the output of the comparator
The second way is selected by setting the T0CS bit
(OPTION<5>), setting the C1T0CS bit (CM1CON0)
and clearing the C1OUTEN bit (CM1CON0<6>). This
allows the output of the comparator onto the T0CKI pin,
while keeping the T0CKI input active. Therefore, any
comparator change on the COUT pin is fed back into
the T0CKI input. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
as discussed in Section 6.1 “Using Timer0 With An
External Clock”.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 “Prescaler” details
the operation of the prescaler.
There are two types of Counter mode. The first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CKI bit (OPTION<5>), setting
the C1T0CS bit (CM1CON0<4>) and setting the
C1OUTEN bit (CM1CON0<6>). In this mode, Timer0
will increment either on every rising or falling edge of
pin T0CKI. The T0SE bit (OPTION<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.1 “Using Timer0 With
An External Clock”.
FIGURE 6-1:
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
T0CKI
Pin
Data Bus
FOSC/4
Internal
Comparator
Output
0
PSOUT
1
1
1
0
T0SE
Programmable
Prescaler(2)
(1)
0
8
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 TCY delay) Sync
3
C1T0CS(3)
Note 1:
2:
3:
T0CS(1)
PS2, PS1, PS0(1)
PSA(1)
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
The prescaler is shared with the Watchdog Timer (Figure 6-5).
Bit C1T0CS is located in the CM1CON0 register, CM1CON0<4>.
© 2007 Microchip Technology Inc.
DS41268D-page 39
PIC12F510/16F506
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
T0 + 1
PC
(Program
Counter)
Write TMR0
executed
PC + 5
PC + 6
NT0 + 1
NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1
PC
PC + 1
MOVWF TMR0
T0
Timer0
PC + 3
T0 + 1
PC + 4
PC + 5
NT0
Write TMR0
executed
TABLE 6-1:
PC + 2
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Executed
01h
PC + 4
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Instruction
Fetch
Addr
PC + 3
T0 + 2
Instruction
Executed
FIGURE 6-3:
PC + 2
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 1
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
TMR0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 – 8-bit Real-Time Clock/Counter
Value on
Power-On
Reset
Value on
All Other
Resets
xxxx xxxx
uuuu uuuu
07h
(2)
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
08h
CM1CON0(3)
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
N/A
TRISGPIO(1)
—
—
I/O Control Register
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
---- 1111
--11 1111
Legend:
Shaded cells not used by Timer0, – = unimplemented, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
2: For PIC12F510.
3: For PIC16F506.
DS41268D-page 40
© 2007 Microchip Technology Inc.
PIC12F510/16F506
6.1
Using Timer0 With An External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI or the
comparator output to be high for at least 2TOSC (and a
small RC delay of 2Tt0H) and low for at least 2TOSC
(and a small RC delay of 2Tt0H). Refer to the electrical
specification of the desired device.
FIGURE 6-4:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling requirement, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
output to have a period of at least 4TOSC (and a small
RC delay of 4Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output(2)
External Clock/Prescaler
Output After Sampling
(3)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
Increment Timer0 (Q4)
Timer0
Note 1:
6.2
T0
T0 + 2
Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2:
External clock if no prescaler selected; prescaler output otherwise.
3:
The arrows indicate the points in time where sampling occurs.
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Figure 10-12). For simplicity, this counter is being referred to as “prescaler”
throughout this data sheet.
Note:
T0 + 1
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1, x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will clear
the prescaler along with the WDT. The prescaler is
neither readable nor writable. On a Reset, the
prescaler contains all ‘0’s.
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
© 2007 Microchip Technology Inc.
DS41268D-page 41
PIC12F510/16F506
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device Reset,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 → WDT)
CLRWDT
CLRF
TMR0
MOVLW ‘00xx1111’b
OPTION
CLRWDT
MOVLW ‘00xx1xxx’b
OPTION
FIGURE 6-5:
MOVLW
;Clear WDT
;Clear TMR0 & Prescaler
;These 3 lines (5, 6, 7)
;are required only if
;desired
;PS<2:0> are 000 or 001
;Set Postscaler to
;desired WDT rate
‘xxxx0xxx’
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0CKI(2)
Pin
TCY (= FOSC/4)
Data Bus
8
0
1
Comparator
Output
1
M
U
X
1
M
U
X
0
0
T0SE(1)
T0CS(1)
Sync
2
Cycles
TMR0 Reg
PSA(1)
C1T0CS(3)
0
Watchdog
Timer
1
M
U
X
8-bit Prescaler
8
8-to-1 MUX
PS<2:0>(1)
PSA(1)
WDT Enable bit
1
0
MUX
PSA(1)
WDT
Time-Out
Note 1:
T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2:
T0CKI is shared with pin GP2 on the PIC12F510 and shared with RC5 on the PIC16F506.
3:
Bit C1T0CS is located in the CM1CON0 register.
DS41268D-page 42
© 2007 Microchip Technology Inc.
PIC12F510/16F506
7.0
COMPARATOR(S)
The PIC12F510 contains one analog comparator
module. The PIC16F506 contains two comparators
and a comparator voltage reference.
REGISTER 7-1:
CM1CON0: COMPARATOR C1 CONTROL REGISTER (PIC12F510)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C1OUT: Comparator Output bit
1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
C1OUTEN: Comparator Output Enable bit(1), (2)
1 = Output of comparator is NOT placed on the C1OUT pin
0 = Output of comparator is placed in the C1OUT pin
bit 5
C1POL: Comparator Output Polarity bit(2)
1 = Output of comparator is not inverted
0 = Output of comparator is inverted
bit 4
C1T0CS: Comparator TMR0 Clock Source bit(2)
1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3
C1ON: Comparator Enable bit
1 = Comparator is on
0 = Comparator is off
bit 2
C1NREF: Comparator Negative Reference Select bit(2)
1 = C1IN- pin
0 = 0.6V internal reference
bit 1
C1PREF: Comparator Positive Reference Select bit(2)
1 = C1IN+ pin
0 = C1IN- pin
bit 0
C1WU: Comparator Wake-up On Change Enable bit(2)
1 = Wake-up On Comparator Change is disabled
0 = Wake-up On Comparator Change is enabled
Note 1:
2:
x = Bit is unknown
Overrides T0CS bit for TRIS control of RB2.
When comparator is turned on, these control bits assert themselves.
© 2007 Microchip Technology Inc.
DS41268D-page 43
PIC12F510/16F506
REGISTER 7-2:
CM1CON0: COMPARATOR C1 CONTROL REGISTER (PIC16F506)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C1OUT: Comparator Output bit
1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
C1OUTEN: Comparator Output Enable bit(1), (2)
1 = Output of comparator is NOT placed on the C1OUT pin
0 = Output of comparator is placed in the C1OUT pin
bit 5
C1POL: Comparator Output Polarity bit(2)
1 = Output of comparator is not inverted
0 = Output of comparator is inverted
bit 4
C1T0CS: Comparator TMR0 Clock Source bit(2)
1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3
C1ON: Comparator Enable bit
1 = Comparator is on
0 = Comparator is off
bit 2
C1NREF: Comparator Negative Reference Select bit(2)
1 = C1IN- pin
0 = 0.6V internal reference
bit 1
C1PREF: Comparator Positive Reference Select bit(2)
1 = C1IN+ pin
0 = C1IN- pin
bit 0
C1WU: Comparator Wake-up On Change Enable bit(2)
1 = Wake-up On Comparator Change is disabled
0 = Wake-up On Comparator Change is enabled
Note 1:
2:
x = Bit is unknown
Overrides T0CS bit for TRIS control of RB2.
When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have
precedence.
DS41268D-page 44
© 2007 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 7-3:
CM2CON0: COMPARATOR C2 CONTROL REGISTER (PIC16F506)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C2OUT: Comparator Output bit
1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
C2OUTEN: Comparator Output Enable bit(1), (2)
1 = Output of comparator is NOT placed on the C2OUT pin
0 = Output of comparator is placed in the C2OUT pin
bit 5
C2POL: Comparator Output Polarity bit(2)
1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4
C2PREF2: Comparator Positive Reference Select bit(2)
1 = C1IN+ pin
0 = C2IN- pin
bit 3
C2ON: Comparator Enable bit
1 = Comparator is on
0 = Comparator is off
bit 2
C2NREF: Comparator Negative Reference Select bit(2)
1 = C2IN- pin
0 = CVREF
bit 1
C2PREF1: Comparator Positive Reference Select bit(2)
1 = C2IN+ pin
0 = C2PREF2 controls analog input selection
bit 0
C2WU: Comparator Wake-up on Change Enable bit(2)
1 = Wake-up on Comparator change is disabled
0 = Wake-up on Comparator change is enabled.
Note 1:
2:
x = Bit is unknown
Overrides TOCS bit for TRIS control of RC4.
When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have
precedence.
© 2007 Microchip Technology Inc.
DS41268D-page 45
PIC12F510/16F506
FIGURE 7-1:
COMPARATOR 1 BLOCK DIAGRAM FOR PIC12F510/16F506
C1PREF
To
Data Bus
C1IN-
MUX
0
C1IN+
RD_CM1CON0
1
D
C1WUF
Q
Q3 * RD_CM1CON0
C1NREF
EN
CL
NRESET
C1ON(1)
C1WU
C1OUTEN
C1IN-
+
0.6V
(Internal Reference)
MUX
1
-
C1OUT
C1
C1OUT
0
C1POL
Note 1:
When C1ON = 0, the comparator, C1, will produce a ‘0’ output to the XOR Gate.
FIGURE 7-2:
COMPARATOR 2 BLOCK DIAGRAM (PIC16F506 ONLY)
To
Data Bus
RD_CM2CON0
D
C2PREF1
C2PREF2
C2ON(1)
1
1
MUX
C1IN+
0
+
C2WU
C2OUT
C2
-
C2OUTEN
0
C2IN-
EN
CL
NRESET
MUX
C2IN+
Q3 * RD_CM2CON0
C2WUF
Q
C2NREF
C2POL
C2OUT
1
MUX
C2IN-
CVREF
Note
1:
0
When C2ON = 0, the comparator, C2, will produce a ‘0’ output to the XOR Gate.
DS41268D-page 46
© 2007 Microchip Technology Inc.
PIC12F510/16F506
7.1
Comparator Operation
A single comparator is shown in Figure 7-3 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. The shaded area of the output of
the comparator in Figure 7-3 represent the uncertainty
due to input offsets and response time. See Table 13-1
for Common Mode Voltage.
FIGURE 7-3:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Result
Note:
7.5
Analog levels on any pin that is defined as
a digital input may cause the input buffer to
consume more current than is specified.
Comparator Wake-up Flag
The Comparator Wake-up Flag is set whenever all of
the following conditions are met:
• C1WU = 0 (CM1CON0<0>) or
C2WU = 0 (CM2CON0<0>)
• CM1CON0 or CM2CON0 has been read to latch
the last known state of the C1OUT and C2OUT bit
(MOVF CM1CON0, W)
• Device is in Sleep
• The output of a comparator has changed state
The wake-up flag may be cleared in software or by
another device Reset.
7.6
VIN-
Comparator Operation During
Sleep
VIN+
When the comparator is enabled it is active. To minimize power consumption while in Sleep mode, turn off
the comparator before entering Sleep.
Result
7.7
7.2
Comparator Reference
An internal reference signal may be used depending on
the comparator operating mode. The analog signal that
is present at VIN- is compared to the signal at VIN+, and
the digital output of the comparator is adjusted accordingly (Figure 7-3). Please see Section 8.0 “Comparator Voltage Reference Module (PIC16F506 only)” for
internal reference specifications.
7.3
Comparator Response Time
Response time is the minimum time after selecting a
new reference voltage or input source before the comparator output is to have a valid level. If the comparator
inputs are changed, a delay must be used to allow the
comparator to settle to its new state. Please see
Table 13-1
for
comparator
response
time
specifications.
7.4
Effects of Reset
A Power-on Reset (POR) forces the CM2CON0
register to its Reset state. This forces the Comparator
input pins to analog Reset mode. Device current is
minimized when analog inputs are present at Reset
time.
7.8
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
Comparator Output
The comparator output is read through the CM1CON0
or CM2CON0 register. This bit is read-only. The
comparator output may also be used externally, see
Figure 7-3.
© 2007 Microchip Technology Inc.
DS41268D-page 47
PIC12F510/16F506
FIGURE 7-4:
ANALOG INPUT MODE
VDD
VT = 0.6V
RS < 10 K
RIC
AIN
CPIN
5 pF
VA
ILEAKAGE
±500 nA
VT = 0.6V
VSS
Legend:
TABLE 7-1:
Add
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the Pin
Interconnect Resistance
Source Impedance
Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
GPWUF
CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
qq0q quuu
07h
(1)
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
uuuu uuuu
08h
CM1CON0(2)
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
uuuu uuuu
0Bh
CM2CON0(2)
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
N/A
TRISB(2)
—
—
I/O Control Register
--11 1111
--11 1111
N/A
TRISC(2)
—
—
I/O Control Register
--11 1111
--11 1111
N/A
TRISGPIO(1)
—
—
I/O Control Register
--11 1111
--11 1111
03h
Legend:
Note 1:
2:
STATUS
x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition.
PIC12F510 only.
PIC16F506 only.
DS41268D-page 48
© 2007 Microchip Technology Inc.
PIC12F510/16F506
8.0
COMPARATOR VOLTAGE
REFERENCE MODULE
(PIC16F506 ONLY)
8.2
The comparator voltage reference module also allows
the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON
register (Register 8-1) controls the voltage reference
module shown in Figure 8-1.
8.1
Configuring The Voltage
Reference
The voltage reference can output 32 voltage levels; 16
in a high range and 16 in a low range.
Equation 8-1 determines the output voltages:
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 8-1)
keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the
VREN bit (VRCON<7>). When disabled, the reference
voltage is VSS when VR<3:0> is ‘0000’ and the VRR
(VRCON<5>) bit is set. This allows the comparator to
detect a zero-crossing and not consume the CVREF
module current.
The voltage reference is VDD derived and, therefore,
the CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage
reference can be found in Section 13.2 “DC Characteristics: PIC12F510/16F506 (Extended)”.
EQUATION 8-1:
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
REGISTER 8-1:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER (PIC16F506 ONLY)
R/W-0
R/W-0
R/W-1
U-1
R/W-1
R/W-1
R/W-1
R/W-1
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’, except if denoted
otherwise
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
VREN: CVREF Enable bit
1 = CVREF is powered on
0 = CVREF is powered down, no current is drawn
bit 6
VROE: CVREF Output Enable bit(1)
1 = CVREF output is enabled
0 = CVREF output is disabled
bit 5
VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4
Unimplemented: Read as ‘1’
bit 3-0
VR<3:0> CVREF Value Selection bit
When VRR = 1: CVREF= (VR<3:0>/24)*VDD
When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
Note 1:
2:
x = Bit is unknown
When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the
CVREF pin.
CVREF controls for ratio metric reference applies to Comparator 2 on the PIC16F506 only.
© 2007 Microchip Technology Inc.
DS41268D-page 49
PIC12F510/16F506
FIGURE 8-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator 2
Input
VR<3:0>
RC2/CVREF
VREN
VR<3:0> = 0000
VRR
VROE
TABLE 8-1:
Add
Name
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other Resets
0Ch
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
001- 1111
001- 1111
08h
CM1CON0(1)
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
uuuu uuuu
0Bh
CM2CON0(1)
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
PIC16F506 only.
DS41268D-page 50
© 2007 Microchip Technology Inc.
PIC12F510/16F506
9.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER
The A/D Converter allows conversion of an analog
signal into an 8-bit digital signal.
9.1
Clock Divisors
The ADC has 4 clock source settings ADCS<1:0>.
There are 3 divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of 4. These settings will
allow a proper conversion when using an external
oscillator at speeds from 20 MHz to 350 kHz. Using
an external oscillator at a frequency below 350 kHz
(TAD > 50 μs) requires the ADC oscillator setting to be
INTOSC/4 for valid ADC results.
The ADC requires 13 TAD periods to complete a
conversion. The divisor values do not affect the number
of TAD periods required to perform a conversion. The
divisor values determine the length of the TAD period.
When the ADCS<1:0> bits are changed while an ADC
conversion is in process, the new ADC clock source will
not be selected until the next conversion is started. This
clock source selection will be lost when the device
enters Sleep.
9.1.1
VOLTAGE REFERENCE
There is no external voltage reference for the ADC. The
ADC reference voltage will always be VDD.
9.1.2
ANALOG MODE SELECTION
The ANS<1:0> bits are used to configure pins for
analog input. Upon any Reset, ANS<1:0> defaults to
11. This configures pins AN0, AN1 and AN2 as analog
inputs. Pins configured as analog inputs are not available for digital output. Users should not change the
ANS bits while a conversion is in process. ANS bits are
active regardless of the condition of ADON.
9.1.3
When the CHS<1:0> bits are changed during an ADC
conversion, the new channel will not be selected until
the current conversion is completed. This allows the
current conversion to complete with valid results. All
channel selection information will be lost when the
device enters Sleep.
TABLE 9-1:
CHANNEL SELECT (ADCS)
BITS AFTER AN EVENT
Event
MCLR
ADCS<1:0>
11
Conversion completed
CS<1:0>
Conversion terminated
CS<1:0>
Power-on
11
Wake from Sleep
11
9.1.4
THE GO/DONE BIT
The GO/DONE bit is used to determine the status of a
conversion, to start a conversion and to manually halt a
conversion in process. Setting the GO/DONE bit starts
a conversion. When the conversion is complete, the
ADC module clears the GO/DONE bit. A conversion
can be terminated by manually clearing the GO/DONE
bit while a conversion is in process. Manual termination
of a conversion may result in a partially converted
result in ADRES.
The GO/DONE bit is cleared when the device enters
Sleep, stopping the current conversion. The ADC does
not have a dedicated oscillator, it runs off of the instruction clock. Therefore, no conversion can occur in sleep.
The GO/DONE bit cannot be set when ADON is clear.
ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to
be sampled by the ADC. The CHS<1:0> bits can be
changed at any time without adversely effecting a conversion. To acquire an analog signal the CHS<1:0>
selection must match one of the pin(s) selected by the
ANS<1:0> bits. When the ADC is on (ADON = 1) and a
channel is selected that is also being used by the
comparator, then both the comparator and the ADC will
see the analog voltage on the pin.
Note:
It is the users responsibility to ensure that
use of the ADC and comparator simultaneously on the same pin, does not
adversely affect the signal being
monitored or adversely effect device
operation.
© 2007 Microchip Technology Inc.
DS41268D-page 51
PIC12F510/16F506
9.1.5
SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bit will be cleared.
This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11 and CHS<1:0> = 11.
• For accurate conversions, TAD must meet the
following:
• 500 ns < TAD < 50 μs
• TAD = 1/(FOSC/divisor)
Shaded areas indicate TAD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/4 for the ADC clock source.
TABLE 9-2:
Source
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
ADCS
<1:0>
Divisor
20(1)
MHz
16(1)
MHz
11
4
—
—
.5 μs
1 μs
INTOSC
8 MHz 4 MHz 1 MHz
—
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
—
—
—
—
—
FOSC
10
4
.2 μs
.25 μs
.5 μs
1 μs
4 μs
8 μs
11 μs
20 μs
40 μs
125 μs
FOSC
01
8
.4 μs
.5 μs
1 μs
2 μs
8 μs
16 μs
23 μs
40 μs
80 μs
250 μs
FOSC
00
16
.8 μs
1 μs
2 μs
4 μs
16 μs
32 μs
46 μs
80 μs
160 μs
500 μs
Note 1:
When operating with external oscillator frequencies of 16 MHz or higher, better ADC performance will result
from selection of a suitable FOSC divisor value from Table 9-2 than from use of the INTOSC/4 option for the
ADC clock.
TABLE 9-3:
EFFECTS OF SLEEP ON ADCON0
ANS1
Entering
Sleep
ANS0
Unchanged Unchanged
Wake or
Reset
DS41268D-page 52
1
1
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
1
1
1
1
0
0
1
1
1
1
0
0
© 2007 Microchip Technology Inc.
PIC12F510/16F506
9.1.6
ANALOG CONVERSION RESULT
REGISTER
The ADRES register contains the results of the last
conversion. These results are present during the sampling period of the next analog conversion process.
After the sampling period is over, ADRES is cleared
(= 0). A ‘leading one’ is then right shifted into the
ADRES to serve as an internal conversion complete
bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES. After a total of 9 right
REGISTER 9-1:
shifts of the ‘leading one’ have taken place, the conversion is complete; the ‘leading one’ has been shifted out
and the GO/DONE bit is cleared.
If the GO/DONE bit is cleared in software during a conversion, the conversion stops. The data in ADRES is
the partial conversion result. This data is valid for the bit
weights that have been converted. The position of the
‘leading one’ determines the number of bits that have
been converted. The bits that were not converted
before the GO/DONE was cleared are unrecoverable.
ADCON0: A/D CONTROL REGISTER (PIC12F510)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
ANS<1:0>: ADC Analog Input Pin Select bits(1), (2)
00 = No pins configured for analog input
01 = AN2 configured as an analog input
10 = AN2 and AN0 configured as analog inputs
11 = AN2, AN1 and AN0 configured as analog inputs
bit 5-4
ADCS<1:0>: ADC Conversion Clock Select bits
00 = FOSC/16
01 = FOSC/8
10 = FOSC/4
11 = INTOSC/4
bit 3-2
CHS<1:0>: ADC Channel Select bits
00 = Channel AN0
01 = Channel AN1
10 = Channel AN2
11 = 0.6V absolute voltage reference
bit 1
GO/DONE: ADC Conversion Status bit(4)
1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is
automatically cleared by hardware when the ADC is done converting.
0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in
process terminates the current conversion.
bit 0
ADON: ADC Enable bit
1 = ADC module is operating
0 = ADC module is shut-off and consumes no power
Note 1:
2:
3:
4:
When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin function previously defined. The only exception to this is the comparator, where the analog
input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure
that the ADC loading on the comparator input does not affect their application.
The ANS<1:0> bits are active regardless of the condition of ADON.
CHS<1:0> bits default to 11 after any Reset.
If the ADON bit is clear, the GO/DONE bit cannot be set.
© 2007 Microchip Technology Inc.
DS41268D-page 53
PIC12F510/16F506
REGISTER 9-2:
ADRES REGISTER
R-X
R-X
R-X
R-X
R-X
R-X
R-X
R-X
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
EXAMPLE 9-1:
PERFORMING AN
ANALOG-TO-DIGITAL
CONVERSION
EXAMPLE 9-2:
;Sample code operates out of BANK0
loop0
MOVLW 0xF1
;configure A/D
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop1
;setup for read of
;channel 1
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
MOVF ADRES, W ;read result
MOVWF result1 ;save result
loop2
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
MOVF ADRES, W ;read result
MOVWF result2 ;save result
CHANNEL SELECTION
CHANGE DURING
CONVERSION
MOVLW 0xF1
MOVWF ADCON0
BSF ADCON0, 1
BSF ADCON0, 2
;configure A/D
loop0
;start conversion
;setup for read of
;channel 1
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop1
BSF ADCON0, 1 ;start conversion
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
MOVF ADRES, W ;read result
MOVWF result1 ;save result
BSF ADCON0, 2
DS41268D-page 54
x = Bit is unknown
loop2
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
MOVF ADRES, W ;read result
MOVWF result2 ;save result
CLRF ADCON0
;optional: returns
;pins to Digital mode and turns off
;the ADC module
© 2007 Microchip Technology Inc.
PIC12F510/16F506
10.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime
applications.
The
PIC12F510/16F506
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide powersaving operating modes and offer code protection.
These features are:
10.1
Configuration Bits
The PIC12F510/16F506 Configuration Words consist
of 12 bits. Configuration bits can be programmed to
select various device configurations. Three bits are for
the selection of the oscillator type; (two bits on the
PIC12F510), one bit is the Watchdog Timer enable bit,
one bit is the MCLR enable bit and one bit is for code
protection (Register 10-1, Register 10-2).
• Oscillator Selection
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
• Clock Out
The PIC12F510/16F506 devices have a Watchdog
Timer, which can be shut off only through Configuration
bit WDTE. It runs off of its own RC oscillator for added
reliability. If using HS (PIC16F506), XT or LP selectable
oscillator options, there is always a delay, provided by
the Device Reset Timer (DRT), intended to keep the
chip in Reset until the crystal oscillator is stable. If using
INTOSC, EXTRC or EC there is an 1.125 ms (nominal)
delay only on VDD power-up. With this timer on-chip,
most applications need no external Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through a change-on-input pin or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4/8 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of Configuration bits are
used to select various options.
© 2007 Microchip Technology Inc.
DS41268D-page 55
PIC12F510/16F506
REGISTER 10-1:
—
CONFIG: CONFIGURATION WORD REGISTER (PIC12F510)(1)
—
—
—
—
—
—
bit 15
—
bit 8
—
—
IOSCFS
MCLRE
CP
WDTE
bit 7
FOSC1
FOSC0
bit 0
bit 15-6
Unimplemented: Read as ‘1’
bit 5
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 4
MCLRE: Master Clear Enable bit
1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3
CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC<1:0>: Oscillator Selection bits
00 = LP oscillator with 18 ms DRT
01 = XT oscillator with 18 ms DRT
10 = INTOSC with 1.125 ms DRT (2)
11 = EXTRC with 1.125 ms DRT (2)
Note 1:
2:
Refer to the “PIC12F510 Memory Programming Specification” (DS41257) to determine how to access the
Configuration Word.
It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will
result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation.
DS41268D-page 56
© 2007 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 10-2:
—
CONFIG: CONFIGURATION WORD REGISTER (PIC16F506)(1)
—
—
—
—
—
—
—
bit 15
bit 8
—
IOSCFS
MCLRE
CP
WDTE
FOSC2
FOSC1
bit 7
FOSC0
bit 0
bit 11-7
Unimplemented: Read as ‘1’
bit 6
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 5
MCLRE: Master Clear Enable bit
1 = RB3/MCLR pin functions as MCLR
0 = RB3/MCLR pin functions as RB3, MCLR tied internally to VDD
bit 4
CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator and 18 ms DRT
001 = XT oscillator and 18 ms DRT
010 = HS oscillator and 18 ms DRT
011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(2)
100 = INTOSC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(2)
101 = INTOSC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(2)
110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT (2)
111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(2)
Note 1:
2:
Refer to the “PIC16F506 Memory Programming Specification” (DS41258) to determine how to access the
Configuration Word.
It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will
result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation.
© 2007 Microchip Technology Inc.
DS41268D-page 57
PIC12F510/16F506
10.2
10.2.1
Oscillator Configurations
FIGURE 10-1:
OSCILLATOR TYPES
The PIC12F510/16F506 devices can be operated in up
to six different oscillator modes. The user can program
up to three Configuration bits (FOSC<1:0>
[PIC12F510], FOSC<2:0> [PIC16F506]). To select one
of these modes:
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
(PIC16F506 only)
•INTOSC: Internal 4/8 MHz Oscillator
•EXTRC: External Resistor/Capacitor
•EC:
External High-Speed Clock Input
(PIC16F506 only)
C1(1)
•LP:
•XT:
•HS:
10.2.2
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
Note 1:
Note 1: This device has been designed to perform to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance characteristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
DS41268D-page 58
RS
(2)
RF(3)
To internal
logic
OSC2
See Capacitor Selection tables for
recommended values of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF approx. value = 10 MΩ.
2:
3:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS (PIC16F506), XT or LP modes, a crystal or
ceramic resonator is connected to the (GP5/RB5)/
OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins
to establish oscillation (Figure 10-1). The PIC12F510/
16F506 oscillator designs require the use of a parallel
cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
When in HS (PIC16F506), XT or LP modes, the device
can have an external clock source drive the (GP5/
RB5)/OSC1/CLKIN pin (Figure 10-2). When the part is
used in this fashion, the output drive levels on the
OSC2 pin are very weak. This pin should be left open
and unloaded. Also, when using this mode, the external
clock should observe the frequency limits for the clock
mode chosen (HS, XT or LP).
Sleep
XTAL
C2(1)
PIC12F510
PIC16F506
OSC1
FIGURE 10-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
ext. system
Open
TABLE 10-1:
PIC12F510
PIC16F506
OSC2
CAPACITOR SELECTION FOR
CERAMIC RESONATORS –
PIC12F510/16F506(1)
Osc.
Type
Resonator
Freq.
Cap. Range
C1
Cap. Range
C2
XT
4.0 MHz
30 pF
30 pF
16 MHz
10-47 pF
10-47 pF
HS(2)
Note 1:
2:
These values are for design guidance
only. Since each resonator has its own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
components.
PIC16F506 only.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 10-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
PIC12F510/16F506(2)
Osc.
Type
Resonator
Freq.
Cap.Range
C1
Cap. Range
C2
LP
32 kHz(1)
15 pF
15 pF
XT
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
20 MHz
15-47 pF
15-47 pF
HS(3)
Note 1:
2:
3:
10.2.3
For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance
only. Rs may be required to avoid overdriving crystals beyond the drive level
specification. Since each crystal has its
own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
PIC16F506 only.
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance or one
with series resonance.
Figure 10-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This
circuit could be used for external oscillator designs.
FIGURE 10-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
CLKIN
74AS04
PIC12F510
PIC16F506
10k
XTAL
10k
20 pF
20 pF
Figure 10-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 10-4:
330
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
Devices
330
74AS04
74AS04
74AS04
CLKIN
10.2.4
0.1 mF
PIC12F510
XTAL
PIC16F506
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the EXTRC device
option offers additional cost savings. The EXTRC oscillator frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 10-5 shows how the R/C combination is
connected to the PIC12F510/16F506 devices. For
REXT values below 5.0 kΩ, the oscillator operation may
become unstable or stop completely. For very high
REXT values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping REXT between 5.0 kΩ and
100 kΩ.
© 2007 Microchip Technology Inc.
DS41268D-page 59
PIC12F510/16F506
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no
capacitance or small external capacitance, the oscillation frequency can vary dramatically due to changes in
external capacitances, such as PCB trace capacitance
or package lead frame capacitance.
Section 13.0 “Electrical Characteristics”, shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger values of R (since leakage current variation will affect RC
frequency more for large R) and for smaller values of C
(since variation of input capacitance will affect RC
frequency more).
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
FIGURE 10-5:
EXTERNAL RC
OSCILLATOR MODE
VDD
In addition, a calibration instruction is programmed into
the last address of memory, which contains the calibration value for the internal RC oscillator. This location is
always uncode protected, regardless of the code-protect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value, and is
placed at the Reset vector. This will load the W register
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Note:
For the PIC12F510/16F506 devices, only bits <7:1> of
OSCCAL are used for calibration. See Register 4-5 for
more information.
Note:
REXT
OSC1
Internal
clock
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
The 0 bit of OSCCAL is unimplemented
and should be written as ‘0’ when modifying OSCCAL for compatibility with future
devices.
N
CEXT
PIC12F510
VSS
PIC16F506
FOSC/4
10.2.5
OSC2/CLKOUT
INTERNAL 4/8 MHz RC
OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock (see Section 13.0 “Electrical
Characteristics” for information on variation over
voltage and temperature).
DS41268D-page 60
© 2007 Microchip Technology Inc.
PIC12F510/16F506
10.3
Reset
The device differentiates between various kinds of
Reset:
•
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Time-out Reset during normal operation
WDT Time-out Reset during Sleep
Wake-up from Sleep Reset on pin change
Wake-up from Sleep Reset on comparator
change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up from
Sleep Reset on pin change or wake-up from Sleep
Reset on comparator change. The exceptions are TO,
PD, CWUF and RBWUF/GPWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 10-4 for a full description of Reset
states of all registers.
TABLE 10-3:
RESET CONDITIONS FOR REGISTERS – PIC12F510
Address
Power-on Reset
MCLR Reset, WDT Time-out,
Wake-up On Pin Change, Wake-up on
Comparator Change
—
qqqq qqqu(1)
qqqq qqqu(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
qq0q quuu(2)
FSR
04h
110x xxxx
11uu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
GPIO
06h
--xx xxxx
--uu uuuu
CM1CON0
07h
1111 1111
uuuu uuuu
ADCON0
08h
1111 1100
uu11 1100
ADRES
09h
xxxx xxxx
uuuu uuuu
OPTION
—
1111 1111
1111 1111
TRISIO
—
--11 1111
--11 1111
Register
W
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2: See Table 10-5 for Reset value for specific conditions.
© 2007 Microchip Technology Inc.
DS41268D-page 61
PIC12F510/16F506
TABLE 10-4:
RESET CONDITIONS FOR REGISTERS – PIC16F506
Register
Address
W
—
Power-on Reset
MCLR Reset, WDT Time-out,
Wake-up On Pin Change, Wake-up on
Comparator Change
qqqq qqqu(1)
qqqq qqqu(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
10uq quuu(2)
FSR
04h
100x xxxx
10uu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
PORTB
06h
--xx xxxx
--uu uuuu
PORTC
07h
--xx xxxx
--uu uuuu
CM1CON0
08h
1111 1111
uuuu uuuu
ADCON0
09h
1111 1100
uu11 1100
ADRES
0Ah
xxxx xxxx
uuuu uuuu
CM2CON0
0Bh
1111 1111
uuuu uuuu
VRCON
0Ch
0011 1111
uuuu uuuu
OPTION
—
1111 1111
1111 1111
TRISB
—
--11 1111
--11 1111
TRISC
—
--11 1111
--11 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2: See Table 10-5 for Reset value for specific conditions.
TABLE 10-5:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
0001 1xxx
1111 1111
MCLR Reset during normal operation
000u uuuu
1111 1111
MCLR Reset during Sleep
0001 0uuu
1111 1111
WDT Reset during Sleep
0000 0uuu
1111 1111
WDT Reset normal operation
0000 uuuu
1111 1111
Wake-up from Sleep Reset on pin change
1001 0uuu
1111 1111
Wake from Sleep Reset on Comparator
Change
0101 0uuu
1111 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.
DS41268D-page 62
© 2007 Microchip Technology Inc.
PIC12F510/16F506
10.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See
Figure 10-6.
FIGURE 10-6:
MCLR SELECT
GPWU/RBWU
(GP3/RB3)/MCLR/VPP
Internal MCLR
MCLRE
10.4
Power-on Reset (POR)
The PIC12F510/16F506 devices incorporate an onchip Power-on Reset (POR) circuitry, which provides
an internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper operation. The POR is active regardless of the state of the
MCLR enable bit. An internal weak pull-up resistor is
implemented using a transistor (refer to Table 13-3 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create an external
Power-on Reset. A maximum rise time for VDD is specified. See Section 13.0 “Electrical Characteristics”
for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
© 2007 Microchip Technology Inc.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 10-7.
The Power-on Reset circuit and the Device Reset
Timer (see Section 10.5 “Device Reset Timer
(DRT)”) circuit are closely related. On power-up, the
Reset latch is set and the DRT is reset. The DRT timer
begins counting once it detects MCLR, internal or
external, to be high. After the time-out period, it will
reset the Reset latch and thus end the on-chip Reset
signal.
A power-up example where MCLR is held low is shown
in Figure 10-8. VDD is allowed to rise and stabilize
before bringing MCLR high. The chip will actually come
out of Reset TDRT msec after MCLR goes high.
In Figure 10-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be (GP3/RB3). The VDD is stable
before the Start-up timer times out and there is no problem in getting a proper Reset. However, Figure 10-10
depicts a problem situation where VDD rises too slowly.
The time between when the DRT senses that MCLR is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 10-9).
Note:
When the devices start normal operation
(exit the Reset condition), device operating parameters (voltage, frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Notes
AN522, “Power-Up Considerations” (DS00522) and
AN607, “Power-up Trouble Shooting” (DS00607).
DS41268D-page 63
PIC12F510/16F506
FIGURE 10-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
(GP3/RB3)/MCLR/VPP
MCLR Reset
S
Q
R
Q
MCLRE
WDT Time-out
Pin Change
Sleep
WDT Reset
Start-up Timer
(10 ms, 1.125 ms
or 18 ms)
CHIP Reset
Wake-up on pin Change Reset
Comparator Change
Wake-up on
Comparator Change
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 10-8:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 10-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS41268D-page 64
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 10-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
© 2007 Microchip Technology Inc.
DS41268D-page 65
PIC12F510/16F506
10.5
Device Reset Timer (DRT)
On the PIC12F510/16F506 devices, the DRT runs any
time the device is powered up. DRT runs from Reset
and varies based on oscillator selection and Reset type
(see Table 10-6).
The DRT operates from a free running on-chip oscillator that is separate from INTOSC. The processor is
kept in Reset as long as the DRT is active. The DRT
delay allows VDD to rise above VDD minimum and for
the oscillator to stabilize.
Oscillator circuits, based on crystals or ceramic resonators, require a certain time after power-up to establish
a stable oscillation. The on-chip DRT keeps the devices
in a Reset for a set period, as stated in Table 10-6, after
MCLR has reached a logic high (VIH MCLR) level.
Programming (GP3/RB3)/MCLR/VPP as MCLR and
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications,
as well as allowing the use of the (GP3/RB3)/MCLR/
VPP pin as a general purpose input.
The DRT delays will vary from chip-to-chip due to VDD,
temperature and process variation. See AC
parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out, Wakeup on Pin Change and Wake-up on Comparator
Change. See Section 10.9.2 “Wake-up from Sleep
Reset”, Notes 1, 2 and 3.
10.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator that does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4/8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset generates a device Reset.
TABLE 10-6:
TYPICAL DRT PERIODS
POR Reset
Subsequent
Resets
LP
18 ms
18 ms
XT
18 ms
18 ms
HS(1)
18 ms
18 ms
EC(1)
1.125 ms
10 μs
INTOSC
1.125 ms
10 μs
EXTRC
1.125 ms
10 μs
Oscillator
Configuration
Note 1:
Note:
10.6.1
PIC16F506 only
It is the responsibility of the application
designer to ensure the use of the
1.125 ms nominal DRT will result in
acceptable operation. Refer to Electrical
Specifications for VDD rise time and
stability requirements for this mode of
operation.
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a divisor ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
10.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see
Section 10.1 “Configuration Bits”). Refer to the
PIC12F510/16F506 Programming Specifications to
determine how to access the Configuration Word.
DS41268D-page 66
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 10-11:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
Watchdog
Timer
1
M
U
X
Postscaler
8-to-1 MUX
PS<2:0>
PSA
WDTE
To Timer0 (Figure 6-4)
0
1
MUX
PSA
WDT Time-out
Note 1:
TABLE 10-7:
Address
T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A
OPTION(1) GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
OPTION(2) RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged.
Note 1: PIC12F510 only.
2: PIC16F506 only.
© 2007 Microchip Technology Inc.
DS41268D-page 67
PIC12F510/16F506
10.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF/RBWUF)
FIGURE 10-13:
VDD
VDD
The TO, PD and (GPWUF/RBWUF) bits in the STATUS
register can be tested to determine if a Reset condition
has been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
TABLE 10-8:
R1
Q1
R2
TO/PD/(GPWUF/RBWUF)
STATUS AFTER RESET
GPWUF/
TO
RBWUF
CWUF
PD
Reset Caused By
0
0
0
0
WDT wake-up from
Sleep
0
0
0
u
WDT time-out (not
from Sleep)
0
0
1
0
MCLR wake-up from
Sleep
0
0
1
1
Power-up
0
0
u
u
MCLR not during
Sleep
0
1
1
0
Wake-up from Sleep
on pin change
1
0
1
0
Wake-up from Sleep
on comparator
change
Note 1:
To reset PIC12F510/16F506 devices when a brownout occurs, external brown-out protection circuits may
be built, as shown in Figure 10-12 and Figure 10-13.
FIGURE 10-12:
MCLR(2)
This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
2:
R1
R1 + R2
= 0.7V
Pin must be configured as MCLR.
FIGURE 10-14:
BROWN-OUT
PROTECTION CIRCUIT 3
VDD
MCP809
VSS
Bypass
Capacitor
VDD
VDD
RST
MCLR
PIC12F510
PIC16F506
Reset on Brown-out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
PIC12F510
PIC16F506
40k(1)
VDD •
Legend: u = unchanged
10.8
BROWN-OUT
PROTECTION CIRCUIT 2
Note:
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller supervisor. There are 7 different trip
point selections to accommodate 5V to 3V
systems.
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
PIC12F510
PIC16F506
10k
Q1
MCLR(2)
40k(1)
Note 1:
2:
This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
Pin must be configured as MCLR.
DS41268D-page 68
© 2007 Microchip Technology Inc.
PIC12F510/16F506
10.9
Power-Down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep Reset).
10.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note:
A device Reset generated by a WDT
time-will not drive the MCLR pin low.
For lowest current consumption while powered down,
all input pins should be at VDD or VSS and (GP3/RB3)/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
10.9.2
WAKE-UP FROM SLEEP RESET
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
4.
An external Reset input on (GP3/RB3)/MCLR/
VPP pin when configured as MCLR.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
A change-on-input pin GP0/RB0, GP1/RB1,
GP3/RB3 or RB4 when wake-up on change is
enabled.
A change in the comparator ouput bits, C1OUT
and C2OUT (if comparator wake-up is enabled).
These events cause a device Reset. The TO, PD,
CWUF and GPWUF/RBWUF bits can be used to determine the cause of device Reset. The TO bit is cleared
if a WDT time-out occurred (and caused wake-up). The
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The CWUF bit indicates a change in
comparator output state while the device was in Sleep.
The GPWUF/RBWUF bit indicates a change in state
while in Sleep at pins GP0/RB0, GP1/RB1, GP3/RB3
or RB4 (since the last file or bit operation on GP/RB
port).
Note:
Note 1: Caution: Right before entering Sleep,
read the comparator Configuration
register(s) CM1CON0 and CM2CON0.
When in Sleep, wake-up occurs when the
comparator output bit C1OUT and
C2OUT change from the state they were
in at the last reading. If a wake-up on
comparator change occurs and the pins
are not read before re-entering Sleep, a
wake-up will occur immediately, even if
no pins change while in Sleep mode.
2: For 16F506 only.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
10.10 Program Verification/Code
Protection
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
The last memory location can be read regardless of the
code protection bit setting on the PIC12F510/16F506
devices.
10.11 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
Use only the lower 4 bits of the ID locations and always
set the upper 4 bits as ‘1’s. The upper 4 bits are
unimplemented.
These locations can be read regardless of the code
protect setting.
Caution: Right before entering Sleep,
read the input pins. When in Sleep, wakeup occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
reentering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
© 2007 Microchip Technology Inc.
DS41268D-page 69
PIC12F510/16F506
10.12 In-Circuit Serial Programming™
(ICSP™)
The PIC12F510/16F506 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to manufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware, or
a custom firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the GP1/RB1 and GP0/RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming
specification).
GP1/RB1
becomes
the
programming clock and GP0/RB0 becomes the
programming data. Both GP1/RB1 and GP0/RB0 are
Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is supplied to the device.
Depending on the command and if the command was a
Load or a Read, 14 bits of program data are then supplied to or from the device. For complete details of serial
programming, please refer to the PIC12F510/16F506
Programming Specifications.
FIGURE 10-15:
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC12F510
PIC16F506
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1/RB1
Data I/O
GP0/RB0
VDD
To Normal
Connections
A typical In-Circuit Serial Programming connection is
shown in Figure 10-15.
DS41268D-page 70
© 2007 Microchip Technology Inc.
PIC12F510/16F506
11.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the categories is presented in Figure 11-1, while the various
opcode fields are summarized in Table 11-1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bits
affected by the operation, while ‘f’ represents the
number of the file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 11-1:
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label
TOS
PC
WDT
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
OPCODE
5
d
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11
OPCODE
8 7
5 4
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Top-of-Stack
Watchdog Timer counter
Time-out bit
Power-down bit
dest
Destination, either the W register or the specified
register file location
[
]
Options
(
)
Contents
∈
FIGURE 11-1:
Program Counter
PD
< >
0xhhh
where ‘h’ signifies a hexadecimal digit.
Label name
TO
→
Figure 11-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
OPCODE FIELD
DESCRIPTIONS
Field
f
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 μs.
Assigned to
Register bit field
In the set of
italics User defined term (font is courier)
© 2007 Microchip Technology Inc.
DS41268D-page 71
PIC12F510/16F506
TABLE 11-2:
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
INSTRUCTION SET SUMMARY
Description
Cycles
12-Bit Opcode
MSb
LSb
Status
Notes
Affected
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
0001 11df ffff C, DC, Z 1, 2, 4
Add W and f
1
0001 01df ffff
AND W with f
1
Z
2, 4
0000 011f ffff
Clear f
1
Z
4
0000 0100 0000
Clear W
1
Z
0010 01df ffff
Complement f
1
Z
0000 11df ffff
Decrement f
1
Z
2, 4
0010 11df ffff
Decrement f, Skip if 0
1(2)
None
2, 4
1
0010 10df ffff
Increment f
Z
2, 4
1(2)
0011 11df ffff
Increment f, Skip if 0
None
2, 4
1
0001 00df ffff
Inclusive OR W with f
Z
2, 4
1
0010 00df ffff
Move f
Z
2, 4
1
0000 001f ffff
Move W to f
None
1, 4
1
0000 0000 0000
No Operation
None
1
0011 01df ffff
Rotate left f through Carry
C
2, 4
1
0011 00df ffff
Rotate right f through Carry
C
2, 4
1
0000 10df ffff C, DC, Z 1, 2, 4
Subtract W from f
1
0011 10df ffff
Swap f
None
2, 4
1
0001 10df ffff
Exclusive OR W with f
Z
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
0100 bbbf ffff
None
2, 4
1
Bit Clear f
BCF
f, b
0101 bbbf ffff
None
2, 4
1
Bit Set f
BSF
f, b
0110 bbbf ffff
None
Bit Test f, Skip if Clear
1(2)
BTFSC
f, b
1(2)
0111 bbbf ffff
None
f, b
Bit Test f, Skip if Set
BTFSS
LITERAL AND CONTROL OPERATIONS
ANDLW
k
AND literal with W
1
1110 kkkk kkkk
Z
CALL
1
k
Call Subroutine
2
1001 kkkk kkkk
None
CLRWDT
–
Clear Watchdog Timer
1
0000 0000 0100 TO, PD
None
GOTO
k
Unconditional branch
2
101k kkkk kkkk
Z
IORLW
k
Inclusive OR literal with W
1
1101 kkkk kkkk
None
MOVLW
k
Move literal to W
1
1100 kkkk kkkk
None
OPTION
–
Load OPTION register
1
0000 0000 0010
None
RETLW
k
Return, place literal in W
2
1000 kkkk kkkk
SLEEP
–
Go into Standby mode
1
0000 0000 0011 TO, PD
None
3
TRIS
f
Load TRIS register
1
0000 0000 0fff
Z
XORLW
k
Exclusive OR literal to W
1
1111 kkkk kkkk
Note 1: The 9th bit of the Program Counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS41268D-page 72
© 2007 Microchip Technology Inc.
PIC12F510/16F506
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
(W) + (f) → (dest)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected:
None
Description:
Description:
Bit ‘b’ in register ‘f’ is cleared.
f,d
Add the contents of the W register
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
f,b
ANDLW
AND literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BSF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W).AND. (k) → (W)
0 ≤ f ≤ 31
0≤b≤7
Status Affected:
Z
Operation:
1 → (f<b>)
Description:
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
ANDWF
AND W with f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDWF
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
(W) .AND. (f) → (dest)
Operation:
skip if (f<b>) = 0
Status Affected: Z
Status Affected:
None
Description:
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruction fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
k
f,d
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
© 2007 Microchip Technology Inc.
f,b
DS41268D-page 73
PIC12F510/16F506
BTFSS
Bit Test f, Skip if Set
CLRW
Clear W
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRW
Operands:
0 ≤ f ≤ 31
0≤b<7
Operands:
None
Operation:
00h → (W);
1→Z
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
Z
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
Description:
The W register is cleared. Zero bit
(Z) is set.
CALL
Subroutine Call
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
(STATUS <6:5>) → PC<10:9>;
0 → PC<8>
Operation:
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
Status Affected:
None
Status Affected:
TO, PD
Description:
Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS <6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
Description:
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 31
Operands:
Operation:
00h → (f);
1→Z
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
DS41268D-page 74
f
f,d
© 2007 Microchip Technology Inc.
PIC12F510/16F506
DECF
Decrement f
INCF
Increment f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – 1 → (dest)
Operation:
(f) + 1 → (dest)
Status Affected:
Z
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – 1 → d;
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruction, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
two-cycle instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 511
Operands:
0 ≤ k ≤ 255
Operation:
k → PC<8:0>;
STATUS <6:5> → PC<10:9>
Operation:
(W) .OR. (k) → (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS <6:5>. GOTO is a twocycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
skip if result = 0
GOTO k
© 2007 Microchip Technology Inc.
INCF f,d
INCFSZ f,d
IORLW k
DS41268D-page 75
PIC12F510/16F506
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
Operation:
Operation:
(W).OR. (f) → (dest)
(W) → (f)
Status Affected:
None
Status Affected:
Z
Description:
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
Move data from the W register to
register ‘f’.
MOVF
Move f
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
None
Operation:
No operation
Operation:
(f) → (dest)
Status Affected:
None
Status Affected:
Z
Description:
No operation.
Description:
The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since Status
flag Z is affected.
MOVLW
Move Literal to W
OPTION
Syntax:
[ label ]
Syntax:
[ label ]
None
(W) → Option
IORWF
f,d
MOVF f,d
MOVLW k
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k → (W)
Operation:
Status Affected:
None
Description:
The eight-bit literal ‘k’ is loaded
into the W register. The “don’t
cares” will be assembled as ‘0’s.
DS41268D-page 76
MOVWF
f
NOP
Load OPTION Register
Option
Status Affected:
None
Description:
The content of the W register is
loaded into the OPTION register.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
RETLW
Return with Literal in W
SLEEP
Enter SLEEP Mode
Syntax:
[ label ]
Syntax:
[label ]
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
k → (W);
TOS → PC
Operation:
Status Affected:
None
Description:
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
00h → WDT;
0 → WDT prescaler;
1 → TO;
0 → PD
Status Affected:
TO, PD, RBWUF
Description:
Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 10.9 “Power-Down
Mode (Sleep)” on Sleep for more
details.
RLF
Rotate Left f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RLF
Syntax:
[label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
Operation:
(f) – (W) → (dest)
Status Affected:
C
Status Affected:
C, DC, Z
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
Description:
Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Rotate Right f through Carry
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
Operation:
Status Affected:
C
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Status Affected:
None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
RETLW k
SUBWF f,d
register ‘f’
C
RRF
f,d
SLEEP
RRF f,d
C
© 2007 Microchip Technology Inc.
register ‘f’
DS41268D-page 77
PIC12F510/16F506
TRIS
Load TRIS Register
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Syntax:
[ label ] TRIS
Operands:
f=6
f
Operation:
(W) → TRIS register f
Status Affected:
None
Operation:
(W) .XOR. (f) → (dest)
Description:
TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register
Status Affected:
Z
Description:
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
XORLW
Exclusive OR literal with W
Syntax:
[label ]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .XOR. k → (W)
XORLW k
Status Affected:
Z
Description:
The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
DS41268D-page 78
f,d
© 2007 Microchip Technology Inc.
PIC12F510/16F506
12.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
12.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
DS41268D-page 79
PIC12F510/16F506
12.2
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
12.3
MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
12.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
12.5
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
12.6
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41268D-page 80
© 2007 Microchip Technology Inc.
PIC12F510/16F506
12.7
MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
12.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection
(CAT5).
12.9
MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single stepping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
12.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
DS41268D-page 81
PIC12F510/16F506
12.11 PICSTART Plus Development
Programmer
12.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
12.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
DS41268D-page 82
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
© 2007 Microchip Technology Inc.
PIC12F510/16F506
13.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Ambient temperature under bias.......................................................................................................... -40°C to +125°C
Storage temperature ............................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................... 0 to +7.0V
Voltage on MCLR with respect to VSS.............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) .................................................................................................................................. 700 mW
Max. current out of VSS pin ................................................................................................................................ 200 mA
Max. current into VDD pin ................................................................................................................................... 150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA
Max. output current sunk by any I/O pin .............................................................................................................. 25 mA
Max. output current sourced by any I/O pin ......................................................................................................... 25 mA
Max. output current sourced by I/O port ............................................................................................................ 100 mA
Max. output current sunk by I/O port ................................................................................................................. 100 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
DS41268D-page 83
PIC12F510/16F506
VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC12F510)
FIGURE 13-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
8
20
25
Frequency (MHz)
FIGURE 13-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC12F510)
Oscillator Mode
LP
XT
EXTRC
INTOSC
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency (MHz)
DS41268D-page 84
© 2007 Microchip Technology Inc.
PIC12F510/16F506
VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC16F506)
FIGURE 13-3:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
8
20
25
Frequency (MHz)
FIGURE 13-4:
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC16F506)
Oscillator Mode
LP
XT
EXTRC
INTOSC
EC
HS
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency (MHz)
© 2007 Microchip Technology Inc.
DS41268D-page 85
PIC12F510/16F506
13.1
DC Characteristics: PIC12F510/16F506 (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
See Figure 14-1
D002
VDR
RAM Data Retention Voltage(2)
—
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 10.4 “Power-on
Reset (POR)” for details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 10.4 “Power-on
Reset (POR)” for details
D010
IDD
Supply Current(3,4)
—
—
175
0.625
275
1.1
μA
mA
FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
—
—
250
1.0
450
1.5
μA
mA
FOSC = 8 MHz, VDD = 2.0V
FOSC = 8 MHz, VDD = 5.0V
—
1.4
2.0
mA
FOSC = 20 MHz, VDD = 5.0V
—
—
11
38
15
52
μA
μA
FOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020
IPD
Power-down Current(5)
—
—
0.1
0.35
1.2
2.4
μA
μA
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current(5)
—
—
1.0
7.0
3.0
16.0
μA
μA
VDD = 2.0V
VDD = 5.0V
D023
ICMP
Comparator Current(5)
—
—
15
55
22
67
μA
μA
VDD = 2.0V (per comparator)
VDD = 5.0V (per comparator)
D022
ICVREF CVREF Current(5)
—
—
30
75
60
125
μA
μA
VDD = 2.0V (high range)
VDD = 5.0V (high range)
D023
IFVR
—
85
120
μA
—
175
205
μA
VDD = 2.0V (0.6V reference and
1 comparator enabled)
VDD = 5.0V (0.6V reference and
1 comparator enabled)
—
120
150
μA
2.0V
—
200
250
μA
5.0V
D024
ΔIAD
Internal 0.6V Fixed Voltage
Reference Current(5)
A/D Conversion Current(5)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD;
WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
6: Does not include current through REXT. The current through the resistor can be estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
DS41268D-page 86
© 2007 Microchip Technology Inc.
PIC12F510/16F506
13.2
DC Characteristics: PIC12F510/16F506 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
See Figure 14-1
D002
VDR
RAM Data Retention Voltage(2)
—
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 10.4 “Power-on
Reset (POR)” for details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 10.4 “Power-on
Reset (POR)” for details
D010
IDD
Supply Current(3,4)
—
—
175
0.625
275
1.1
μA
mA
FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
—
—
250
1.0
450
1.5
μA
mA
FOSC = 8 MHz, VDD = 2.0V
FOSC = 8 MHz, VDD = 5.0V
—
1.4
2.0
mA
FOSC = 20 MHz, VDD = 5.0V
—
—
11
38
16
54
μA
μA
FOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020
IPD
Power-down Current(5)
—
—
0.1
0.35
9.0
15.0
μA
μA
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current(5)
—
—
1.0
7.0
18
22
μA
μA
VDD = 2.0V
VDD = 5.0V
D023
ICMP
Comparator Current(5)
—
—
15
55
25
75
μA
μA
VDD = 2.0V (per comparator)
VDD = 5.0V (per comparator)
D022
ICVREF CVREF Current(5)
—
—
30
75
65
135
μA
μA
VDD = 2.0V (high range)
VDD = 5.0V (high range)
D023
IFVR
—
85
130
μA
—
175
220
μA
VDD = 2.0V (0.6V reference and
1 comparator enabled)
VDD = 5.0V (0.6V reference and
1 comparator enabled)
—
120
150
μA
2.0V
—
200
250
μA
5.0V
D024
ΔIAD
Internal 0.6V Fixed Voltage
Reference Current(5)
A/D Conversion Current(5)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD;
WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
6: Does not include current through REXT. The current through the resistor can be estimated by the formula:
I = VDD/2REXT (mA) with REXT in kΩ.
© 2007 Microchip Technology Inc.
DS41268D-page 87
PIC12F510/16F506
13.3
DC Characteristics: PIC12F510/16F506 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
D030
with TTL buffer
D030A
VSS
—
0.8V
V
For 4.5 ≤ VDD ≤ 5.5V
VSS
—
0.15 VDD
V
otherwise
VSS
—
0.15 VDD
V
D031
with Schmitt Trigger buffer
D032
MCLR, T0CKI
VSS
—
0.15 VDD
V
D033
OSC1 (in EXTRC), EC(1)
VSS
—
0.15 VDD
V
D033
OSC1 (in HS)
VSS
—
0.3 VDD
V
D033
OSC1 (in XT and LP)
VSS
—
0.3 VDD
V
2.0
—
VDD
V
4.5 ≤ VDD ≤ 5.5V
0.25 VDD
—
VDD
V
Otherwise
For entire VDD range
VIH
Input High Voltage
I/O ports
D040
—
with TTL buffer
D040A
+ 0.8V
D041
with Schmitt Trigger buffer
0.85 VDD
—
VDD
V
D042
MCLR, T0CKI
0.85 VDD
—
VDD
V
D043
OSC1 (in EXTRC), EC(1)
0.85 VDD
—
VDD
V
D043
OSC1 (in HS)
0.7 VDD
—
VDD
V
D043
OSC1 (in XT and LP)
1.6
—
VDD
V
GPIO/PORTB Weak Pull-up Current
50
250
400
μA
D070
IPUR
IIL
VDD = 5V, VPIN = VSS
Input Leakage Current(2), (3)
D060
I/O ports
—
—
±1
μA
VSS ≤ VPIN ≤ VDD, Pin at high-impedance
D062
GP3/RB3/MCLR(5)
50
250
400
μA
VDD = 5V
D061A
GP3/RB3/MCLR(4)
—
+0.7
±5
μA
VSS ≤ VPIN ≤ VDD
D063
OSC1
—
—
±5
μA
VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator
configuration
Output Low Voltage
D080
VOL
I/O ports/CLKOUT
D080A
D083
OSC2
D083A
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C
—
—
0.6
V
IOL = 7.0 mA, VDD = 4.5V, –40°C to +125°C
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V, –40°C to +85°C
—
—
0.6
V
IOL = 1.2 mA, VDD = 4.5V, –40°C to +125°C
Output High Voltage
D090
VOH
I/O ports/CLKOUT(3)
D090A
D092
OSC2
D092A
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C
VDD – 0.7
—
—
V
IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 4.5V, –40°C to +85°C
VDD – 0.7
—
—
V
IOH = -1.0 mA, VDD = 4.5V, –40°C to +125°C
In XT, HS and LP modes when external clock
is used to drive OSC1.
Capacitive Loading Specs on Output Pins
D100
D101
Note
COSC2 OSC2 pin
—
—
15
pF
CIO
—
—
50
pF
†
1:
2:
3:
4:
5:
All I/O pins
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F510/16F506 be
driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
This specification applies when GP3/MCLR is configured as an input with the pull-up disabled. The leakage current for the GP3/RB3/
MCLR pin is higher than for the standard I/O port pins.
This specification applies when GP3/RB3/MCLR is configured as the MCLR Reset pin function with the weak pull-up always enabled.
DS41268D-page 88
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-1:
Sym
COMPARATOR SPECIFICATIONS
Characteristics
VOS
Input Offset Voltage
VCM
Input Common Mode Voltage
CMRR
TRT
VIVRF
*
Note 1:
Common Mode Rejection Ratio
Response Time(1)
Internal Voltage Reference
Sym
*
Note 1:
Max
Units
—
±3
±10
mV
0
—
VDD – 1.5
V
+55*
—
—
dB
—
150
400*
ns
0.550
0.6
0.650
V
Comments
(VDD - 1.5V)/2
Internal
COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Characteristics
Min
Typ
Max
Units
Resolution
—
—
VDD/24*
VDD/32
—
—
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy
—
—
—
—
±1/2*
±1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R)
—
—
2K*
—
Ω
Settling Time(1)
Comments
—
—
10*
μs
These parameters are characterized but not tested.
Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
TABLE 13-3:
Param
No.
Typ
These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD – 1.5V.
TABLE 13-2:
CVRES
Min
Sym
A/D CONVERTER CHARACTERISTICS (PIC16F506/PIC12F510)
Characteristic
Min
Typ†
Max
Units
8 bits
bit
Conditions
A01
NR
Resolution
—
—
A03
EIL
Integral Error
—
—
± 1.5
LSb
VDD = 5.0V
A04
EDL
Differential Error
—
—
-1 < EDL ≤ 1.5
LSb
No missing codes to
8 bits VDD = 5.0V
A05
EFS
Full-scale Range
2
—
5.5*
V
A06
EOFF
Offset Error
—
—
± 1.5
LSb
A07
EGN
Gain Error
-0.5
—
+1.75
LSb
A10
—
Monotonicity
—
guaranteed(1)
—
—
A25
VAIN
Analog Input Voltage
VSS
—
VDD
V
A30
ZAIN
Recommended Impedance
of Analog Voltage Source
—
—
10
kΩ
VDD
VDD = 5.0V
VDD = 5.0V
VSS ≤ VAIN ≤ VDD
* These parameters are characterized but not tested.
† Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only are not tested.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
© 2007 Microchip Technology Inc.
DS41268D-page 89
PIC12F510/16F506
13.4
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
T Time
Lowercase (pp) and their meanings:
pp
2
To
mc
MCLR
ck
CLKOUT
osc
Oscillator
cy
Cycle Time
os
OSC1
drt
Device Reset Timer
t0
T0CKI
io
I/O port
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (high-impedance)
V
Valid
L
Low
Z
High-impedance
FIGURE 13-5:
LOAD CONDITIONS
Legend:
CL = 50 pF for all pins except OSC2
Pin
Cl
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
VSS
FIGURE 13-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
DS41268D-page 90
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-4:
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Para
No.
1A
Sym
FOSC
Characteristic
Min
Typ(1)
Max
External CLKIN Frequency(2)
DC
—
4
MHz XT Oscillator mode
DC
—
20
MHz HS/EC Oscillator mode
(PIC16F506 only)
DC
—
200
kHz
Oscillator Frequency
1
TOSC
(2)
External CLKIN Period(2)
Oscillator Period
(2)
Units
—
—
4
MHz EXTRC Oscillator mode
—
4
MHz XT Oscillator mode
4
—
20
MHz HS/EC Oscillator mode
(PIC16F506 only)
—
—
200
kHz
LP Oscillator mode
250
—
—
ns
XT Oscillator mode
50
—
—
ns
HS/EC Oscillator mode
(PIC16F506 only)
5
—
—
μs
LP Oscillator mode
250
—
—
ns
EXTRC Oscillator mode
250
—
10,000
ns
XT Oscillator mode
50
—
250
ns
HS/EC Oscillator mode
(PIC16F506 only)
LP Oscillator mode
5
—
—
μs
TCY
Instruction Cycle Time
200
4/FOSC
—
ns
3
TosL,
TosH
Clock in (OSC1) Low or High
Time
50*
—
—
ns
TosR,
TosF
*
Note 1:
2:
Clock in (OSC1) Rise or Fall
Time
LP Oscillator mode
0.1
2
4
Conditions
XT Oscillator
2*
—
—
μs
LP Oscillator
10
—
—
ns
HS/EC Oscillator
(PIC16F506 only)
—
—
25*
ns
XT Oscillator
—
—
50*
ns
LP Oscillator
—
—
15
ns
HS/EC Oscillator
(PIC16F506 only)
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
© 2007 Microchip Technology Inc.
DS41268D-page 91
PIC12F510/16F506
TABLE 13-5:
CALIBRATED INTERNAL RC FREQUENCIES
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
Param
Sym
No.
Freq.
Min
Tolerance
F10
Characteristic
FOSC Internal Calibrated INTOSC
Frequency(1)
*
Note 1:
Typ(1) Max* Units
±1%
±2%
7.92
7.84
8.00
8.00
8.08
8.16
±5%
7.60
8.00
8.40
Conditions
MHz VDD = 3.5V TA = 25°C
MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 13-7:
I/O TIMING
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
DS41268D-page 92
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-6:
TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
17
TOSH2IOV
OSC1↑ (Q1 cycle) to Port out valid(2), (3)
—
—
100*
ns
18
TOSH2IOI
OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)(2)
50
—
—
ns
19
TIOV2OSH
Port input valid to OSC1↑ (I/O in setup time)
20
—
—
ns
(2), (3)
20
TIOR
Port output rise time
—
10
25**
ns
21
TIOF
Port output fall time(2), (3)
—
10
25**
ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 13-5 for loading conditions.
FIGURE 13-8:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout(2)
Internal
Reset
Watchdog
Timer Reset
31
34
34
I/O pin(1)
Note 1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT Reset only in XT, LP and HS modes.
© 2007 Microchip Technology Inc.
DS41268D-page 93
PIC12F510/16F506
TABLE 13-7:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Param
Sym
No.
Characteristic
30
TMCL MCLR Pulse Width (low)
31
TWDT Watchdog Timer Time-out Period
(No Prescaler)
32
TDRT Device Reset Timer Period
Min
Typ(1)
Max
Units
2000*
—
—
ns
VDD = 5.0V
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
0.5*
0.5*
1.125*
1.125*
2*
2.5*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
—
—
2000*
ns
Standard
Short
34
TIOZ
*
Note 1:
I/O high-impedance from MCLR low
Conditions
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 13-9:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
TABLE 13-8:
TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
AC CHARACTERISTICS
Parm
No.
40
Sym
Tt0H
Characteristic
T0CKI High Pulse Width No Prescaler
With Prescaler
41
Tt0L
T0CKI Low Pulse Width No Prescaler
42
Tt0P
T0CKI Period
With Prescaler
*
Note 1:
Min
Typ(1) Max
Units
0.5 TCY + 20*
—
—
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
Conditions
ns
10*
—
—
ns
20 or TCY + 40* N
—
—
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS41268D-page 94
© 2007 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-9:
VDD (Volts)
PULL-UP RESISTOR RANGES
Temperature (°C)
RB0 (GP0)/RB1 (GP1)
2.0
5.5
RB3 (GP3)
2.0
5.5
Min
Typ
Max
Units
-40
25
85
125
-40
25
85
125
73K
73K
82K
86K
15K
15K
19K
23K
105K
113K
123K
132k
21K
22K
26k
29K
186K
187K
190K
190K
33K
34K
35K
35K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
-40
25
85
125
-40
25
85
125
63K
77K
82K
86K
16K
16K
24K
26K
81K
93K
96k
100K
20k
21K
25k
27K
96K
116K
116K
119K
22K
23K
28K
29K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
© 2007 Microchip Technology Inc.
DS41268D-page 95
PIC12F510/16F506
NOTES:
DS41268D-page 96
© 2007 Microchip Technology Inc.
PIC12F510/16F506
14.0
DC AND CHARACTERISTICS GRAPHS AND CHARTS.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean 3σ) respectively, where s is a standard deviation, over each temperature range.
FIGURE 14-1:
IDD vs. VDD OVER FOSC
XT Mode
1,400
1,200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Maximum
1,000
IDD (μA)
4 MHz
800
Typical
600
4 MHz
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS41268D-page 97
PIC12F510/16F506
FIGURE 14-2:
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical
(Sleep Mode all Peripherals Disabled)
0.45
0.40
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.35
IPD (μA)
0.30
0.25
0.20
0.15
0.10
0.05
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 14-3:
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum
(Sleep Mode all Peripherals Disabled)
18.0
16.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
14.0
Max. 125°C
IPD (μA)
12.0
10.0
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41268D-page 98
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 14-4:
80
COMPARATOR IPD vs. VDD (COMPARATOR ENABLED)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Maximum
IPD (μA)
60
Typical
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VDD (V)
TYPICAL WDT IPD vs. VDD
FIGURE 14-5:
9
8
7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
IPD (μA)
6
5
4
3
2
1
0
2.0
2.5
3.0
3.5
VDD (V)
© 2007 Microchip Technology Inc.
DS41268D-page 99
PIC12F510/16F506
FIGURE 14-6:
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
Maximum
25.0
20.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
IPD (μA)
Max. 125°C
15.0
10.0
Max. 85°C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 14-7:
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Max. 125°C
45
40
Max. 85°C
35
Time (ms)
30
Typical. 25°C
25
20
Min. -40°C
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41268D-page 100
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 14-8:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40×C TO 125×C)
0.8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.7
Max. 125°C
0.6
VOL (V)
0.5
Max. 85°C
0.4
Typical 25°C
0.3
0.2
Min. -40°C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 14-9:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
Typical:
Statistical
Mean @25×C
Maximum:
Mean
(Worst-Case
Temp) + 3σ
Maximum: Meas(-40×C
+ 3 to 125×C)
(-40°C to 125°C)
0.40
Max. 125°C
0.35
Max. 85°C
VOL (V)
0.30
0.25
Typ. 25°C
0.20
0.15
Min. -40°C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
© 2007 Microchip Technology Inc.
DS41268D-page 101
PIC12F510/16F506
FIGURE 14-10:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
VOH (V)
2.0
1.5
1.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
FIGURE 14-11:
(VDD = 5.0V)
VOH vs. IOH OVER TEMPERATURE
(
,
)
5.5
5.0
Max. -40°C
Typ. 25°C
VOH (V)
4.5
Min. 125°C
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
DS41268D-page 102
© 2007 Microchip Technology Inc.
PIC12F510/16F506
FIGURE 14-12:
TTL INPUT THRESHOLD VIN vs. VDD
(TTL Input, -40×C TO 125×C)
1.7
1.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Max. -40°C
VIN (V)
1.3
Typ. 25°C
1.1
Min. 125°C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 14-13:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
(ST Input, -40×C TO 125×C)
4.0
VIH Max. 125°C
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
VIH Min. -40°C
VIN (V)
3.0
2.5
2.0
VIL Max. -40°C
1.5
VIL Min. 125°C
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS41268D-page 103
PIC12F510/16F506
FIGURE 14-14:
DEVICE RESET TIMER (HS, XT AND LP) vs. VDD
Maximum
(Sleep Mode all Peripherals Disabled)
45
40
35
Max. 125°C
DRT (ms)
30
25
Max. 85°C
20
Typical 25°C
15
Min. -40°C
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Note:
See Table 13-7 if another clock mode is selected.
DS41268D-page 104
© 2007 Microchip Technology Inc.
PIC12F510/16F506
15.0
PACKAGING
15.1
Package Marking Information
8-Lead PDIP
Example
12F510/P
017
0410
XXXXXXXX
XXXXXNNN
YYWW
14-Lead PDIP
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
PIC16F506-I/P
0410017
8-Lead SOIC (3.90 mm)
Example
XXXXXXXX
XXXXYYWW
NNN
PIC12F510-I
/SN0410
017
8-Lead 2x3 DFN*
Example
XXX
YWW
NN
BE0
610
17
TABLE 15-1:
8-LEAD 2X3 DFN (MC) TOP MARKING
Part Number
Marking
PIC12F510(T)-I/MC
BS0
PIC12F510-E/MC
BT0
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PIC® device marking consists of Microchip part number, year code, week code and traceability code. For
PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For
QTP devices, any special marking adders are included in QTP price.
© 2007 Microchip Technology Inc.
DS41268D-page 105
PIC12F510/16F506
15.2
Package Marking Information (Cont’d)
14-Lead SOIC (3.90 mm)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
8-Lead MSOP
XXXXXX
YWWNNN
14-Lead TSSOP (4.4 mm)
XXXXXXXX
YYWW
NNN
DS41268D-page 106
Example
PIC16F506
-I/SL
0410017
Example
602/MS
310017
Example
16F506/ST
0410
017
© 2007 Microchip Technology Inc.
PIC12F510/16F506
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DS41268D-page 107
PIC12F510/16F506
/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',[email protected]
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DS41268D-page 109
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© 2007 Microchip Technology Inc.
PIC12F510/16F506
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DS41268D-page 113
PIC12F510/16F506
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DS41268D-page 114
© 2007 Microchip Technology Inc.
PIC12F510/16F506
APPENDIX A:
REVISION HISTORY
Revision A
Original release.
Revision B
Page 3 – Special Microcontroller Features and LowPower Features sections.
PIC12F510 Pin Diagram.
Section 3.0 – Figure 3-1, Figure 3-2, Table 3-2,
Table 3-3.
Section 4.0 – First paragraph, Section 4.2 - Figure
references, Tables 4-1 and 4-2 (Note 1).
Section 5.0 – Table 5-2, Table 5-6 Title.
Section 6.0
Section 7.0 – First paragraph, Section 7.7, Register
7-1, Register 7-2, Register 7-3, Figure 7-1, Figure 7-2,
Sections 7.4 through 7.7, Table 7-1.
Section 8.0 – Sections 8.0 through 8.2, Figure 8-1,
Table 8-1.
Section 9.0 – Table 9-2, Register 9-1, Register 9-2,
Table 9-3.
Section 10.0 – Registers 10-1 and 10-2 (Note 1), Table
10-2 (Note 2), Section 10.2.5, Section 10.3,
Table 10-3, Table 10-4, Table 10-5, Section 10.4,
Section 10.5, Section 10.6.1, Section 10.9, 10.9.1,
10.9.2, Section 10.11.
Section 13.0 – 13.1 DC Characteristics, 13.2 DC
Characteristics, Table 13-1, Table 13-3, Table 13-4.
Revision C (03/2007)
Revised Table 3-2 GP3 and Legend; Revised Table 33 RB3 and Legend; Updated Registers to new format;
Revised Section 9.1; Revised Table 9-2; Revised 13.1
DC Characteristics D025; Revised Table 13-2 and
Table 13-3 and Notes; Replaced Package Drawings
(Rev. AN); Added DFN package; Replaced Development Support Section; Revised Product ID System.
Revision D (11/2007)
Revised Table 1-1; Table 4-1, Table 4-2; Figure 4-5;
Register 7-1 (Note 1); Register 8-1; Figure 13-4; 13.1 13.3; Table 13-1, Table 13-3, Table 13-6, Table 13-7,
Table 13-9; Figure 14-4, Figure 14-14; Section 14.0;
Packaging; Product ID System.
© 2007 Microchip Technology Inc.
DS41268D-page 115
PIC12F510/16F506
NOTES:
DS41268D-page 116
© 2007 Microchip Technology Inc.
PIC12F510/16F506
INDEX
A
M
ALU ....................................................................................... 9
Assembler
MPASM Assembler..................................................... 80
Block Diagram
Comparator for the PIC12F510................................... 46
Comparator for the PIC16F506................................... 46
On-Chip Reset Circuit ................................................. 64
Timer0......................................................................... 39
TMR0/WDT Prescaler................................................. 42
Watchdog Timer.......................................................... 67
Brown-Out Protection Circuit .............................................. 68
Memory Organization ......................................................... 15
Data Memory .............................................................. 16
Program Memory (PIC12F510/16F506) ..................... 15
Microchip Internet Web Site.............................................. 108
MPLAB ASM30 Assembler, Linker, Librarian ..................... 80
MPLAB ICD 2 In-Circuit Debugger ..................................... 81
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator...................................................... 81
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator...................................................... 81
MPLAB Integrated Development Environment Software.... 79
MPLAB PM3 Device Programmer ...................................... 81
MPLINK Object Linker/MPLIB Object Librarian .................. 80
C
O
C Compilers
MPLAB C18 ................................................................ 80
MPLAB C30 ................................................................ 80
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 14
Code Protection ............................................................ 55, 69
Configuration Bits................................................................ 55
Configuration Word (PIC12F510) ....................................... 56
Configuration Word (PIC16F506) ....................................... 57
Customer Change Notification Service ............................. 108
Customer Notification Service........................................... 108
Customer Support ............................................................. 108
OPTION Register................................................................ 20
OSC Selection .................................................................... 55
OSCCAL Register............................................................... 22
Oscillator Configurations..................................................... 58
Oscillator Types
HS............................................................................... 58
LP ............................................................................... 58
RC .............................................................................. 58
XT ............................................................................... 58
B
D
DC ....................................................................................... 88
DC Characteristics (Extended) ........................................... 87
DC Characteristics (Industrial) ............................................ 86
DC Characteristics (Industrial, Extended) ........................... 88
Development Support ......................................................... 79
Digit Carry ............................................................................. 9
E
Errata .................................................................................... 3
F
Family of Devices
PIC12F510/16F506....................................................... 5
FSR ..................................................................................... 24
I
I/O Interfacing ..................................................................... 27
I/O Ports .............................................................................. 27
I/O Programming Considerations........................................ 37
ID Locations .................................................................. 55, 69
INDF.................................................................................... 24
Indirect Data Addressing..................................................... 24
Instruction Cycle ................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Set Summary..................................................... 72
Internet Address................................................................ 108
L
Loading of PC ..................................................................... 23
© 2007 Microchip Technology Inc.
P
PIC12F510/16F506 Device Varieties ................................... 7
PICSTART Plus Development Programmer....................... 82
POR
Device Reset Timer (DRT) ................................... 55, 66
PD............................................................................... 68
Power-on Reset (POR)............................................... 55
TO............................................................................... 68
PORTB ............................................................................... 27
Power-down Mode.............................................................. 69
Prescaler ............................................................................ 41
Program Counter ................................................................ 23
Q
Q cycles .............................................................................. 14
R
RC Oscillator....................................................................... 59
Reader Response............................................................. 109
Read-Modify-Write.............................................................. 37
Register File Map
PIC12F510 ................................................................. 16
PIC16F506 ................................................................. 16
Registers
Special Function ......................................................... 17
Reset .................................................................................. 55
Reset on Brown-Out ........................................................... 68
S
Sleep ............................................................................ 55, 69
Software Simulator (MPLAB SIM) ...................................... 80
Special Features of the CPU .............................................. 55
Special Function Registers ................................................. 17
Stack................................................................................... 23
STATUS Register ..................................................... 9, 18, 51
DS41268D-page 117
PIC12F510/16F506
T
Timer0
Timer0 ......................................................................... 39
Timer0 (TMR0) Module ............................................... 39
TMR0 with External Clock........................................... 41
Timing Diagrams and Specifications................................... 91
Timing Parameter Symbology and Load Conditions........... 91
TRIS Registers.................................................................... 27
W
Wake-up from Sleep ........................................................... 69
Watchdog Timer (WDT) ................................................ 55, 66
Period.......................................................................... 66
Programming Considerations ..................................... 66
WWW Address.................................................................. 108
WWW, On-Line Support........................................................ 3
Z
Zero bit .................................................................................. 9
DS41268D-page 118
© 2007 Microchip Technology Inc.
PIC12F510/16F506
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2007 Microchip Technology Inc.
DS41268D-page 119
PIC12F510/16F506
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
Device: PIC12F510/16F506
N
Literature Number: DS41268D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41268D-page 120
© 2007 Microchip Technology Inc.
PIC12F510/16F506
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
c)
PIC16F506
PIC12F510
PIC16F506T(1)
PIC12F510T(2)
PIC16F506-E/P 301 = Extended Temp., PDIP
package, QTP pattern #301
PIC16F506-I/SN = Industrial Temp., SOIC
package
PIC16F506T-E/P = Extended Temp., PDIP
package, Tape and Reel
VDD range 2.0V to 5.5V
Temperature
Range:
I
E
= -40°C to +85°C
= -40°C to +125°C
Package:
MC
MS
P
SL
SN
ST
=
=
=
=
=
=
Pattern:
(Industrial)
(Extended)
8L DFN 2x3 (DUAL Flatpack No-Leads)(3, 4)
Micro-Small Outline Package (MSOP)(3, 4)
Plastic (PDIP)(4)
14L Small Outline, 3.90 mm (SOIC)(4)
8L Small Outline, 3.90 mm Narrow (SOIC)(4)
Thin Shrink Small Outline (TSSOP)(4)
Note 1:
2:
3:
4:
T
= in tape and reel SOIC and TSSOP
packages only
T = in tape and reel SOIC and MSOP
packages only.
PIC12F510 only.
Pb-free.
QTP, SQTP Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
DS41268D-page 121
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
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Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
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Tel: 45-4450-2828
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Tel: 91-20-2566-1512
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Tel: 33-1-69-53-63-20
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Tel: 81-45-471- 6166
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Tel: 49-89-627-144-0
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Atlanta
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Tel: 678-957-9614
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Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
10/05/07
DS41268D-page 122
© 2007 Microchip Technology Inc.