MCP2003/4/3A/4A LIN J2602 Transceiver Features Description • The MCP2003/2003A and MCP2004/2004A are compliant with Local Interconnect Network (LIN) Bus Specifications 1.3, 2.0 and 2.1 and are compliant to SAE J2602 • Support Baud Rates up to 20 Kbaud with LIN-compatible output driver • 43V load dump protected • Very low EMI meets stringent OEM requirements • Very high ESD immunity: - >20kV on VBB (IEC 61000-4-2) - >14kV on LBUS (IEC 61000-4-2) • Very high immunity to RF disturbances meets stringent OEM requirements • Wide supply voltage, 6.0V-27.0V continuous • Extended Temperature Range: -40 to +125°C • Interface to PIC® MCU EUSART and standard USARTs • LIN bus pin: - Internal pull-up resistor and diode - Protected against battery shorts - Protected against loss of ground - High current drive • Automatic thermal shutdown • Low-power mode: - Receiver monitoring bus and transmitter off, (≅ 5 µA) This device provides a bidirectional, half-duplex communication, physical interface to automotive and industrial LIN systems to meet the LIN bus specification Revision 2.1 and SAE J2602. The device is shortcircuit and over-temperature protected by internal circuitry. The device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. MCP200X family members: • 8-pin PDIP, DFN and SOIC packages: - MCP2003, LIN-compatible driver, with WAKE pins, wake up on falling edge of LBUS - MCP2003A, LIN-compatible driver, with WAKE pins, wake up on rising edge of LBUS - MCP2004, LIN-compatible driver, with FAULT/TXE pins, wake up on falling edge of LBUS - MCP2004A, LIN-compatible driver, with FAULT/TXE pins, wake up on rising edge of LBUS Package Types MCP2003/ 2003A PDIP, SOIC MCP2004/ 2004A PDIP, SOIC RXD 1 8 VREN CS 2 7 VBB WAKE 3 RXD 1 8 VREN CS/WAKE 2 7 VBB 6 LBUS FAULT/TXE 3 5 VSS TXD 4 TXD 4 MCP2003/ 2003A 4x4 DFN* RXD 1 8 VREN CS 2 7 VBB WAKE 3 TXD 4 EP 9 6 LBUS 5 VSS 6 LBUS 5 VSS MCP2004/ 2004A 4x4 DFN* RXD 1 CS/WAKE 2 FAULT/TXE 3 TXD 4 8 VREN EP 9 7 VBB 6 LBUS 5 VSS * Includes Exposed Thermal Pad (EP); see Table 1-1. © 2010-2011 Microchip Technology Inc. DS22230D-page 1 MCP2003/4/3A/4A MCP2003/2003A Block Diagram VREN VBB Ratiometric Reference 4.3V Wake-Up Logic and Power Control WAKE RXD CS ~30 kΩ TXD LBUS OC VSS Thermal Protection Short Circuit Protection MCP2004/2004A Block Diagram VREN VBB 4.3V 4.3V Ratiometric Reference Wake-Up Logic and Power Control RXD CS/WAKE ~30 kΩ TXD LBUS OC FAULT/TXE VSS Thermal Protection DS22230D-page 2 Short Circuit Protection © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 1.0 DEVICE OVERVIEW 1.2.3 THERMAL PROTECTION The MCP2003/4/3A/4A devices provide a physical interface between a microcontroller and a LIN bus. These devices will translate the CMOS/TTL logic levels to LIN logic level, and vice versa. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter. LIN specification 2.1 requires that the transceiver of all nodes in the system is connected via the LIN pin, referenced to ground and with a maximum external termination resistance load of 510Ω from LIN bus to battery supply. The 510Ω corresponds to 1 master and 15 slave nodes. • LIN bus output overload • Increase in die temperature due to increase in environment temperature The VREN pin can be used to drive the logic input of an external voltage regulator. This pin is high in all modes except for Power-Down mode. 1.1 1.1.1 There are two causes for a thermal overload. A thermal shut down can be triggered by either, or both, of the following thermal overload conditions. Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low). After a thermal overload event, the device will automatically recover once the die temperature has fallen below the recovery temperature threshold. See Figure 1-1. External Protection REVERSE BATTERY PROTECTION FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAM An external reverse-battery-blocking diode should be used to provide polarity protection (see Example 1-1). 1.1.2 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a 50Ω transient protection resistor (RTP) in series with the battery supply and the VBB pin serve to protect the device from power transients (see Example 1-1) and ESD events. While this protection is optional, it is considered good engineering practice. 1.2 1.2.1 LIN bus Shorted to VBB Operation Transmitter Mode Shutdown Temp < SHUTDOWNTEMP Internal Protection ESD PROTECTION For component-level ESD ratings, please refer to the maximum operation specifications. 1.2.2 GROUND LOSS PROTECTION The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a high-impedance level. © 2010-2011 Microchip Technology Inc. DS22230D-page 3 MCP2003/4/3A/4A 1.3 1.3.3 Modes of Operation For an overview of all operational modes, refer to Table 1-1. 1.3.1 In this mode, all internal modules are operational. The device will go into the Power-Down mode on the falling edge of CS. For the MCP2003/4 device, a specific process should be followed to put all nodes into Power-down mode. Refer to Section 1.6 “Enter Power-Down Mode” and Figure 1-6. The device will enter Transmitter Off mode in the event of a Fault condition. These include: thermal overload, bus contention and TXD timer expiration. POWER-DOWN MODE In Power-Down mode, everything is off except the wake-up section. This is the lowest power mode. The receiver is off, thus its output is open-drain. On CS going to a high level or a falling edge on WAKE (MCP2003/MCP2003A only), the device will enter Ready Mode as soon as internal voltage stabilizes. Refer to the AC Spec table. In addition, LIN bus activity will change the device from power-down mode to ready mode; MCP2003/4 wakes up on a falling edge of LIN bus and MCP2003/4A on a rising edge, following a low level lasting at least 20 µS of time. Refer to Figure 1-2 – Figure 1-5 about remote wake up. If CS is held high as the device transitions from Power-Down to Ready mode, the device will transition to either Operation or Transmitter Off mode, depending on TXD input, as soon as internal voltages stabilize. 1.3.2 The MCP2004/2004A device can also enter Transmitter Off mode if the FAULT/TXE pin is pulled low. The VBB-LBUS pull-up resistor is connected only in Operation mode. 1.3.4 TRANSMITTER OFF MODE Transmitter Off mode is reached whenever the transmitter is disabled either due to a Fault condition or pulling the nFAULT/TXE pin low on the MCP2004/ 2004A. The fault conditions include: thermal overload, bus contention or TXD timer expiration. READY MODE The device will go into Power-Down mode on the falling edge of CS, or return to Operation mode if all faults are resolved and the FAULT/TXE pin on the MCP2004/ 2004A is high. Upon entering the Ready mode, VREN is enabled and the receiver detect circuit is powered up. The transmitter remains disabled and the device is ready to receive data but not to transmit. Upon VBB supply pin power-on, the device will remain in Ready mode as long as CS is low. When CS transitions high, the device will either enter Operation mode, if TXD pin is held high, or the device will enter Transmitter Off mode, if TXD pin is held low. FIGURE 1-2: OPERATION MODE OPERATIONAL MODES STATE DIAGRAM – MCP2003 POR VREN OFF RX OFF TX OFF VBAT>5.5V Ready VREN ON RX ON TX OFF CS=1 & TXD=1 CS=1 & TXD=0 Falling edge on LIN or CS=1 or falling edge on WAKE PIN TOFF Mode VREN ON RX ON TX OFF CS=1 & TXD=1 & No Fault Fault (thermal or timer) Operation Mode VREN ON RX ON TX ON CS=0 CS=0 POWER DOWN VREN OFF RX OFF TX OFF DS22230D-page 4 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A FIGURE 1-3: OPERATIONAL MODES STATE DIAGRAM – MCP2003A POR VREN OFF RX OFF TX OFF VBAT>5.5V Ready VREN ON RX OFF TX OFF CS=1 & TXD=1 CS=1 & TXD=0 TOFF Mode VREN ON RX ON TX OFF Rising edge on LIN or CS=1 Or falling edge on WAKE PIN CS=1 & TXD=1 & No Fault Fault (thermal or timer) Operation Mode VREN ON RX ON TX ON CS=0 CS=0 POWER DOWN VREN OFF RX OFF TX OFF FIGURE 1-4: OPERATIONAL MODES STATE DIAGRAM – MCP2004 POR VREN OFF RX OFF TX OFF VBAT>5.5V Ready VREN ON RX ON TX OFF CS=1 & TXD=1 & TXE=1 CS=1 & (TXE=0 or TXD=0) Falling edge on LIN or CS=1 TOFF Mode VREN ON RX ON TX OFF CS=1 & TXD=1 &TXE=1 & No Fault Fault (thermal or timeout) or FAULT/TXE=0 Operation Mode VREN ON RX ON TX ON CS=0 CS=0 POWER DOWN VREN OFF RX OFF TX OFF © 2010-2011 Microchip Technology Inc. DS22230D-page 5 MCP2003/4/3A/4A FIGURE 1-5: OPERATIONAL MODES STATE DIAGRAM – MCP2004A POR VREN OFF RX OFF TX OFF Ready VREN ON RX ON TX OFF VBAT>5.5V CS=1 & TXD=1 & TXE=1 CS=1 & (TXE=0 or TXD=0) TOFF Mode VREN ON RX ON TX OFF Rising edge on LIN or CS=1 CS=1 & TXD=1 &TXE=1 & No Fault Fault (thermal or timeout) or FAULT/TXE=0 Operation Mode VREN ON RX ON TX ON CS=0 CS=0 POWER DOWN VREN OFF RX OFF TX OFF TABLE 1-1: State OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Vren Operation Comments POR OFF OFF OFF Check CS, if low then Ready; VBB > VBB (min) If high transitions to either TOFF or Operation and Internal mode, depending on TXD (2003/A), or TXD Supply stable and FAULT/TXE (2004/A). Ready OFF ON ON If CS high level, then either Operation or TXOFF mode. Operation ON ON ON If CS low level, then Power-Down; Normal Operation If FAULT/TXE low level, then Transmitter Off mode mode. Power-Down OFF Activity Detect OFF On CS high level, go to READY then either Low Power mode Operation mode or TXOFF. MCP2003/2003A: Falling edge on WAKE will put the device into READY mode. MCP2003/MCP2004: falling edge on LIN bus will put the device into READY mode. MCP2003A/MCP2004A: rising edge on LIN bus will put the device into READY mode. Transmitter Off OFF ON ON If CS low level, then Power-Down; FAULT/TXE only If FAULT/TXE and TXD high, then Operation available on mode MCP2004/2004A DS22230D-page 6 Bus Off state © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 1.4 Typical Applications EXAMPLE 1-1: TYPICAL MCP2003/2003A APPLICATION +12 optional resistor and transient suppressor +12 50W 43V 1.0 µF (See Note) Master Node Only +12 3.9KW Voltage Reg Vdd Vbb Vren 4.7KW Txd Txd Rxd Rxd I/O CS 1 KW LIN Bus Lbus 43V WAKE Wake-up Note: Vss For applications with current requirements of less than 20 mA, the connection to +12V can be deleted, and voltage to the regulator supplied directly from the VREN pin. EXAMPLE 1-2: TYPICAL MCP2004/2004A APPLICATION +12 +12 optional resistor and transient suppressor 50W 43V Wake-up 1.0 µF Master Node Only +12 220 KW Voltage Reg Vdd Vren Vbb 4.7KW Txd Txd Rxd Rxd I/O CS/WAKE I/O FAULT/TXE ZD1 © 2010-2011 Microchip Technology Inc. 100 pF 1 KW LIN Bus Lbus 43V Vss DS22230D-page 7 MCP2003/4/3A/4A EXAMPLE 1-3: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBB LIN bus MCP200X LIN bus MCP200X Slave 1 µC LIN bus MCP200X LIN bus MCP200X Slave 2 µC Slave n <23 µC Master µC DS22230D-page 8 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 1.5 Pin Descriptions TABLE 1-2: PINOUT DESCRIPTIONS MCP2003/2003A MCP2004/2004A Normal Operation Normal Operation 8-Pin PDIP, SOIC 8-Pin DFN RXD 1 1 Receive Data Output (OD), HV tolerant Receive Data Output (OD), HV tolerant CS 2 2 Chip Select (TTL), HV tolerant Chip Select/Local WAKE (TTL), HV tolerant WAKE (MCP2003/2003A only) FAULT/TXE (MCP2004/2004A only) 3 3 Wake up, HV tolerant Fault Detect Output (OD) Transmitter Enable (TTL) HV tolerant TXD 4 4 Transmit Data Input (TTL), HV tolerant Transmit Data Input (TTL), HV tolerant VSS 5 5 Ground Ground LBUS 6 6 LIN Bus (bidirectional) LIN Bus (bidirectional) VBB 7 7 Battery Positive Battery Positive VREN 8 8 Voltage Regulator Enable Output Voltage Regulator Enable Output EP — 9 Exposed Thermal Pad. Do not electrically connect or connect to Vss Pin Name Exposed Thermal Pad. Do not electrically connect or connect to Vss Legend: TTL = TTL Input Buffer; OD = Open-Drain Output 1.5.1 RECEIVE DATA OUTPUT (RXD) The Receive Data Output pin is an open drain (OD) output and follows the state of the LIN pin, except in Power Down mode. 1.5.2 CS (CHIP SELECT) This is the Chip Select Input pin. An internal pull-down resistor will keep the CS pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and an I/O initialization sequence. The pin must detect a high level to activate the transmitter. An internal LowPass filter, with a typical time constant of 10 µS, prevents unwanted wake-up (or transition to Power Down mode) on glitches. If CS = 0 when the VBB supply is turned on, the device goes to Ready mode as soon as internal voltages stabilize, and stays there as long as the CS pin is held low (0). In Ready mode, the receiver is on, and the LIN transmitter driver is off. If CS = 1 when the VBB supply is turned on, the device will proceed to Operation mode, or TXOFF (refer to Figure 1-2 – Figure 1-5), as soon as internal voltages stabilize. This pin may also be used as a local wake-up input (refer to Example 1-1). In this implementation, the microcontroller I/O controlling the CS should be © 2010-2011 Microchip Technology Inc. converted to a high-impedance input allowing the internal pull-down resistor to keep CS low. An external switch, or other source, can then wake-up both the transceiver and the microcontroller (if powered). Refer to Section 1.3 “Modes of Operation”, for detailed operation of CS. Note: 1.5.3 It is not recommended to tie CS high as this can result in the device entering Operation mode before the microcontroller is initialized and may result in unintentional LIN traffic. WAKE UP INPUT (WAKE) This pin is only available on the MCP2003/2003A. The WAKE pin has an internal 800K pull up to VBB. A falling edge on the WAKE pin causes the device to wake from Power-Down mode. Upon waking, the MCP2003/3A will enter Ready mode. 1.5.4 FAULT/TXE This pin is only available on the MCP2004/2004A. This pin is bidirectional and allows disabling of the transmitter, as well as fault reporting related to disabling the transmitter. This pin is an open-drain output, with states as defined in TABLE 1-3: “FAULT/ TXE Truth Table”. The transmitter is disabled whenever this pin is low (‘0’), either from an internal DS22230D-page 9 MCP2003/4/3A/4A Fault condition or by an external drive. While the transmitter is disabled, the internal 30 kΩ pull-up resistor on the LBUS pin is also disconnected to reduce current. Note: The FAULT/TXE pin is true (‘0’) whenever the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. TABLE 1-3: FAULT/TXE TRUTH TABLE FAULT/TXE TXD In RXD Out LINBUS I/O Thermal Override L H VBB H H L Definition External Input Driven Output OFF H L FAULT, TXD driven low, LINBUS shorted to VBB (Note 1) VBB OFF H H OK L GND OFF H H OK H L GND OFF H H OK, data is being received from the LINBUS x x VBB ON H L FAULT, Transceiver in thermal shutdown x x VBB x L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. 1.5.5 TRANSMIT DATA INPUT (TXD) The Transmit Data Input pin has an internal pull-up. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. For extra bus security, TXD is internally forced to ‘1’ whenever the transmitter is disabled regardless of external TXD voltage. 188.8.131.52 TXD Dominant Timeout If TXD is driven low for longer than approximately 25 mS, the LBUS pin is switched to recessive mode and the part enters TOFF Mode. This is to prevent the LIN node from permanently driving the LIN Bus dominant. The transmitter is reenabled on TXD rising edge. 1.5.6 GROUND (VSS) 184.108.40.206 The Bus Dominant Timer is an internal timer that deactivates the LBUS transmitter after approximately 25 milliseconds of dominant state on the LBUS pin. The timer is reset on any recessive LBUS state. The LIN bus transmitter will be reenabled after a recessive state on the LBUS pin as long as CS is high. Disabling can be caused by the LIN bus being externally held dominant, or by TXD being driven low. Additionally, on the MCP2004/2004A, the FAULT pin will be driven low to indicate the Transmitter Off state. 1.5.8 LIN BUS (LBUS) The bidirectional LIN Bus pin (LBUS) is controlled by the TXD input. LBUS has a current limited open collector output. To reduce EMI, the edges during the signal changes are slope controlled and include corner rounding control for both falling and rising edges. BATTERY (VBB) This is the Battery Positive Supply Voltage pin. 1.5.9 This is the Ground pin. 1.5.7 Bus Dominant Timer VOLTAGE REGULATOR ENABLE OUTPUT (VREN) This is the External Voltage Regulator Enable pin. Open source output is pulled high to VBB in all modes, except Power-Down. 1.5.10 EXPOSED THERMAL PAD (EP) Do not electrically connect, or connect to Vss. The internal LIN receiver observes the activities on the LIN bus, and matches the output signal RXD to follow the state of the LBUS pin. DS22230D-page 10 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 1.6 MCP2003/4 and MCP2003A/4A Difference Details The differences between the MCP2003/4 and the MCP2003/4A devices are isolated to the wake-up functionality. The changes were implemented to make the device more robust to LIN bus conditions, outside of the normal operating conditions. The MCP2003/4 will wake-up from Power Down Mode during any LIN falling edge held low longer than 20us. In the case where a LIN system is designed to minimize stand-by current by disconnecting all bus pull-ups resistors (including the external master pullup resistor to VBB), the original MCP2003/4 could wake up, if the floating bus drifted to a valid low level. The MCP2003/4A revisions were modified to require a rising edge after a valid low level. This will prevent an undesired system wake-up in this scenario, while maintaining functional capability with the original version. It should be noted that the original MCP2003/4 meets all LIN transceiver specification requirements and modules can be designed to pass all LIN system requirements. However, when all bus pull-up resistors are disconnected, the MCP2003/4 requires the module designer to write firmware to monitor the LIN Bus after any wake-up event to prevent the transceiver from automatically transitioning from Ready mode to Operational mode. If the MCP2003/4 is placed into Operational mode, VBB-LBUS pull-up resistor is automatically connected, FIGURE 1-6: Sequence which will raise the LIN bus to a recessive level; then putting the device to Power-Down mode may cause LBUS to be floating, and thus wake up all bus nodes. To prevent this, the designer should insure TXD (MCP2003) or TXE (MCP2004) is held low until valid bus activity is verified (see Figure 1-6). This will ensure the transceiver transitions from Ready mode to Transmitter Off mode, until bus activity can be verified. In the case of valid bus activity, the transceiver can shift to Operation mode, while if there is no bus activity, the device can be again placed into Power Down. The design practices needed to accomplish this are fully detailed in Tech Brief TB3067 - “MCP2003 Power-Down Mode and Wake-Up Handling in Case of LIN Bus Loss” (DS93067). The revised MCP2003/4A devices now eliminate the need for firmware to prevent system wide wake-up. The revised devices now require a longer valid bus low (see updated tBDB value in the Specification tables and FIGURE 2-7: “MCP2003A/4A Remote Wake-up”), which enables a rising edge detect circuit. The device will now only wake up after a rising edge, following a low longer than tBDB. While the module designer can still hold TXD (MCP2003) or TXE (MCP2004) low during wake-up, to enter Transmitter Off mode from Ready mode, it is not required to prevent an advertent system wake-up. In addition to the longer tBDB value, the time from wake-up detect to VREN enable is shortened as documented in the Specification table. MCP2003/2004 Switching Timing Diagram for the Forced Power-Down Mode tTx2CS >= 100ns tCSactive >= 100µs CS VREN TXD state depending on how the Slave Microcontroller is powered TXD to 0 forced externally TXD LIN bus disconnected LBUS State Power Down Mode after Master Sleep instruction © 2010-2011 Microchip Technology Inc. Ready Mode Transmitter OFF Mode Power Down Mode DS22230D-page 11 MCP2003/4/3A/4A 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD, TXD, FAULT/TXE, CS ............................................................................................. -0.3 to +43V VIN DC Voltage on WAKE and VREN .............................................................................................................-0.3 to +VBB VBB Battery Voltage, continuous, non-operating (Note 1)............................................................................. -0.3 to +40V VBB Battery Voltage, non-operating (LIN bus recessive) (Note 2) ................................................................ -0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VLBUS Bus Voltage, continuous ...................................................................................................................... -18 to +40V VLBUS Bus Voltage, transient (Note 3) ........................................................................................................... -27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB, WAKE (IEC 61000-4-2) (Note 4)............................................................................... ±8 KV ESD protection on LIN, VBB (Human Body Model) (Note 5) ................................................................................... ±8 KV ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................ ±4 KV ESD protection on all pins (Charge Device Model) (Note 6)................................................................................... ±2 KV ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V Maximum Junction Temperature ............................................................................................................................. 150°C Storage Temperature...................................................................................................................................-65 to +150°C Note 1: LIN 2.x compliant specification. 2: SAE J2602 compliant specification. 3: ISO 7637/1 load dump compliant (t < 500 ms). 4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications  to . For WAKE pin to meet the specification, series resistor must be in place (refer to Example 1-2). 5: According to AEC-Q100-002 / JESD22-A114. 6: According to AEC-Q100-011B. 7: According to AEC-Q100-003 / JESD22-A115. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device, at those or any other conditions above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2.2 Nomenclature used in this document Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent values are shown below. LIN 2.1 Name Term used in the following tables Definition VBAT not used ECU operating voltage VSUP VBB Supply voltage at device pin IBUS_LIM ISC Current Limit of Driver VBUSREC VIH(LBUS) Recessive state VBUSDOM VIL(LBUS) Dominant state DS22230D-page 12 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 2.3 DC Specifications DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 30.0V TA = -40°C to +125°C Sym Min. Typ. Max. Units Conditions 90 150 µA Operating Mode, bus recessive (Note 1) 75 120 µA Transmitter off, bus recessive (Note 1) Power VBB Quiescent Operating Current IBBQ VBB Transmitter-off Current IBBTO — VBB Power-Down Current IBBPD — 5 15 µA IBBNOGND -1 — 1 mA High Level Input Voltage (TXD, FAULT/TXE) VIH 2.0 — 30 V Low Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 — 0.8 V High Level Input Current (TXD, FAULT/TXE) IIH -2.5 — — µA Input voltage = 4.0V Low Level Input Current (TXD, FAULT/TXE) High Level Voltage (VREN) IIL -10 — — µA Input voltage = 0.5V VHVREN -0.3 — VBB+0.3 IHVREN -20 — -10 mA Output voltage = VBB0.5V High Level Input Voltage (CS) VIH 2.0 — 30 V Low Level Input Voltage (CS) VIL -0.3 — 0.8 V High Level Input Current (CS) IIH — — 10.0 µA Input voltage = 4.0V Low Level Input Current (CS) IIL — — 5.0 µA Input voltage = 0.5V Low Level Input Voltage (WAKE) VIL VBB – 4.0V — — V Low Level Output Voltage (RXD) VOL — — 0.4 V IIN = 2 mA High Level Output Current (RXD) IOH -1 — -1 µA VLIN = VBB, VRXD = 5.5V VBB Current with VSS Floating VBB = 12V, GND to VBB, VLIN = 0-27V Microcontroller Interface High Level Output Current (VREN) Note 1: 2: Through a current limiting resistor Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Node has to sustain the current that can flow under this condition; bus must be operational under this condition. © 2010-2011 Microchip Technology Inc. DS22230D-page 13 MCP2003/4/3A/4A 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 30.0V TA = -40°C to +125°C Sym Min. Typ. Max. Units Conditions High Level Input Voltage VIH(LBUS) 0.6 VBB — — V Recessive state Low Level Input Voltage VIL(LBUS) -8 — 0.4 VBB V Dominant state VHYS — — 0.175 VBB V Low Level Output Current IOL(LBUS) 40 — 200 mA High Level Output Current IOH(LBUS) — — 20 µA Pull-up Current on Input IPU(LBUS) 5 — 180 µA ~30 kΩ internal pull-up @ VIH (LBUS) = 0.7 VBB (Note 1) Bus Interface Input Hysteresis VIH(LBUS) – VIL(LBUS) Output voltage = 0.1 VBB, VBB = 12V Short Circuit Current Limit ISC 50 — 200 mA High Level Output Voltage VOH(LBUS) 0.9 VBB — VBB V Driver Dominant Voltage V_LOSUP — — 1.2 V VBB = 7V, RLOAD = 500Ω Driver Dominant Voltage V_HISUP — — 2.0 V VBB = 18V, RLOAD = 500Ω Driver Dominant Voltage V_LOSUP-1K 0.6 — — V VBB = 7V, RLOAD = 1 kΩ Driver Dominant Voltage V_HISUP-1K 0.8 — — V VBB = 18V, RLOAD = 1 kΩ Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 -0.4 — mA Driver off, VBUS = 0V, VBB = 12V Input Leakage Current (at the receiver during recessive bus level) IBUS_PAS_REC — 12 20 µA Driver off, 8V < VBB < 18V 8V < VBUs < 18V VBUS ≥ VBB Leakage Current (disconnected from ground) IBUS_NO_GND -10 1.0 +10 µA GNDDEVICE = VBB, 0V < VBUS < 18V, VBB = 12V Leakage Current (disconnected from VBB) IBUS_NO_VBB — — 10 µA VBB = GND, 0 < VBUS < 18V, (Note 2) Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2 Slave Termination RSLAVE 20 30 47 kΩ Capacitance of Slave Node CSLAVE 50 pF Note 1: 2: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS22230D-page 14 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 2.4 AC Specifications AC CHARACTERISTICS VBB = 6.0V to 27.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions Bus Interface – Constant Slope Time Parameters tslope 3.5 — 22.5 µs 7.3V <= VBB <= 18V ttranspd — — 4.0 µs ttranspd = max (ttranspdr or ttranspdf) Propagation Delay of Receiver trecpd — — 6.0 µs trecpd = max (trecpdr or trecpdf) Symmetry of Propagation Delay of Receiver Rising Edge w.r.t. Falling Edge trecsym -2.0 — 2.0 µs trecsym = max (trecpdf – trecpdr) RRXD 2.4Ω TO VCC, CRXD 20 PF ttranssym -2.0 — 2.0 µs ttranssym = max (ttranspdf - ttranspdr) tfault — — 32.5 µs tfault = max (ttranspd + tslope + trecpd) Duty Cycle 1 @20.0 kbit/sec .396 — — Cbus; Rbus conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THrec(max) = 0.744 x VBB, THdom(max) = 0.581 x VBB, VBB =7.0V – 18V; tbit = 50 µs D1 = tbus_rec(min)/2 x tbit) Duty Cycle 2 @20.0 kbit/sec — — .581 Cbus; Rbus conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THrec(max) = 0.284 x VBB, THdom(max) = 0.422 x VBB, VBB =7.6V – 18V; tbit = 50 µs D2 = tbus_rec(max)/2 x tbit) Duty Cycle 3 @10.4 kbit/sec .417 — — Cbus; Rbus conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THrec(max) = 0.778 x VBB, THdom(max) = 0.616 x VBB, VBB =7.0V – 18V; tbit = 96 µs D3 = tbus_rec(min)/2 x tbit) Duty Cycle 4 @10.4 kbit/sec — — .590 Cbus; Rbus conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THrec(max) = 0.251 x VBB, THdom(max) = 0.389 x VBB, VBB =7.6V – 18V; tbit = 96 µs D4 = tbus_rec(max)/2 x tbit) 20 µs MCP2003/2004 70 125 µs MCP2003A/2004A Slope Rising and Falling Edges Propagation Delay of Transmitter Symmetry of Propagation Delay of Transmitter Rising Edge w.r.t. Falling Edge Time to Sample of FAULT/TXE for Bus Conflict Reporting Wake-up Timing Bus Activity Debounce time tBDB 5 30 Bus Activity to Vren on tBACTVE 35 10 30 150 µs MCP2003/2004 90 µs MCP2003A/2004A 150 µs WAKE to Vren on tWAKE Chip Select to Vren on tCSOR — 150 µs Vren floating Chip Select to Vren off tCSPD — 80 µs Vren floating © 2010-2011 Microchip Technology Inc. DS22230D-page 15 MCP2003/4/3A/4A 2.5 Thermal Specifications THERMAL CHARACTERISTICS Parameter Symbol Typ Max Units Recovery Temperature θRECOVERY +140 — °C Shutdown Temperature θSHUTDOWN +150 — °C tTHERM 1.5 5.0 ms Short Circuit Recovery Time Test Conditions Thermal Package Resistances Thermal Resistance, 8L-DFN θJA 35.7 — °C/W Thermal Resistance, 8L-PDIP θJA 89.3 — °C/W Thermal Resistance, 8L-SOIC θJA 149.5 — °C/W Note 1: The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the device will go into thermal shutdown. DS22230D-page 16 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 2.6 Typical Performance Curves Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VBB = 6.0V to 18.0V, TA = -40°C to +125°C. TYPICAL IBBQ FIGURE 2-3: 0.14 0.12 0.12 0.1 0.1 -40C 25C 85C 125C 0.08 0.06 0.04 Current (mA) Current (mA) FIGURE 2-1: TYPICAL IBBTO 0.08 -40C 25C 85C 125C 0.06 0.04 0.02 0.02 0 0 6 7.3 12 14.4 18 6V VBB (V) FIGURE 2-2: 7.3V 12V 14.4V 18V VBB (V) TYPICAL IBBPD 0.008 0.007 Current (mA) 0.006 0.005 -40C 25C 85C 125C 0.004 0.003 0.002 0.001 0 6 7.3 12 14.4 18 VBB (V) © 2010-2011 Microchip Technology Inc. DS22230D-page 17 MCP2003/4/3A/4A 2.7 Timing Diagrams and Specifications FIGURE 2-4: BUS TIMING DIAGRAM TXD 50% 50% LBUS .95VLBUS .50VBB 0.05VLBUS TTRANSPDR TTRANSPDF TRECPDF 0.0V TRECPDR RXD 50% Internal TXD/RXD Compare Match 50% Match Match Match Match FAULT Sampling TFAULT TFAULT FAULT/TXE Output Stable FIGURE 2-5: CS Hold Value Stable Hold Value Stable CS TO VREN TIMING DIAGRAM TCSOR VBB VREN OFF TCSPD DS22230D-page 18 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A FIGURE 2-6: MCP2003/4 REMOTE WAKE-UP FIGURE 2-7: MCP2003A/4A REMOTE WAKE-UP © 2010-2011 Microchip Technology Inc. DS22230D-page 19 MCP2003/4/3A/4A 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4) Examples: XXXX YYWW NNN 2004A E/MD^^e3 1148 256 2004 e3 E/MD^^ 0948 256 PIN 1 8-Lead PDIP (300 mil) Examples: MCP2003A e3 E/P^^256 1148 XXXXXXXX XXXXXNNN MCP2003 e3 E/P^^256 0948 YYWW 8-Lead SOIC (150 mil) MCP2003E e3 SN^^1148 256 NNN Legend: XX...X Y YY WW NNN e3 * Note: DS22230D-page 20 Examples: 2003AE e3 SN^^0948 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 © 2010-2011 Microchip Technology Inc. DS22230D-page 21 MCP2003/4/3A/4A 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 DS22230D-page 22 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010-2011 Microchip Technology Inc. DS22230D-page 23 MCP2003/4/3A/4A 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; < & & & = = ##44!! - 1!& & = = "#& "#>#& . - - ##4>#& . < : 9& -< -? & & 9 - 9#4!! < ) ? ) < 1 = = 69#>#& 9 *9#>#& : *+ 1, - !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/!# '! #& .0 1,21!'! &$& "! **& "&& ! * ,<1 DS22230D-page 24 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010-2011 Microchip Technology Inc. DS22230D-page 25 MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22230D-page 26 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A ! ""#$%& !' 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 © 2010-2011 Microchip Technology Inc. DS22230D-page 27 MCP2003/4/3A/4A NOTES: DS22230D-page 28 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A APPENDIX A: REVISION HISTORY Revision D (December 2011) The following is the list of modifications: 1. 2. Added the MCP2003A and MCP2004A devices and related information throughout the document. Updated Figures 1.2, 1.3, 1.4, 1.5, 2.6, 2.7. Revision C (August 2010) The following is the list of modifications: 1. Updated all references of Sleep mode to PowerDown mode, and updated the Max. parameter for Duty Cycle 2 in Section 2.4 “AC Specifications”. Revision B (July 2010) The following is the list of modifications: 1. Added Section 2.2 “Nomenclature used in this document”, and added the “Capacitance of Slave Node” parameter to Section 2.3 “DC Specifications”. Revision A (March 2010) • Original Release of this Document. © 2010-2011 Microchip Technology Inc. DS22230D-page 29 MCP2003/4/3A/4A NOTES: DS22230D-page 30 © 2010-2011 Microchip Technology Inc. MCP2003/4/3A/4A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device: MCP2003: LIN Transceiver, with WAKE pins, wake up on falling edge of LBUS MCP2003T: LIN Transceiver, with WAKE pins, wake up on falling edge of LBUS (Tape and Reel) (DFN and SOIC) MCP2003A: LIN Transceiver, with WAKE pins, wake up on rising edge of LBUS MCP2003AT: LIN Transceiver, with WAKE pins, wake up on rising edge of LBUS (Tape and Reel) (DFN and SOIC) MCP2004: LIN Transceiver with FAULT/TXE pins, wake up on falling edge of LBUS MCP2004T: LIN Transceiver with FAULT/TXE pins, wake up on falling edge of LBUS (Tape and Reel) (DFN and SOIC) MCP2004A: LIN Transceiver with FAULT/TXE pins, wake up on rising edge of LBUS MCP2004AT: LIN Transceiver with FAULT/TXE pins, wake up on rising edge of LBUS (Tape and Reel) (DFN and SOIC) Temperature Range: E Package: = -40°C to +125°C c) d) e) a) b) c) d) e) MCP2003A-E/MD: Extended Temperature, 8L-DFN package MCP2003A-E/P: Extended Temperature, 8L-PDIP package MCP2003A-E/SN: Extended Temperature, 8L-SOIC package MCP2003AT-E/MD: Tape and Reel, Extended Temperature, 8L-DFN package MCP2003AT-E/SN: Tape and Reel, Extended Temperature, 8L-SOIC package MCP2004-E/MD: Extended Temperature, 8L-DFN package MCP2004-E/P: Extended Temperature, 8L-PDIP package MCP2004A-E/SN: Extended Temperature, 8L-SOIC package MCP2004AT-E/MD: Tape and Reel, Extended Temperature, 8L-DFN package MCP2004AT-E/SN: Tape and Reel, Extended Temperature, 8L-SOIC package MD = Plastic Micro Small Outline (4x4), 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead © 2010-2011 Microchip Technology Inc. DS22230D-page 31 MCP2003/4/3A/4A NOTES: DS22230D-page 32 © 2010-2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-920-5 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2010-2011 Microchip Technology Inc. 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