TMP175 TMP75 TM P75 TM P17 5 SBOS288C – JANUARY 2004 – REVISED MARCH 2004 Digital Temperature Sensor with Two-Wire Interface DESCRIPTION FEATURES 27 ADDRESSES (TMP175) 8 ADDRESSES (TMP75) DIGITAL OUTPUT: Two-Wire Serial Interface RESOLUTION: 9- to 12-Bits, User-Selectable ACCURACY: ±1.5°C (max) from –25°C to +85°C ±2.0°C (max) from –40°C to +125°C LOW QUIESCENT CURRENT: 50µ µA, 0.1µ µA Standby WIDE SUPPLY RANGE: 2.7V to 5.5V SMALL SO-8 PACKAGE The TMP175 and TMP75 are Two-Wire, serial output temperature sensors available in an SO-8 package. Requiring no external components, the TMP175 and TMP75 are capable of reading temperatures with a resolution of 0.0625°C. The TMP175 and TMP75 feature a Two-Wire interface that is SMBus-compatible, with the TMP175 allowing up to 27 devices on one bus and the TMP75 allowing up to eight devices on one bus. The TMP175 and TMP75 both feature an SMBus alert function. The TMP175 and TMP75 are ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. APPLICATIONS POWER-SUPPLY TEMPERATURE MONITORING COMPUTER PERIPHERAL THERMAL PROTECTION NOTEBOOK COMPUTERS CELL PHONES BATTERY MANAGEMENT OFFICE MACHINES THERMOSTAT CONTROLS ENVIRONMENTAL MONITORING and HVAC ELECTROMECHANICAL DEVICE TEMPERATURE The TMP175 and TMP75 are specified for operation over a temperature range of –40°C to +125°C. Temperature SDA SCL ALERT GND 1 Diode Temp. Sensor Control Logic 2 3 4 8 7 ∆Σ A/D Converter OSC V+ A0 Serial Interface 6 Config. and Temp. Register 5 A1 A2 TMP175, TMP75 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Power Supply, V+ ............................................................................... 7.0V Input Voltage(2) .................................................................... –0.5V to 7.0V Input Current ..................................................................................... 10mA Operating Temperature Range ..................................... –55°C to +127°C Storage Temperature Range ......................................... –60°C to +130°C Junction Temperature (TJ Max) .................................................... +150°C Lead Temperature (soldering) ....................................................... +300°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTES: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. (2) Input voltage rating applies to all TMP175 and TMP75 input voltages. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TMP175 SO-8 D –40°C to +125°C TMP175 " " " " " TMP75 SO-8 D –40°C to +125°C TMP75 " " " " " TMP175AID TMP175AIDR TMP75AID TMP75AIDR Rails, 100 Tape and Reel, 2500 Rails, 100 Tape and Reel, 2500 PRODUCT NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PIN CONFIGURATIONS Top View SO-8 SCL 2 ALERT 3 GND 4 8 V+ SDA 1 7 A0 SCL 2 6 A1 ALERT 3 5 A2 GND 4 TMP75 1 TMP175 SDA 8 V+ 7 A0 6 A1 5 A2 NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. 2 TMP175, 75 www.ti.com SBOS288C ELECTRICAL CHARACTERISTICS At TA = –40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted. TMP175 PARAMETER CONDITION TEMPERATURE INPUT Range Accuracy (Temperature Error) MIN –40 –25°C to +85°C –40°C to +125°C vs Supply Resolution(1) ±0.5 ±1.0 0.2 +0.0625 Selectable DIGITAL INPUT/OUTPUT Input Capacitance Input Logic Levels: VIH VIL Leakage Input Current, IIN Input Voltage Hysteresis Output Logic Levels: VOL SDA VOL ALERT Resolution Conversion Time 0.7(V+) –0.5 0V - VIN - 6V SCL and SDA Pins MIN +125 ±1.5 ±2.0 ±0.5 –40 0 0 25 2.7 IQ ISD Serial Serial TEMPERATURE RANGE Specified Range Operating Range Thermal Resistance, θJA Serial Bus Inactive Bus Active, SCL Freq = Bus Active, SCL Freq = Serial Bus Inactive Bus Active, SCL Freq = Bus Active, SCL Freq = 50 100 410 0.1 60 380 400kHz 3.4MHz 400kHz 3.4MHz –40 –55 SO-8 UNITS +125 ±2.0 ±3.0 ±0.5 °C °C °C °C/V °C 0.7(V+) –0.5 pF 6.0 0.3(V+) 1 V V µA mV 0.4 0.4 V V Bits ms ms ms ms ms 500 0.4 0.4 37.5 75 150 300 74 5.5 85 0 0 25 0.15 0.15 9 to 12 27.5 55 110 220 54 2.7 50 100 410 0.1 60 380 3 +125 +127 150 MAX 3 6.0 0.3(V+) 1 0.15 0.15 9 to 12 27.5 55 110 220 54 TYP ±0.5 ±1.0 0.2 +0.0625 500 IOL = 3mA IOL = 4mA Selectable 9-Bit 10-Bit 11-Bit 12-Bit Serial Serial Shutdown Current MAX 3 Timeout Time POWER SUPPLY Operating Range Quiescent Current TYP TMP75 –40 –55 37.5 75 150 300 74 5.5 85 3 +125 +127 150 V µA µA µA µA µA µA °C °C °C/W NOTE: (1) Specified for 12-bit resolution. TMP175, 75 SBOS288C www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, V+ = 5.0V, unless otherwise noted. SHUTDOWN CURRENT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 1.0 85 0.9 75 0.8 V+ = 5V 0.7 0.6 ISD (µA) IQ (µA) 65 55 0.5 0.4 0.3 45 0.2 V+ = 2.7V 0.1 35 0.0 Serial Bus Inactive –0.1 25 –60 –10 40 90 –60 140 –40 –20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) CONVERSION TIME vs TEMPERATURE TEMPERATURE ACCURACY vs TEMPERATURE 300 2.0 Temperature Error (°C) Conversion Time (ms) 1.5 250 V+ = 5V 200 V+ = 2.7V 150 1.0 0.5 0.0 –0.5 –1.0 –1.5 12-bit resolution. 3 typical units 12-bit resolution. 100 –2.0 –60 –10 40 90 140 –60 –40 –20 0 Temperature (°C) 20 40 60 80 100 120 140 160 Temperature (°C) QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE 500 Hs MODE FAST MODE 450 400 IQ (µA) 350 300 250 200 125°C 150 25°C 100 50 –55°C 0 1k 10k 100k 1M 10M Frequency (Hz) 4 TMP175, 75 www.ti.com SBOS288C APPLICATIONS INFORMATION The TMP175 and TMP75 are digital temperature sensors that are optimal for thermal management and thermal protection applications. The TMP175 and TMP75 are Two-Wire and SMBus interface-compatible, and are specified over a temperature range of –40°C to +125°C. Pointer Register Temperature Register The TMP175 and TMP75 require no external components for operation except for pull-up resistors on SCL, SDA, and ALERT, although a 0.1µF bypass capacitor is recommended, as shown in Figure 1. SCL Configuration Register I/O Control Interface TLOW Register SDA THIGH Register V+ 0.1µF 8 To Two-Wire Controller SCL SDA 7 2 1 TMP175 TMP75 6 5 3 4 FIGURE 2. Internal Register Structure of TMP175 and TMP75. A0 A1 A2 ALERT (Output) P6 P5 P4 P3 P2 0 0 0 0 0 0 P1 P0 Register Bits TABLE I. Pointer Register Byte. NOTE: SCL, SDA, and ALERT pins require pull-up resistors. GND FIGURE 1. Typical Connections of the TMP175 and TMP75. The sensing device of the TMP175 and TMP75 is the chip itself. Thermal paths run through the package leads as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. To maintain accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive will assist in achieving accurate surface temperature measurement. Figure 2 shows the internal register structure of the TMP175 and TMP75. The 8-bit Pointer Register of the devices are used to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers should respond to a read or write command. Table I identifies the bits of the Pointer Register byte. Table II describes the pointer address of the registers available in the TMP175 and TMP75. Power-up Reset value of P1/P0 is 00. P1 P0 0 0 1 1 0 1 0 1 REGISTER Temperature Register (READ Only) Configuration Register (READ/WRITE) TLOW Register (READ/WRITE) THIGH Register (READ/WRITE) TABLE II. Pointer Addresses of the TMP175 and TMP75 Registers. TEMPERATURE REGISTER The Temperature Register of the TMP175 or TMP75 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table III and Table IV. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. Data format for temperature is summarized in Table V. Following power-up or reset, the Temperature Register will read 0°C until the first conversion is complete. POINTER REGISTER D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 TABLE III. Byte 1 of Temperature Register. D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 TABLE IV. Byte 2 of Temperature Register. TMP175, 75 SBOS288C P7 www.ti.com 5 TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) 128 127.9375 100 80 75 50 25 0.25 0.0 –0.25 –25 –55 –128 0111 0111 0110 0101 0100 0011 0001 0000 0000 1111 1110 1100 1000 1111 1111 0100 0000 1011 0010 1001 0000 0000 1111 0111 1001 0000 HEX 1111 1111 0000 0000 0000 0000 0000 0100 0000 1100 0000 0000 0000 7FF 7FF 640 500 4B0 320 190 004 000 FFC E70 C90 800 THIGH Measured Temperature TLOW TMP75/TMP175 ALERT PIN (Comparator Mode) POL = 0 TMP75/TMP175 ALERT PIN (Interrupt Mode) POL = 0 TMP75/TMP175 ALERT PIN (Comparator Mode) POL = 1 TABLE V. Temperature Data Format. The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to zero. TMP75/TMP175 ALERT PIN (Interrupt Mode) POL = 1 Read Read Read Time FIGURE 3. Output Transfer Function Diagrams. CONFIGURATION REGISTER The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration Register for the TMP175 and TMP75 is shown in Table VI, followed by a breakdown of the register bits. The power-up/reset value of the Configuration Register is all bits equal to 0. Byte D7 D6 D5 D4 D3 D2 D1 D0 1 OS R1 R0 F1 F0 POL TM SD TABLE VI. Configuration Register Format. SHUTDOWN MODE (SD) The Shutdown Mode of the TMP175 and TMP75 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to typically less than 0.1µA. Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is completed. When SD is equal to 0, the device will maintain a continuous conversion state. FAULT QUEUE (F1/F0) A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert function. If the temperature falls below TLOW, prior to reaching the number of programmed consecutive faults limit, the count is reset to 0. Table VII defines the number of measured faults that may be programmed to trigger an alert condition in the device. F1 F0 CONSECUTIVE FAULTS 0 0 1 1 0 1 0 1 1 2 4 6 TABLE VII. Fault Settings of the TMP175 and TMP75. CONVERTER RESOLUTION (R1/R0) THERMOSTAT MODE (TM) The Thermostat Mode bit of the TMP175 and TMP75 indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the section, High and Low Limit Registers. The Converter Resolution Bits control the resolution of the internal Analog-to-Digital (A/D) converter. This allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table VIII identifies the Resolution Bits and relationship between resolution and conversion time. POLARITY (POL) The Polarity Bit of the TMP175 and TMP75 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active LOW, as shown in Figure 3. For POL = 1, the ALERT Pin will be active HIGH, and the state of the ALERT Pin is inverted. R1 R0 RESOLUTION CONVERSION TIME (typical) 0 0 1 1 0 1 0 1 9 Bits (0.5°C) 10 Bits (0.25°C) 11 Bits (0.125°C) 12 Bits (0.0625°C) 27.5ms 55ms 110ms 220ms TABLE VIII. Resolution of the TMP175 and TMP75. 6 TMP175, 75 www.ti.com SBOS288C ONE-SHOT (OS) The TMP175 and TMP75 feature a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a 1 to the OS bit will start a single temperature conversion. The device will return to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption in the TMP175 and TMP75 when continuous temperature monitoring is not required. When the configuration register is read, the OS will always read zero. HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT pin of the TMP175 and TMP75 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin will remain active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin will become active and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle will repeat, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This will also clear the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). Byte D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 H3 H2 H1 H0 0 0 0 0 TABLE IX. Bytes 1 and 2 of THIGH Register. Byte D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 TABLE X. Bytes 1 and 2 of TLOW Register. speed (1kHz to 3.4MHz) modes. All data bytes are transmitted MSB first. SERIAL BUS ADDRESS To communicate with the TMP175 and TMP75, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP175 features three address pins to allow up to 27 devices to be addressed on a single bus interface. Table XI describes the pin logic levels used to properly connect up to 27 devices. ‘1’ indicates the pin is connected to the supply (VCC); ‘0’ indicates the pin is connected to GND; Float indicates the pin is left unconnected. The state of pins A0, A1, and A2 is sampled on every bus communication and should be set prior to any activity on the interface. Both operational modes are represented in Figure 3. Tables IX and X describe the format for the THIGH and TLOW registers. Power-up Reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C. The format of the data for THIGH and TLOW is the same as for the Temperature Register. All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE The TMP175 and TMP75 operate only as slave devices on the Two-Wire bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP175 and TMP75 both support the transmission protocol for fast (1kHz to 400kHz) and high- A1 A0 SLAVE ADDRESS 0 0 0 0 1 1 1 1 Float Float Float Float Float Float Float Float 0 0 1 1 0 0 1 1 0 1 Float 0 0 1 1 0 0 1 1 0 0 0 1 1 1 Float Float Float Float Float Float 0 1 0 1 Float Float Float 0 1 0 1 0 1 0 1 0 Float 1 0 Float 1 0 1 0 1 0 1 Float Float Float Float Float Float Float 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110101 0110110 0110111 TABLE XI. Address Pins and Slave Addresses for TMP175. TMP175, 75 SBOS288C A2 www.ti.com 7 The TMP75 features three address pins allowing up to eight devices to be connected per bus. Pin logic levels are described in Table XII. The address pins of the TMP175 and TMP75 are read after reset, at start of communication, or in response to a Two-Wire address acquire request. Following reading the state of the pins the address is latched to minimize power dissipation associated with detection. A2 A1 A0 SLAVE ADDRESS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 SLAVE MODE OPERATIONS The TMP175 and TMP75 can operate as slave receivers or slave transmitters. Slave Receiver Mode: TABLE XII. Address Pins and Slave Addresses for TMP75. BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH. WRITING/READING TO THE TMP175 AND TMP75 Accessing a particular register on the TMP175 and TMP75 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the TMP175 and TMP75 requires a value for the Pointer Register. (Refer to Figure 5.) When reading from the TMP175 and TMP75, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See Figure 7 for details of this 8 sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes, as the TMP175 and TMP75 will remember the Pointer Register value until it is changed by the next write operation. The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP175 or TMP75 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP175 or TMP75 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer register. The TMP175 and TMP75 will acknowledge reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. SMBus ALERT FUNCTION The TMP175 and TMP75 support the SMBus Alert function. When the TMP75 and TMP175 are operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP75 or TMP175 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP75 or TMP175 is active, the devices will acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to Figure 8 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command will determine which device will clear its ALERT status. If the TMP75 or TMP175 wins the arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP75 or TMP175 loses the arbitration, its ALERT pin will remain active. TMP175, 75 www.ti.com SBOS288C GENERAL CALL TIMING DIAGRAMS The TMP175 and TMP75 respond to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to commands in the second byte. If the second byte is 00000100, the TMP175 and TMP75 will latch the status of their address pins, but will not reset. If the second byte is 00000110, the TMP175 and TMP75 will latch the status of their address pins and reset their internal registers to their power-up values. The TMP175 and TMP75 are Two-Wire and SMBus compatible. Figures 4 to 8 describe the various operations on the TMP175 and TMP75. Bus definitions are given below. Parameters for Figure 4 are defined in Table XIII. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. HIGH-SPEED MODE Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. In order for the Two-Wire bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP175 and TMP75 will not acknowledge this byte, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP175 and TMP75 will switch the input and output filter back to fast-mode operation. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a NotAcknowledge on the last byte that has been transmitted by the slave. TIMEOUT FUNCTION The TMP175 and TMP75 will reset the serial interface if either SCL or SDA are held low for 54ms (typ) between a START and STOP condition. The TMP175 and TMP75 will release the bus if it is pulled low and will wait for a start condition. The timeout function requires a communication speed of at least 1kHz for SCL operating frequency. FAST MODE PARAMETER HIGH-SPEED MODE MIN MAX MIN MAX UNITS 0.4 0.001 3.4 MHz SCL Operating Frequency f(SCL) 0.001 Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns t(HDSTA) 100 100 ns Repeated START Condition Setup Time t(SUSTA) 100 100 ns STOP Condition Setup Time t(SUSTO) 100 100 ns Data Hold Time t(HDDAT) 0 0 ns Data Setup Time t(SUDAT) 100 10 ns SCL Clock LOW Period t(LOW) 1300 160 ns SCL Clock HIGH Period t(HIGH) 600 60 ns Hold Time After Repeated START Condition. After this period, the first clock is generated. Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns TABLE XIII. Timing Diagram Definitions for TMP175 and TMP75. TMP175, 75 SBOS288C www.ti.com 9 I2C TIMING DIAGRAMS t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(SUSTO) t(SUSTA) t(HDDAT) t(SUDAT) SDA t(BUF) P S S P FIGURE 4. Two-Wire Timing Diagram. 1 9 1 9 … SCL SDA 0 1 0 1 A2 A1 A0 R/W Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP75 ACK By TMP75 Frame 2 Pointer Register Byte Frame 1 Two-Wire Slave Address Byte 1 1 9 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 D1 D0 ACK By TMP75 ACK By TMP75 Frame 3 Data Byte 1 Stop By Master Frame 4 Data Byte 2 FIGURE 5. Two-Wire Timing Diagram for TMP75 Write Word Format. 1 9 9 1 … SCL SDA A7 A6 A5 A4 A3 A2 A1 A0 R/W Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP175 ACK By TMP175 Frame 1 Two-Wire Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 ACK By TMP175 Frame 3 Data Byte 1 D2 D1 D0 ACK By TMP175 Stop By Master Frame 4 Data Byte 2 FIGURE 6. Two-Wire Timing Diagram for TMP175 Write Word Format. 10 TMP175, 75 www.ti.com SBOS288C 1 9 1 9 … SCL SDA 0 1 0 1 0 0 R/W 0 Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP175 or TMP75 ACK By TMP175 or TMP75 Frame 1 Two-Wire Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 … SCL (Continued) SDA (Continued) 1 0 0 0 1 0 0 D7 R/W Start By Master D6 D5 D4 D3 ACK By TMP175 or TMP75 D1 … D0 From TMP175 or TMP75 Frame 3 Two-Wire Slave Address Byte 1 D2 ACK By Master Frame 4 Data Byte 1 Read Register 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 From TMP175 or TMP75 ACK By Master Stop By Master Frame 5 Data Byte 2 Read Register NOTE: Address Pins A0, A1, A2 = 0 FIGURE 7. Two-Wire Timing Diagram for Read Word Format. ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 Start By Master 0 R/W 1 ACK By TMP175 or TMP75 Frame 1 SMBus ALERT Response Address Byte 0 0 1 0 0 0 Status From NACK By TMP175 or TMP75 Master Stop By Master Frame 2 Slave Address Byte NOTE: Address Pins A0, A1, A2 = 0 FIGURE 8. Timing Diagram for SMBus ALERT. TMP175, 75 SBOS288C www.ti.com 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated