THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 D D D D D D D D THS4081 D OR DGN PACKAGE (TOP VIEW) Ultralow 3.4 mA Per Channel Quiescent Current High Speed – 175 MHz Bandwidth (–3 dB, G = 1) – 230 V/µs Slew Rate – 43 ns Settling Time (0.1%) High Output Drive, IO = 85 mA (typ) Excellent Video Performance – 35 MHz Bandwidth (0.1 dB, G = 1) – 0.01% Differential Gain – 0.05° Differential Phase Very Low Distortion – THD = –64 dBc (f = 1 MHz, RL = 150 Ω) – THD = –79 dBc (f = 1 MHz, RL = 1 kΩ) Wide Range of Power Supplies – VCC = ±5 V to ±15 V Available in Standard SOIC or MSOP PowerPAD Package Evaluation Module Available NC IN – IN + 1 8 2 7 3 6 VCC– 4 5 NC VCC+ OUT NC NC – No internal connection THS4082 D OR DGN PACKAGE (TOP VIEW) 1OUT 1IN – 1IN + VCC– 1 8 2 7 3 6 4 5 VCC+ 2OUT 2IN – 2IN+ Cross Section View Showing PowerPAD Option (DGN) description SUPPLY CURRENT vs SUPPLY VOLTAGE 3.8 3.6 I CC – Supply Current – mA The THS4081 and THS4082 are ultralow-power, high-speed voltage feedback amplifiers that are ideal for communication and video applications. These amplifiers operate off of a very low 3.4-mA quiescent current per channel and have a high output drive capability of 85 mA. The signal-amplifier THS4081 and the dual-amplifier THS4082 offer very good ac performance with 175-MHz bandwidth, 230-V/µs slew rate, and 43-ns settling time (0.1%). With total harmonic distortion (THD) of –64 dBc at f = 1 MHz, the THS4081 and THS4082 are ideally suited for applications requiring low distortion. TA=85°C 3.4 3.2 TA=25°C 3.0 2.8 2.6 TA=–40°C 2.4 2.2 5 RELATED DEVICES DEVICE DESCRIPTION THS4011/2 THS4031/2 THS4051/2 290-MHz Low Distortion High-Speed Amplifiers 100-MHz Low Noise High Speed-Amplifiers 70-MHz High-Speed Amplifiers 7 9 11 13 ± VCC - Supply Voltage - V 15 CAUTION: The THS4081 and THS4082 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 AVAILABLE OPTIONS PACKAGED DEVICES TA 0°C to 70°C – 40°C to 85°C NUMBER OF CHANNELS PLASTIC SMALL OUTLINE† (D) PLASTIC MSOP† (DGN) MSOP SYMBOL EVALUATION MODULE 1 THS4081CD THS4081CDGN AEO THS4081EVM 2 THS4082CD THS4082CDGN AER THS4082EVM 1 THS4081ID THS4081IDGN AEQ — 2 THS4082ID THS4082IDGN AEP — † The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4081CDGN). functional block diagram IN– IN+ 2 6 3 OUT Figure 1. THS4081 – Single Channel VCC 1IN– 1OUT 1IN+ 2IN– 2OUT 2IN+ –VCC Figure 2. THS4082 – Dual Channel 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE θJA (°C/W) θJC (°C/W) TA = 25°C POWER RATING D 167‡ 38.3 740 mW DGN§ 58.4 4.7 2.14 W ‡ This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W. § This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC. For further information, refer to Application Information section of this data sheet. recommended operating conditions MIN Supply voltage voltage, VCC+ CC and VCC– CC Operating free-air free air temperature, temperature TA NOM MAX Dual supply ±5 ±15 Single supply 10 30 0 70 – 40 85 C-suffix I-suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V °C 3 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) dynamic performance PARAMETER MIN TYP Gain = 1 VCC = ± 15 V VCC = ± 5 V Gain = –1 1 Bandwidth for 0.1 0 1 dB flatness VCC = ± 15 V VCC = ± 5 V Gain = 1 Full power bandwidth† VO(pp) = 20 V, VO(pp) = 5 V, VCC = ± 15 V VCC = ± 5 V Slew rate‡ VCC = ± 15 V, VCC = ± 5 V, 20-V step, Gain = 5 230 5-V step Gain = 1 170 Settling time to 0 0.1% 1% VCC = ± 15 V, VCC = ± 5 V, 5-V step Settling time to 0 0.01% 01% VCC = ± 15 V, VCC = ± 5 V, 5-V step Small signal bandwidth (–3 ( 3 dB) Small-signal BW SR TEST CONDITIONS VCC = ± 15 V VCC = ± 5 V ts 2-V step 2-V step MAX 175 MHz 160 70 MHz 65 35 MHz 35 2.7 MHz 7.1 V/µs 43 Gain = –1 1 ns 30 233 Gain = –1 1 UNIT ns 280 † Slew rate is measured from an output level range of 25% to 75%. ‡ Full power bandwidth = slew rate/2π VO(Peak). noise/distortion performance PARAMETER THD Vn In XT 4 Total harmonic distortion TEST CONDITIONS VO( O(pp)) = 2 V,, f = 1 MHz, Gain = 2 VCC = ± 15 V VCC = ± 5 V MIN TYP RL = 150 Ω –64 RL = 1 kΩ –79 RL = 150 Ω –64 RL = 1 kΩ –77 MAX UNIT dBc VCC = ± 5 V or ± 15 V, VCC = ± 5 V or ± 15 V, f = 10 kHz 10 nV/√Hz f = 10 kHz 0.7 pA/√Hz Differential gain error Gain = 2,, 40 IRE modulation, NTSC,, ± 100 IRE ramp VCC = ± 15 V VCC = ± 5 V 0.01% Differential phase error Gain = 2,, 40 IRE modulation, NTSC,, ± 100 IRE ramp VCC = ± 15 V VCC = ± 5 V 0.05° Channel-to-channel crosstalk (THS4082 only) VCC = ± 5 V or ± 15 V, f = 1 MHz Input voltage noise Input current noise POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.01% 0.05° –75 dB THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) dc performance PARAMETER TEST CONDITIONS VCC = ± 15 V V, VO = ± 10 V V, RL = 1 kΩ TA = 25°C TA = full range† VCC = ± 5 V V, VO = ± 2 2.5 5V V, RL = 250 Ω TA = 25°C TA = full range† Open loop gain VOS Offset voltage drift Input bias current IOS Input offset current TYP 10 19 8 VCC = ± 5 V or ± 15 V MAX 16 V/mV 7 1 7 8 1.2 TA = 25°C TA = full range† 20 6 8 250 400 TA = full range† † Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix Offset current drift mV µV/°C 15 TA = 25°C TA = full range† UNIT V/mV 9 TA = 25°C TA = full range† TA = full range† Input offset voltage IIB MIN 0.3 µA nA nA/°C input characteristics PARAMETER TEST CONDITIONS VICR Common mode input voltage range VCC = ± 15 V VCC = ± 5 V CMRR Common mode rejection ratio VCC = ± 15 V, VICR = ± 12 V, VCC = ± 5 V, VICR = ± 2 V, RI Input resistance TA = full range† TA = full range† MIN TYP ± 13.8 ±14.1 ± 3.8 ± 3.9 84 93 78 90 dB 1 MΩ 1.5 pF CI Input capacitance † Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix MAX UNIT V dB output characteristics PARAMETER VO Output voltage swing TEST CONDITIONS VCC = ± 15 V VCC = ± 5 V MIN TYP RL = 250 Ω ±12 ±13.6 RL = 150 Ω ±3.4 ± 3.8 ±13.5 ±13.8 ±3.5 ± 3.9 65 85 50 70 VCC = ± 15 V VCC = ± 5 V RL = 1 kΩ RL = 20 Ω IO Output current VCC = ± 15 V VCC = ± 5 V ISC Short-circuit current‡ VCC = ± 15 V 100 MAX UNIT V V mA mA RO Output resistance Open loop 13 Ω ‡ Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued) power supply PARAMETER VCC Supply voltage operating range TEST CONDITIONS Dual supply Single supply VCC = ± 15 V ICC Supply current (per amplifier) VCC = ± 5 V PSRR Power supply rejection ratio VCC = ± 5 V or ± 15 V † Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix 6 POST OFFICE BOX 655303 MIN TYP MAX ±4.5 ±16.5 9 33 TA = 25°C TA = full range† 3.4 4.2 TA = 25°C TA = full range† TA = full range† 2.9 3.7 • DALLAS, TEXAS 75265 5 UNIT V mA 4.5 79 90 dB THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 TYPICAL CHARACTERISTICS OPEN LOOP GAIN & PHASE RESPONSE vs FREQUENCY 0° 60.00 Gain 40.00 –45° 90° Phase 20.00 135° 0.00 VCC = ±15 V Gain = 1 RF = 0 Ω RL = 150 Ω 0 Crosstalk – dB 80.00 20 Phase Responce 45° Open Loop Gain – dB 100.00 CROSSTALK vs FREQUENCY –20 –40 –60 180° VCC = ±5 V and ±15 V –20.00 100 1k 10k 100k 1M 10M 100M –225° 1G –80 100k 1M f – Frequency – Hz TOTAL HARMONIC DISTORTION vs FREQUENCY –60 RL = 150 Ω –70 RL = 1 kΩ –90 100.00 1M f - Frequency - Hz –50 RL = 150 Ω –70 RL = 1 kΩ –80 –90 VCC = ±5 V(0.1%) VCC = ±15 V(0.1%) 2 1000.00 10M 3 4 5 VO – Output Step Voltage – V Figure 7 DISTORTION vs OUTPUT VOLTAGE DISTORTION vs OUTPUT VOLTAGE –50 –50 2nd Harmonic 2nd Harmonic –VCC –40 +VCC –60 –60 3rd Harmonic –70 –80 VCC = ± 15 V RL = 1 kΩ Gain = 5 f = 1 MHz –90 –80 Distortion – dBc –20 Distortion – dBc PSRR - Power Supply Rejection Ratio - dB VCC = ±15 V(0.01%) 130 10 100.00 1M f - Frequency - Hz –60 100M 3rd Harmonic –70 –80 VCC = ± 15 V RL = 150 Ω Gain = 5 f = 1 MHz –90 –100 Figure 8 VCC = ±5 V(0.01%) 170 50 VCC = ± 15 V & ± 5 V 1M 10M f - Frequency - Hz 210 Figure 6 POWER SUPPLY REJECTION RATIO vs FREQUENCY –100 100k 250 90 Figure 5 0 290 –60 –100 10.00 100k 1000.00 10M 330 VCC = ± 5 V Gain = 2 VO(PP) = 2 V Settling Time – ns THD - Total Harmonic Distortion - dBc THD - Total Harmonic Distortion - dBc –40 VCC = ± 15 V Gain = 2 VO(PP) = 2 V –100 10.00 100k 1G SETTLING vs OUTPUT STEP TOTAL HARMONIC DISTORTION vs FREQUENCY –40 –80 100M Figure 4 Figure 3 –50 10M f – Frequency – Hz –100 0 5 10 15 20 VO – Output Voltage – V Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 5 10 15 20 VO – Output Voltage – V Figure 10 7 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 TYPICAL CHARACTERISTICS DISTORTION vs FREQUENCY –60 –70 2nd Harmonic –80 DISTORTION vs FREQUENCY –50 VCC = ± 5 V RL = 1 kΩ Gain = 2 VO(PP) = 2 V –70 VCC = ± 15 V RL = 150 Ω Gain = 2 VO(PP) = 2 V –60 Distortion – dBc Distortion – dBc –60 –50 VCC = ± 15 V RL = 1 kΩ Gain = 2 VO(PP) = 2 V Distortion – dBc –50 DISTORTION vs FREQUENCY 2nd Harmonic –80 3rd Harmonic –70 2nd Harmonic –80 3rd Harmonic –90 –90 –90 3rd Harmonic –100 10.00 100k 100.00 1M –100 10.00 100k 1000.00 10M f – Frequency – Hz Figure 11 Figure 12 Figure 13 OUTPUT AMPLITUDE vs FREQUENCY 2nd Harmonic –80 –90 –2 f – Frequency – Hz Figure 14 –4 VCC = ± 15 V Gain = 1 RL = 1 kΩ VO(PP) = 63 mV 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz Figure 17 8 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz Figure 16 OUTPUT AMPLITUDE vs FREQUENCY 2 RF = 1.3 kΩ 0 RF = 0 Ω –2 –4 –6 –8 10.00 100k VCC = ± 5 V Gain = 1 RL = 1 kΩ VO(PP) = 63 mV Figure 18 • DALLAS, TEXAS 75265 RF = 2 kΩ 0 RF = 1 kΩ –2 –4 –6 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz POST OFFICE BOX 655303 Output Amplitude – dB –2 VCC = ± 5 V Gain = 1 RL = 150 Ω VO(PP) = 63 mV RF = 51 Ω Output Amplitude – dB Output Amplitude – dB RF = 0 Ω –2 –6 10.00 100k 2 RF = 51 Ω 0 RF = 0 Ω –4 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz RF = 130 Ω 0 OUTPUT AMPLITUDE vs FREQUENCY 2 –8 10.00 100k VCC = ± 15 V Gain = 1 RL = 150 Ω VO(PP) = 63 mV RF = 51 Ω 2 Figure 15 OUTPUT AMPLITUDE vs FREQUENCY –6 RF = 130 Ω RF = 0 Ω –6 10.00 100k 1000.00 10M RF = 51 Ω 0 –4 100.00 1M 4 Output Amplitude – dB 3rd Harmonic –70 2 1000.00 10M OUTPUT AMPLITUDE vs FREQUENCY 4 VCC = ± 5 V RL = 150 Ω Gain = 2 VO(PP) = 2 V –100 10.00 100k 100.00 1M f – Frequency – Hz Output Amplitude – dB Distortion – dBc –60 –100 10.00 100k 1000.00 10M f – Frequency – Hz DISTORTION vs FREQUENCY –50 100.00 1M –8 10.00 100k VCC = ± 15 V Gain = –1 RL = 150 Ω VO(PP) = 63 mV 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz Figure 19 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 2 2 2 RF = 2 kΩ RF = 1 kΩ –2 –4 VCC = ± 5 V Gain = –1 RL = 150 Ω VO(PP) = 63 mV RF = 1.3 kΩ –2 –4 –6 –8 10.00 100k 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz VCC = ± 15 V Gain = –1 RL = 1 kΩ VO(PP) = 63 mV Figure 22 OUTPUT AMPLITUDE vs FREQUENCY 4 2 0 –2 10.00 100k 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz VCC = ± 5 V Gain = 2 RL = 150 Ω VO(PP) = 126 mV V O – Output Voltage – V 6 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz 2 –2 10.00 100k VCC = ± 15 V Gain = 2 RL = 1 kΩ VO(PP) = 126 mV 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz Figure 25 5-V STEP RESPONSE 3 VCC = ± 5 V Gain = 2 RF = 1.2 kΩ RL = 150 Ω 0.8 VCC = ± 5 V Gain = 2 RL = 1 kΩ VO(PP) = 126 mV 4 2-V STEP RESPONSE RF = 1.2 kΩ 2 RF = 1.2 kΩ 0 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz 1.2 8 4 6 Figure 24 OUTPUT AMPLITUDE vs FREQUENCY RF = 1.5 kΩ Output Amplitude – dB VCC = ± 15 V Gain = 2 RL = 150 Ω VO(PP) = 126 mV RF = 750 Ω 2 V O – Output Voltage – V 2 RF = 1.5 kΩ RF = 1.5 kΩ Figure 23 Output Amplitude – dB 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz 8 6 Output Amplitude – dB Output Amplitude – dB 4 Figure 26 VCC = ± 5 V Gain = –1 RL = 1 kΩ VO(PP) = 63 mV RF = 1.2 kΩ RF = 1.5 kΩ RF = 750 Ω –2 10.00 100k –4 –8 10.00 100k 8 RF = 1.2 kΩ 0 –2 OUTPUT AMPLITUDE vs FREQUENCY 8 –2 10.00 100k RF = 1.3 kΩ Figure 21 OUTPUT AMPLITUDE vs FREQUENCY 6 0 –6 100.00 1000.00 10000.00 1M 10M 100M 100000.00 1G f - Frequency - Hz Figure 20 0 RF = 1.5 kΩ RF = 2 kΩ 0 Output Amplitude – dB 0 –8 10.00 100k RF = 1.5 kΩ Output Amplitude – dB Output Amplitude – dB RF = 1.3 kΩ –6 OUTPUT AMPLITUDE vs FREQUENCY 0.4 0.0 –0.4 –0.8 1 0 –1 VCC = ± 5 V Gain = –1 RF = 1.3 kΩ RL = 150 Ω –2 –1.2 –3 0 200 400 600 t - Time - ns 800 1000 Figure 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 200 400 600 t - Time - ns 800 1000 Figure 28 9 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 TYPICAL CHARACTERISTICS 2-V STEP RESPONSE VCC = ± 15 V Gain = 2 RF = 1.2 kΩ RL = 150 Ω 0.8 0.6 8 0.4 0.2 –0.0 –0.2 –0.4 –0.6 6 4 2 0 –2 –4 –6 –0.8 –8 –1.0 –10 –1.2 1.5 VCC = ± 15 V Gain = 5 RF = 1.2 kΩ RL = 150 Ω 10 V O – Output Voltage – V 1.0 –12 0 200 400 600 t - Time - ns 800 1000 0 200 Figure 29 400 600 t - Time - ns 800 1000 V 1.8 VO - Output Voltage - VCC = ±15 V 1.6 1.5 I VCC = ± 5 V 13 11 RL = 1 kΩ 9 RL = 150 Ω 7 5 3 –20 0 20 40 60 80 TA - Free-Air Temperature - °C 5 100 7 9 11 13 ±VCC - Supply Voltage - V Figure 32 1 –40 VCC = ± 5 V RL = 1 kΩ VCC = ± 5 V RL = 150 Ω –20 0 20 40 60 80 TA – Free-Air Temperature – _C Figure 35 10 I CC – Supply Current – mA VO – Output Voltage – V 7 3 11 9 7 5 3 5 7 9 11 13 ±VCC - Supply Voltage - V 15 Figure 34 VOLTAGE & CURRENT NOISE vs FREQUENCY 100 3.6 VCC = ± 15 V RL = 1 kΩ 5 TA=25°C 15 3.8 VCC = ± 15 V RL = 150 Ω 100 13 SUPPLY CURRENT vs SUPPLY VOLTAGE 15 –20 0 20 40 60 80 TA - Free-Air Temperature - °C 15 Figure 33 OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 9 0.3 –40 V n – Voltage Noise – nV/ Hz I n – Current Noise – pA/ Hz IB – Input Bias Current – µ A 1.9 11 VCC = ± 5 V 0.5 COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE 15 13 0.7 Figure 31 TA=25°C 1.3 –40 0.9 OUTPUT VOLTAGE vs SUPPLY VOLTAGE 2.0 1.4 VCC = ± 15 V 1.1 Figure 30 INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 1.7 1.3 V ICR – Common-Mode Input Voltage – ± V V O – Output Voltage – V 20-V STEP RESPONSE 12 V IO – Input Offset Voltage – mV 1.2 INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE TA=85°C 3.4 VCC = ± 15 V and ± 5 V TA = 25°C VN 10 3.2 TA=25°C 3.0 2.8 TA=–40°C 2.6 IN 1 2.4 100 0.1 2.2 5 7 9 11 13 ± VCC - Supply Voltage - V 15 Figure 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 100 1k 10k f - Frequency - Hz Figure 37 100k THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION theory of operation The THS408x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 38. (7) VCC + (6) OUT IN – (2) IN + (3) (4) VCC – Figure 38. THS4081 Simplified Schematic noise calculations and noise figure Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ratio (SNR) is very important. The noise model for the THS408x is shown in Figure 39. This model includes all of the noise sources as follows: • • • • en = Amplifier internal voltage noise (nV/√Hz) IN+ = Noninverting current noise (pA/√Hz) IN– = Inverting current noise (pA/√Hz) eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx ) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN– RG Ǹǒ Ǔ Figure 39. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e + ni Where: en 2 ǒ ) IN ) Ǔ )ǒ ǒ 2 R S IN– R ǓǓ ǒ Ǔ ø RG ) 4 kTRs ) 4 kT RF ø RG F 2 k = Boltzmann’s constant = 1.380658 × 10–23 T = Temperature in degrees Kelvin (273 +°C) RF || RG = Parallel resistance of RF and RG ǒ Ǔ To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + eni AV + e ni 1 ) RR F (noninverting case) G As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits Applications Report (literature number SLVA043). 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. NF + 10log ȱȧ Ȳǒ ȳȧ Ǔȴ e 2 ni 2 e Rs Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: ȱȧ ȡȧǒ ȧȧ )Ȣ ȧȲ e NF + 10log 1 Ǔ )ǒ ) 2 n IN 4 kTR Ǔ ȣȧȤȳȧ 2 R S S ȧȧ ȧȴ Figure 40 shows the noise figure graph for the THS408x. NOISE FIGURE vs SOURCE RESISTANCE 40.00 35.00 f = 10 kHz TA = 25°C Noise Figure (dB) 30.00 25.00 20.00 15.00 10.00 5.00 0.00 10 100 1k 10k 100k Source Resistance – RS (Ω) Figure 40. Noise Figure vs Source Resistance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS408x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 41. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 1.3 kΩ 1.3 kΩ _ Input 20 Ω Output THS408x + CLOAD Figure 41. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB– RG + – VI VO + RS ǒ ǒ ǓǓ ǒ ǒ ǓǓ IIB+ V OO + VIO 1 ) R R F G " IIB) RS 1 ) R R F G " IIB– RF Figure 42. Output Offset Voltage Model 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 43). RG RF – VI VO + R1 V O V I C1 ǒ Ǔǒ + 1 ) RRF G 1 f –3dB Ǔ 1 + 2pR1C1 ) sR1C1 1 Figure 43. Single-Pole Low-Pass Filter circuit layout considerations To achieve the levels of high frequency performance of the THS408x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS408x evaluation board is available to use as a guide for layout or for evaluating the device performance. D D D D D Ground planes – It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components – Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general PowerPAD design considerations The THS408x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 44(a) and Figure 44(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 44(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 44. Views of Thermally Enhanced DGN Package 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils) Figure 45. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 45. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS408xDGN IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered, so wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS408xDGN package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the THS408xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The actual thermal performance achieved with the THS408xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches, then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of the THS408x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 46 and is calculated by the following formula: P + D Where: ǒ Ǔ T –T MAX A q JA PD = Maximum power dissipation of THS408x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE Maximum Power Dissipation – W 3.5 DGN Package θJA = 58.4°C/W 2 oz. Trace And Copper Pad With Solder 3 2.5 SOIC Package High-K Test PCB θJA = 98°C/W 2 TJ = 150°C DGN Package θJA = 158°C/W 2 oz. Trace And Copper Pad Without Solder 1.5 1 0.5 SOIC Package Low-K Test PCB θJA = 167°C/W 0 –40 –20 60 80 0 20 40 TA – Free-Air Temperature – °C 100 NOTE A: Results are with no air flow and PCB size = 3”× 3” Figure 46. Maximum Power Dissipation vs Free-Air Temperature More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 47 to Figure 50 show this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result. When using VCC = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4082), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical. THS4081 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS VCC = ± 5 V TJ = 150°C TA = 50°C 180 1000 Maximum Output Current Limit Line | IO | – Maximum RMS Output Current – mA | IO | – Maximum RMS Output Current – mA 200 160 140 Package With θJA < = 127°C/W 120 100 SO-8 Package θJA = 167°C/W Low-K Test PCB 80 60 40 Safe Operating Area 20 THS4081 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 0 TJ = 150°C TA = 50°C VCC = ± 15 V DGN Package θJA = 58.4°C/W Maximum Output Current Limit Line 100 SO-8 Package θJA = 167°C/W Low-K Test PCB SO-8 Package θJA = 98°C/W High-K Test PCB Safe Operating Area 10 0 4 1 2 3 | VO | – RMS Output Voltage – V 5 0 3 6 9 12 | VO | – RMS Output Voltage – V 15 Figure 48 Figure 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION general PowerPAD design considerations (continued) THS4082 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 1000 Maximum Output Current Limit Line Package With θJA ≤ 64°C/W | IO | – Maximum RMS Output Current – mA | IO | – Maximum RMS Output Current – mA 200 160 140 120 100 SO-8 Package θJA = 167°C/W Low-K Test PCB 80 60 Safe Operating Area 40 SO-8 Package θJA = 98°C/W High-K Test PCB 20 0 0 VCC = ± 5 V TJ = 150°C TA = 50°C Both Channels 4 1 2 3 | VO | – RMS Output Voltage – V THS4082 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS VCC = ± 15 V TJ = 150°C TA = 50°C Both Channels 100 SO-8 Package θJA = 98°C/W High-K Test PCB 10 DGN Package θJA = 58.4°C/W Safe Operating Area 5 1 0 SO-8 Package θJA = 167°C/W Low-K Test PCB 3 6 9 12 | VO | – RMS Output Voltage – V Figure 50 Figure 49 20 Maximum Output Current Limit Line POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 APPLICATION INFORMATION evaluation board An evaluation board is available for the THS4081 (literature number SLOP242) and THS4082 (literature number SLOP239). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 51. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the THS4081 EVM User’s Guide or the THS4082 EVM User’s Guide. To order the evaluation board, contact your local TI sales office or distributor. VCC+ + C3 0.1 µF C2 6.8 µF R4 1.3 kΩ IN + R5 49.9 Ω + R3 49.9 Ω OUT THS4081 _ R2 1.3 kΩ + C4 0.1 µF C1 6.8 µF IN – R1 49.9 Ω VCC – Figure 51. THS4081 Evaluation Board POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 0.050 (1,27) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (4,00) 0.150 (3,81) 1 Gage Plane 7 A 0.010 (0,25) 0°– 8° 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / D 10/96 NOTES: A. B. C. D. 22 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS4081, THS4082 175-MHz LOW-POWER HIGH-SPEED AMPLIFIERS SLOS274C – DECEMBER 1999 – REVISED MAY 2000 MECHANICAL INFORMATION DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note D) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-187 PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated