STMICROELECTRONICS STM690RM6E

STM690, STM704, STM795
STM802, STM804, STM805, STM806
3 V supervisor with battery switchover
Features
■
RST or RST outputs
■
NVRAM supervisor for external LPSRAM
■
Chip enable gating (STM795 only) for external
LPSRAM (7 ns max prop delay)
■
Manual (push-button) reset input
■
200 ms (typ) trec
■
Watchdog timer - 1.6 s (typ)
■
Automatic battery switchover
■
Low battery supply current - 0.4 µA (typ)
■
Power-fail comparator (PFI/PFO)
■
Low supply current - 40 µA (typ)
■
Guaranteed RST (RST) assertion
down to VCC = 1.0 V
■
Operating temperature:
–40 °C to 85 °C (industrial grade)
■
RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1.
8
1
SO8 (M)
TSSOP8 3x3 (DS)(1)
1. Contact local ST sales office for availability.
Device summary
Watchdog
Input
STM690T/S/R
✓
Manual
reset
input
✓
✓
STM704T/S/R
✓
(2)
STM802T/S/R
✓
STM804T/S/R
✓
STM805T/S/R
✓
Battery
Power-fail
switchover comparator
✓
✓
✓
✓
✓
✓
STM795T/S/R
STM806T/S/R
Active- low Active- high
RST(1)
RST(1)
✓
✓
✓
✓
✓
✓(2)
✓
✓
✓(2)
✓
✓
✓
✓
✓
Chip enable
gating
1. All RST outputs push-pull (unless otherwise noted).
2. Open drain output.
August 2010
Doc ID 10519 Rev 9
1/42
www.st.com
1
Contents
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.1
MR (manual reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.2
WDI (watchdog input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.3
RST (active-low reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.4
RST (active-high reset - open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.5
PFI (power-fail input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.6
PFO (power-fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.7
VOUT (supply output voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.8
Vccsw (VCC switch output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.9
E (chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.10
ECON (conditional chip enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.11
VBAT (backup battery input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Push-button reset input (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Watchdog input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . 14
2.4
Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Chip enable gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6
Chip enable input (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7
Chip enable output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8
Power-fail input/output (NOT available on STM795) . . . . . . . . . . . . . . . . 17
2.9
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10
Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 19
2.11
Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Contents
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 10519 Rev 9
3/42
List of tables
STM690, STM704, STM795, STM802, STM804, STM805, STM806
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
4/42
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Logic diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip enable waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-fail comparator waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . . 18
Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCC to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VBAT to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 25
Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26
RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 28
E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
E to ECON propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 38
Doc ID 10519 Rev 9
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Description
1
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Description
The STM690/704/795/802/804/805/806 supervisors are self-contained devices which
provide microprocessor supervisory functions with the ability to non-volatize and writeprotect external LPSRAM. A precision voltage reference and comparator monitors the VCC
input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset
output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog
timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795)
to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1.
Logic diagram (STM690/802/804/805)
VCC VBAT
VOUT
WDI
PFI
STM690/
802/804/
805
RST (RST) (1)
PFO
VSS
AI08846
1. For STM804/805, reset output is active-high and open drain.
Figure 2.
Logic diagram (STM704/806)
VCC VBAT
VOUT
MR
PFI
STM704
STM806
RST
PFO
VSS
6/42
Doc ID 10519 Rev 9
AI08847
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 3.
Description
Logic diagram (STM795)
VCC VBAT
VOUT
VCCSW
STM795
RST
E
ECON
VSS
Table 2.
Signal names
MR
Push-button reset input
WDI
Watchdog input
RST
Active-low reset output
RST
AI08848
(1)
(2)
E
Active-high reset output
Chip enable input
ECON(2)
Conditioned chip enable output
Vccsw(2)
VCC switch output
VOUT
Supply voltage output
VCC
Supply voltage
VBAT
Backup supply voltage
PFI
Power-fail input
PFO
Power-fail output
VSS
Ground
1. Open drain for STM804/805 only.
2. STM795.
Doc ID 10519 Rev 9
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Description
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 4.
STM690/802/804/805 connections
SO8/TSSOP8
VOUT
VCC
VSS
PFI
1
2
3
4
8
7
6
5
VBAT
RST (RST)(1)
WDI
PFO
AI08849
1. For STM804/805, reset output is active-high and open drain.
Figure 5.
STM704/806 connections
SO8/TSSOP8
VOUT
VCC
VSS
PFI
1
2
3
4
8
7
6
5
V BAT
RST
MR
PFO
AI08850
Figure 6.
STM795 connections
SO8/TSSOP8
VOUT
VCC
VCCSW
VSS
8/42
1
2
3
4
8
7
6
5
Doc ID 10519 Rev 9
VBAT
RST
ECON
E
AI08851
STM690, STM704, STM795, STM802, STM804, STM805, STM806
1.1
Pin descriptions
1.1.1
MR (manual reset)
Description
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2
WDI (watchdog input)
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
1.1.3
RST (active-low reset)
Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold
or when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.4
RST (active-high reset - open drain)
Pulses high for trec when triggered, and stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
1.1.5
PFI (power-fail input)
When PFI is less than VPFI or when VCC falls below VSW (2.4 V), PFO goes low; otherwise,
PFO remains high. Connect to ground if unused.
1.1.6
PFO (power-fail output)
When PFI is less than VPFI, or VCC falls below VSW, PFO goes low; otherwise, PFO remains
high. Leave open if unused. Output type is push-pull.
1.1.7
VOUT (supply output voltage)
When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through
a P-channel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT. Connect
to VCC if no battery is used.
1.1.8
Vccsw (VCC switch output)
When VOUT switches to battery, Vccsw is high. When VOUT switches back to VCC, Vccsw is
low. It can be used to drive gate of external PMOS transistor for IOUT requirements
exceeding 75 mA. Output type is push-pull.
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Description
1.1.9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
E (chip enable input)
The input to the chip enable gating circuit. Connect to ground if unused.
1.1.10
ECON (conditional chip enable)
ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is
asserted, ECON will remain low for 15 µs or until E goes high, whichever occurs first. In the
disabled mode, ECON is pulled up to VOUT.
1.1.11
VBAT (backup battery input)
When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO +
hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is
used.
Table 3.
Pin description
Pin
Name
Function
STM795
STM690
STM802
STM704
STM806
STM804
STM805
—
—
6
—
MR
Push-button reset input
—
6
—
6
WDI
Watchdog input
7
7
7
—
RST
Active-low reset output
—
—
—
7
RST
Active-high reset output
—
4
4
4
PFI
Power-fail input
—
5
5
5
PFO
Power-fail output (push-pull)
1
1
1
1
VOUT
Supply output for external LPSRAM
2
2
2
2
VCC
Supply voltage
3
—
—
—
Vccsw
4
3
3
3
VSS
5
—
—
—
E
6
—
—
—
ECON
Conditioned chip enable output
8
8
8
8
VBAT
Backup battery input
10/42
Doc ID 10519 Rev 9
VCC switch output (push-pull)
Ground
Chip enable input
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 7.
Description
Block diagram (STM690/802/804/805)
V CC
V OUT
V BAT
V SO
COMPARE
V RST
COMPARE
WATCHDOG
TIMER
WDI
trec
generator
(1)
RST (RST)
PFI
V PFI
COMPARE
PFO
AI07897
1. For STM804/805, reset output is active-high and open drain.
Figure 8.
Block diagram (STM704/806)
V CC
V OUT
V BAT
V SO
COMPARE
V RST
COMPARE
trec
generator
MR
RST
PFI
V PFI
COMPARE
PFO
AI07898
Doc ID 10519 Rev 9
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Description
Figure 9.
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Block diagram (STM795)
V CC
V OUT
V BAT
V SO
COMPARE
V RST
COMPARE
V CCSW
t rec
generator
RST
E CON OUTPUT
CONTROL
E
E CON
PFI
V PFI
COMPARE
PFO
AI08852
12/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Description
Figure 10. Hardware hookup
VCCSW (2)
Regulator
Unregulated
voltage
VIN
VCC
VCC
VOUT
VCC
VCC
STM690/704/
795/802/804/
805/806
0.1 F
LPSRAM
E
E
0.1 F
WDI (1)
From microprocessor
E(2)
ECON(2)
R1
PFI (3)
PFO (3)
MR (4)
RST
To microprocessor NMI
R2
Push-button
To microprocessor reset
VBAT
AI08853
1. For STM690/802/804/805.
2. For STM795 only.
3. Not available on STM795.
4. For STM704/806.
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Operation
STM690, STM704, STM795, STM802, STM804, STM805, STM806
2
Operation
2.1
Reset output
The STM690/704/795/802/804/805/806 supervisor asserts a reset signal to the MCU
whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when
the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic
high for STM804/805) for 0 V < VCC < VRST if VBAT is greater than 1 V. Without a backup
battery, RST is guaranteed valid down to VCC = 1 V.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
2.2
Push-button reset input (STM704/806)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 36) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
2.3
Watchdog input (NOT available on STM704/795/806)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within tWD (1.6 s typ), the reset is asserted. The internal
watchdog timer is cleared by either:
1.
a reset pulse, or
2.
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (tWD + trec).
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see Figure 37).
Note:
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Input frequency greater than 20 ns (50 MHz) will be filtered.
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
2.4
Operation
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices
automatically switch the SRAM to the backup supply when VCC falls.
Note:
When the battery is first connected without VCC power applied, the device does not
immediately provide battery backup voltage on VOUT. Only after VCC exceeds VRST will the
switchover operate as described below. This mode allows a battery to be attached during
manufacturing but not used until after the system has been activated for the first time. As a
result, no battery power is consumed by the device during storage and shipment. If the
backup battery is not used, connect both VBAT and VOUT to VCC.
This family of supervisors does not always connect VBAT to VOUT when VBAT is greater than
VCC. VBAT connects to VOUT (through a 100 Ω switch) when VCC is below VSW (2.4 V) or
VBAT (whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V lithium cell)
to have a higher voltage than VCC.
Assuming that VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered
before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most
external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO
point. VOUT is connected to VCC through a 3 Ω PMOS power switch.
Note:
The backup battery may be removed while VCC is valid, assuming VBAT is adequately
decoupled (0.1 µF typ), without danger of triggering a reset.
Table 4.
I/O status in battery backup
Pin
Status
VOUT
Connected to VBAT through internal switch
VCC
Disconnected from VOUT
PFI
Disabled
PFO
Logic low
E
High impedance
ECON
Logic high
WDI
Watchdog timer is disabled
MR
Disabled
RST
Logic low
RST
Logic high
VBAT
Connected to VOUT
Vccsw
Logic high (STM795)
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Operation
2.5
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Chip enable gating (STM795 only)
Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the
external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series
transmission gate from E to ECON (see Figure 11). During normal operation (reset not
asserted), the E transmission gate is enabled and passes all E transitions. When reset is
asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS
RAM. The short E propagation delay from E to ECON enables the STM795 to be used with
most µPs. If E is low when reset asserts, ECON remains low for typically 10 µs to permit the
current write cycle to complete.
2.6
Chip enable input (STM795 only)
The chip enable transmission gate is disabled and E is high impedance (disabled mode)
while reset is asserted. During a power-down sequence when VCC passes the reset
threshold, the chip enable transmission gate disables and E immediately becomes high
impedance if the voltage at E is high. If E is low when reset asserts, the chip enable
transmission gate will disable 10 µs after reset asserts (see Figure 12). This permits the
current write cycle to complete during power-down.
Any time a reset is generated, the chip enable transmission gate remains disabled and E
remains high impedance (regardless of E activity) for the first half of the reset time-out
period (trec/2). When the chip enable transmission gate is enabled, the impedance of E
appears as a 40 Ω resistor in series with the load at ECON. The propagation delay through
the chip enable transmission gate depends on VCC, the source impedance of the drive
connected to E, and the loading on ECON. The chip enable propagation delay is production
tested from the 50% point on E to the 50% point on ECON using a 50 Ω driver and a 50 pF
load capacitance (see Figure 35). For minimum propagation delay, minimize the capacitive
load at ECON and use a low-output impedance driver.
2.7
Chip enable output (STM795 only)
When the chip enable transmission gate is enabled, the impedance of ECON is equivalent to
a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission
gate is off and an active pull-up connects ECON to VOUT (see Figure 11). This pull-up turns
off when the transmission gate is enabled.
Figure 11. Chip enable gating
V CC
V RST
trec
generator
COMPARE
RST
V OUT
E CON OUTPUT
CONTROL
E
E CON
AI08802
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Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Operation
Figure 12. Chip enable waveform (STM795)
V CC
E CON
V RST
V BAT
½ trec
RST
trec
½ trec
10 µs
trec
E
AI08855c
2.8
Power-fail input/output (NOT available on STM795)
The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from
the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail
Output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 10) to either the unregulated DC input (if it is available) or the regulated output
of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls
below VPFI several milliseconds before the regulated VCC input to the STM690/704/795/802/
804/805/806 or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator is turned off and PFO goes (or remains)
low (see Figure 13). This occurs after VCC drops below VSW (2.4 V). When power returns,
the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI
should be connected to VSS and PFO left unconnected. PFO may be connected to MR on
the STM704/806 so that a low voltage on PFI will generate a reset output.
2.9
Applications information
These supervisor circuits are not short-circuit protected. Shorting VOUT to ground excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both VCC and VBAT pins to ground by placing 0.1 µF capacitors as close to
the device as possible.
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Operation
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806)
V CC
V RST
V SW (2.4 V )
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
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Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
2.10
Operation
Using a SuperCap™ as a backup power source
SuperCaps™ are capacitors with extremely high capacitance values (e.g., order of 0.47 F)
for their size. Figure 14 shows how to use a SuperCap as a backup power source. The
SuperCap may be connected through a diode to the VCC supply. Since VBAT can exceed
VCC while VCC is above the reset threshold, there are no special precautions when using
these supervisors with a Super-Cap.
Figure 14. Using a SuperCap™
5V
VCC
VOUT
To external SRAM
STMXXX
VBAT
RST
To µP
GND
AI08805
2.11
Negative-going VCC transients
The STM690/704/795/802/804/805/806 supervisors are relatively immune to negative-going
VCC transients (glitches). Figure 32 was generated using a negative pulse applied to VCC,
starting at VRST + 0.3 V and ending below the reset threshold by the magnitude indicated
(comparator overdrive). The graph indicates the maximum pulse width a negative VCC
transient can have without causing a reset pulse. As the magnitude of the transient
increases (further below the threshold), the maximum allowable pulse width decreases. Any
combination of duration and overdrive which lies under the curve will NOT generate a reset
signal. Typically, a VCC transient that goes 100 mV below the reset threshold and lasts 40 µs
or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible
to the VCC pin provides additional transient immunity.
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Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
3
Typical operating characteristics
Note:
Typical values are at TA = 25 °C.
Figure 15. VCC to VOUT on-resistance vs. temperature
V CC to V OUT
on-resistance (
)
5.0
VCC = 3.0 V
4.0
VCC = 4.5 V
VCC = 5.5 V
3.0
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI10498
Figure 16. VBAT to VOUT on-resistance vs. temperature
V BAT to V OUT on-resistance ( )
160
140
120
100
80
60
40
VBAT = 2.0 V
VBAT = 3.0 V
20
VBAT = 3.3 V
VBAT = 3.6 V
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09140b
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STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 17. Supply current vs. temperature (no load)
30
25
Supply current ( µ A)
20
15
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
10
5
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
Figure 18. Battery current vs. temperature
Battery supply current (nA)
1000
100
VBAT = 2.0 V
VBAT = 3.0 V
VBAT = 3.6 V
10
1
0.1
–40
–20
0
20
40
60
80
100
120
Tempe r ature (°C)
AI10499
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Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 19. VPFI threshold vs. temperature
1.270
1.265
V PFI threshold (V)
1.260
1.255
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
1.250
1.245
1.240
1.235
1.230
1.225
–40
–20
0
20
40
Temperature (°C)
60
80
100
120
AI09142b
Figure 20. Reset comparator propagation delay vs. temperature
30
28
Propagation delay (µs)
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
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STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 21. Power-up trec vs. temperature
240
235
t rec (ms)
230
VCC = 3.0 V
225
VCC = 4.5 V
VCC = 5.5 V
220
215
210
–40
–20
0
20
40
60
Temperature (°C)
80
100
120
AI09144b
Figure 22. Normalized reset threshold vs. temperature
Normalized reset threshold
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
Temperature (°C)
Doc ID 10519 Rev 9
80
100
120
AI09145b
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Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 23. Watchdog time-out period vs. temperature
1.90
Watchdog time-out period (s)
1.85
1.80
1.75
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
1.70
1.65
1.60
–40
–20
0
20
40
60
80
100
120
Tempe rature (°C)
AI09146b
Figure 24. E to ECON on-resistance vs. temperature
60
E to E CON on-resistance ( )
50
40
30
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
20
10
0
–40
–20
0
20
40
60
Temper ature (°C)
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Doc ID 10519 Rev 9
80
100
120
AI09147b
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 25. PFI to PFO propagation delay vs. temperature
4.0
PFI to PFO propagation delay (µs)
VCC = 3.0 V
VCC = 3.6 V
3.0
VCC = 4.5 V
VCC = 5.5 V
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
Figure 26. Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C)
5.00
V OUT (V)
4.98
4.96
4.94
0
10
20
30
I OUT (mA)
Doc ID 10519 Rev 9
40
50
AI10496
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Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 27. Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C)
2.80
2.78
V OUT (V)
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
0.6
0.8
1.0
I OUT (mA)
AI10497
Figure 28. RST output voltage vs. supply voltage
V RST (V)
VRST
VCC
4
4
3
3
2
2
1
1
0
0
500 ms / div
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Doc ID 10519 Rev 9
V CC (V)
5
5
AI09149b
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 29. RST output voltage vs. supply voltage
5
5
V RST
VCC
4
3
3
2
2
1
1
0
0
500 ms / div
V CC (V)
V RST (V)
4
AI09150b
Figure 30. Power-fail comparator response time (assertion)
5V
1 V / div
PFO
0V
1.3 V
PFI
500 mV / div
0V
500 ns / div
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AI09153b
27/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 31. Power-fail comparator response time (de-assertion)
5V
1 V / div
PFO
0V
1.3 V
PFI
500 mV / div
0V
500 ns / div
AI09154b
Figure 32. Maximum transient duration vs. reset threshold overdrive
6000
Transient duration (µs)
5000
4000
Reset occurs
above the curve
3000
2000
1000
0
0.001
0.01
0.1
Reset comparator overdrive, V RST – V CC (V)
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1
10
AI09156b
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 33. E to ECON propagation delay vs. temperature
E to ECON propagation delay (ns)
4.0
3.0
2.0
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09157b
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Maximum ratings
4
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
TSTG
TSLD(1)
VIO
Parameter
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Input or output voltage
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC +0.3
V
VCC/VBAT
Supply voltage
–0.3 to 6.0
V
IO
Output current
20
mA
PD
Power dissipation
320
mW
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
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STM690, STM704, STM795, STM802, STM804, STM805, STM806
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived tests performed under the measurement conditions summarized in
Table 6. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 6.
Operating and AC measurement conditions
STM690/704/795/
802/804/805/806
Unit
VCC/VBAT supply voltage
1.0 to 5.5
V
Ambient operating temperature (TA)
–40 to 85
°C
≤ 55
ns
Input pulse voltages
0.2 to 0.8 VCC
V
Input and output timing ref. voltages
0.3 to 0.7 VCC
V
Parameter
Input rise and fall times
Figure 34. E to ECON propagation delay test circuit
VCC
VCC
VBAT
3.6 V
25 equivalent
source impedance
STM690/704/
795/802/804/
805/806
ECON
E
50
50 cable
50 pF C L(1)
50
GND
AI08854
1. CL includes load capacitance and scope probe capacitance.
Figure 35. AC testing input/output waveforms
0.8 V CC
0.7 V CC
0.3 V CC
0.2 V CC
AI02568
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DC and AC parameters
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 36. MR timing waveform
MR
RST
(1)
tMLRL
trec
tMLMH
AI07837a
1. RST for STM805.
Figure 37. Watchdog timing
VCC
RST
trec
tWD
WDI
AI07891
Table 7.
Sym
VCC,
VBAT(2)
DC and AC characteristics
Alternative
Description
Operating voltage
VOUT2
TA = –40 to +85 °C
1.1(3)
Max
Unit
5.5
V
60
µA
Excluding IOUT (VCC < 3.6 V)
35
50
µA
VCC supply current in battery
backup mode
Excluding IOUT (VBAT = 2.3 V,
VCC = 2.0 V, MR = VCC)
25
35
µA
VBAT supply current in battery
backup mode
Excluding IOUT (VBAT = 3.6 V)
0.4
1.0
µA
VOUT voltage (active)
IOUT1 = 5 mA(5)
VCC –
0.03
VCC –
0.015
V
IOUT1 = 75 mA
VCC –
0.3
VCC –
0.15
V
IOUT1 = 250 µA, VCC > 2.5 V(5)
VCC – VCC –
0.0015 0.0006
V
IOUT2 = 250 µA, VBAT = 2.3 V
VBAT – VBAT –
0.1
0.034
V
VBAT –
0.14
V
VOUT voltage (battery backup)
IOUT2 = 1 mA, VBAT = 2.3 V
VCC to VOUT on-resistance
32/42
Typ
40
ICC
VOUT1
Min
Excluding IOUT (VCC < 5.5 V)
VCC supply current
IBAT(4)
Test condition(1)
3
Doc ID 10519 Rev 9
4
Ω
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 7.
Sym
DC and AC parameters
DC and AC characteristics (continued)
Alternative
Test condition(1)
Description
Min
VBAT to VOUT on-resistance
ILI
Typ
Max
Unit
Ω
100
Input leakage current (MR)
STM704/806 only;
MR = 0 V, VCC = 3 V
20
75
350
µA
Input leakage current (PFI)
0 V < VIN < VCC
–20
2
+25
nA
Input leakage current (WDI)
0 V < VIN < VCC
–1
+1
µA
STM804/805/795;
0 V < VIN < VCC(6)
–1
+1
µA
0.7 VCC
ILO
Output leakage current
VIH
Input high voltage (MR, WDI)
VRST (max) < VCC < 5.5 V
VIL
Input low voltage (MR, WDI)
VRST (max) < VCC < 5.5 V
0.3 VCC
V
Output low voltage (PFO,
RST, RST, Vccsw)
VCC = VRST (max),
ISINK = 3.2 mA
0.3
V
Output low voltage (ECON)
VCC = VRST (max),
IOUT = 1.6 mA, E = 0 V
0.2 VCC
V
IOL = 40 µA,
VCC = 1.0 V, VBAT = VCC,
TA = 0 °C to 85 °C
0.3
V
IOL = 200 µA,
VCC = 1.2 V, VBAT = VCC
0.3
V
VOL
VOL
Output low voltage (RST)
Output high voltage (RST,
RST)(7)
VOH
V
ISOURCE = 1 mA,
VCC = VRST (max)
2.4
V
Output high voltage (ECON)
VCC = VRST (max),
IOUT = 1.6 mA, E = VCC
0.8 VCC
V
Output high voltage (PFO)
ISOURCE = 75 µA,
VCC = VRST (max)
0.8 VCC
V
VOH battery backup (Vccsw,
RST)
ISOURCE = 100 µA,
VCC = 0 V, VBAT = 2.8 V
0.8 VBAT
V
VOH battery backup (ECON)
ISOURCE = 75 µA,
VCC = 0 V, VBAT = 2.8 V
0.8 VBAT
V
VOHB
Power-fail comparator (NOT available on STM795)
VPFI
PFI falling
(VCC < 3.6 V)
PFI input threshold
PFI hysteresis
tPFD
STM802/
804/806
1.212
1.237
1.262
V
STM690/
704/805
1.187
1.237
1.287
V
10
20
mV
PFI rising (VCC < 3.6 V)
PFI to PFO propagation delay
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2
µs
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DC and AC parameters
Table 7.
Sym
STM690, STM704, STM795, STM802, STM804, STM805, STM806
DC and AC characteristics (continued)
Alternative
PFO output short to GND
current
ISC
Test condition(1)
Min
Typ
Max
Unit
VCC = 3.6 V, PFO = 0 V
0.1
0.75
2.0
mA
Description
Battery switchover
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VSW
2.4
V
Hysteresis
40
mV
Power-down
Battery backup switchover
voltage(8)(9)
VSO
Power-up
Reset thresholds
VCC falling
STM690T/
704T/795T/ 805T V rising
CC
3.00
3.075
3.15
V
3.00
3.085
3.17
V
VCC falling
3.00
3.075
3.12
V
VCC rising
3.00
3.085
3.14
V
VCC falling
STM690S/
704S/795S/ 805S V rising
CC
2.85
2.925
3.00
V
2.85
2.935
3.02
V
VCC falling
2.88
2.925
3.00
V
VCC rising
2.88
2.935
3.02
V
VCC falling
STM690R/
704R/795R/ 805R V rising
CC
2.55
2.625
2.70
V
2.55
2.635
2.72
V
VCC falling
2.59
2.625
2.70
V
VCC rising
2.59
2.635
2.72
V
140
200
280
ms
100
20
STM802T/
804T/806T
VRST(10)
Reset threshold
STM802S/
804S/806S
STM802R/
804R/806R
RST pulse width
trec
VCC < 3.6 V
Push-button reset input (STM704/806)
tMLMH
tMR
MR pulse width
tMLRL
tMRD MR to RST output delay
ns
60
500
ns
2.24
s
Watchdog timer (NOT available on STM704/795/806)
tWD
Watchdog timeout period
VRST (max) < VCC < 3.6 V
1.12
1.60
WDI pulse width
VRST (max) < VCC < 3.6 V
100
20
ns
46
Ω
Chip enable gating (STM795 only)
E to ECON resistance
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VCC = VRST (max)
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 7.
Sym
DC and AC parameters
DC and AC characteristics (continued)
Alternative
Description
E to ECON propagation delay
Test condition(1)
Min
VCC = VRST (max)
Reset to ECON high delay
ISC
ECON short circuit current
Typ
Max
Unit
2
7
ns
10
VCC = 3.6 V, disable mode,
ECON = 0 V
0.1
0.75
µs
2.0
mA
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max) to 5.5 V; and VBAT = 2.8 V (except where
noted).
2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality,
state of RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC
(min). Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.
3. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not
asserted (output high impedance).
7. Not valid for STM795/804/805 (open drain).
8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.
9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) - 75 mV.
10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
internal oscillation.
Doc ID 10519 Rev 9
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Package mechanical data
6
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
36/42
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Package mechanical data
Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical drawing
A2
A
C
B
ddd
e
D
8
E
H
1
A1
L
SO-A
Table 8.
SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
—
1.35
1.75
—
0.053
0.069
A1
—
0.10
0.25
—
0.004
0.010
B
—
0.33
0.51
—
0.013
0.020
C
—
0.19
0.25
—
0.007
0.010
D
—
4.80
5.00
—
0.189
0.197
ddd
—
—
0.10
—
—
0.004
E
—
3.80
4.00
—
0.150
0.157
e
1.27
—
—
0.050
—
—
H
—
5.80
6.20
—
0.228
0.244
h
—
0.25
0.50
—
0.010
0.020
L
—
0.40
0.90
—
0.016
0.035
α
—
0°
8°
—
0°
8°
N
8
Doc ID 10519 Rev 9
8
37/42
Package mechanical data
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
5
c
E1
1
E
4
L
A1
A
A2
L1
CP
b
Table 9.
e
TSSOP8BM
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
inches
Symb
38/42
Typ
Min
Max
Typ
Min
Max
A
—
—
1.10
—
—
0.043
A1
—
0.05
0.15
—
0.002
0.006
A2
0.85
0.75
0.95
0.034
0.030
0.037
b
—
0.25
0.40
—
0.010
0.016
c
—
0.13
0.23
—
0.005
0.009
CP
—
—
0.10
—
—
0.004
D
3.00
2.90
3.10
0.118
0.114
0.122
e
0.65
—
—
0.026
—
—
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.90
3.10
0.118
0.114
0.122
L
0.55
0.40
0.70
0.022
0.016
0.030
L1
0.95
—
—
0.037
—
—
α
—
0°
6°
—
0°
6°
N
8
8
Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806
7
Part numbering
Part numbering
Table 10.
Ordering information scheme
Example:
STM690
T
M
6
E
Device type
STM690/704/795/802/804/805/806
Reset threshold voltage
T = STM690/704/795/805 = VRST = 3.00 V to 3.15 V
STM802/804/806 = VRST = 3.00 V to 3.12 V
S = STM690/704/795/805 = VRST = 2.85 V to 3.00 V
STM802/804/806 = VRST = 2.88 V to 3.00 V
R = STM690/704/795/805 = VRST = 2.55 V to 2.70 V
STM802/804/806 = VRST = 2.59 V to 2.70 V
Package
M = SO8
DS(1)= TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10519 Rev 9
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Part numbering
STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 11.
40/42
Marking description
Part number
Reset threshold
STM690T
3.075
STM690S
2.925
STM690R
2.625
STM704T
3.075
STM704S
2.925
STM704R
2.625
STM795T
3.075
STM795S
2.925
STM795R
2.625
STM802T
3.075
STM802S
2.925
STM802R
2.625
STM804T
3.075
STM804S
2.925
STM804R
2.625
STM805T
3.075
STM805S
2.925
STM805R
2.625
STM806T
3.075
STM806S
2.925
STM806R
2.625
Doc ID 10519 Rev 9
Package
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
Topside marking
690T
690S
690R
704T
704S
704R
795T
795S
795R
802T
802S
802R
804T
804S
804R
805T
805S
805R
806T
806S
806R
STM690, STM704, STM795, STM802, STM804, STM805, STM806
8
Revision history
Revision history
Table 12.
Document revision history
Date
Revision
Changes
31-Oct-2003
1
Initial release.
22-Dec-2003
2
Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 37;
Table 1, 3, 4, 7, 9, 11).
16-Jan-2004
2.1
Added Typical operating characteristics (Figure 17, 18, 20 to 26, 29,
30 to 34).
07-Apr-2004
2.2
Updated characteristics (Figure 13, 29, 30, Table 1, 3, 7)
25-May-2004
3
Update characteristics (Table 3, 7)
02-Jul-2004
4
Update package availability, pin description; promote document
(Figure 1, 14; Table 3, 10)
29-Sep-2004
5
Clarify root part numbers, pin descriptions, update characteristics
(Figure 2, to, 11, 13, 14, 35; Table 1, 3, 6, 7, 10)
25-Feb-2005
6
Update characteristics (Figure 11, 16, to 35; Table 7)
05-Apr-2006
7
Update characteristics (Figure 13)
20-Nov-2009
8
Updated Section 1.1.6, Section 1.1.8, Figure 10, 11, 19, Table 3, 5, 7;
added text to Section 6.
18-Aug-2010
9
Updated Features, Section 2.4: Backup battery switchover.
Doc ID 10519 Rev 9
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STM690, STM704, STM795, STM802, STM804, STM805, STM806
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