STMICROELECTRONICS STM813LM6F

STM705, STM706
STM707, STM708, STM813L
5 V supervisor
Features
■
5 V operating voltage
■
Precision VCC monitor
– STM705/707/813L
– 4.50 V ≤ VRST ≤ 4.75 V
– STM706/708
– 4.25 ≤ VRST ≤ 4.50 V
8
1
SO8 (M)
■
RST and RST outputs
■
200 ms (typ) trec
■
Watchdog timer - 1.6 s (typ)
■
Manual reset input (MR)
■
Power-fail comparator (PFI/PFO)
■
Low supply current - 40 µA (typ)
■
Guaranteed RST (RST) assertion down to
VCC = 1.0 V
■
Operating temperature: –40 °C to 85 °C
(industrial grade)
■
RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1.
TSSOP8 3x3 (DS)(1)
1. Contact local ST sales office for availability.
Device summary
Watchdog
input
Watchdog
output(1)
Active-low
RST(1)
STM705
✓
✓
STM706
✓
✓
Active-high
RST(1)
Manual reset
input
Power-fail
comparator
✓
✓
✓
✓
✓
✓
STM707
✓
✓
✓
✓
STM708
✓
✓
✓
✓
✓
✓
✓
STM813L
✓
✓
1. Push-pull output
August 2010
Doc ID 10520 Rev 9
1/33
www.st.com
1
Contents
STM705, STM706, STM707, STM708, STM813L
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7
PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
Watchdog input (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Watchdog output (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5
Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6
Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12
3.7
Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 13
4
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO8 - 8-lead plastic small outline, 150 mils body width, pack. mech. data . . . . . . . . . . . . 28
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 10520 Rev 9
3/33
List of figures
STM705, STM706, STM707, STM708, STM813L
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
4/33
Logic diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM705/706/813L SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM705/706/813L TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM707/708 SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM707/708 TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output voltage vs. load current (VCC = 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog timing (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO8 – 8-lead plastic small outline, 150 mils body width, outline . . . . . . . . . . . . . . . . . . . . 28
TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . 29
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
1
Description
Description
The STM705/706/707/708/813L supervisors are self-contained devices which provide
microprocessor supervisory functions. A precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition
occurs, the reset output (RST) is forced low (or high in the case of RST).
These devices also offer a watchdog timer (except for STM707/708) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1.
Logic diagram (STM705/706/813L)
VCC
WDO
WDI
MR
STM705/706;
STM813L
RST(1)
RST(2)
PFI
PFO
VSS
AI08825
1. For STM705/706 only.
2. For STM813L only.
Figure 2.
Logic diagram (STM707/708)
VCC
RST
MR
STM707/708
RST
PFI
PFO
VSS
Doc ID 10520 Rev 9
AI08826
5/33
Description
STM705, STM706, STM707, STM708, STM813L
Table 2.
Signal names
MR
Push-button reset input
WDI
Watchdog input
WDO
Watchdog output
RST
Active-low reset output
RST(1)
Active-high reset output
VCC
Supply voltage
PFI
Power-fail input
PFO
Power-fail output
VSS
Ground
NC
No connect
1. For STM813L only.
Figure 3.
STM705/706/813L SO8 connections
SO8
MR
1
8
WDO
VCC
VSS
2
7
RST (RST)(1)
3
6
WDI
PFI
4
5
PFO
AI08827a
1. For STM813L, reset output is active-high.
Figure 4.
STM705/706/813L TSSOP8 connections
TSSOP8
(RST) RST(1)
1
8
WDI
2
7
PFO
MR
3
6
PFI
VCC
4
5
VSS
WDO
AI09114
1. For STM813L, reset output is active-high.
6/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Figure 5.
Description
STM707/708 SO8 connections
SO8
MR
1
8
RST
VCC
VSS
2
7
RST
3
6
NC
PFI
4
5
PFO
AI08828a
Figure 6.
STM707/708 TSSOP8 connections
TSSOP8
RST
RST
MR
VCC
8
NC
2
7
PFO
3
6
PFI
4
5
VSS
1
AI09115
Doc ID 10520 Rev 9
7/33
Pin descriptions
2
Pin descriptions
2.1
MR
STM705, STM706, STM707, STM708, STM813L
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2
WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset
(or WDO) is triggered. The internal watchdog timer clears while reset is asserted or when
WDI sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
2.3
WDO
It goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also
goes low when VCC falls below the reset threshold; however, unlike the reset output, WDO
goes high as soon as VCC exceeds the reset threshold. Output type is push-pull.
Note:
For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO
is connected to MR.
2.4
RST
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, or MR goes from low to high.
2.5
RST
Goes high with triggered, and stays high whenever VCC is above the reset threshold or
when MR is a logic high. It stays high for trec after either VCC falls below the reset threshold,
or MR goes from high to low.
2.6
PFI
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to
ground if unused.
8/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
2.7
Pin descriptions
PFO
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Leave open if
unused. Output type is push-pull.
Table 3.
Pin description
Pin
Name
Function
STM813L
STM707
STM708
STM705
STM706
1
1
1
MR
Push-button reset input
6
—
6
WDI
Watchdog input
8
—
8
WDO
Watchdog output (push-pull)
—
7
7
RST
Active-low reset output
7
8
—
RST
Active-high reset output
2
2
2
VCC
Supply voltage
4
4
4
PFI
Power-fail input
5
5
5
PFO
Power-fail output (push-pull)
3
3
3
VSS
Ground
—
6
—
NC
No connect
Figure 7.
Block diagram (STM705/706/813L)
WDI
transitional
detector
WDI
VCC
WATCHDOG
TIMER
VRST
WDO
COMPARE
VCC
trec
generator
MR
RST (RST)(1)
PFI
VPFI
COMPARE
PFO
AI08829
1. For STM813L only.
Doc ID 10520 Rev 9
9/33
Pin descriptions
Figure 8.
STM705, STM706, STM707, STM708, STM813L
Block diagram (STM707/708)
VCC
COMPARE
VRST
RST
VCC
trec
generator
MR
PFI
COMPARE
VPFI
RST
PFO
AI08830
Figure 9.
Hardware hookup
5V
Regulator
Unregulated
voltage
VIN
VCC
VCC
0.1 mF
STM705
STM706
STM707
STM708
STM813L
WDI(1)
R1
WDO(1)
To microprocessor IRQ
PFI
PFO
To microprocessor NMI
MR
RST
To microprocessor reset
From microprocessor
R2
Push-button
AI08831a
1. For STM705/706/813L.
10/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
3
Operation
3.1
Reset output
Operation
The STM705/706/707/708/813L supervisor asserts a reset signal to the MCU whenever
VCC goes below the reset threshold (VRST), a watchdog time-out occurs (if WDO is tied to
MR), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic
low (logic high for STM707/708/813L) for VCC < VRST down to VCC =1 V for TA = 0 °C to
85 °C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
3.2
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 29) after it returns high. The MR input has an internal 40 Ω pull-up resistor, allowing it
to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
3.3
Watchdog input (STM705/706/813L)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within tWD (1.6 s), the reset is asserted. The internal 1.6s
timer is cleared by either:
1.
a reset pulse, or
2.
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (tWD + trec), if WDO is
connected to MR.
See Figure 30 for STM705/706/813L.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note:
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
Doc ID 10520 Rev 9
11/33
Operation
3.4
STM705, STM706, STM707, STM708, STM813L
Watchdog output (STM705/706/813L)
When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
3.5
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below
VPFI several milliseconds before the regulated VCC input to the STM705/706/707/708/ 813L
or the microprocessor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to VSS and PFO left unconnected.
PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will
generate a reset output.
3.6
Ensuring a valid reset output down to VCC = 0 V
When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
STMXXX
RST
R1
AI08835
12/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
3.7
Operation
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM705-708 reset
output. For example, if the reset output is driven high and the micro wants to pull it low,
signal contention will result. To prevent this from occurring, connect a 4.7 kΩ resistor
between the reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bidirectional reset I/O
Buffered reset to other
system components
VCC
VCC
STMXXX
Microprocessor
4.7 k
RST
GND
RST
GND
AI08836
Doc ID 10520 Rev 9
13/33
Typical operating characteristics
4
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Typical values are at TA = 25 °C.
Figure 12. Supply current vs. temperature (no load)
30
25
Supply current (µA)
20
15
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
10
5
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
Figure 13. VPFI threshold vs. temperature
1.270
1.265
V PFI threshold (V)
1.260
1.255
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
1.250
1.245
1.240
1.235
1.230
1.225
–40
14/33
–20
0
20
40
Temperature (°C)
Doc ID 10520 Rev 9
60
80
100
120
AI09142b
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 14. Reset comparator propagation delay vs. temperature
30
28
Propagation delay (µs)
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
Figure 15. Power-up trec vs. temperature
240
235
t rec (ms)
230
VCC = 3.0 V
225
VCC = 4.5 V
VCC = 5.5 V
220
215
210
–40
–20
0
20
40
60
Temperature (°C)
Doc ID 10520 Rev 9
80
100
120
AI09144b
15/33
Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 16. Normalized reset threshold vs. temperature
Normalized reset threshold
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
Figure 17. Watchdog time-out period vs. temperature
1.90
Watchdog time-out pe riod (s)
1.85
1.80
1.75
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
1.70
1.65
1.60
–40
–20
0
20
40
60
80
100
120
Tempe rature (°C)
AI09146b
16/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 18. PFI to PFO propagation delay vs. temperature
4.0
PFI to PFO propagation delay (µs)
VCC = 3.0 V
VCC = 3.6 V
3.0
VCC = 4.5 V
VCC = 5.5 V
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C)
5.00
V OUT (V)
4.98
4.96
4.94
0
10
20
30
I OUT (mA)
Doc ID 10520 Rev 9
40
50
AI10496
17/33
Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 20. RST output voltage vs. supply voltage
V RST (V)
VRST
VCC
4
4
3
3
2
2
1
1
0
0
500 ms / div
V CC (V)
5
5
AI09149b
Figure 21. RST output voltage vs. supply voltage
5
V RST
VCC
V RST (V)
4
3
3
2
2
1
1
0
0
500 ms / div
18/33
4
Doc ID 10520 Rev 9
V CC (V)
5
AI09150b
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 22. RST response time (assertion)
5V
1 V / div
VCC
4V
5V
4V
RST
1V/div
0V
5 µs / div
AI09151b
1. VRST = 4.603 V at 25 °C.
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Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 23. RST response time (assertion)
5V
VCC
4V
1 V / div
4V
RST
1 V / div
0V
5 µs / div
AI09152b
1. VRST = 4.603 V at 25 °C.
Figure 24. Power-fail comparator response time (assertion)
5V
1 V / div
PFO
0V
1.3 V
PFI
500 mV / div
0V
500 ns / div
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Doc ID 10520 Rev 9
AI09153b
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 25. Power-fail comparator response time (de-assertion)
5V
1 V / div
PFO
0V
1.3 V
PFI
500 mV / div
0V
AI09154b
500 ns / div
Figure 26. Maximum transient duration vs. reset threshold overdrive
6000
Transient duration (µs)
5000
4000
Reset occurs
above the curve
3000
2000
1000
0
0.001
0.01
0.1
Reset comparator overdrive, V RST – V CC (V)
Doc ID 10520 Rev 9
1
10
AI09156b
21/33
Maximum ratings
5
STM705, STM706, STM707, STM708, STM813L
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4.
Absolute maximum ratings
Symbol
TSTG
TSLD(1)
1.
22/33
Parameter
Storage temperature (VCC Off)
Lead solder temperature for 10 seconds
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC +0.3
V
VIO
Input or output voltage
VCC
Supply voltage
–0.3 to 7.0
V
IO
Output current
20
mA
PD
Power dissipation
320
mW
Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM705/706/707/708; STM813L
Unit
VCC supply voltage
1.0 to 5.5
V
Ambient operating temperature (TA)
–40 to 85
°C
≤5
ns
Input pulse voltages
0.2 to 0.8 VCC
V
Input and output timing ref. voltages
0.3 to 0.7 VCC
V
Input rise and fall times
Figure 27. AC testing input/output waveforms
0.8 V CC
0.7 V CC
0.3 V CC
0.2 V CC
AI02568
Figure 28. Power-fail comparator waveform
VCC
VRST
trec
PFO
RST
AI08834b
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DC and AC parameters
STM705, STM706, STM707, STM708, STM813L
Figure 29. MR timing waveform
MR
RST
(1)
tMLRL
trec
tMLMH
AI07837a
1. RST for STM805.
Figure 30. Watchdog timing (STM705/706/813L)
VCC
RST
trec
tWD
WDI
WDO
AI08833
24/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Table 6.
Sym
DC and AC characteristics
Description
VCC
Operating voltage
ICC
VCC supply current
ILI
DC and AC parameters
Test condition(1)
Min
1.2
Typ
Max
Unit
5.5
V
25
60
µA
(2)
Input leakage current (MR)
4.5 V < VCC < 5.5 V
75
125
300
µA
Input leakage current (PFI)
0 V < VIN < VCC
–25
2
+25
nA
120
160
µA
Input leakage current (WDI)
WDI = VCC, time average
WDI = GND, time average
–20
VIH
Input high voltage (MR)
4.5 V < VCC < 5.5 V
2.0
V
VIH
Input high voltage (WDI)
VRST (max) < VCC < 5.5 V
0.7 VCC
V
VIL
Input low voltage (MR)
4.5 V < VCC < 5.5 V
0.8
V
VIL
Input low voltage (WDI)
VRST (max) < VCC < 5.5 V
0.3 VCC
V
VOL
Output low voltage (PFO, RST,
RST, WDO)
VCC = VRST (max), ISINK = 3.2 mA
0.3
V
VOL
Output low voltage (RST)
ISINK = 50 µA, VCC = 1.0 V,
TA = 0 °C to 85 °C
0.3
V
ISINK = 100 µA, VCC = 1.2 V
0.3
V
VOH
VOH
–15
µA
Output high voltage (RST, RST,
WDO)
ISOURCE = 1 mA,
VCC = VRST (max)
2.4
V
Output high voltage (PFO)
ISOURCE = 75 µA,
VCC = VRST (max)
0.8 VCC
V
Output high voltage (RST)
ISOURCE = 4 µA, VCC = 1.1 V,
TA = 0 °C to 85 °C
0.8
V
ISOURCE = 4 µA, VCC = 1.2 V
0.9
V
1.30
V
Power-fail comparator
VPFI
PFI input threshold
tPFD
PFI to PFO propagation delay
PFI falling (VCC = 5 V)
1.20
1.25
2
Doc ID 10520 Rev 9
µs
25/33
DC and AC parameters
Table 6.
STM705, STM706, STM707, STM708, STM813L
DC and AC characteristics
Sym
Description
Test condition(1)
Min
Typ
Max
Unit
STM705/707/813L
4.50
4.65
4.75
V
STM706/708
4.25
4.40
4.50
V
Reset thresholds
VRST
Reset threshold(3)
Reset threshold hysteresis
trec
RST pulse width
25
mV
Blank (see Table 9)
140
200
280
A (see Table 9)
160
200
280
ms
Push-button reset input
tMLMH
MR pulse width
(or tMR)
150
ns
tMLRL
MR to RST output delay
(tMRD)
250
ns
2.24
s
Watchdog timer (STM705/706/813L)
tWD
Watchdog timeout period
4.5 V < VCC < 5.5 V
1.12
WDI pulse width
4.5 V < VCC < 5.5 V
50
1.60
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for STM705/707/813L;
VCC = 4.5 V to 5.5 V for STM706/708 (except where noted).
2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
3. For VCC falling.
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Doc ID 10520 Rev 9
ns
STM705, STM706, STM707, STM708, STM813L
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 10520 Rev 9
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Package mechanical data
STM705, STM706, STM707, STM708, STM813L
Figure 31. SO8 – 8-lead plastic small outline, 150 mils body width, outline
A2
A
C
B
ddd
e
D
8
E
H
1
A1
L
SO-A
1. Drawing is not to scale.
Table 7.
SO8 - 8-lead plastic small outline, 150 mils body width, pack. mech. data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
—
1.35
1.75
—
0.053
0.069
A1
—
0.10
0.25
—
0.004
0.010
B
—
0.33
0.51
—
0.013
0.020
C
—
0.19
0.25
—
0.007
0.010
D
—
4.80
5.00
—
0.189
0.197
ddd
—
—
0.10
—
—
0.004
E
—
3.80
4.00
—
0.150
0.157
e
1.27
—
—
0.050
—
—
H
—
5.80
6.20
—
0.228
0.244
h
—
0.25
0.50
—
0.010
0.020
L
—
0.40
0.90
—
0.016
0.035
α
—
0°
8°
—
0°
8°
N
28/33
8
Doc ID 10520 Rev 9
8
STM705, STM706, STM707, STM708, STM813L
Package mechanical data
Figure 32. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
5
c
E1
1
E
4
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
1. Drawing is not to scale.
Table 8.
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
—
—
1.10
—
—
0.043
A1
—
0.05
0.15
—
0.002
0.006
A2
0.85
0.75
0.95
0.034
0.030
0.037
b
—
0.25
0.40
—
0.010
0.016
c
—
0.13
0.23
—
0.005
0.009
CP
—
—
0.10
—
—
0.004
D
3.00
2.90
3.10
0.118
0.114
0.122
e
0.65
—
—
0.026
—
—
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.90
3.10
0.118
0.114
0.122
L
0.55
0.40
0.70
0.022
0.016
0.030
L1
0.95
—
—
0.037
—
—
α
—
0°
6°
—
0°
6°
N
8
8
Doc ID 10520 Rev 9
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Part numbering
8
STM705, STM706, STM707, STM708, STM813L
Part numbering
Table 9.
Ordering information scheme
Example:
STM705
M
6
E
Device type and reset threshold voltage
STM705/707/813L = VRST = 4.50 V to 4.75 V
STM706/708 = VRST = 4.25 V to 4.50 V
RST pulse width
Blank = 140 to 280 ms
A(1) = 160 to 280 ms
Package
M = SO8
DS(2) = TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
1. Available for STM706/708 in SO8 (M) package only.
2. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 10.
30/33
Marking description
Part number
Reset threshold
STM705
4.63 V
STM706
4.38 V
STM707
4.63 V
STM708
4.38 V
STM813L
4.63 V
Doc ID 10520 Rev 9
Package
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
Topside marking
705
706
707
708
813L
STM705, STM706, STM707, STM708, STM813L
9
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
Sep-2003
1
31-Oct-2003
1.1
12-Dec-2003
2
16-Jan-2004
2.1
09-Apr-2004
3
Reformatted; update characteristics (Figure 14, 18, 20 to 23, 26;
Table 7)
25-May-2004
4
Update characteristics (Table 4, 7)
02-Jul-2004
5
Document promoted; corrected waveform (Figure 28)
21-Sep-2004
6
Clarify root part numbers, pin descriptions (Figure 2, 3, 10; Table 6, 7,
10)
08-Mar-2005
7
Update typical characteristics (Figure 12 to 26)
02-Nov-2009
8
Updated Table 1, 3, 4, 6, 9, Section 2.3, Section 2.7, text in Section 7.
06-Aug-2010
9
Updated Features, Section 4: Typical operating characteristics,Table 9.
Initial release.
Update Table 6.
Reformatted; update characteristics (Figure 1, 2, 3, 4, 6, 8, 9, 10, 28;
29, 30, Table 7, 9, 11)
Add typical characteristics (Figure 12 to 18, 20 to 26)
Doc ID 10520 Rev 9
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STM705, STM706, STM707, STM708, STM813L
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