STMICROELECTRONICS STM813L

STM705, STM706,
STM707, STM708, STM813L
5V Supervisor
FEATURES SUMMARY
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■
■
■
■
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5V OPERATING VOLTAGE
PRECISION VCC MONITOR
– STM705/707/813L
4.50V ≤ VRST ≤ 4.75V
– STM706/708
4.25 ≤ VRST ≤ 4.50V
RST AND RST OUTPUTS
200ms (TYP) trec
WATCHDOG TIMER - 1.6sec (TYP)
MANUAL RESET INPUT (MR)
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)
Table 1. Device Options
Watchdog
Input
Watchdog
Output
Active-Low
RST(1)
STM705
✔
✔
STM706
✔
✔
Active-High
RST(1)
Manual
Reset Input
Power-fail
Comparator
✔
✔
✔
✔
✔
✔
STM707
✔
✔
✔
✔
STM708
✔
✔
✔
✔
✔
✔
✔
STM813L
✔
✔
Note: 1. Push-pull Output
March 2005
1/27
STM705/706/707/708/813L
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM705/706/813L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. STM705/706/813L SO8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. STM705/706/813L TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM707/708 SO8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM707/708 TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Output (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ensuring a Valid Reset Output Down to VCC = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O . . . . . . . . . . . . . . . . . . . . . . 10
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 14
Figure 21.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 15
Figure 22.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STM705/706/707/708/813L
Figure 26.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 18
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 30.Power-fail Comparator Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 31.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 32.Watchdog Timing (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 33.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . . 23
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 23
Figure 34.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 24
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
STM705/706/707/708/813L
SUMMARY DESCRIPTION
The STM705/706/707/708/813L Supervisors are
self-contained devices which provide microprocessor supervisory functions. A precision voltage
reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid
VCC condition occurs, the reset output (RST) is
forced low (or high in the case of RST).
These devices also offer a watchdog timer (except
for STM707/708) as well as a power-fail comparator to provide the system with an early warning of
impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM705/706/813L)
Figure 3. Logic Diagram (STM707/708)
VCC
VCC
WDO
WDI
MR
STM705/706;
STM813L
PFI
RST
RST(1)
MR
RST(2)
PFI
PFO
PFO
VSS
Note: 1. For STM705/706 only.
2. For STM813L only.
VSS
AI08825
AI08826
Table 2. Signal Names
MR
Push-button Reset Input
WDI
Watchdog Input
WDO
Watchdog Output
RST
Active-Low Reset Output
RST(1)
Active-High Reset Output
VCC
Supply Voltage
PFI
Power-fail Input
PFO
Power-fail Output
VSS
Ground
NC
No Connect
Note: 1. For STM813L only.
4/27
RST
STM707/708
STM705/706/707/708/813L
Figure 4. STM705/706/813L SO8 Connections
Figure 6. STM707/708 SO8 Connections
SO8
MR
VCC
VSS
PFI
1
2
3
4
SO8
8
7
6
5
WDO
RST(RST)(1)
WDI
PFO
MR
VCC
VSS
PFI
1
2
3
4
8
7
6
5
AI08827a
RST
RST
NC
PFO
AI08828a
Note: 1. For STM813L, reset output is active-high.
Figure 5. STM705/706/813L TSSOP8
Connections
Figure 7. STM707/708 TSSOP8 Connections
TSSOP8
TSSOP8
(RST)RST(1)
WDO
MR
VCC
1
2
3
4
8
7
6
5
WDI
PFO
PFI
VSS
AI09114
RST
RST
MR
VCC
1
2
3
4
8
7
6
5
NC
PFO
PFI
VSS
AI09115
Note: 1. For STM813L, reset output is active-high.
5/27
STM705/706/707/708/813L
Pin Descriptions
MR. A logic low on MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset (or WDO)
is triggered. The internal watchdog timer clears
while reset is asserted or when WDI sees a rising
or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
WDO. It goes low when a transition does not occur on WDI within 1.6sec, and remains low until a
transition occurs on WDI (indicating the watchdog
interrupt has been serviced). WDO also goes low
when VCC falls below the reset threshold; however, unlike the reset output, WDO goes high as
soon as VCC exceeds the reset threshold.
Note: For those devices with a WDO output, a
watchdog timeout will not trigger reset unless
WDO is connected to MR.
RST. Pulses low when triggered, and stays low
whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, or MR
goes from low to high.
RST. Goes high with triggered, and stays high
whenever VCC is above the reset threshold or
when MR is a logic high. It stays high for trec after
either VCC falls below the reset threshold, or MR
goes from high to low.
PFI. When PFI is less than VPFI, PFO goes low;
otherwise, PFO remains high. Connect to ground
if unused.
PFO. When PFI is less than VPFI, PFO goes low;
otherwise, PFO remains high. Leave open if unused.
Table 3. Pin Description
Pin
Name
Function
STM813L
STM707
STM708
STM705
STM706
1
1
1
MR
Push-button Reset Input
6
–
6
WDI
Watchdog Input
8
–
8
WDO
Watchdog Output
–
7
7
RST
Active-Low Reset Output
7
8
–
RST
Active-High Reset Output
2
2
2
VCC
Supply Voltage
4
4
4
PFI
PFI Power-fail Input
5
5
5
PFO
PFO Power-fail Output
3
3
3
VSS
Ground
–
6
–
NC
No Connect
6/27
STM705/706/707/708/813L
Figure 8. Block Diagram (STM705/706/813L)
WDI
Transitional
Detector
WDI
VCC
WATCHDOG
TIMER
VRST
WDO
COMPARE
VCC
trec
Generator
MR
RST(RST)(1)
PFI
VPFI
COMPARE
PFO
AI08829
Note: 1. For STM813L only.
Figure 9. Block Diagram (STM707/708)
VCC
VRST
COMPARE
RST
VCC
trec
Generator
MR
PFI
VPFI
COMPARE
RST
PFO
AI08830
7/27
STM705/706/707/708/813L
Figure 10. Hardware Hookup
Regulator
Unregulated
Voltage
VIN
VCC
VCC
0.1µF
STM705/706/
707/708;
STM813L
(1)
WDO(1)
To Microprocessor IRQ
PFI
PFO
To Microprocessor NMI
MR
RST
To Microprocessor Reset
WDI
R1
From Microprocessor
R2
Push-button
AI08831
Note: 1. For STM705/706/813L.
8/27
STM705/706/707/708/813L
OPERATION
Reset Output
The STM705/706/707/708/813L Supervisor asserts a reset signal to the MCU whenever VCC
goes below the reset threshold (VRST), a watchdog time-out occurs (if WDO is tied to MR), or
when the Push-button Reset Input (MR) is taken
low. RST is guaranteed to be a logic low (logic
high for STM707/708/813L) for VCC < VRST down
to VCC =1V for TA = 0°C to 85°C.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
31., page 21) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (STM705/706/813L)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec), the reset is asserted. The internal 1.6sec timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (tWD + trec), if WDO is
connected to MR.
See Figure 32., page 21 for STM705/706/813L.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting.
Note: The watchdog function may be disabled by
floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Watchdog Output (STM705/706/813L)
When VCC drops below the reset threshold, WDO
will go low even if the watchdog timer has not yet
timed out. However, unlike the reset output, WDO
goes high as soon as VCC exceeds the reset
threshold. WDO may be used to generate a reset
pulse by connecting it to the MR input.
Power-fail Input/Output
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the VRST
comparator). If PFI is less than the power-fail
threshold (VPFI), the Power-Fail Output (PFO) will
go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external
voltage divider (see Figure 10., page 8) to either
the unregulated DC input (if it is available) or the
regulated output of the VCC regulator. The voltage
divider can be set up such that the voltage at PFI
falls below VPFI several milliseconds before the
regulated VCC input to the STM705/706/707/708/
813L or the microprocessor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO
may be connected to MR on the STM703/704/818
so that a low voltage on PFI will generate a reset
output.
9/27
STM705/706/707/708/813L
Ensuring a Valid Reset Output Down to
VCC = 0V
When VCC falls below 1V, the state of the RST output can no longer be guaranteed, and becomes
essentially an open circuit. If a high value pulldown resistor is added to the RST pin, the output
will be held low during this condition. A resistor value of approximately 100kΩ will be large enough to
not load the output under operating conditions, but
still sufficient to pull RST to ground during this low
voltage condition (see Figure 11).
Figure 11. Reset Output Valid to Ground
Circuit
Interfacing to Microprocessors with Bidirectional Reset Pins
Microprocessors with bi-directional reset pins can
contend with the STM705-708 reset output. For
example, if the reset output is driven high and the
micro wants to pull it low, signal contention will result. To prevent this from occurring, connect a
4.7kΩ resistor between the reset output and the
micro’s reset I/O as in Figure 12.
Figure 12. Interfacing to Microprocessors with
Bi-directional Reset I/O
Buffered Reset to other
System Components
STMXXX
RST
R1
VCC
VCC
STMXXX
Microprocessor
4.7k
RST
AI08835
GND
RST
GND
AI08836
10/27
STM705/706/707/708/813L
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C.
Figure 13. Supply Current vs. Temperature (no load)
30
Supply Current (µA)
25
20
15
VCC = 2.7V
VCC = 3.0V
VCC = 3.6V
VCC = 4.5V
VCC = 5.5V
10
5
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI09141b
Figure 14. VPFI Threshold vs. Temperature
1.270
1.265
VCC = 3.0V
VCC = 4.5V
VCC = 4.75V
VCC = 5.5V
VPFI Threshold (V)
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
–40
–20
0
20
40
Temperature (°C)
60
80
100
120
AI09142b
11/27
STM705/706/707/708/813L
Figure 15. Reset Comparator Propagation Delay vs. Temperature
30
28
Propagation Delay (µs)
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI09143b
Figure 16. Power-up trec vs. Temperature
240
235
trec (ms)
230
VCC = 3.0V
225
VCC = 4.5V
VCC = 5.5V
220
215
210
–40
–20
0
20
40
60
Temperature (°C)
12/27
80
100
120
AI09144b
STM705/706/707/708/813L
Figure 17. Normalized Reset Threshold vs. Temperature
Normalized Reset Threshold
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
Figure 18. Watchdog Time-out Period vs. Temperature
Watchdog Time-out Period (sec)
1.90
1.85
1.80
1.75
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
1.70
1.65
1.60
–40
–20
0
20
40
Temperature (°C)
60
80
100
120
AI09146b
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STM705/706/707/708/813L
Figure 19. PFI to PFO Propagation Delay vs. Temperature
PFI to PFO Propagation Delay (µs)
4.0
VCC = 3.0V
VCC = 3.6V
3.0
VCC = 4.5V
VCC = 5.5V
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI09148b
Figure 20. Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C)
5.00
VOUT (V)
4.98
4.96
4.94
0
10
20
30
IOUT (mA)
14/27
40
50
AI10496
STM705/706/707/708/813L
Figure 21. Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C)
2.80
2.78
VOUT (V)
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
0.6
0.8
IOUT (mA)
1.0
AI10497
Figure 22. RST Output Voltage vs. Supply Voltage
5
5
VRST (V)
4
4
3
3
2
2
1
1
0
VCC (V)
VRST
VCC
0
500ms/div
AI09149b
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STM705/706/707/708/813L
Figure 23. RST Output Voltage vs. Supply Voltage
5
5
VRST
VCC
4
3
3
2
2
1
1
0
0
500ms/div
AI09150b
Figure 24. RST Response Time (Assertion)
5V
1V/div
VCC
4V
5V
4V
RST
1V/div
0V
5µs/div
Note: VRST = 4.603V at 25°C.
16/27
VCC (V)
VRST (V)
4
AI09151b
STM705/706/707/708/813L
Figure 25. RST Response Time (Assertion)
5V
VCC
4V
1V/div
4V
RST
1V/div
0V
5µs/div
AI09152b
Note: VRST = 4.603V at 25°C.
Figure 26. Power-fail Comparator Response Time (Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
AI09153b
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STM705/706/707/708/813L
Figure 27. Power-fail Comparator Response Time (De-Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
AI09154b
Figure 28. Maximum Transient Duration vs. Reset Threshold Overdrive
6000
Transient Duration (µs)
5000
4000
Reset occurs
above the curve.
3000
2000
1000
0
0.001
0.01
0.1
Reset Comparator Overdrive, VRST – VCC (V)
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1
10
AI09156b
STM705/706/707/708/813L
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 4. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC +0.3
V
VIO
Input or Output Voltage
VCC
Supply Voltage
–0.3 to 7.0
V
IO
Output Current
20
mA
PD
Power Dissipation
320
mW
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
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STM705/706/707/708/813L
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 5, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 5. Operating and AC Measurement Conditions
STM705/706/707/708;
STM813L
Unit
VCC Supply Voltage
1.0 to 5.5
V
Ambient Operating Temperature (TA)
–40 to 85
°C
≤5
ns
Input Pulse Voltages
0.2 to 0.8VCC
V
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
V
Parameter
Input Rise and Fall Times
Figure 29. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 30. Power-fail Comparator Waveform
VCC
VRST
trec
PFO
RST
AI08834b
20/27
STM705/706/707/708/813L
Figure 31. MR Timing Waveform
MR
tMLRL
RST
(1)
trec
tMLMH
AI07837a
Note: 1. RST for STM805.
Figure 32. Watchdog Timing (STM705/706/813L)
VCC
RST
trec
tWD
WDI
WDO
AI08833
Table 6. DC and AC Characteristics
Sym
Alternative
Description
VCC
Operating Voltage
ICC
VCC Supply Current
Test Condition(1)
Min
Typ
Max
Unit
5.5
V
25
60
µA
1.2(2)
Input Leakage Current (MR)
4.5V < VCC < 5.5V
75
125
300
µA
Input Leakage Current (PFI)
0V = VIN = VCC
–25
2
+25
nA
120
160
µA
ILI
Input Leakage Current (WDI)
WDI = VCC, time average
WDI = GND, time average
–20
–15
µA
VIH
Input High Voltage (MR)
4.5V < VCC < 5.5V
2.0
V
VIH
Input High Voltage (WDI)
VRST (max) < VCC < 5.5V
0.7VCC
V
VIL
Input Low Voltage (MR)
4.5V < VCC < 5.5V
0.8
V
VIL
Input Low Voltage (WDI)
VRST (max) < VCC < 5.5V
0.3VCC
V
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STM705/706/707/708/813L
Sym
Alternative
Description
VOL
Output Low Voltage (PFO, RST,
RST, WDO)
VOL
Output Low Voltage (RST)
Min
Typ
Max
Unit
VCC = VRST (max),
ISINK = 3.2mA
0.3
V
ISINK = 50µA, VCC = 1.0V,
TA = 0°C to 85°C
0.3
V
ISINK = 100µA, VCC = 1.2V
0.3
V
Output High Voltage (RST, RST,
WDO)
ISOURCE = 1mA,
VCC = VRST (max)
2.4
V
Output High Voltage (PFO)
ISOURCE = 75µA,
VCC = VRST (max)
0.8VCC
V
VOH
VOH
Test Condition(1)
Output High Voltage (RST)
ISOURCE = 4µA,
VCC = 1.1V,
TA = 0°C to 85°C
0.8
V
ISOURCE = 4µA,
VCC = 1.2V
0.9
V
1.30
V
Power-fail Comparator
VPFI
PFI Input Threshold
tPFD
PFI to PFO Propagation Delay
PFI Falling (VCC = 5V)
1.20
1.25
2
µs
Reset Thresholds
Reset Threshold(3)
VRST
STM705/707/813L
4.50
4.65
4.75
V
STM706/708
4.25
4.40
4.50
V
Reset Threshold Hysteresis
trec
25
RST Pulse Width
140
150
200
mV
280
ms
Push-button Reset Input
tMLMH
tMR
MR Pulse Width
tMLRL
tMRD
MR to RST Output Delay
ns
250
ns
2.24
s
Watchdog Timer (STM705/706/813L)
tWD
Watchdog Timeout Period
4.5V < VCC < 5.5V
1.12
WDI Pulse Width
4.5V < VCC < 5.5V
50
1.60
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.75V to 5.5V for STM705/707/813L; VCC = 4.5V to 5.5V for
STM706/708 (except where noted).
2. VCC (min) = 1.0V for TA = 0°C to +85°C.
3. For VCC falling.
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STM705/706/707/708/813L
PACKAGE MECHANICAL
Figure 33. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
1.35
1.75
–
0.053
0.069
A1
–
0.10
0.25
–
0.004
0.010
B
–
0.33
0.51
–
0.013
0.020
C
–
0.19
0.25
–
0.007
0.010
D
–
4.80
5.00
–
0.189
0.197
ddd
–
–
0.10
–
–
0.004
E
–
3.80
4.00
–
0.150
0.157
e
1.27
–
–
0.050
–
–
H
–
5.80
6.20
–
0.228
0.244
h
–
0.25
0.50
–
0.010
0.020
L
–
0.40
0.90
–
0.016
0.035
α
–
0°
8°
–
0°
8°
N
8
8
23/27
STM705/706/707/708/813L
Figure 34. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
–
1.10
–
–
0.043
A1
–
0.05
0.15
–
0.002
0.006
A2
0.85
0.75
0.95
0.034
0.030
0.037
b
–
0.25
0.40
–
0.010
0.016
c
–
0.13
0.23
–
0.005
0.009
CP
–
–
0.10
–
–
0.004
D
3.00
2.90
3.10
0.118
0.114
0.122
e
0.65
–
–
0.026
–
–
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.90
3.10
0.118
0.114
0.122
L
0.55
0.40
0.70
0.022
0.016
0.030
L1
0.95
–
–
0.037
–
–
α
–
0°
6°
–
0°
6°
N
24/27
8
8
STM705/706/707/708/813L
PART NUMBERING
Table 9. Ordering Information Scheme
Example:
STM705
M
6
E
Device Type and Reset Threshold Voltage
STM705/707/813L = VRST = 4.50V to 4.75V
STM706/708 = VRST = 4.25V to 4.50V
Package
M = SO8
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
E = Tubes
F = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 10. Marking Description
Part Number
Reset Threshold
STM705
4.63V
Package
Topside Marking
SO8
705
TSSOP8
SO8
STM706
4.38V
706
TSSOP8
SO8
STM707
4.63V
707
TSSOP8
SO8
STM708
4.38V
708
TSSOP8
SO8
STM813L
4.63V
813L
TSSOP8
25/27
STM705/706/707/708/813L
REVISION HISTORY
Table 11. Document Revision History
Date
Version
September 2003
1.0
First Issue
31-Oct-03
1.1
Update DC Characteristics (Table 6)
12-Dec-03
2.0
Reformatted; update characteristics (Figure 1, 2, 3, 4, 6, 8, 9, 10, 31, 32, 30; Table
6, 8, 10)
16-Jan-04
2.1
Add Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27, 28)
09-Apr-04
3.0
Reformatted; update characteristics (Figure 15, 19, 22, 23, 24, 25, 28; Table 6)
25-May-04
4.0
Update characteristics (Table 3, 6)
02-Jul-04
5.0
Document promoted; corrected waveform (Figure 30)
21-Sep-04
6.0
Clarify root part numbers, pin descriptions (Figure 2, 3, 10; Table 5, 6, 9)
08-Mar-05
7.0
Update Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28)
26/27
Revision Details
STM705/706/707/708/813L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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