TI TPS3705-33DR

SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
TPS3705 . . . D PACKAGE
(TOP VIEW)
features
D Power-On Reset Generator with Fixed
Delay Time of 200 ms, no External
Capacitor Needed
Precision Supply Voltage Monitor 2.5 V, 3 V,
3.3 V, and 5 V
Pin-For-Pin Compatible with the MAX705
through MAX708 Series
Integrated Watchdog Timer (TPS3705 only)
Voltage Monitor for Power-Fail or
Low-Battery Warning
Maximum Supply Current of 50 µA
MSOP-8 and SO-8 Packages
Temperature Range . . . −40°C to 85°C
D
D
D
D
D
D
D
MR
VDD
GND
PFI
8
2
7
3
6
4
5
WDO
RESET
WDI
PFO
TPS3707 . . . D PACKAGE
(TOP VIEW)
MR
VDD
GND
PFI
1
8
2
7
3
6
4
5
RESET
RESET
NC
PFO
NC − No internal connection
TPS3705 . . . DGN PACKAGE
(TOP VIEW)
typical applications
D Designs Using DSPs, Microcontrollers or
Microprocessors
Industrial Equipment
Programmable Controls
Automotive Systems
Portable/Battery Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Notebook/Desktop Computers
D
D
D
D
D
D
D
1
RESET
WDO
MR
VDD
1
8
2
7
3
6
4
5
WDI
PFO
PFI
GND
TPS3707 . . . DGN PACKAGE
(TOP VIEW)
12 V
5V
RESET
RESET
MR
VDD
1
8
2
7
3
6
4
5
NC
PFO
PFI
GND
NC − No internal connection
VDD
VDD
PFO
TPS3705−50
MR
100 nF
RESET
910 kΩ
MSP430P112
RESET/NMI
WDO
I/O
WDI
I/O
PFI
120 kΩ
GND
GND
Figure 1. Typical MSP430 Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999−2005, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %" "!$%!"
"!)) ,!-* )$#! &#%"". )%" ! %#%""(- #($)%
!%"!. (( &%!%"*
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
description
The TPS3705, TPS3707 family of microprocessor supply-voltage supervisors provide circuit initialization and
timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors VDD and keeps RESET active as long as VDD remains below the threshold
voltage VIT+. An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time, td typ = 200 ms, starts after VDD has risen above the threshold voltage VIT+. When the supply
voltage drops below the threshold voltage VIT– , the output becomes active (low) again. No external components
are required. All the devices of this family have a fixed-sense threshold voltage VIT– set by an internal voltage
divider.
The TPS3705-xx and TPS3707-xx devices incorporate a manual reset input, MR. A low level at MR causes
RESET to become active.
The TPS370x-xx families integrate a power-fail comparator which can be used for low-battery detection,
power-fail warning, or for monitoring a power supply other than the main supply.
The TPS3705-xx devices have a watchdog timer that is periodically triggered by a positive or negative transition
at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
tt(out) = 1.6 s, WDO becomes active. This event also reinitializes the watchdog timer. Leaving WDI unconnected
disables the watchdog.
The TPS3707-xx devices do not have the Watchdog function, but include a high-level output RESET.
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in
either 8-pin MSOP or standard SOIC packages. The TPS3705, TPS3707 devices are characterized for
operation over a temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C
−40
C to 85
85°C
C
2
THRESHOLD
VOLTAGE
SMALL OUTLINE
(D)
POWER−PAD
µ-SMALL OUTLINE
(DGN)
MARKING DGN
PACKAGE
CHIP FORM
(Y)
2.63 V
TPS3705−30D
TPS3705−30DGN
TIAAT
TPS3705-30Y
2.93 V
TPS3705−33D
TPS3705−33DGN
TIAAU
TPS3705−33Y
4.55 V
TPS3705−50D
TPS3705−50DGN
TIAAV
TPS3705−50Y
2.25 V
TPS3707−25D
TPS3707−25DGN
TIAAW
TPS3707−25Y
2.63 V
TPS3707−30D
TPS3707−30DGN
TIAAX
TPS3707−30Y
2.93 V
TPS3707−33D
TPS3707−33DGN
TIAAY
TPS3707−33Y
4.55 V
TPS3707−50D
TPS3707−50DGN
TIAAZ
TPS3707−50Y
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• DALLAS, TEXAS 75265
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
Function Tables
TRUTH TABLE, TPS3705
MR
VDD>VIT
RESET
TYPICAL
DELAY
H→L
1
H→L
30 ns
L→H
1
L→H
200 ms
H
1→0
H→L
3 µs
H
0→1
L→H
200 ms
TRUTH TABLE, TPS3707
MR
VDD>VIT
RESET
RESET
TYPICAL
DELAY
H→L
1
H→L
L→H
30 ns
200 ms
L→H
1
L→H
H→L
H
1→0
H→L
L→H
3 µs
H
0→1
L→H
H→L
200 ms
TRUTH TABLE, TPS370x
PFI>VIT
PFO
TYPICAL
DELAY
0→1
L→H
0.5 µs
1→0
H→L
0.5 µs
functional block diagram
TPS3705
TPS3707
VDD
14 kΩ
MR
Reset
Logic + Timer
R1
+
_
RESET
RESET
Only
TPS3707
R2
GND
Oscillator
Reference
Voltage
of 1.25 V
_
WDI
Only
TPS3705
PFO
+
PFI
Transition
Detection
Watchdog
Logic + Timer
Only
TPS3705
40 kΩ
POST OFFICE BOX 655303
WDO
• DALLAS, TEXAS 75265
3
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
timing diagrams
VDD
5V
4.5 V
1.1 V
0V
t
MR
5V
4.5 V
1.1 V
0V
RESET
t
td
td
td
5V
4.5 V
1.1 V
0V
t
Don’t Care
1.1 V
Don’t Care
5V
4.5 V
Don’t Care
Undefined Behavior
WDI
0V
t
WDO
t t(out)
5V
4.5 V
1.1 V
0V
4
t
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• DALLAS, TEXAS 75265
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
TPS370xY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS370x. Thermal
compression or ultrasonic bonding may be caused on the doped-aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(1)
(8)
(7)
(2)
(3)
TPS3705Y
TPS3707Y
(4)
(6)
(5)
46
CHIP THICKNESS: 10 MILS TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
50
Terminal Functions
TERMINAL
NAME
NO.
I/O
MR
1
VDD
2
GND
3
PFI
4
I
Power-fail comparator input
5
O
Power-fail comparator output
I
Watchdog timer input
PFO
WDI
TPS3705
NC
TPS3707
RESET
TPS3705
RESET
TPS3707
8
Manual reset
Supply voltage
Ground
6
7
WDO
I
DESCRIPTION
No internal connection
O
Active-low reset output
O
Watchdog timer output
O
Active-high reset output
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5
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
PFI voltage range, VPFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA <25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
DGN
D
2.14 W
725 mW
17.1 mW/_C
5.8 mW/_C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
1.37 W
464 mW
1.11 W
377 mW
recommended operating conditions at specified temperature range
MIN
MAX
UNIT
Supply voltage, VDD
2
6
V
Input voltage, VI
0
VDD+0.3
V
High-level input voltage, VIH
0.7×VDD
Low-level input voltage, VIL
Input transition rise and fall rate at MR or WDI, ∆t/∆V
Operating free-air temperature range, TA
6
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
0.3×VDD
100
ns/V
V
85
_C
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TPS370x-xx
VDD = 1.1 V
IOH = − 4 µA
MIN
TYP
MAX
UNIT
0.8
TPS3707-25
TPS370x-30
VOH
High-level output voltage
TPS370x-33
VDD = VIT+ + 0.2 V,
IOH = −500 µA
TPS370x-50
VDD = VIT+ + 0.2 V,
IOH = −800 µA
TPS370x-xx
VDD = 6 V,
0.7×V
0.7
VDD
V
VDD −1.5 V
IOH = −800 µA
TPS3707-25
TPS370x-30
VOL
TPS370x-xx
Power-up reset voltage (see Note 2)
Negative-going input
threshold voltage
(see Note 3)
VDD = VIT++0.2 V,
IOL = 2.5 mA
VDD = 6 V
VDD ≥ 1.1 V,
2.20
2.25
2.30
2.57
2.63
2.68
2.87
2.93
2.98
TPS370x-50
4.45
4.55
4.63
TPS3707-25
2.20
2.25
2.32
2.57
2.63
2.70
2.87
2.93
3.0
4.45
4.55
4.65
1.20
1.25
1.30
TPS370x-33
TA = 0°C to 85°C
TA = −40°C to 85°C
TPS370x-50
Hysteresis
VDD
PFI
IIH(AV)
TPS370x-xx
Average low-level input
current
IIH
High-level input current
IIL
Low-level input current
II
Input current
IDD
Supply current
VDD ≥ 2 V,
TA = −40°C to 85°C
TPS3707-25
40
TPS370x-30
50
TPS370x-33
50
TPS370x-50
70
TPS370x-xx
10
Average high-level input
current
IIL(AV)
0.3
TPS370x-30
TPS370x-30
PFI
0.4
IOL = 3 mA
IOL = 50 µA
TPS3707-25
TPS370x-33
Vhys
0.3
V
TPS370x-33
Low-level output voltage
TPS370x-50
VIT−
VDD = VIT++0.2 V, IOL = 1 mA
WDI
V
V
V
V
V
mV
WDI = VDD = 6 V,
Time average (dc = 88%)
100
150
µA
WDI = 0 V,
VDD = 6 V,
Time average (dc = 12%)
−15
−20
µA
WDI
WDI = VDD = 6 V
120
170
MR
−130
−180
WDI
MR = 0.7×VDD, VDD = 6 V
WDI = 0 V,
VDD = 6 V
−120
−170
MR
MR = 0 V,
−430
−600
PFI
VDD = 6 V,
VDD = 2 V to 6 V, MR = VDD, MR,
WDI and outputs unconnected
0
1
µA
20
50
µA
30
50
µA
TPS3707-xx
TPS3705-xx
VDD = 6 V
0 V ≤ VI ≤ VDD
VDD = 2 V to 6 V, MR= VDD, MR,
WDI and outputs unconnected
−1
µA
µA
Ci
Input capacitance
VI = 0 V to VDD
5
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
at VDD
at MR
VDD = VIT+ + 0.2 V,
VDD ≥ VIT++ 0.2 V,
at WDI
VDD ≥ VIT++ 0.2 V,
MIN
VDD = VIT−−0.2 V
VIL = 0.3 × VDD, VIH = 0.7 × VDD
VIL = 0.3 × VDD, VIH = 0.7 × VDD
TYP
MAX
UNIT
6
µs
100
ns
100
ns
switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tt(out)
Watchdog time out
VDD ≥ VIT+ + 0.2 V,
See timing diagram
1.1
1.6
2.3
s
td
Delay time
VDD > VIT+ + 0.2 V,
See timing diagram
140
200
280
ms
tPHL
Propagation (delay) time, high-to-low-level
output
MR to RESET delay
50
250
tPLH
Propagation (delay) time, low-to-high-level
output
MR to RESET delay
(TPS3707−xx only)
50
250
tPHL
Propagation (delay) time, high-to-low-level
output
VDD to RESET delay
3
5
tPLH
Propagation (delay) time, low-to-high-level
output
VDD to RESET delay
(TPS3707-xx only)
3
5
tPHL
Propagation (delay) time, high-to-low-level
output
0.5
1
0.5
1
tPLH
8
Propagation (delay) time, low-to-high-level
output
PFI to PFO delay
POST OFFICE BOX 655303
VDD ≥ VIT+ + 0.2 V,
VIL = 0.3 × VDD
VIH = 0.7 × VDD
ns
µss
µss
VDD = 2 V to 6 V
• DALLAS, TEXAS 75265
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
Normalized Input Threshold Voltage VIT(TA), VIT (25 °C )
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
1.002
VDD = 6 V
PFI = 1.05 V
MR = Open
1.001
1
0.999
−40
60
−15
10
35
TA − Free-Air Temperature − °C
85
Figure 2
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
50
VDD = 6 V
PFI = 1.05 V
0
I I − Input Current − µ A
I DD − Supply Current − µ A
30
PFI = 1.05 V
MR = Open
TA = 25°C
TPS3707−50
10
−10
−100
−200
−300
−40°C
−30
−400
85°C
−50
−0.5
−500
0.5
1.5
2.5
3.5
4.5
5.5
6.5
−1
0
1
2
3
4
5
6
VI − Input Voltage at MR − V
VDD − Supply Voltage − V
Figure 3
Figure 4
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• DALLAS, TEXAS 75265
9
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
PFI = 1.05 V
MR = Open
VOH − High-Level Output Voltage − V
tw − Minimum Pulse Duration at VDD − µ s
10
8
6
4
2
0
0
200
400
800
600
VDD = 3.2 V
PFI = 1.05 V
MR = Open
3
2.5
2
1.5
−40°C
1
85°C
0.5
0
1000
0
VDD − Threshold Overdrive − mV
−1
−2
−3
Figure 5
−5
−6
−7
−8
−9 −10
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
6.5
5.5
VOL − Low-Level Output Voltage − V
VDD = 6 V
PFI = 1.05 V
MR = Open
6
VOH − High-Level Output Voltage − V
−4
IOH − High-Level Output Current − mA
5
4.5
4
3.5
−40°C
3
85°C
2.5
2
1.5
1
VDD = 2.67 V
PFI = 1.05 V
MR = Open
2.5
2
1.5
85°C
−40°C
1
0.5
0.5
0
0
0
−5
−10
−15
−20
−25
−30
0
1
IOH − High-Level Output Current − mA
Figure 7
10
2
3
4
5
6
Figure 8
POST OFFICE BOX 655303
7
8
9
10 11 12 13
IOL − Low-Level Output Current − mA
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3705-30D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-30DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-30DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-30DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-30DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-30DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-33DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3705-50DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3705-50DRG4
ACTIVE
SOIC
D
8
TPS3707-25D
ACTIVE
SOIC
D
8
75
TPS3707-25DG4
ACTIVE
SOIC
D
8
TPS3707-25DGN
ACTIVE
MSOPPower
PAD
DGN
TPS3707-25DGNG4
ACTIVE
MSOPPower
PAD
TPS3707-25DGNR
ACTIVE
TPS3707-25DGNRG4
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-25DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-25DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-30DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3707-33DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-33DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3707-50DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
11-Jun-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS3705-30DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3705-33DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3705-33DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3705-50DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3705-50DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3707-25DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3707-25DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3707-30DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3707-30DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3707-33DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3707-33DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TPS3707-50DGNR
DGN
8
HNT
330
12
5.3
3.4
1.4
8
12
NONE
TPS3707-50DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TPS3705-30DR
D
TPS3705-33DGNR
DGN
8
TAI
346.0
346.0
29.0
8
HNT
358.0
335.0
35.0
TPS3705-33DR
D
8
TAI
346.0
346.0
29.0
TPS3705-50DGNR
DGN
8
HNT
358.0
335.0
35.0
TPS3705-50DR
D
8
TAI
346.0
346.0
29.0
TPS3707-25DGNR
DGN
8
HNT
358.0
335.0
35.0
TPS3707-25DR
D
8
TAI
346.0
346.0
29.0
TPS3707-30DGNR
DGN
8
HNT
358.0
335.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TPS3707-30DR
D
8
TAI
346.0
346.0
29.0
TPS3707-33DGNR
DGN
8
HNT
358.0
335.0
35.0
TPS3707-33DR
D
8
TAI
346.0
346.0
29.0
TPS3707-50DGNR
DGN
8
HNT
358.0
335.0
35.0
TPS3707-50DR
D
8
TAI
346.0
346.0
29.0
Pack Materials-Page 3
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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www.ti.com/opticalnetwork
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