59C11 1K 5.0V Microwire Serial EEPROM FEATURES PACKAGE TYPES DIP 1 8 V CC CLK 2 7 RDY/BSY DI 3 6 ORG DO 4 5 V SS CS 1 8 V CC CLK 2 7 RDY/BSY DI 3 6 ORG DO 4 5 V SS SOIC 59C11 DESCRIPTION The Microchip Technology Inc. 59C11 is a 1K bit Electrically Erasable PROM. The device is configured as 128 x 8 or 64 x 16, selectable externally by means of the control pin ORG. Advanced CMOS technology makes this device ideal for low power nonvolatile memory applications. The 59C11 is available in the standard 8-pin DIP and a surface mount SOIC package. CS 59C11 • Low power CMOS technology • Pin selectable memory organization - 128 x 8 or 64 x 16 bit organization • Single 5V only operation • Self timed WRITE, ERAL and WRAL cycles • Automatic erase before WRITE • RDY/BSY status information during WRITE • Power on/off data protection circuitry • 1,000,000 ERASE/WRITE cycles guaranteed • Data Retention > 200 Years • 8-pin DIP or SOIC package • Temperature ranges supported - Commercial (C): 0˚C to +70˚C - Industrial (I): -40˚C to +85˚C - Automotive (E): -40˚C to +125˚C BLOCK DIAGRAM VCC ORG VSS MEMORY ARRAY 128 x 8 or 64 x 16 DATA REGISTER ADDRESS DECODER OUTPUT BUFFER DO DI CS MODE DECODE LOGIC CLK CLOCK GENERATOR RDY/BSY Microwire is a registered trademark of National Semiconductor Incorporated. 1996 Microchip Technology Inc. DS20040J-page 1 This document was created with FrameMaker 4 0 4 59C11 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name Function CS CLK DI DO VSS ORG RDY/BSY VCC VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .................................. -65˚C to +150˚C Ambient temperature with power applied...... -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Chip Select Serial Clock Data In Data Out Ground Memory Array Organization Ready/Busy Status +5V Power SUpply DC CHARACTERISTICS VCC = +5.0V (±10%) Commercial (C): Industrial (I): Automotive (E): Parameter Symbol Min Max = 0°C to 70°C = -40°C to +85°C = -40°C to 125°C Units VCC detector threshold VTH 2.8 4.5 V High level input voltage VIH 2.0 Vcc+1 V Low level input voltage VIL -0.3 0.8 V High level output voltage VOH 2.4 — V Low level output voltage VOL — 0.4 V — 10 µA Input leakage current ILI Output leakage current ILO — 10 µA Pin capacitance CIN, — 7 pF (all inputs/outputs) COUT Operating current (all modes) ICC write — 4 mA — 100 µA Standby current ICCS Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7. 2: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: Tamb Tamb Tamb Conditions IOH = -400 µA IOL = 3.2 mA VIN = 0V to VCC (Note 1) VOUT = 0V to VCC (Note 1) VIN/VOUT = 0V (Note 2) Tamb = 25°C, f = 1 MHz FCLK = 1 MHz, VCC = 5.5V CS = 0V, VCC = 5.5V SYNCHRONOUS DATA TIMING TCKH TCKL TCSH V IH CLK V IL TDIH TDIS TDIH TDIS V IH DI VALID VALID V IL TCSL CS TCSS V IH V IL TPD TPD DO VALID TCZ VALID HIGH Z DS20040J-page 2 V IH/ V OH V IL/ V OL 1996 Microchip Technology Inc. 59C11 TABLE 1-3: AC CHARACTERISTICS Parameter Symbol Min Max Units 1 MHz Conditions Clock frequency FCLK Clock high time TCKH 500 — ns Clock low time TCKL 500 — ns Chip select setup time TCSS 50 — ns Chip select hold time TCSH 0 — ns Chip select low time TCS 100 — ns Data input setup time TDIS 100 — ns Data input hold time TDIH 100 — ns Data output delay time TPD — 400 ns CL = 100 pF Data output disable time (from CS = low) TCZ 0 100 ns CL = 100 pF Data output disable time (from last clock) TDDZ 0 400 ns CL = 100 pF RDY/BSY delay time TRBD — 400 ns Program cycle time (Auto Erase and Write) Twc — 1 15 ms ms — 1M — cycles Endurance for 8-bit mode for ERAL and WRAL in 8/16-bit modes 25°C, Vcc = 5.0V, Block Mode (Note 1) Note 1: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. TABLE 1-4: INSTRUCTION SET 6 X 16 MODE, ORG = 1 Instruction Start Bit Opcode Address Data In Data Out Number of Req. CLK CYcles READ 1 1 0 X X A5 A4 A3 A2 A1 A0 — D15-D0 27 WRITE 1 X 1 X X A5 A4 A3 A2 A1 A0 D15-D0 High-Z 27 EWEN 1 0 0 1 1 X X X X X X — High-Z 11 EWDS 1 0 0 0 0 X X X X X X — High-Z 11 ERAL 1 0 0 1 0 X X X X X X — High-Z 11 WRAL 1 0 0 0 1 X X X X X X D15-D0 High-Z 27 Data In Data Out Number of Req. CLK CYcles 128 X 8 MODE, ORG = 0 Instruction Start Bit Opcode Address READ 1 1 0 X X A6 A5 A4 A3 A2 A1 A0 — D7-D0 20 WRITE 1 X 1 X X A6 A5 A4 A3 A2 A1 A0 D7-D0 High-Z 20 EWEN 1 0 0 1 1 X X X X X X X — High-Z 12 EWDS 1 0 0 0 0 X X X X X X X — High-Z 12 ERAL 1 0 0 1 0 X X X X X X X — High-Z 12 WRAL 1 0 0 0 1 X X X X X X X D7-D0 High-Z 20 1996 Microchip Technology Inc. DS20040J-page 3 59C11 2.0 FUNCTIONAL DESCRIPTION 2.4 2.1 START Condition The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy bit (logical 0) precedes the 8- or 16-bit output string. The output data changes during the high state of the system clock (CLK). The dummy bit is output TPD after the positive edge of CLK, which was used to clock in the last address bit (A0). Therefore, care must be taken if DI and DO are connected together as a bus contention will occur for one clock cycle if A0 is a one. The START bit is detected by the device if CS and DI are both High with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition) without resulting in any device operation (READ, WRITE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e. clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected. Note: 2.2 CS must go LOW between consecutive instructions. DI/DO Pins It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. 2.3 Data Protection During power-up, all modes of operation are inhibited until VCC has reached a level of 2.8 V. During powerdown, the source data protection circuitry acts to inhibit all modes when VCC has fallen below 2.8 V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, EWEN instruction must be performed before any WRITE, ERAL or WRAL instruction can be executed. After programming is completed, the EWDS instruction offers added protection against unintended data changes. DS20040J-page 4 READ Mode DO will go into HIGH-Z mode with the positive edge of the next CLK cycle. This follows the output of the last data bit D0 or the negative edge of CS, whichever occurs first. D0 remains stable between CLK cycles for an unlimited time as long as CS stays HIGH. The most significant data bit (D15 or D7) is always output first, followed by the lower significant bits (D14 - D0 or D6 - D0). 2.5 WRITE The WRITE instruction is followed by 8 or 16 bits of data which are written into the specified address. The most significant data bit (D15 or D7) has to be clocked in first followed by the lower significant data bits (D14 – D0 or D6 – D0). If a WRITE instruction is recognized by the device and all data bits have been clocked in, the device performs an automatic erase cycle on the specified address before the data are written. The WRITE cycle is completely self timed and commences automatically after the rising edge of the CLK signal for the last data bit (D0). The WRITE cycle takes 1 ms maximum for 8-bit mode and 2 ms maximum for 16-bit mode. 2.6 Erase/Write Enable and Disable (EWEN, EWDS) The device is automatically in the ERASE/WRITE Disable mode (EWDS) after power-up. Therefore, EWEN instruction has to be performed before any WRITE, ERAL, or WRAL instruction is executed by the device. For added data protection, the device should be put in the ERASE/WRITE Disable mode (EWDS) after programming operations are completed. 2.7 ERASE All (ERAL) The entire chip will be erased to logical “1s” if this instruction is received by the device and it is in the EWEN mode. The ERAL cycle is completely self-timed and commences after the rising edge of the CLK signal for the last dummy address bit. ERAL takes 15 ms maximum. 1996 Microchip Technology Inc. 59C11 2.8 WRITE All (WRAL) The entire chip will be written with the data specified in that command. The WRAL cycle is completely selftimed and commences after the last data bit (D0) has been clocked in. WRAL takes 15 ms maximum. Note: The WRAL does not include an automatic ERASE cycle for the chip. Therefore, the WRAL instruction must be preceded by an ERAL instruction and the chip must be in the EWEN status in both cases. The WRAL instruction is used for testing and/or device initialization. FIGURE 2-1: READ MODE CLK T CSL CS OPCODE SB AN A0 DI 1 1 0 X X X X T DDZ TPD HIGH - Z DO NOTE: FIGURE 2-2: ORGANIZATION AN 0 D0 DN DN 128 x 8 A6 D7 64 x 16 A5 D15 NEW INSTRUCTION OR STANDBY (CS = 0) WRITE MODE CLK TCSL CS SB OPCODE AN A0 X X DN D0 DI 1 X 1 DO X X X X HIGH - Z TRBD RDY/BSY NOTE: ORGANIZATION 128 x 8 64 x 16 1996 Microchip Technology Inc. AN DN TWC A6 A5 D7 D15 NEW INSTRUCTION OR STANDBY (CS = 0) DS20040J-page 5 59C11 FIGURE 2-3: ERASE/WRITE ENABLE AND DISABLE CLK TCSL CS SB OPCODE AN A0 X X SB DI 1 0 0 DO 0 1 EWDS EWEN HIGH - Z NOTE: ORGANIZATION 128 x 8 64 x 16 FIGURE 2-4: 0 1 AN A6 A5 NEW INSTRUCTION OR STANDBY (CS = 0) ERASE ALL (ERAL) CLK T CSH T CSL CS SB OPCODE AN A0 X X SB DI 1 0 0 1 DO 0 HIGH - Z TRBD RDY/BSY NOTE: FIGURE 2-5: ORGANIZATION AN 128 x 8 A6 64 x 16 A5 TWC NEW INSTRUCTION OR STANDBY (CS = 0) WRITE ALL CLK TCSH TCSL CS SB OPCODE AN A0 DN D0 X X X X DI 1 0 0 0 1 HIGH - Z DO T RBD RDY/BSY NOTE: ORGANIZATION DS20040J-page 6 AN DN 128 x 8 A6 D7 64 x 16 A5 D15 T WC NEW INSTRUCTION OR STANDBY (CS = 0) 1996 Microchip Technology Inc. 59C11 3.0 PIN DESCRIPTION 3.4 3.1 Chip Select (CS) Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This output is in HIGH–Z mode except if data is clocked out as a result of a READ instruction. A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a WRITE cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought LOW during a WRITE cycle, the device will go into standby mode as soon as the WRITE cycle is completed. CS must be LOW for 100 ns (TCSL) minimum between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 59C11. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be continued anytime (with respect to clock high time (TCKH) and clock low time (TCKL)). This gives freedom in preparing opcode, address and data for the controlling master. CLK is a “Don't Care” if CS is LOW (device deselected). If CS is HIGH, but a START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). Data Out (DO) DI and DO can be connected together to perform a 3wire interface (CS, CLK, DI/DO). Care must be taken with the leading dummy zero which is output after a READ command has been detected. Also, the controlling device must not drive the DI/DO bus during WRITE cycles. 3.5 Organization (ORG) This input selects the memory array organization. When the ORG pin is connected to +5 V the 64 x 16 organization is selected. When it is connected to ground, the 128 x 8 organization is selected. If the ORG pin is left unconnected, then an internal pull-up device will select the 64 x 16 organization. In applications subject to electrical noise, it is recommended that this pin not be left floating, but tied either high or low. 3.6 Ready/Busy (RDY/BSY) Pin 7 provides RDY/BSY status information. RDY/BSY is low if the device is performing a WRITE, ERAL, or WRAL operation. When it is HIGH the internal, selftimed WRITE, ERAL or WRAL operation has been completed and the device is ready to receive a new instruction. CLK cycles are not required during the self-timed WRITE (i.e., auto erase/write) cycle. After detection of a START condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (see instruction set truth table). When that limit has been reached, CLK and DI become “Don't Care” inputs until CS is brought LOW for at least chip select low time (TCSL) and brought HIGH again and a WRITE cycle (if any) is completed. 3.3 Data In (DI) Data In is used to clock in START bit, opcode, address and data synchronously with the CLK input. 1996 Microchip Technology Inc. DS20040J-page 7 59C11 NOTES: DS20040J-page 8 1996 Microchip Technology Inc. 59C11 NOTES: 1996 Microchip Technology Inc. DS20040J-page 9 59C11 NOTES: DS20040J-page 10 1996 Microchip Technology Inc. 59C11 59C11 Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 59C11 – I /P Package: Temperature Range: Device: 1996 Microchip Technology Inc. P = Plastic DIP (300 mil Body) SN = Plastic SOIC (150 mil Body) SM = Plastic SOIC (207 mil Body) Blank = 0°C to +70°C I = -40°C to +85°C E = -40°C to +125°C 59C11 59C11T 1K Microwire Serial EEPROM 1K Microwire Serial EEPROM (Tape and Reel) DS20040J-page 11 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. 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Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS20040J-page 12 1996 Microchip Technology Inc.