TI TLC5618AID

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
DIN
SCLK
CS
OUT A
1
8
2
7
3
6
4
5
VDD
OUT B
REFIN
AGND
VDD
NC
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
NC
4
18 NC
SCLK
5
17 OUTB
NC
6
16 NC
CS
7
15 REFIN
NC
8
14 NC
9
10 11 12 13
NC
Digital control of the TLC5618 is over a 3-wire
CMOS-compatible serial bus. The device receives a 16-bit word for programming and
producing the analog output. The digital inputs
feature Schmitt triggers for high noise immunity.
Digital communication protocols include the
SPI, QSPI, and Microwire standards.
D, P, OR JG PACKAGE
(TOP VIEW)
AGND
The TLC5618 is a dual 12-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DACs
have an output voltage range that is two times the
reference voltage, and the DACs are monotonic.
The device is simple to use, running from a single
supply of 5 V. A power-on reset function is
incorporated in the device to ensure repeatable
start-up conditions.
D
D
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones
NC
description
D
D
D
NC
D
D
D
D
applications
DIN
D
D
D
D
Input Data Update Rate of 1.21 MHz
Monotonic Over Temperature
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
OUTA
D
D
D
D
NC
D
Programmable Settling Time to 0.5 LSB
2.5 µs or 12.5 µs Typ
Two 12-Bit CMOS Voltage Output DACs in
an 8-Pin Package
Simultaneous Updates for DAC A and
DAC B
Single Supply Operation
3-Wire Serial Interface
High-Impedance Reference Inputs
Voltage Output Range . . . 2 Times the
Reference Input Voltage
Software Powerdown Mode
Internal Power-On Reset
TMS320 and SPI Compatible
Low Power Consumption:
3 mW Typ in Slow Mode,
8 mW Typ in Fast Mode
NC
D
Two versions of the device are available. The
TLC5618 does not have an internal state machine
and is dependent on all external timing signals. The TLC5618A has an internal state machine that counts the
number of clocks from the falling edge of CS and then updates and disables the device from accepting further
data inputs. The TLC5618A is recommended for TMS320 and SPI processors, and the TLC5618 is
recommended only for SPI or 3-wire serial port processors. The TLC5618A is backward-compatible and
designed to work in TLC5618 designed systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
description (continued)
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5618C is characterized for operation from 0°C to 70°C. The TLC5618I is characterized for operation
from – 40°C to 85°C. The TLC5618Q is characterized for operation from – 40°C to 125°C. The TLC5618M is
characterized for operation from – 55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE†
(D)
PLASTIC DIP
(P)
CERAMIC DIP
(JG)
20 PAD LCC
(FK)
0°C to 70°C
TLC5618CD
TLC5618ACD
TLC5618CP
TLC5618ACP
—
—
—
—
– 40°C to 85°C
TLC5618ID
TLC5618AID
TLC5618IP
TLC5618AIP
—
—
—
—
– 40°C to 125°C
TLC5618AQD
—
—
– 55°C to 125°C
—
—
—
TLC5618AMJG
† The D package is available in tape and reel by adding R to the part number
(e.g., TLC5618CDR)
DEVICE
2
COMPATIBILITY
TLC5618
SPI, QSPI and Microwire
TLC5618A
TMS320Cxx, SPI, QSPI, and Microwire
POST OFFICE BOX 655303
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TLC5618AMFK
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
functional block diagram
REFIN
AGND
6
_
DAC A
+
DAC
+
_
4
×2
5
Power-Up
Reset
R
OUT A
(Voltage Output)
R
12-Bit DAC Register Latch A
CS
SCLK
DIN
Control
Logic
3
(LSB)
2
(MSB)
12 Data Bits
1
4
Program
Bits
16-Bit Shift Register
Double
Buffer
Latch
12-Bit DAC Register Latch B
_
+
DAC
+
_
DAC B
×2
7 OUT B
(Voltage Output)
R
R
Terminal Functions
TERMINAL
NAME
NO.
AGND
5
CS
3
DIN
OUT A
I/O
DESCRIPTION
Analog ground
I
Chip select, active low
1
I
Serial data input
4
O
DAC A analog output
OUT B
7
O
DAC B analog output
REFIN
6
I
Reference voltage input
SCLK
2
I
Serial clock input
VDD
8
Positive power supply
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Reference input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Output voltage at OUT from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Continuous current at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, TA: TLC5618C, TLC5618AC . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC5618I, TLC5618AI . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
TLC5618AQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
TLC5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
635 mW
5.08 mW/°C
407 mW
330 mW
—
FK
1375 mW
11.00 mW/°C
880 mW
715 mW
275 mW
JG
1050 mW
8.40 mW/°C
672 mW
546 mW
210 mW
P
1202 mW
9.61 mW/°C
769 mW
625 mW
—
‡ This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘJA). Thermal Resistances are not production tested and are for
informational purposes only.
recommended operating conditions
Supply voltage, VDD
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
VDD = 5 V
VDD = 5 V
MIN
NOM
4.5
5
2
2
TLC5618C, TLC5618AC
0
2.048
VDD – 1.1
V
V
70
– 40
85
TLC5618AQ
– 40
125
TLC5618AM
– 55
125
• DALLAS, TEXAS 75265
V
kΩ
TLC5618I, TLC5618AI
POST OFFICE BOX 655303
UNIT
V
0.3 VDD
Load resistance, RL
4
5.5
0.7 VDD
Reference voltage, Vref to REFIN terminal
Operating free-air
free air temperature,
temperature TA
MAX
°C
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref(REFIN) = 2.048 V (unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
Resolution
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 1
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 3
Zero-scale-error temperature coefficient
Gain error
Vref(REFIN) = 2.048 V,
See Note 5
Vref(REFIN) = 2.048 V,
See Note 6
Differential nonlinearity (DNL)
EG
Zero-scale error (offset error at zero scale)
Gain error temperature coefficient
UNIT
±4
LSB
±1
LSB
bits
± 0.5
See Note 2
± 12
See Note 4
3
Gain
Power-supply
Power-su
ly rejection ratio
mV
ppm/°C
± 0.29
1
Zero scale
PSRR
MAX
12
Integral nonlinearity (INL), end point adjusted
EZS
TYP
% of FS
voltage
ppm/°C
65
Slow
65
See Notes 7 and 8
Zero scale
dB
65
Fast
Gain
65
NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUT A and OUT B output specifications
PARAMETER
VO
IOSC(sink)
IOSC(source)
IO(sink)
IO(source)
TEST CONDITIONS
Voltage output range
RL = 10 kΩ
MIN
TYP
0
Output load regulation accuracy
VO(OUT) = 4.096 V,
RL = 2 kΩ
VO(A OUT) = VDD,
VO(B OUT) = VDD,
Input code zero
Fast
38
Output
Out
ut short circuit sink current
Slow
23
VO(A OUT) = 0 V,
VO(B OUT) = 0 V
V,
Full-scale code
Fast
–54
Slow
–29
Output
Out
ut short circuit source current
Output sink current
Output source current
UNIT
VDD–0.4
V
± 0.29
% of FS
voltage
mA
mA
VO(OUT) = 0.25 V
VO(OUT) = 4.2 V
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MAX
• DALLAS, TEXAS 75265
5
mA
5
mA
5
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref(REFIN) = 2.048 V (unless otherwise noted) (continued)
reference input (REFIN)
PARAMETER
VI
Ri
Input voltage range
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
0
Input resistance
Reference feedthrough
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)
Reference input bandwidth (f – 3 dB)
REFIN = 0.2
0 2 Vpp + 1.024
1 024 V dc
VDD– 2
UNIT
V
10
MΩ
5
pF
– 60
dB
Slow
0.5
Fast
1
MHz
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp
at 1 kHz.
digital inputs (DIN, SCLK, CS)
PARAMETER
IIH
IIL
High-level digital input current
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
VI = VDD
VI = 0 V
Low-level digital input current
MAX
UNIT
±1
µA
±1
µA
8
pF
power supply
PARAMETER
IDD
TEST CONDITIONS
VDD = 5.5 V,
No load,
load
All inputs = 0 V or VDD
Power supply current
Power down supply current
MIN
TYP
MAX
Slow
0.6
1
Fast
1.6
2.5
UNIT
mA
D13 = 0 (see Table 2)
µA
1
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref(REFIN) = 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER
SR+
SR
SR–
Output slew rate
rate, positive
Output slew rate,
rate negative
TEST CONDITIONS
CL = 100 pF,
RL = 10 kΩ,
kΩ
Code 32 to Code 4096,
Vref(REFIN) = 2.048 V,
TA = 25°C
25°C,
VO from 10% to 90%
CL = 100 pF,
RL = 10 kΩ,
kΩ
Code 4096 to Code 32,
Vref(REFIN) = 2.048 V,
TA = 25°C
25°C,
VO from 10% to 90%
MIN
TYP
Slow
0.3
0.5
Fast
2.4
3
Slow
0.15
0.25
Fast
1.2
1.5
UNIT
V/µs
V/µs
ts
Output settling time
To ± 0.5 LSB,,
RL = 10 kΩ,
CL = 100 pF,
See Note 10
Slow
12.5
Fast
2.5
ts(c)
( )
Output settling
g time,,
code-to-code
To ± 0.5 LSB,,
RL = 10 kΩ,
CL = 100 pF,
See Note 11
Slow
2
Fast
2
Glitch energy
DIN = All 0s to all 1s,
f(SCLK) = 100 kHz
CS = VDD,
Signal to noise + distortion
Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000
S/(N+D)
MAX
µs
µs
5
nV–s
78
dB
NOTES: 10. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.
6
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%,
Vref(REFIN) = 2.048 V (unless otherwise noted) (continued)
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(DS)
th(DH)
Setup time, DIN before SCLK low
5
ns
Hold time, DIN valid after SCLK low
5
ns
tsu(CSS)
tsu(CS1)
Setup time, CS low to SCLK low
5
ns
10
ns
tsu(CS2)
tw(CL)
Setup time, SCLK ↑ to CS ↓, start of next write cycle
5
ns
Pulse duration, SCLK low
25
ns
tw(CH)
Pulse duration, SCLK high
25
ns
td(CS1)
Delay time, CLK↑ to data disable (TLC5618A only)
Setup time, SCLK ↓ to CS ↑, external end-of-write
5
20
ns
CS
tsu(CSS)
tsu(CS1)
tw(CL)
tw(CH)
tsu(CS2)
SCLK
(see Note A)
ÎÎÎ
ÎÎÎ
ÎÎÎ
tsu(DS)
DIN
DAC A/B
OUT
th(DH)
D15
D14
D13
ÏÏÏÏÏÏ
Program Bits (4)
D12
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÏÏÏÏÏ
ÎÎÎÎÎÎÎ
ÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
D11
D0
DAC Data
Bits (12)
ts
≤ Final Value ±0.5 LSB
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
Figure 1. Timing Diagram for the TLC5618
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7
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
Internally Generated
Disable at This Time
td(CS1)
CS
tsu(CSS)
tsu(CS1)
tw(CL)
tw(CH)
tsu(CS2)
SCLK
(see Note A)
DIN
ÎÎÎ
ÎÎÎ
ÎÎÎ
(see Note A)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÈÈÈÈ ÈÈ
ÈÈÈÈ
16th Falling Edge
tsu(DS)
th(DH)
D15
D14
D13
D12
ÈÈÈÈÈÈ
D11
D0
DAC Data
Bits (12)
Program Bits (4)
DAC A/B
OUT
ts
≤ Final Value ±0.5 LSB
Internal
Latch
Control
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
Figure 2. Timing Diagram for TLC5618A Only
8
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT (FAST MODE)
vs
OUTPUT LOAD VOLTAGE
OUTPUT SOURCE CURRENT (FAST MODE)
vs
OUTPUT LOAD VOLTAGE
–60
40
VDD = 5 V,
Input Code = 4095
35
Output Source Current – mA
Output Sink Current – mA
–50
30
25
20
15
10
5
–5
–30
–20
–10
VDD = 5 V,
Input Code = 0
0
–40
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
0.5
1
Figure 3
2
2.5
3
3.5
4
4.5
Figure 4
OUTPUT SINK CURRENT (SLOW MODE)
vs
OUTPUT LOAD VOLTAGE
OUTPUT SOURCE CURRENT (SLOW MODE)
vs
OUTPUT LOAD VOLTAGE
25
–30
20
–25
Output Source Current – mA
Output Sink Current – mA
1.5
Output Load Voltage – V
Output Load Voltage – V
15
10
5
0
–20
–15
–10
–5
VDD = 5 V,
Input Code = 0
–0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VDD = 5 V,
Input Code = 4095
0
0
0.5
Output Load Voltage – V
1
1.5
2
2.5
3
3.5
4
4.5
Output Load Voltage – V
Figure 5
Figure 6
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9
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
RELATIVE GAIN (FAST MODE)
vs
FREQUENCY
5
1.6
Fast Mode
1.4
0
–5
Relative Gain – dB
Supply Current – mA
1.2
1
0.8
Slow Mode
0.6
–10
–15
–20
0.4
VDD = 5 V,
VREFIN = 2.048 V,
TA = 25°C
0.2
0
– 60 – 40 – 20
0
VCC = 5 V,
VREFIN = 0.2 VPP + 2.048 Vdc,
TA = 25°C
–25
20 40 60 80
Temperature – °C
–30
100
100 120 140
Figure 7
TOTAL HARMONIC DISTORTION (SLOW MODE)
vs
FREQUENCY
5
95
THD – Total Harmonic Distortion – dB
0
Relative Gain – dB
–5
–10
–15
–20
–25
–30
VCC = 5 V,
VREFIN = 0.2 VPP +2.048 Vdc,
TA = 25°C
–40
100
90
85
80
75
70
65
10 K
1000
1
f – Frequency – kHz
10
f – Frequency – kHz
Figure 9
10
10 K
Figure 8
RELATIVE GAIN (SLOW MODE)
vs
FREQUENCY
–35
1000
f – Frequency – kHz
Figure 10
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100
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
85
85
80
75
70
65
60
1
75
70
1
10
f – Frequency– kHz
f – Frequency– kHz
Figure 11
Figure 12
90
85
80
75
100
10
85
80
75
70
65
1
10
f – Frequency – kHz
f – Frequency – kHz
Figure 13
Figure 14
POST OFFICE BOX 655303
100
TOTAL HARMONIC DISTORTION + NOISE (FAST MODE)
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – dB
95
1
80
65
100
10
TOTAL HARMONIC DISTORTION (FAST MODE)
vs
FREQUENCY
THD – Total Harmonic Distortion – dB
SIGNAL-TO-NOISE RATIO (SLOW MODE)
vs
FREQUENCY
SNR – Signal-To-Noise Ratio – dB
THD+N – Total Harmonic Distortion + Noise – dB
TOTAL HARMONIC DISTORTION + NOISE (SLOW MODE)
vs
FREQUENCY
• DALLAS, TEXAS 75265
100
11
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO (FAST MODE)
vs
FREQUENCY
SNR – Signal-To-Noise Ratio – dB
85
80
75
70
65
1
10
f – Frequency – kHz
Figure 15
12
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100
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
DNL – Differential Nonlinearity – LSB
TYPICAL CHARACTERISTICS
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
500
1000
1500
2000
2500
3000
3500
4095
3500
4095
Samples
INL – Integral Nonlinearity – LSB
Figure 16. Differential Nonlinearity With Input Code
1
0.5
0
–0.5
–1
–1.5
–2
–2.5
–3.0
0
500
1000
1500
2000
2500
3000
Samples
Figure 17. Integral Nonlinearity With Input Code
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
general function
The TLC5618 uses a resistor string network buffered with an op amp to convert 12-bit digital data to analog
voltage levels (see functional block diagram and Figure 18). The output is the same polarity as the reference
input (see Table 1).
ǒ
Ǔ
The output code is given by: 2 V REFIN CODE
4096
An internal circuit resets the DAC register to all 0s on power up.
+
_
REFIN
Resistor
String
DAC
DIN
CS
×2
+
_
OUT
R
SCLK
R
AGND
VDD
5V
0.1 µF
Figure 18. TLC5618 Typical Circuit
Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2
INPUT
1111
1111
1111
:
1000
0000
0001
1000
0000
0000
0111
1111
1111
:
14
0000
0000
0001
0000
0000
0000
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ǒ
ǒ
2 V
ǒ
Ǔ
Ǔ
OUTPUT
4095
REFIN 4096
2 V
Ǔ
:
2049
REFIN 4096
2048
2 V
V
REFIN 4096
REFIN
ǒ
2 V
ǒ
Ǔ
+
2047
REFIN 4096
2 V
Ǔ
:
1
REFIN 4096
0V
• DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs, typical to within ± 0.5 LSB of final value.
external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
f(SCLK)max
+t
1
+ 20 MHz
)
t ǒ Ǔ
wǒCHǓmin
w CL min
ǒ ǒ Ǔ ǒ ǓǓ
The digital update rate is limited by the chip-select period, which is:
tp(CS)
+ 16
t
w CH
) tw CL ) tsuǒCS1Ǔ
This equals an 810-ns or 1.23-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in, most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked
into the input register.
The 16 bits of data can be transferred with the sequence shown in Figure 19.
16 Bits
Program Bits
D15
D14
MSB (Input Word)
D13
Data Bits
D12
D11
12 Data Bits
MSB (Data)
D0
LSB (Data, Input Word)
Figure 19. Input Data Word Format
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Table 2 shows the function of program bits D15 – D12.
Table 2. Program Bits D15 – D12 Function
PROGRAM BITS
DEVICE FUNCTION
D15
D14
D13
D12
1
X
X
X
Write to latch A with serial interface register data
and latch B updated with buffer latch data
0
X
X
0
Write to latch B and double buffer latch
0
X
X
1
Write to double buffer latch only
X
0
X
X
12.5 µs settling time
X
1
X
X
2.5 µs settling time
X
X
0
X
Powered-up operation
X
X
1
X
Power down mode
function of the latch control bits (D15 and D12)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.
latch A write, latch B update (D15 = high, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output
updates of both DACs.
Serial
Interface
Register
D12 = X
D15 = High
Double
Buffer Latch
Latch A
To DAC A
Latch B
To DAC B
Figure 20. Latch A Write, Latch B Update
latch B and double-buffer 1 write (D15 = low, D12 = low)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
Serial
Interface
Register
D12 = Low
D15 = Low
Double
Buffer Latch
Latch A
To DAC A
Latch B
To DAC B
Figure 21. Latch B and Double-Buffer Write
16
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
double-buffer-only write (D15 = low, D12 = high)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
Serial
Interface
Register
Double
Buffer
D12 = High
D15 = Low
Latch A
To DAC A
Latch B
To DAC B
Figure 22. Double-Buffer-Only Write
purpose and use of the double buffer
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change
after a single write. This is achieved by the two following steps.
1. A double-buffer-only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2. Following the previous step, a write to latch A is executed. This writes the SIR data to latch A and also
writes the double-buffer contents to latch B. Thus both DACs receive their new data at the same time,
and so both DAC outputs begin to change at the same time.
Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.
operational examples
changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right)
1X0X 1111 1111 1111
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other X can be
zero or one (don’t care).
The latch B contents and the DAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.
changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right).
0X00 1111 1111 1111
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data (bits D0
to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
double-buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g., after power-up), if DAC A is to be driven to mid-scale and
DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
First,
0d01 1111 1111 1111
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double
buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the
DAC A output are also unaffected by this write operation.
Changing from fast to slow or slow to fast mode changes the supply current which can glitch the outputs, and
so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous
write.
Next,
1X0X 1000 0000 0000
is written (bit D15 on the left, D0 on the right) to the serial interface. Bit D14 can be zero to select slow mode
or one to select fast mode. The other X can be zero or one (don’t care). This writes the mid-scale code
(100000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC
outputs thus begin to rise after the second write.
DSP serial interface
Utilizing a simple 3-wire serial interface shown in Figure 23, the TLC5618A can be interfaced to TMS320
compatible serial ports. The 5618A has an internal state machine that will count 16 clocks after receiving a falling
edge of CS and then disable further clocking in of data until the next falling edge is received on CS. Therefore
CS can be connected directly to the FS pins of the serial port and only the leading falling edge of the DSP will
be used to start the write process. The TLC5618A is designed to be used with the TMS320Cxx DSP in burst
mode serial port transmit operation.
18
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
VCC
FSR
FSX
CS
Analog
Output
OUT A
TLC5618A
Analog
Output
OUT B
CLKX
SCLK
TMS320C203
DSP
CLKR
DX
DIN
REFIN
2.5 V dc
GND
To Source
Ground
Figure 23. Interfacing The TLC5618A to the TMS320C203 DSP
general serial interface
Both the TLC5618 and TLC5618A are compatible with SPI, QSPI, or Microwire serial standards. The hardware
connections are shown in Figures 24 and 25. The TLC5618A has an internal state machine that will count 16
clocks after the falling edge of CS and then internally disable the device. The internal edge is ORed together
with CS so that the rising edge can be provided to CS prior to the occurrence of the internal edge to also disable
the device.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.
SCLK
DIN
TLC5618,
TLC5618A
CS
SK
SO Microwire
Port
I/O
Figure 24. Microwire Connection
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
SCK
SCLK
MOSI
DIN
TLC5618,
TLC5618A
I/O
CS
SPI/QSPI
Port
CPOL = 1, CPHA = 0
Figure 25. SPI/QSPI Connection
linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 26.
Output
Voltage
0V
DAC Code
Negative
Offset
Figure 26. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.
20
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well-managed.
A 0.1-µF ceramic bypass capacitor should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figure 27 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
8
2
7
3
6
4
5
0.1 µF
Figure 27. Power-Supply Bypassing
saving power
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINALS SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.740
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / C 11/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold-plated.
Falls within JEDEC MS-004
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MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
MECHANICAL DATA
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
24
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
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25
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