TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 D D D D D D D D D D D 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5-V Single Supply Operation 3-Wire Serial Interface High-Impedance Reference Inputs Voltage Output Range . . . 2 Times the Reference Input Voltage Internal Power-On Reset Low Power Consumption . . . 1.75 mW Max Update Rate of 1.21 MHz Settling Time to 0.5 LSB . . . 12.5 µs Typ Monotonic Over Temperature Pin Compatible With the Maxim MAX515 applications D D D D D Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones D, P, OR DGK PACKAGE (TOP VIEW) DIN SCLK CS DOUT 1 8 2 7 3 6 4 5 VDD OUT REFIN AGND description The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards. The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE† (D) 0°C to 70°C TLC5615CD PLASTIC SMALL OUTLINE (DGK) TLC5615CDGK – 40°C to 85°C TLC5615ID TLC5615IDGK † Available in tape and reel as the TLC5615CDR and the TLC5615IDR PLASTIC DIP (P) TLC5615CP TLC5615IP Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 functional block diagram _ + _ 2 DAC + REFIN OUT (Voltage Output) AGND Power-ON Reset R R 10-Bit DAC Register Control Logic CS 2 0s SCLK (LSB) (MSB) 10 Data Bits DIN 4 Dummy Bits 16-Bit Shift Register DOUT Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DIN 1 I Serial data input SCLK 2 I Serial clock input CS 3 I Chip select, active low DOUT 4 O Serial data output for daisy chaining AGND 5 REFIN 6 I Reference input OUT 7 O DAC analog voltage output VDD 8 Analog ground Positive power supply absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Reference input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage at OUT from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Continuous current at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating free-air temperature range, TA: TLC5615C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC5615I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 recommended operating conditions MIN NOM MAX Supply voltage, VDD 4.5 5 5.5 High-level digital input voltage, VIH 2.4 2 Load resistance, RL 0.8 V 2.048 VDD – 2 V 2 Operating free-air free air temperature, temperature TA kΩ 0 70 °C – 40 85 °C TLC5615C TLC5615I V V Low-level digital input voltage, VIL Reference voltage, Vref to REFIN terminal UNIT electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) static DAC specifications PARAMETER TEST CONDITIONS Resolution Differential nonlinearity (DNL) Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient EG Gain error Gain-error temperature coefficient Vref = 2.048 V, Vref = 2.048 V, See Note 1 MAX Vref = 2.048 V, Vref = 2.048 V, See Note 3 Vref = 2.048 V, Vref = 2.048 V, See Note 5 Power supply rejection ratio Power-supply Analog full scale output Gain UNIT bits ± 0.1 See Note 2 See Note 4 ±1 LSB ± 0.5 LSB ±3 LSB 3 ppm/°C ±3 See Note 6 Zero scale PSRR TYP 10 Integral nonlinearity, end point adjusted (INL) EZS MIN 1 LSB ppm/°C 80 See Notes 7 and 8 dB 80 RL = 100 kΩ 2Vref(1023/1024) V NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). 2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text). 4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). 5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scale error. 6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change. voltage output (OUT) PARAMETER VO TEST CONDITIONS Voltage output range RL = 10 kΩ Output load regulation accuracy VO(OUT) = 2 V, RL = 2 kΩ OUT to VDD or AGND IOSC Output short circuit current VOL(low) VOH(high) Output voltage, low-level Output voltage, high-level IO(OUT) ≤ 5 mA IO(OUT) ≤ –5 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP 0 MAX UNIT VDD–0.4 0.5 LSB 20 mA 0.25 4.75 V V V 3 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) (continued) reference input (REFIN) PARAMETER VI ri Input voltage Ci Input capacitance TEST CONDITIONS MIN TYP MAX 0 Input resistance VDD– 2 10 UNIT V MΩ 5 pF digital inputs (DIN, SCLK, CS) PARAMETER VIH VIL High-level digital input voltage IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS MIN TYP MAX 2.4 V Low-level digital input voltage VI = VDD VI = 0 Low-level digital input current UNIT 0.8 V ±1 µA ±1 µA 8 pF digital output (DOUT) PARAMETER VOH VOL TEST CONDITIONS Output voltage, high-level IO = –2 mA IO = 2 mA Output voltage, low-level MIN TYP MAX VDD–1 UNIT V 0.4 V power supply PARAMETER VDD IDD TEST CONDITIONS Supply voltage Power supply current MIN TYP MAX 4.5 5 5.5 V UNIT VDD = 5.5 V, No load, All inputs = 0 V or VDD Vref = 0 150 250 µA VDD = 5.5 V, No load, All inputs = 0 V or VDD Vref = 2.048 V 230 350 µA MAX UNIT analog output dynamic performance PARAMETER Signal-to-noise + distortion, S/(N+D) TEST CONDITIONS Vref = 1 Vpp at 1 kHz + 2.048 Vdc, code = 11 1111 1111, See Note 9 NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 60 TYP dB TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 digital input timing requirements (see Figure 1) PARAMETER tsu(DS) th(DH) Setup time, DIN before SCLK high tsu(CSS) tsu(CS1) th(CSH0) th(CSH1) Hold time, SCLK low to CS low Hold time, SCLK low to CS high tw(CS) tw(CL) tw(CH) MIN NOM MAX UNIT 45 ns Hold time, DIN valid after SCLK high 0 ns Setup time, CS low to SCLK high 1 ns Setup time, CS high to SCLK high 50 ns 1 ns 0 ns Pulse duration, minimum chip select pulse width high 20 ns Pulse duration, SCLK low 25 ns Pulse duration, SCLK high 25 ns output switching characteristic PARAMETER tpd(DOUT) TEST CONDITIONS Propagation delay time, DOUT MIN NOM CL = 50 pF MAX 50 UNIT ns operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP 0.3 0.5 V/µs 12.5 µs SR Output slew rate CL = 100 pF, TA = 25°C RL = 10 kΩ, ts Output settling time To 0.5 LSB, RL = 10 kΩ, CL = 100 pF, See Note 10 Glitch energy DIN = All 0s to all 1s MAX UNIT nVs 5 NOTE 10: Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. reference input (REFIN) PARAMETER TEST CONDITIONS Reference feedthrough REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11) Reference input bandwidth (f–3dB) REFIN = 0.2 Vpp + 2.048 Vdc REFIN = 0.2 Vpp + 2.048 Vdc MIN TYP MAX UNIT – 80 dB 30 kHz NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048 Vdc + 1 Vpp at 1 kHz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION CS th(CSH0) SCLK ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu(CSS) tw(CS) tw(CH) tw(CL) See Note A tsu(DS) DIN See Note C th(DH) tpd(DOUT) DOUT ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ th(CSH1) Previous LSB MSB tsu(CS1) See Note A LSB See Note B NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE 20 IO – Output Sink Current – mA 18 16 VDD = 5 V VREFIN = 2.048 V TA = 25°C 14 12 10 8 6 4 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1 VO – Output Pulldown Voltage – V Figure 2 OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE IO– Output Source Current – mA 30 VDD = 5 V VREFIN = 2.048 V TA = 25°C 25 20 15 10 5 0 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 VO – Output Pullup Voltage – V 3.2 3 Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE 280 I DD – Supply Current – µ A 240 200 160 120 80 40 VDD = 5 V VREFIN = 2.048 V TA = 25°C 0 – 60 – 40 – 20 0 20 40 60 80 t – Temperature – °C 100 120 140 Figure 4 VREFIN TO V(OUT) RELATIVE GAIN vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN 4 70 2 Signal-To-Noise + Distortion – dB VDD = 5 V VREFIN = 0.2 VPP + 2.048 V dc TA = 25°C G – Relative Gain – dB 0 –2 –4 –6 –8 – 10 50 40 30 20 10 – 12 – 14 1 100 1k 10 k 100 k 0 1k fI – Input Frequency – Hz 10 k Figure 6 POST OFFICE BOX 655303 100 k Frequency – Hz Figure 5 8 VDD = 5 V TA = 25°C VREFIN = 4 VPP 60 • DALLAS, TEXAS 75265 300 k TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0 255 511 767 1023 Input Code Figure 7. Differential Nonlinearity With Input Code Integral Nonlinearity – LSB 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 255 511 767 1023 Input Code Figure 8. Integral Nonlinearity With Input Code POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 APPLICATION INFORMATION general function The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up. DIN + _ REFIN SCLK CS Resistor String DAC DOUT + _ OUT R R AGND VDD 5V 0.1 µF Figure 9. TLC5615 Typical Operating Circuit Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2 INPUT† 1111 1111 ǒ ǒ OUTPUT Ǔ Ǔ 1023 REFIN 1024 11(00) 2 V 513 2 V REFIN 1024 : 1000 0000 01(00) 1000 0000 00(00) 0111 1111 11(00) : 0000 0000 01(00) 0000 0000 00(00) ǒ 2 V Ǔ : 512 REFIN 1024 ǒ 2 V ǒ Ǔ + VREFIN 511 REFIN 1024 2 V Ǔ : 1 REFIN 1024 0V † A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 APPLICATION INFORMATION buffer amplifier The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF load capacitance. Settling time is 12.5 µs typical to within 0.5 LSB of final value. external reference The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF independent of input code. The reference voltage determines the DAC full-scale output. logic interface The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels. serial clock and update rate Figure 1 shows the TLC5615 timing. The maximum serial clock rate is: f(SCLK)max +t ) twǒCLǓ wǒCHǓ 1 ǒ ǒ Ǔ ǒ ǓǓ or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is: tp(CS) + 16 t w CH ) tw CL ) twǒCSǓ and is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 µs limits the update rate to 80 kHz for full-scale input step transitions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 APPLICATION INFORMATION serial interface When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SLCK input shifts the data into the input register. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked into the input register. All CS transitions should occur when the SCLK input is low. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequence with the MSB first can be used as shown in Figure 10: 12 Bits 10 Data Bits x MSB LSB x 2 Extra (Sub-LSB) Bits x = don’t care Figure 10. 12-Bit Input Data Sequence or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first. 16 Bits 4 Upper Dummy Bits 10 Data Bits MSB x LSB x 2 Extra (Sub-LSB) Bits x = don’t care Figure 11. 16-Bit Input Data Sequence The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1). The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data converter transfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI†, and Microwire serial standards. The hardware connections are shown in Figure 12 and Figure 13. The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC input register in one write cycle. † CPOL = 0, CPHA = 0, QSPI protocol designations 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 APPLICATION INFORMATION serial interface (continued) SCLK DIN TLC5615 CS DOUT SCLK SK SO Microwire Port DIN TLC5615 CS I/O DOUT SI NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired. SCK MOSI I/O SPI/QSPI Port MISO CPOL = 0, CPHA = 0 NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer. Figure 12. Microwire Connection Figure 13. SPI/QSPI Connection daisy-chaining devices DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, tsu(CSS), (CS low to SCLK high) is greater than the sum of the setup time, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT remains at the value of the last data bit and does not go into a high-impedance state. linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (Single Supply) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies (continued) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. For the TLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the maximum specification for the negative offset. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 15 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 15. Power-Supply Bypassing saving power Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output load when the system is not using the DAC. ac considerations digital feedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT. analog feedthrough Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to REFIN, and monitoring the DAC output. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 MECHANICAL DATA DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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