SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1A 2Y GND 1 8 2 7 3 6 4 5 VCC 2OE 1Y 2A YEP OR YZP PACKAGE (BOTTOM VIEW) GND 2Y 1A 1OE 4 5 3 6 2 7 1 8 2A 1Y 2OE VCC DESCRIPTION/ORDERING INFORMATION This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP Tape and reel SN74AUC2G125YEPR NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Tape and reel SN74AUC2G125YZPR SSOP – DCT Tape and reel SN74AUC2G125DCTR U25_ _ _ VSSOP – DCU Tape and reel SN74AUC2G125DCUR UM_ _ _ _UM_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1 1OE 1A 2 6 1Y 7 2OE 5 2A 2 3 2Y SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCES532A – DECEMBER 2003 – REVISED MARCH 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.6 V –0.5 3.6 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg (1) (2) (3) DCT package 220 DCU package 227 YEP/YZP package 102 Storage temperature range –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 VCC = 1.1 V to 1.95 V 0.65 × VCC 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current 0 3.6 Active state 0 VCC 3-state 0 3.6 VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 0.8 V to 1.65 TA (1) (2) (3) Input transition rise or fall rate Operating free-air temperature V 0.7 VCC = 2.3 V ∆t/∆v V 1.7 VCC = 0.8 V Low-level input voltage V VCC VCC = 2.3 V to 2.7 V VIL UNIT V V mA mA 9 V (2) 20 VCC = 1.65 V to 1.95 V (3) 20 VCC = 2.3 V to 2.7 V (3) 15 –40 85 ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1). The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1). 3 SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC TYP (1) MIN MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA IOZ VO = VCC or GND 2.7 V ±10 µA ICC VI = VCC or GND, 10 µA Ci VI = VCC or GND 2.5 V 2.5 pF Co VO = VCC or GND 2.5 V 5.5 pF II (1) A or OE inputs IO = 0 0.8 V to 2.7 V All typical values are at TA = 25°C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX tpd A Y 5.1 1 3.6 0.7 2.3 0.6 1 1.8 0.5 1.3 ns ten OE Y 5.9 1.1 4.1 1 2.6 0.9 1.3 2 0.8 1.5 ns tdis OE Y 6.6 2 4.8 1.5 3.5 1.8 2.6 3.7 1.4 2.9 ns PARAMETER UNIT Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A ten OE tdis OE PARAMETER 4 VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V UNIT MIN TYP MAX MIN MAX Y 0.8 1.6 2.6 0.7 1.8 ns Y 1.1 1.7 2.9 0.9 2.2 ns Y 1.7 2.3 3.6 0.8 2 ns SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 16 16 16 17 18 UNIT pF 5 SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 VCC/2 Data Input 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VCC/2 VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AUC2G125DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G125DCTR ACTIVE SM8 DCT 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G125DCUR ACTIVE US8 DCU 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G125YEPR ACTIVE WCSP YEP 8 3000 TBD SNPB Level-1-260C-UNLIM SN74AUC2G125YZPR ACTIVE WCSP YZP 8 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. 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