TI SN74BCT2420FN

SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
•
•
•
•
•
•
Designed for NuBus Interface
Applications
Conforms to ANSI/IEEE Std 1196-1987
On-Chip Comparator Provides I/D Slot
Identification
AEN
ACLK
Multiplexed Real-Time and Latched
ID3
Address/Data
SSEQ
Designed to Operate With SN74ACT2440
AD7
NuBus Controller
AD6
AD5
BiCMOS Design Substantially Reduces
AD4
Standby Current
GND
Dependable Texas instruments Quality and
AD3
Reliability
AD2
and data information in NuBus applications. An
on-chip comparator has been included to detect
when a NuBus transfer cycle is requesting the
local board. The device conforms to ANSI/IEEE
Std 1196-1987 and operates with Texas instruments SN74ACT2440 NuBus Controller. In
addition, the device is easily configured around
ASIC or other PAL -based controllers.
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 3536 37 38 39 40 41 42
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
ID0
ALE
IDEQ
VCC
AD15
AD14
AD13
AD12
GND
AD11
AD10
AD9
AD8
ID1
ADEN
DCLK
ID2
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
AD1
AD0
VCC
The ’BCT2420 consists of bus transceiver circuits, A/D
D-type flip-flops, latches, and control circuitry DLE
arranged for multiplexed transmission of address DEN
description
FN PACKAGE
(TOP VIEW)
A0
A1
A2
A3
A4
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
A14
A15
•
The ’BCT2420 was designed using Texas Instruments BiCMOS process, which features bipolar drive
characteristics and greatly reduces the standby power of the device when disabled. This feature is especially
valuable when the device is not performing a NuBus transaction.
The AEN, DEN and ADEN inputs control the transceiver functions. Three 16-bit I/O ports, A15–A0, D15–D0,
and AD15–AD0, provide for address and data transfer. When the NuBus performs a write cycle to the local
board, address information is saved on the rising edge of ACLK. During the last portion of the NuBus write
cycle, data information is saved on the rising edge of DCLK.
When the local board is performing a write to the NuBus, address and data is multiplexed onto the NuBus
via the A/D line. Address and data can be latched by using the ALE and DLE input lines respectively.
The IDEQ output is used to signal that the local board is being requested by the NuBus. This output is typically
fed to the NuBus controller. IDEQ goes active (low) when AD15–AD12 are low and AD11–AD8 match ID3–ID0.
IDEQ stays valid until the next address clock (ACLK) occurs. Internal 10-kΩ pullup resistors are included on the
ID3–ID0 inputs.
The SSEQ output is used to signal the local board that super-slot addresses are being requested. This output
is active (low) whenever AD15–AD12 are equal to ID3–AD0, except when ID3–ID0 are all low.
In typical NuBus applications, two devices are required to provide the full 32-bit address/data path. Refer to
the typical NuBus interface diagram on page 9 for additional information.
The SN74BCT2420 is characterized for operation from 0°C to 70°C.
NuBus is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
Copyright  1989, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
Function Tables
INPUTS
OUTPUTS
A15–A0
D15–D0
ALE
DLE
A/D
ADEN
H
X
L
X
L
L
L
L
X
L
X
L
L
H
X
X
H
X
L
L
QO
X
H
X
L
H
L
L
X
L
X
L
H
L
H
X
X
X
H
H
L
QO
X
X
X
X
X
H
Z
INPUTS
AD15–AD0
OUTPUTS
AD15–AD0
ACLK, DCLK
AEN, DEN
A15–A0, D15–DO
H
↑
L
L
L
↑
L
H
X
L
L
QO
X
X
H
L
AD15–AD12
ID3–ID0
SSEQ
EQ ID3–ID0
NE ID3–ID0
X
NE 0
X
EQ 0
L
H
H
AD15–AD12
EQ 0
X
NE 0
AD11–AD8
IDEQ
EQ ID3–ID0
NE ID3–ID0
X
L
H
H
NOTE: Symbol ‘QO’ denotes previous logic state preserved. Symbol ‘Z’ denotes high-impedance state.
2
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
logic symbol†
ID0
60
47
ID1
44
ID2
12
ID3
AEN
A0
10
9
8
A1
7
A2
6
A3
5
A4
4
A5
3
A6
2
A7
68
A8
67
A9
66
A10
65
A11
64
A12
63
A13
62
A14
61
A15
ACLK
DEN
D0
27
28
D1
29
D2
30
D3
31
D4
32
D5
33
D6
34
D7
36
D8
37
D9
38
D10
39
D11
40
D12
41
D13
42
D14
43
D15
DCLK
45
59
ALE
25
DLE
24
A/D
ADEN
0
46
SSEQ
ID
IDEQ
13
58
SSEQ
IDEQ
3
AEN
0
ADDR
0
22
AD0
21
15
11
26
φ
ADDR/DATA XCVR/REG
SN74BCT2420
ACLK
ADDR/DATA
DEN
0
15
AD1
20
AD2
19
AD3
17
AD4
16
AD5
15
AD6
14
AD7
48
AD8
49
AD9
50
AD10
51
AD11
53
AD12
54
AD13
55
AD14
56
AD15
DATA
15
DCLK
ALE
DLE
ADDR
DATA
ADEN
† This symbol is in accordance with ANSI/IEEE Std. 91-1984.
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3
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
logic diagram
ID3–ID0
4
4
SSEQ
4
4x
4
4
A’11-A’8
IDEQ
4x
4
A’15-A’12
ACLK
C1
AEN
A15–A12
A11–A8
4
4
4x
4
4
4x
8
8
8x
4
AD15–AD12
1D
4
AD11–AD8
1D
8
AD7–AD0
1D
A7–A0
16
DCLK
D15–D0
C1
16
16
16
16 x
1D
DEN
16
ALE
MUX
C1
16 x
16
1D
DLE
C1
16 x
1D
A/D
16
1
16
1
G1
ADEN
4
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
Terminal Functions
PIN NAME
DESCRIPTION
A15–A0
Address bus. This 16-bit I/O port is connected to the local board’s address bus. When information is transferred between this
port and the NuBus port (AD15–AD0), the data is inverted to conform to NuBus specifications.
ACLK
Address clock. This input saves the address portion of NuBus read or write cycles. Data present at the AD15–AD0 inputs
is clocked into the address register on the low-to-high transition of ACLK.
A/D
Address/data select. This input controls the address/data multiplexer. When A/D is driven low, the local address port, A15–A0,
is selected as input to the AD15–AD0 outputs. When A/D is taken high, the local data port, D15–D0, is selected as input to the
AD15–AD0 outputs.
AD15–AD0
Address/data port. This 16-bit active-low I/O port directly interfaces to the NuBus address/data lines. These lines are
multiplexed to carry address information at the beginning of a NuBus cycle and data information later in the cycle.
ADEN
Address/data output enable. This active-low input enables the AD15–AD0 outputs. When ADEN is taken high, the AD15–AD0
outputs are in the high impedance state, allowing input from the NuBus .
AEN
Address enable. This active-low input enables the local address outputs. A15–A0, to place data onto the local board. When
AEN is taken high, the A15–A0 outputs are in the high-impedance state, allowing input from the local address bus.
ALE
Address latch enable. This active-low input controls the latch that holds the address received from the local address bus,
A15–A0. When ALE is low, the latch is transparent. When ALE is taken high, the address present at the A15–A0 inputs is latched
and remains latched while ALE is held high.
D15–D0
Data bus. This 16-bit I/O port is connected to the local board’s data bus. When information is transferred between this port and
the NuBus port (AD15–AD0), the data is inverted to conform to NuBus specifications.
t
t
t
t
t
t
t
t
t write cycles. Data present at the AD15–AD0 inputs is clocked into
DCLK
Data clock. This input saves the data portion of NuBus
the data register on the low-to-high transition of DCLK.
DEN
Data enable. This active-low input enables the local data port outputs, D15–D0, to place data onto the local board. When DEN
is taken high, the D15–D0 outputs are in the high-impedance state, allowing input from the local board.
DLE
Data latch enable. This active-low input controls the latch that holds the data received from the local data bus, D15–D0. When
DLE is low, the latch is transparent. When DLE is taken high, the data present at the D15–D0 inputs is latched and remains
latched while DLE is held high.
ID3–ID0
Card-slot identification. These four inputs accept binary-coded location information for each NuBus slot position on the
backplane. These four lines are typically hard wired logic levels unique to each NuBus slot connector. For convenient
implementation, the inputs have internal 10-kΩ pull up resistors that ensure the logic high level when the inputs are left open
circuited. The internal comparator uses these inputs to identify when the local hardware card is being accessed.
IDEQ
Identification equal. This active-low output is used to signal that the board is being accessed by the NuBus . IDEQ goes low
whenever AD15–AD12 are low and AD11–AD8 match ID3–ID0. Since the internal comparator uses data from the address
register, the address register must be clocked before the local board samples IDEQ. IDEQ is valid for the entire NuBus cycle
after ACLK.
t
t
t
t
SSEQ
Super-slot equal. This active-low output is used to signal the local board that super-slot addresses are being requested in the
super-slot mode. SSEQ goes low when AD15–AD12 match ID3–ID0 and ID3–ID0 are not all low. Since the internal comparator
uses data from the address register, the address register must be clocked before the local board samples SSEQ. SSEQ is valid
for the entire NuBus cycle after ACLK.
t
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (all inputs and I/O ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
PARAMETER
VCC
VIH
Supply voltage
VIL
Low-level input voltage
High-level input voltage
IOH
High level input current
High-level
IOL
Low level input current
Low-level
fclock
Clock frequency
tw
tsu
th
TA
6
Pulse duration
Setup time
Hold time
MIN
NOM
MAX
4.5
5
5.5
2
0.8
– 15
SSEQ, IDEQ outputs
2.6
Ax, Dx, ADx outputs
24
SSEQ, IDEQ outputs
16
0
12.5
ACLK, DCLK low
12.5
ALE, DLE low
12.5
ADx before ACLK↑, DCLK↑
5
Ax before ALE↑
5
Dx before DLE↑
5
ADx after ACLK↑, DCLK↑
2
Ax after ALE↑
2
Dx after DLE↑
2
Operating free-air temperature
0
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V
V
Ax, Dx, ADx outputs
ACLK, DCLK high
UNIT
40
V
mA
mA
MHz
ns
ns
ns
70°
°C
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
TEST CONDITIONS
MIN
TYP†
IOH = – 3 mA
IOH = – 15 mA
SSEQ IDEQ
SSEQ,
VCC = 4.5 V to 5.5 V,
VCC = 4.5 V,
IOH = – 400 µA
IOH = – 2.6 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOL = 12 mA
IOL = 24 mA
0.25
0.4
Ax Dx,
Ax,
Dx ADx
0.35
0.5
IOL = 8 mA
IOL = 16 mA
0.25
0.4
SSEQ IDEQ
SSEQ,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VI = 5.5 V
100
VCC = 5.5 V,
VI = 2.7 V
– 400
VOL
II
VCC – 1.5
2.8
3.6
V
2
VCC – 2
2.4
3.2
0.35
ID3–ID0
All other inputs
ID3–ID0
All other inputs
IOS§
Enabled
Disabled
V
0.5
µA
20
AEN, DEN, ADEN
ICC
V
VCC = 4.5 V,
VCC = 4.5 V,
VOH
IIL‡
UNIT
– 1.2
II = – 18 mA
IOH = – 400 µA
Ax, Dx, ADx
IIH‡
MAX
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
µA
– 100
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
VCC = 5.5 V,
VO = 0 V
VCC = 5.5 V,,
VIH = 3 V,
VIL = 0.5 V,,
Outputs open
– 750
– 200
– 60
– 225
110
160
30
40
µA
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
LOAD CONDITIONS
PARAMETER
fmax
R1, R2, and RL
CL
LOAD CIRCUIT
Maximum clock frequency
MIN
TYP†
MAX
40
UNIT
MHz
tpd
d
Propagation time
time, ACLK↑ to Ax (AEN = L)
R1 = 500 Ω,
R2 = 500 Ω
tpd
d
Propagation time
time, DCLK↑ to Dx (DEN = L)
R1 = 500 Ω,
R2 = 500 Ω
50 pF
S1 Open‡
9
16
ns
tpd
d
time Ax to ADx ( ALE = L,
L A/D = L)
Propagation time,
R1 = 270 Ω,
R2 = 470 Ω
300 pF
S1 Closed§
10
18
ns
tpd
d
Propagation time
time, Dx to ADx ( DLE = L,
L A/D = H)
R1 = 270 Ω,
R2 = 470 Ω
300 pF
S1 Closed§
11
18
ns
tpd
d
Propagation time,
time ALE low to ADx (A/D = L)
R1 = 270 Ω,
R2 = 470 Ω
300 pF
S1 Closed§
10
18
ns
tpd
d
Propagation time,
time DLE low to ADx (A/D = H)
R1 = 270 Ω,
R2 = 470 Ω
300 pF
S1 Closed§
11
18
ns
tpd
d
Propagation time,
time A/D to ADx
R1 = 270 Ω,
R2 = 470 Ω
300 pF
S1 Closed§
10
16
ns
tpd
tpd
Propagation time, ACLK to IDEQ
RL = 500 Ω
50 pF
¶
12
20
ns
Propagation time, ACLK to SSEQ
RL = 500 Ω
50 pF
¶
12
18
ns
tpd
tpd
Propagation time, IDx to IDEQ
RL = 500 Ω
50 pF
¶
12
22
ns
Propagation time, IDx to SSEQ
RL = 500 Ω
50 pF
¶
12
22
ns
ten
Enable time,
time AEN to Ax
R1 = 500 Ω,
R2 = 500 Ω
50 pF
‡
10
16
ns
ten
Enable time
time, DEN to Dx
R1 = 500 Ω,
R2 = 500 Ω
50 pF
‡
10
16
ns
ten
Enable time,
time ADEN to ADx
R1 = 270 Ω,
R2 = 470 Ω
300 pF
§
10
18
ns
tdi
dis
Disable time
time, AEN to Ax
R1 = 500 Ω,
R2 = 500 Ω
50 pF
‡
6
10
ns
tdi
dis
Disable time
time, DEN to Dx
R1 = 500 Ω,
R2 = 500 Ω
50 pF
‡
6
10
ns
tdis
Disable time,
time ADEN to ADx
R1 = 270 Ω,
R2 = 470 Ω
50 pF
F
§
6
10
ns
50 pF
S1 Open‡
9
16
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ See Parameter Measurement Information for load circuit (3-state outputs, A15–A0, D15–D0) and voltage waveforms.
§See Parameter Measurement Information for load circuit (NuBus Interface, AD15–AD0) and voltage waveforms.
¶See Parameter Measurement Information for load circuit (bi-state totem-pole outputs, SSEQ, IDEQ) and voltage waveforms.
8
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL
CL
(See Note A)
VCC
S1
S1
R1
R1
From Output
Under Test
CL
(See Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
SSEQ, IDEQ
From Output
Under Test
Test
Point
R2
Test
Point
R2
CL
(See Note A)
LOAD CIRCUIT FOR
3–STATE OUTPUTS
A15–A0, D15–D0
LOAD CIRCUIT FOR
NuBus INTERFACE
AD15–AD0
3.5 V
3.5 V
Timing
Input
1.3 V
1.3 V
High-Level
Pulse
0.3 V
tsu
Data
Input
th
1.3 V
1.3 V
3.5 V
1.3 V
0.3 V
tw
tw
Low-Level
Pulse
1.3 V
3.5 V
1.3 V
0.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Input
1.3 V
tPLH
In-Phase
Output
1.3 V
tPHL
Out-of-Phase
Output
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOL
3.5 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
tPLZ
3.5 V
1.3 V
tPZH
tPHZ
1.3 V
VOL
0.3 V
VOH
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES,3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal condition such that the output is high except when disabled by the output control.
C. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%
D. The outputs are measured one at a time with one transition per measurement.
Figure 1
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SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
APPLICATION INFORMATION
DATA/ADDRESS
INTERFACE
SN74BCT2420
BOARD SPECIFIC
FUNCTION
A31/A0
32
16
32
16
2
D31/D0
NuBus
CONTROLLER
SN74ACT2440
B
Y
T
E
M
A
S
T
E
R
I
N
P
U
S T
L S
A
V
E
N
u
B
u
s
S
T
A
T
U
S
D
E
C
O
D
E
NREQ
MRDY
MLREQ
LACK
MHOLD
NMREQ
LOCTM0
LOCTM1
SGNTA
SIACK
NMSTR
NSTART
NACK
NLOCK
NLTM0
NLTM1
NCLK
NCLK
NLRST
MDONE
NTM0
NTM1
SEREQ
PFW
SP
ADEN
IDEQ
16
AEN
ACLK
16
DEN
DCLK
A/D
DATA/ADDRESS
INTERFACE
SN74BCT2420
IDEQ
A15/A0
AEN
ACLK
D15/D0
DEN
DCLK
ADEN
ALE
DLE
16
16
32
AD31–AD0
A/D
ADEN
4
4
ID3-0
ARB0-3
CLK
NMRQ
RESET
START
RQST
ACK
TM0
TM1
SPV
2
Figure 2. Typical Nubus Interface
10
ID3–ID0
A/D
AD/A1
BT0
BT1
BT2
BT3
IDEQ
A15/A0
AEN
ACLK
D15/D0
DEN
DCLK
ALE
DLE
NuBus
CARD-SLOT
SIGNALS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ID3-0
ARB0-3
CLK
NMRQ
RESET
START
RQST
ACK
TM0
TM1
SPV
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74BCT2420FN
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
SN74BCT2420FNR
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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