TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 D D D D D D D D D D D Single-Chip Token-Ring Solution IBM Token-Ring Network Compatible Compatible With ISO / IEC IEEE Std. 802.5:1992 Token-Ring Access-Method and Physical-Layer Specifications Compatible With TI380FPA FNL PacketBlaster Glueless Memory Interface Digital Phase-Locked Loop – Precise Control of Bandwidths – Improved Jitter Tolerance – Minimizes Accumulated Phase Slope Phantom Drive for Physical Insertion Onto Ring Differential Line Receiver With Level-Dependent Frequency Equalization Low-Impedance Differential Line Driver to Ease Transmit-Filter Design On-Chip Watchdog Timer Internal Crystal Oscillator for Reference-Clock Generation D D D D D D Expandable LAN-Subsystem Memory Up to 2 Mbytes 80x8x or 68xxx-Type Bus and Memory Organization Dual-Port DMA and Direct I/O Transfers to Host Bus Supports 8 - or 16-Bit Pseudo-DMA Operation 176-Pin Thin Quad Flat Package (PGF Suffix) 0.8 -µm CMOS Technology Operating Temperature Range 0°C to 70°C Token-Ring Features – 16- or 4-Mbps Data Rates – Supports up to 18-KByte Frame Size (16 Mbps Only) – Supports Universal and Local Addressing – Early Token-Release Option (16 Mbps Only) – Built-In Real-Time Error Detection – Automatic Frame-Buffer Management – 2- to 33-MHz System-Bus Clock – Slow-Clock Low-Power Mode ADVANCE INFORMATION D D D 32-Bit Host Address Bus LAN Subsystem Attached System Bus (2 MHz to 33 MHz) Transmit To Network TI380C30 Receive Memory Figure 1. Network-Commprocessor Applications Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IBM and Token-Ring Network are trademarks of International Business Machines Corp. PacketBlaster is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 pin assignments 135 134 133 139 138 137 136 143 142 141 140 147 146 145 144 151 150 149 148 155 154 153 152 159 158 157 156 163 162 161 160 167 166 165 164 171 170 169 168 88 80 81 82 83 76 77 78 79 72 73 74 75 68 69 70 71 64 65 66 67 60 61 62 63 56 57 58 59 52 53 54 55 48 49 50 51 VDD V SSL V DDL MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 NMI CLKDIV V SSC NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SCS SBRLS SBBSY S8 / SHALT SRS2 / SBERR V DDL SI / M SINTR / SIRQ SHLDA / SBGR SDDIR SRAS / SAS SWR / SLDS V SS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3 VDD V SSL 84 85 86 87 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ADVANCE INFORMATION MREF MAL MACS MROMEN OSC32 OSCIN TCLK TMS TRST VSSC VSS SYNCIN VDDL VDD MDDIR MAX0 MAX2 MCAS MW MRAS VSSC VSSL MOE MBEN MADH7 MADH6 MADH5 MADH4 VDD VSS MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR VSS MAXPL MADL7 MADL6 MADL5 MADL4 MADL3 175 174 173 172 176 MBIAEN MRESET MBCLK2 MBCLK1 OSCOUT NSELOUT1 WRAP DRVR+ DRVR – WFLT NC TDI TDO PXTAL RCVR RCLK V SSC1 V SSD RATER V DDD NABL S4 / 16 PWRDN V1SSL1 EQ+ EQ – V SSA1 RCV+ V DDA1 RCV– V DDL1 V DDX XMT– XMT+ V SSX PHOUTB V SSP PHOUTA V DDP RES V SSL1 NC V DDL1 V DDO PGF PACKAGE ( TOP VIEW ) 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XT2 VSSO XT1 VDDA2 ATEST VSSA2 IREF VSSA3 REDY VDDA3 FRAQ NSRT VSSL VDD XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSS VDD VSSC SADH6 SADH7 SPH SRD / SUDS SRDY / SDTACK SOWN SDBEN SBHE / SRNW SHRQ / SBRQ SPL SADL0 SADL1 SADL2 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 description The TI380C30 is a single-chip token-ring solution, combining both the commprocessor and the physical-layer interface onto a single device. The TI380C30 supports both 16 and 4 Mbps of operation, conforms to ISO 8802–5/ IEEE 802.5 – 1992 standards, and has been verified to be completely IBM Token-Ring Network compatible. The TI380C30 provides a high degree of integration as it combines the functions of the TI380C25 and the TI380C60 onto a single chip. With this chip, only local memory and minimal additional components such as PAL devices and crystal oscillators need to be added to complete the LAN-subsystem design. The TI380C30 supports addressing for up to 2 Mbytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data-base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host. The proprietary CPU used in the TI380C30 allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols [such as logical link control (LLC)] to the LAN-subsystem, overall system performance is increased. This is accomplished by offloading processing from the host-system to the TI380C30, which can also reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance is possible. The TI380C30 includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries and burst size, and track host- and LAN-subsystem-buffer status. Previously, these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN-subsystem performance is improved. The TI380C30 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C30 has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture. At the physical-layer interface, the Manchester-encoded data stream is received and phase aligned using an on-chip dual-digital phase-locked loop (PLL). Both the recovered clock and data are passed on to the protocol-handling circuits on the TI380C30 for serial-to-parallel conversion and data processing. On transmit, the TI380C30 buffers the output from the protocol-handling circuit and drives the media via suitable isolation and waveform-shaping components. The TI380C30 uses CMOS technology to reduce power consumption to PCMCIA-compatible levels. Power-management features are incorporated to support Green PC compatibility. In addition to the PLL, all other functions required to interface to an IEEE-802.5 token ring are provided. These functions include the phantom drive to control the relays within a trunk-coupling unit and wire-fault detection circuits; an internal-wrap function for self-test ; and a watchdog timer to provide fail-safe deinsertion from the ring in the event of a station, microcode or commprocessor failure. The major blocks of the TI380C30 include the communications processor (CP), the system interface (SIF), the memory interface (MIF), the protocol handler (PH), the clock generator (CG), the adapter-support function (ASF), and the physical-layer interface (PHY), as shown in the functional block diagram. PAL is a registered trademark of Advanced Micro Devices Inc. Other companies also manufacture programmable array logic devices. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 ADVANCE INFORMATION The TI380C30 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TI380C30 supports direct I/O and a low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 functional block diagram System Interface (SIF) SADH0 SADH7 SADL0 Memory Interface (MIF) • DIO Control • Bus Control • DMA Control SADL7 ADVANCE INFORMATION SPH SPL SBRLS SINTR/ SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/ SUDS SWR/ SLDS SRDY/SDTACK SI/M SHLDA/ SBGR SBHE/ SRNW SRAS/ SAS S8/ SHALT SRESET SRS0 SRS1 SRS2/ SBERR SCS SRSX SHRQ/ SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1 • DRAM Refresh • Local-Bus Arbitrator • Local-Bus Control • Local Parity-Check / Generator Clock Generator (CG) AdapterSupport Function (ASF) Communications Processor RCLK† REDY† WFLT† RCVR† PXTAL† OCS32 TCLK TMS TRST ATEST XT1 XT2 PHOUTA PHOUTB EQ – EQ+ • Interrupts • Test Function MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MW MOE MDDIR MAL MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV NMI EXTINT0 EXTINT3 TEST0 TEST5 Token-Ring Protocol Handler (PH) XMATCH XFAIL Physical-Layer-Interface Test Port FRAQ† NSRT† WRAP† DRVR+† DRVR –† Physical-Layer Interface = Analog Signal † Signals are provided for test monitoring purposes. 4 MADH0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XMT+ XMT– RDV+ RCV– PWRDN S4 / 16 NABL RATER TDO TDI TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions PIN NAME ATEST BTSTRP NO. 128 60 I/O/E† E I DESCRIPTION Analog test. Should be left unconnected. Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (i.e., when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM, the TI380C30 is denied access to the local-memory bus until the CPHALT bit in the SIFACL register is cleared. H = Chapters 0 and 31 of local memory are RAM-based (see Note 1). L = Chapters 0 and 31 of local memory are ROM-based. Clock divider select (see Note 2) CLKDIV 56 I DRVR+ DRVR – 169 168 O O Differential-driver data outputs (reserved) EQ + EQ – 152 151 E E Equalization / gain points. Connections to allow frequency tuning of equalization circuit. EXTINT0 EXTINT1 EXTINT2 EXTINT3 54 53 52 51 I/O Reserved; must be pulled high (see Note 3) FRAQ 122 O Frequency-acquisition control. H = Clock recovery PLL is initialized. L = Normal operation IREF 126 E Internal reference. IREF allows the internal bias current of analog circuitry to be set via an external resistor. MACS 3 I Reserved; must be tied low (see Note 4) MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 34 33 32 31 28 27 26 25 ADVANCE INFORMATION I/O H = 64-MHz OSCIN for 4-MHz local bus L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus Local-memory address, data, and status bus — high byte. For the first quarter of the local-memory cycle, these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0 and the least significant bit is MADH7. Signal 1Q AX4, A0 – A6 Memory Cycle 2Q 3Q Status D0 – D7 4Q D0 – D7 MADL0 50 Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory MADL1 49 cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4 MADL2 48 and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant MADL3 44 bit is MADL0 and the least significant bit is MADL7. I/O MADL4 43 Memory Cycle MADL5 42 1Q 2Q 3Q 4Q MADL6 41 Signal A7 – A14 AX4, A0 – A6 D8 – D15 D8 – D15 MADL7 40 † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 2. The TI380FPA and TMS380SRA are currently supported only with the 4-MHz local bus in either CLKDIV state. Expansion to support the 6-MHz local bus is under development. 3. Each pin must be individually tied to VDD with a 1-kΩ pullup resistor. 4. Pin should be connected to ground. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME MAL NO. 2 I/O/E† DESCRIPTION O Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH, MAX2, MAXPL, MADH0 – MADH7, and MADL0 – MADL7. Three 8-bit transparent latches can be used to retain a 20-bit static address throughout the cycle. Rising edge = No signal latching Falling edge = Allows the above address signals to be latched Local-memory extended-address bit. MAX0 drives AX0 at row-address time and A12 at column-address and data-valid times for all cycles. MAX0 can be latched by MRAS. Driving A12 eases interfacing to a burn-in address (BIA) ROM. MAX0 16 I/O Signal ADVANCE INFORMATION MAX2 MAXPH MAXPL 17 35 39 1Q AX0 Memory Cycle 2Q 3Q A12 A12 4Q A12 I/O Local-memory extended-address bit. MAX2 drives AX2 at row-address time, which can be latched by MRAS, and A14 at column-address and data-valid times for all cycles. Driving A14 eases interfacing to a BIA ROM. Memory Cycle 1Q 2Q 3Q 4Q Signal AX2 A14 A14 A14 I/O Local-memory extended address and parity — high byte. For the first quarter of a memory cycle, MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, MAXPH carries the extended-address bit AX0; and for the last half of the memory cycle, MAXPH carries the parity bit for the high data byte. Memory Cycle 1Q 2Q 3Q 4Q Signal AX1 AX0 Parity Parity I/O Local-memory extended address and parity — low byte. For the first quarter of a memory cycle, MAXPL carries the extended-address bit AX3; for the second quarter of a memory cycle, MAXPL carries extended-address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for the low data byte. Memory Cycle 1Q 2Q 3Q 4Q Signal AX3 AX2 Parity Parity Local-bus clock 1 and local-bus clock 2. MBCLK1 and MBCLK2 are referenced for all local-bus transfers. MBCLK2 lags MBCLK1 by a quarter of a cycle. MBCLK1 and MBCLK2 operate according to: MBCLK1 MBCLK2 MBEN 173 174 24 O O MBCLK [1:2] 8 MHz 8 MHz 12 MHz OSCIN 64 MHz 32 MHz 48 MHz CLKDIV H L L Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and MADL buses during the data phase. MBEN is used in conjunction with MDDIR, which selects the buffer-output direction. H = Buffer output disabled L = Buffer output enabled MBGR 37 I/O Reserved; must be left unconnected Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM containing the adapter’s BIA. MBIAEN 176 O H = MBIAEN is driven high for any write accesses to the addresses between > 00.0000 and > 00.000F, or any accesses (read/write) to any other address. L = MBIAEN is driven low for any read from addresses between > 00.0000 and > 00.000F. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME MBRQ NO. 36 I/O/E† I/O DESCRIPTION Reserved; must be pulled high (see Note 3) Column-address strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle following the row-address portion of the cycle. MCAS is driven low every memory cycle while the column address is valid on MADL0 – MADL7, MAXPH, and MAXPL, except when one of the following conditions occurs: MCAS 18 O • • • When the address accessed is in the BIA ROM (> 00.0000 – > 00.000F) When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in the SIFACL register is zero and an access is made between > 00.0010 and > 00.FFFF or > 1F.0000 and > 1F.FFFF) When the cycle is a refresh cycle, in which case MCAS is driven low at the start of the cycle before MRAS (for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CAS-before-RAS refresh, it can be necessary to disable MCAS with MREF during the refresh cycle. Data direction. MDDIR is used as a direction control for bidirectional bus drivers. MDDIR becomes valid before MBEN becomes active. MDDIR 15 I/O ADVANCE INFORMATION H = TI380C30 memory-bus write L = TI380C30 memory-bus read Memory-output enable. MOE enables the outputs of the DRAM memory during a read cycle. MOE is high for EPROM or BIA ROM read cycles. MOE 23 O H = Disable DRAM outputs L = Enable DRAM outputs MRAS 20 O Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS is driven low every memory cycle while the row address is valid on MADL0 – MADL7, MAXPH, and MAXPL for both RAM and ROM cycles. MRAS is also driven low during refresh cycles when the refresh address is valid on MADL0 – MADL7. DRAM refresh cycle in progress. MREF indicates that a DRAM refresh cycle is occurring. It is also used for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh. MREF 1 O H = DRAM refresh cycle in process L = Not a DRAM refresh cycle Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL register is set or SRESET is asserted. MRESET is used for resetting external local-bus glue logic. MRESET 175 O H = External logic not reset L = External logic reset MROMEN 4 O ROM enable. During the first 5/16 of the memory cycle, MROMEN is used to provide a chip select for ROMs when the BOOT bit of the SIFACL is zero (i.e., when code is resident in ROM, not RAM). MROMEN can be latched by MAL. MROMEN goes low for any read from addresses > 00.0010 – > 00.FFFF or > 1F.0000 – > 1F.FFFF when the BOOT bit in the SIFACL register is zero. MROMEN stays high for writes to these addresses, accesses of other addresses, or accesses of any address when the BOOT bit is 1. During the final three quarters of the memory cycle, MROMEN outputs the A13 address signal for interfacing to a BIA ROM. This means MBIAEN, MAX0, ROMEN, and MAX2 form a glueless interface for the BIA ROM. H = ROM disabled L = ROM enabled MW 19 O Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the MADH0 – MADH7 and MADL0 – MADL7 buses is valid while MW is low. DRAMs latch data on the falling edge of MW, while SRAMs latch data on the rising edge of MW. H = Not a local-memory write cycle L = Local-memory write cycle † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 3: Each pin must be individually tied to VDD with a 1-kΩ pullup resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME NO. NABL 156 NC 135 166 NMI 55 NSELOUT0 NSELOUT1 58 171 I/O/E† I DESCRIPTION Output-enable control. NABL is used in the physical-layer circuitry (see Note 1). These pins should be left unconnected. I O O Nonmaskable interrupt request. NMI must be left unconnected. Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the corresponding bits of the SIFACL register. The value of NSELOUT0 and NSELOUT1 can be changed only while the TI380C30 is reset. NSELOUT0 L H NSELOUT1 H H DESCRIPTION 16-Mbps token ring 4-Mbps token ring ADVANCE INFORMATION NSRT 121 O Insert control. NSRT enables the phantom-driver outputs (PHOUTA and PHOUTB) through the watchdog timer for insertion onto the token ring. Static high = Inactive, phantom current removed (due to watchdog timer) Static low = Inactive, phantom current removed (due to watchdog timer) Falling edge = Active, current output on PHOUTA and PHOUTB OSC32 5 O Oscillator output . OSC32 provides a 32-MHz clock output and can be used to drive OSCIN and one other TTL load. I External oscillator input. OSCIN provides the clock frequency to the TI380C30 for a 4-MHz or 6-MHz internal bus (see Notes 5 and 6). CLKDIV OSCIN H 64 MHz for a 4-MHz local bus L 32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus OSCIN 6 Oscillator output OSCOUT PHOUTA PHOUTB PRTYEN 172 139 141 59 O O O I CLKDIV L OSCOUT OSCIN ÷ 4 H OSCIN ÷ 8 (if OSCIN = 32 MHz, OSCOUT = 8 MHz; if OSCIN = 48 MHz, OSCOUT = 12 MHz) (if OSCIN = 64 MHz, OSCOUT = 8 MHz) Phantom-driver outputs A and B. PHOUTA and PHOUTB cause insertion onto the token ring. PHOUTA and PHOUTB should be connected to the center tap of the transmit transformer secondary winding for phantom-drive generation. Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e., when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. PRTYEN enables parity checking for the local memory. H = Local-memory data bus checked for parity (see Note 1). L = Local-memory data bus not checked for parity. PWRDN 154 I Power-down control (see Note 7) H = Normal operation L = TI380C30 physical-layer circuitry is placed into a power-down state. All TTL outputs of the physical layer are driven to the high-impedance state. PXTAL 163 O Reference-clock output. PXTAL is synthesized from the 8-MHz crystal oscillator used for XT1 and XT2. For 16 Mbps it is a 32-MHz clock, for 4 Mbps it is a 8-MHz clock. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 3. Each pin must be individually tied to VDD with a 1-kΩ pullup resistor. 5. Pin has an expanded input voltage specification. 6. A maximum of two TI380C30 devices can be connected to any one oscillator. 7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) NO. I/O/E† DESCRIPTION RATER 158 O RATER indicates that there are transitions on the RCV+ / RCV– input pair (DRVR +/ DRVR – if WRAP is asserted low) but that the transition rate is not consistent with the ring speed selected by the S4 / 16 pin. RCLK 161 O Recovered clock. RCLK is the clock recovered from the token-ring received data. For 16-Mbps operation, it is a 32-MHz clock. For 4-Mbps operation, it is an 8-MHz clock. RCV+ RCV– 149 147 I I Receiver. RCV+ and RCV– are differential inputs that receive the token-ring data via isolation transformers. RCVR 162 O Recovered data. RCVR contains the data recovered from the token ring. REDY 124 O PLL ready. REDY is normally asserted (active) low. It is cleared following the assertion of FRAQ and reasserted after the data recovery PLL has been reinitialized. H = Received data not valid L = Received data valid RES 137 — Reserved. Should be left unconnected. SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 110 109 108 107 106 105 101 100 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 91 90 89 86 85 84 83 82 I/O SALE 80 O System address/data bus — high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADH0, and the least significant bit is SADH7. I/O ADVANCE INFORMATION PIN NAME Address multiplexing: Bits 31 – 24 and bits 15 – 8 ‡ Data multiplexing: Bits 15 – 8 ‡ System address/data bus — low byte (see Note 1). These lines make up the least significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0, and the least significant bit is SADL7. Address multiplexing: Bits 23 – 16 and bits 7 – 0 ‡ Data multiplexing : Bits 7 – 0 ‡ System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched address. System bus busy. The TI380C30 samples the value on SBBSY during arbitration (see Note 1). The sample has one of two values: SBBSY 68 I H = Not busy. The TI380C30 can become bus master if the grant condition is met. L = Busy. The TI380C30 cannot become bus master. SBCLK 81 I System bus clock. The TI380C30 requires the external clock to synchronize its bus timings for all DMA transfers. Valid frequencies are 2 MHz – 33 MHz. SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA; it is an input at all other times. Intel Mode SBHE / SRNW 94 H = System byte high not enabled (see Note 1) L = System byte high enabled I/O Motorola Mode SRNW is used for system read not write. SRNW serves as a control signal to indicate a read or write cycle. H = Read cycle (see Note 1) L = Write cycle † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning ‡ Typical bit ordering for Intel and Motorola processor buses NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). Intel is a trademark of Intel Corporation. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME NO. I/O/E† DESCRIPTION System-bus release. SBRLS indicates to the TI380C30 that a higher-priority device requires the system bus. The value on SBRLS is ignored when the TI380C30 is not performing DMA. SBRLS is internally synchronized to SBCLK. SBRLS 67 I H = The TI380C30 can hold onto the system bus (see Note 1). L = The TI380C30 should release the system bus upon completion of current DMA cycle. If the DMA transfer is not yet complete, the SIF rearbitrates for the system bus. System-chip select. SCS activates the system interface of the TI380C30 for a DIO read or write. SCS 66 I H = Not selected (see Note 1) L = Selected System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN is activated during both DIO and DMA. SDBEN 95 O H = Keep external data buffers in the high-impedance state L = Cause external data buffers to begin driving data ADVANCE INFORMATION System data direction. SDDIR provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the TI380C30). During DIO reads and DMA writes, SDDIR is high (data direction is out from the TI380C30). When the system interface is not involved in a DIO or DMA operation, SDDIR is high by default. SDDIR 75 O SDDIR H L Intel Mode SHLDA / SBGR 74 DATA DIRECTION output input DIO read write DMA write read SHLDA is used for system-hold acknowledge. SHLDA indicates that the system DMA-hold request has been acknowledged. SHLDA is internally synchronized to SBCLK (see Note 1). H = Hold request acknowledged L = Hold request not acknowledged I Motorola Mode SBGR is used for system bus grant. SBGR is an active-low bus grant, as defined in the standard 68xxx interface, and is internally synchronized to SBCLK (see Note 1). H = System bus not granted L = System bus granted SHRQ is used for system-hold request. SHRQ is used to request control of the system bus in preparation for a DMA transfer. SHRQ is internally synchronized to SBCLK. Intel Mode SHRQ / SBRQ 93 H = System bus requested L = System bus not requested O Motorola Mode SBRQ is used for system-bus request. SBRQ is used to request control of the system bus in preparation for a DMA transfer. SBRQ is internally synchronized to SBCLK. H = System bus not requested L = System bus requested System-interrupt acknowledge. SIACK is from the host processor to acknowledge the interrupt request from the TI380C30. SIACK 61 I H = System interrupt not acknowledged (see Note 1) L = System interrupt acknowledged: The TI380C30 places its interrupt vector onto the system bus. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME NO. I/O/E† DESCRIPTION System-Intel / Motorola mode select. The value on SI / M specifies the system-interface mode. SI / M 72 I H = Intel-compatible-interface mode selected. Intel interface can be 8-bit or 16-bit mode (see S8 / SHALT description and Note 1). L = Motorola-compatible-interface mode selected. Motorola-interface mode is always 16 bits. SINTR is used for system-interrupt request. TI380C30 activates SINTR to signal an interrupt request to the host processor. Intel Mode 73 O Motorola Mode SOWN 96 O SIRQ is used for system-interrupt request. TI380C30 activates SIRQ to signal an interrupt request to the host processor. H = No interrupt request L = Interrupt request by TI380C30 System bus owned. SOWN indicates to external devices that TI380C30 has control of the system bus. SOWN drives the enable signal of the bus-transceiver chips that drive the address and bus-control signals. H = TI380C30 does not have control of the system bus. L = TI380C30 has control of the system bus. SPH 99 I/O System parity high. SPH is the optional odd-parity bit for each address or data byte transmitted over SADH0 – SADH7 (see Note 1). SPL 92 I/O System parity low. SPL is the optional odd-parity bit for each address or data byte transmitted over SADL0 – SADL7 (see Note 1). Intel Mode SRAS / SAS 76 SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied to the SALE output of the system bus. The latching capability can be defeated since the internal latch for these inputs remains transparent as long as SRAS remains high. This permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE to be applied independently of the SALE strobe from the system bus. During DMA, SRAS remains an input. H L Falling edge I/O Motorola Mode = Transparent mode = Holds latched values of SCS, SRSX – SRS2, and SBHE = Latches SCS, SRSX – SRS2, and SBHE SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low address strobe that is an input during DIO (although ignored as an address strobe) and an output during DMA. H = Address is not valid. L = Address is valid and a transfer operation is in progress. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 ADVANCE INFORMATION SINTR / SIRQ H = Interrupt request by TI380C30 L = No interrupt request TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME NO. I/O/E† DESCRIPTION SRD is used for system-read strobe (see Note 7). SRD is the active-low strobe indicating that a read cycle is performed on the system bus. SRD is an input during DIO and an output during DMA. Intel Mode SRD / SUDS 98 H = Read cycle is not occurring. L = If DMA, host provides data to system bus. If DIO, SIF provides data to system bus. I/O Motorola Mode ADVANCE INFORMATION Intel Mode SRDY / SDTACK 97 SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data strobe. SUDS is an input during DIO and an output during DMA. H = Not valid data on SADH0 – SADH7 lines L = Valid data on SADH0 – SADH7 lines SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that a data transfer is complete. SRDY is asynchronous but during DMA and pseudo-DMA cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. SRDY is an output when the TI380C30 is selected for DIO; otherwise, it is an input. H = System bus is not ready. L = Data transfer is complete; system bus is ready. I/O Motorola Mode SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK is an output when the TI380C30 is selected for DIO; otherwise, it is an input. H = System bus is not ready. L = Data transfer is complete; system bus is ready. System reset. SRESET is activated to place the TI380C30 into a known initial state. Hardware reset puts most of the TI380C30 outputs into the high-impedance state and places all blocks into the reset state. The Intel-mode DMA bus-width selection (S8) is latched on the rising edge of SRESET. SRESET 62 I H = No system reset L = System reset Rising edge = Latch bus width for DMA operations (for Intel-mode applications) Intel Mode SRSX and SRS0 – SRS2 are used for system-register select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS2 (see Note 1). MSb Register selected = SRSX SRSX SRS0 SRS1 SRS2 / SBERR 65 64 63 70 SRS0 SRS1 LSb SRS2 / SBERR SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS1 (see Note 1). I Motorola Mode Register selected MSb = SRSX SRS0 LSb SRS1 SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx microprocessor. It is internally synchronized to SBCLK. SBERR is driven low during a DMA cycle to indicate to the TI380C30 that the cycle must be terminated (see Section 3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide (SPWU005) for more information). † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME NO. I/O/E† DESCRIPTION SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe that is an input during DIO and an output during DMA. Intel Mode 77 I/O SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an output during DMA. Motorola Mode H = Not valid data on SADL0 – SADL7 lines L = Valid data on SADL0 – SADL7 lines SXAL 79 O System extended-address latch. SXAL provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension. SYNCIN 12 I Reserved. SYNCIN must be left unconnected (see Note 1). S4 / 16 155 I Speed switch. S4 / 16 specifies the token-ring data rate for the physical layer. H = 4-Mbps data rate L = 16-Mbps data rate Intel Mode S8 / SHALT 69 H = Selects 8-bit mode (see Note 1) L = Selects 16-bit mode I Motorola Mode TCLK TMS TDI TDO 7 8 165 164 I I I O S8 is used for system 8- /16-bit bus select. S8 selects the bus width used for communications through the system interface. On the rising edge of SRESET, the TI380C30 latches the DMA bus width; otherwise, the value on S8 dynamically selects the DIO bus width. SHALT is used for system halt / bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the last DMA cycle. This is the rerun operation as defined in the 68xxx specification. The BERETRY counter is not decremented by SBERR when SHALT is asserted (see Section 3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide (SPWU005) for more information). Test ports used during the production test of the device. Should be left unconnected. Network select inputs. TEST0 – TEST2 are used to select the network speed and type to be used by the TI380C30. These inputs should be changed only during adapter reset. Connect TEST2 to VDDL. TEST0 TEST1 TEST2 116 115 114 I I I TEST3 TEST4 TEST5 113 112 111 I I I Test inputs. TEST3 – TEST5 should be left unconnected (see Note 1). Module-in-place test mode is achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C30 outputs are in the high-impedance state. Internal pullups on all TI380C30 inputs are disabled (except TEST3 – TEST5). TRST 9 I Test-port reset. TRST should be tied to ground for normal operation of the TI380C30. H = Reserved L = Test ports forced to an idle state TEST0 L H X TEST1 NC NC X TEST2 H H L DESCRIPTION 16-Mbps token ring 4-Mbps token ring Reserved † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 ADVANCE INFORMATION SWR / SLDS H = Write cycle is not occurring. L = If DMA, data to be driven from SIF to host bus. If DIO, on the rising edge, the data is latched and written to the selected register. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME I/O/E† DESCRIPTION 14 29 45 87 103 119 — Positive-supply voltage for commprocessor output buffers. All VDD pins must be attached to the common-system power-supply plane. VDDA1 VDDA2 148 — Positive-supply voltage for receiver circuits 129 — Positive-supply voltage for data recovery PLL VDDA3 VDDD 123 VDD NO. Positive-supply voltage for the current-bias generator ADVANCE INFORMATION 157 — Positive-supply voltage for physical layer output buffers VDDL 13 47 71 — Positive-supply voltage for commprocessor digital logic. All VDDL pins must be attached to the common-system power-supply plane. VDDL1 134 146 — Positive-supply voltage for physical layer digital logic. All VDDL pins must be attached to the common-system power-supply plane. VDDO VDDP 133 — Positive-supply voltage for XTAL oscillator 138 — Positive-supply voltage for phantom drive VDDX 145 — Positive-supply voltage for transmit output VSS 11 30 38 78 104 — Ground connections for commprocessor output buffers. All VSS pins must be attached to system ground plane. VSSA1 VSSA2 150 — Ground reference for receiver circuits 127 — Ground reference for data recovery PLL VSSA3 125 VSSC 10 21 57 102 VSSC1 VSSD Ground reference for the current-bias generator — 160 Ground reference for commprocessor output buffers (clean ground). All VSSC pins must be attached to the common-system ground plane. Ground reference for physical layer output buffers 159 — Ground reference for physical layer output buffers VSSL 22 46 88 120 — Ground reference for digital logic. All VSSL pins must be attached to the common-system ground plane. VSSL1 136, 153 — Ground reference for internal logic VSSO VSSP 131 — Ground reference for XTAL oscillator 140 — Ground reference for phantom drive VSSX 142 — Ground reference for transmit output O Phantom-wire fault. WFLT provides an indication of the presence of a short or open circuit on PHOUTA or PHOUTB. H = No fault L = Open or short. The DC fault condition is present in the phantom-drive lines. WFLT 167 † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Pin Functions (Continued) PIN NAME WRAP XFAIL NO. 170 117 I/O/E† DESCRIPTION O Internal wrap mode control. WRAP indicates the TI380C30 has placed the physical layer in the loopback-wrap mode for adapter self test. H = Normal ring operation L = Physical-layer wrap mode selected I External fail-to-match signal. An enhanced address copy option (EACO) device uses XFAIL to indicate to the TI380C30 that it should not copy the frame nor set the ARI/FCI bits in a token-ring frame due to an external address match.The ARI/FCI bits in a token-ring frame can be set due to an internal address-matched frame. If an EACO device is not used, XFAIL must be left unconnected. XFAIL is ignored when CAF mode is enabled [see table in XMATCH description section (see Note 1)]. H = No address match by external address checker L = External address-checker-armed state H = Address match recognized by external address checker L = External address-checker-armed state XMATCH 118 I XMATCH 0 0 1 1 Hi-Z XMT+ XMT– 143 144 E XFAIL 0 1 0 1 Hi-Z FUNCTION Armed (processing frame data) Do not externally match the frame (XFAIL takes precedence) Copy the frame Do not externally match the frame (XFAIL takes precedence) Reset state (adapter not initialized) Transmit differential outputs XMT+ and XMT– provide a low-impedance differential source for line drive via filtering and transformer isolation. XT1 130 I XTAL connection. An 8-MHz crystal network can be connected here to provide a reference clock for XT2 132 E the TI380C30. Alternatively, an 8-MHz TTL clock source can be connected to XT1. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 ADVANCE INFORMATION External match signal. An EACO device uses XMATCH to indicate to the TI380C30 to copy the frame and set the ARI/FCI bits in a token-ring frame. If an EACO device is not used, XMATCH must be left unconnected. XMATCH is ignored when CAF mode is enabled (see Note 1). TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 architecture The major blocks of the TI380C30 include the communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter-support function (ASF), and physical-layer interface. The functionality of each block is described in the following sections. communications processor (CP) The CP performs the control and monitoring of the other functional blocks in the TI380C30. The control and monitoring protocols are specified by the software (downloaded or ROM-based) in local memory. Available protocols include: D D D Media access control (MAC) software Logical link control (LLC) software Copy all frames (CAF) software The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for pipelining of instructions. These features enhance the TI380C30 maximum performance capability to about 8 million instructions per second (MIPS) with an average of about 5 MIPS. ADVANCE INFORMATION system interface (SIF) The SIF performs the interfacing of the LAN subsystem to the host system. This interface may require additional logic depending on the application. The system interface can transfer information / data using any of these three methods: D D D Direct memory access (DMA) Direct input / output (DIO) Pseudo-direct memory access (PDMA) DMA (or PDMA) is used to transfer all data to / from host memory from / to local memory. The main uses of DIO are for loading the software to local memory and for initializing the TI380C30. DIO also allows command / status interrupts to occur to and from the TI380C30. The system interface can be hardware selected for either of two modes by using SI / M. The mode selected determines the memory organizations and control signals used. These modes are: D D The Intel mode (80x8x families): 8-, 16-, and 32-bit bus devices The Motorola mode (68xxx microprocessor family): 16- and 32-bit bus devices The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host system memory). This allows greater flexibility in using / accessing host-system memory. System designers are allowed to customize the system interface to their particular bus by: D D Programmable burst transfers or cycle-steal DMA operations Optional parity protection These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported. The system-interface hardware also includes features to enhance the integrity of the TI380C30 operation and the data. These features include the following: D D D Always internally maintain odd-byte parity regardless of parity being disabled Monitor for the presence of a clock failure Provide switchable SIF speeds at 2MHz to 33MHz On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks become invalid, the TI380C30 enters the slow-clock mode which prevents latch-up of the TI380C30. If the SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the TI380C30 is placed in slow-clock mode. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 system interface (SIF) (continued) When the TI380C30 enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock, and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the TI380C30 must be reinitialized. For DMA with a 16-MHz clock, a continuous transfer rate of 64 Mbps ( 8 MBps) can be obtained. For DMA with a 25-MHz clock, a continuous transfer rate of 96 Mbps (12 MBps) can be obtained. For DMA with a 33-MHz clock, a continuous transfer rate of 128 Mbps ( 16MBps) can be obtained. For 8-bit and 16-bit pseudo-DMA, the following data rates can be obtained: LOCAL BUS SPEED 8-BIT PDMA 16-BIT PDMA 4 MHz 48 Mbps 64 Mbps 6 MHz 72 Mbps 96 Mbps memory interface (MIF) The MIF performs memory management to allow the TI380C30 to address 2 Mbytes in local memory. Hardware in the MIF allows the TI380C30 to be directly connected to DRAMs without additional circuitry. This glueless-DRAM connection includes the DRAM refresh controller. The MIF also handles all internal bus arbitration between these blocks. When required, the MIF arbitrates for the external bus. The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs, burned-in addresses (BIA), and external devices are appropriately addressed when required by the system interface, protocol handler when required for a DMA transfer. The memory interface is capable of a 64-Mbps continuous transfer rate when using a 4-MHz local bus (64-MHz device crystal) and a 96-Mbps continuous transfer rate when using a 6-MHz local bus. protocol handler (PH) The PH performs the hardware-based real-time protocol functions for a token-ring LAN. Network type is determined by TEST0 – TEST2. Token-ring network is determined by software and can be either 16 Mbps or 4 Mbps. These speeds are fixed by the software not by the hardware. The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the received serial data to parallel data. The PH data-management state machines direct the transmission/ reception of data to / from local memory through the MIF. The PH buffer-management state machines automatically oversee this process, directly sending / receiving linked lists of frames without CPU intervention. The PH contains many state machines that provide the following features: D D D D D D D Transmit and receive frames Capture tokens Provide token-priority controls Manage the TI380C30 buffer memory Provide frame-address recognition (group, specific, functional, and multicast) Provide internal parity protection Control and verify the physical-layer circuitry-interface signals Integrity of the transmitted and received data is assured by cyclic-redundancy checks (CRC), detection of network-data violations, and parity on internal data paths. All data paths and registers are optionally parity protected to assure functional integrity. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 ADVANCE INFORMATION Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant issue. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 adapter-support function (ASF) The ASF performs support functions not contained in the other blocks. The features are: D D D D The TI380C30 base timer Identification, management, and service of internal and external interrupts Test-pin mode control, including the unit-in-place mode for board testing Checks for illegal states, such as illegal opcodes and parity clock generator (CG) The CG performs the generation of all internal clocks required by the other functional blocks, including the local memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all input clocks (SBCLK, OSCIN, RCLK, and PXTALIN). If no transition is detected within the period of the reference timer on any input clock signal, the CG places the TI380C30 into slow-clock mode. The frequency of the reference timer is in the range of 10 kHz – 100 kHz. physical-layer interface (PHY) ADVANCE INFORMATION The major blocks of the TI380C30 PHY include the receiver / equalizer, clock recovery PLL, wrap function, phantom drive with wire-fault detector, and watchdog timer. Figure 2 is the block diagram illustrating these major blocks, and the functionality of each block is described in the following sections. External Equalizer WRAP EQ + EQ – XTAL 8 MHz XT1 S4 / 16 ATEST FRAQ XT2 OSC CKT RCV+ RCV– Receiver NABL PXTAL RCVR RCV Data Receiver Clock Recovery RCLK OSC32 FRAQ REDY DRVR+ DRVR– XMT+ Transmit XMT– WFLT PHOUTA Phantom Drive PHOUTB PWRDN Error Rate RATER Watchdog Timer (22 ms) NSRT (internal) Test Port Bias Gen IREF TDI TDO TLCK TMS Figure 2. Functional Block Diagram of the PHY 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TRST TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 receiver Figure 3 shows the arrangement of the line-receiver / equalizer circuit. The differential-input pair, RCV+ and RCV–, are designed to be connected to a floating winding of an isolation transformer. Each is equipped with a bias circuit to center the operating point of the differential input at approximately VDD ÷ 2. The differential-input pair consists of a pair of MOSFETs, each with an identical current source in its source terminal that is set to supply a nominal current of 1.5 mA. At low signal levels, the gain of this pair is inversely proportional to the impedance connected between their sources on EQ – and EQ +. A frequency-equalization network can be connected between EQ + and EQ – to provide equalization for media-signal distortion. The internal-wrap mode is provided for self test of the device. When selected by taking WRAP low, the normal input path is disabled by a multiplexer and a path is enabled from the DRVR+ / DRVR– input pair. Receiver gain, thresholds, and equalization are unchanged in the internal-wrap mode. VDD LOAD ADVANCE INFORMATION LOAD Bias Network RCV– WRAP MUX RCV+ DATA External Equalizer EQ + R1 R2 DATA EQ – WRAP IEQB C1 IEQB From DRVR+ / DRVR– VSS Figure 3. Line Receiver / Equalizer receiver-clock recovery The clock and data recovery in TI380C30 is performed by an advanced, digitally controlled phase-locked loop. In contrast to the TMS38054, the PLL of the TI380C30 is digitally controlled and the loop parameters are set by internally programmed digital constants. This results in precise control of loop parameters and requires no external loop-filter components. The TI380C30 implements an intelligent algorithm to determine the optimum phase position for data sampling and extracted-clock synthesis. The resulting action of the TI380C30 can be modeled as two cascaded PLLs as shown in Figure 4. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 receiver-clock recovery (continued) PLL1 PLL2 RCLK RCV Data RCVR f3dB ≅ 680 KHz f3dB ≅ 162 KHz NOTE A: f3dB = 3dB bandwidth of PLL Figure 4. Dual PLL Arrangement ADVANCE INFORMATION PLL1 represents the algorithm to recover data from the incoming stream detected by the receiver. It has a relatively high bandwidth to provide good jitter tolerance. Data and embedded-clock-phase information are fed as digital values to PLL2 that generates the extracted clock (RCLK) for the commprocessor. The recovered data is sent to the commprocessor as the RCVR signal synchronously with RCLK. In addition to sampling the RCVR signal, the commprocessor uses RCLK to retransmit data in most cases. The lower bandwidth of PLL2 greatly reduces the rate of accumulation of data-correlated phase jitter in a token-ring network and provides very good accumulated-phase-slope (APS) characteristics. In addition to RCLK, the token-ring reference clock (PXTAL) and a fixed-frequency 32-MHz clock (OSC32) are also synthesized from the 8-MHz crystal reference. line driver and wrap function The line-drive function of the TI380C30 is performed by XMT+ / XMT–. Unlike the TMS38054, these pins are low-impedance outputs and require external-series resistance to provide line termination. These pins provide buffering of the differential signal from the PH on DRVR+/ DRVR– with action to control skew and asymmetry, and with no retiming in the transmit path. The wrap function is designed to provide a signal path for system self-test diagnostics. When the PH drives WRAP low, the receiver inputs are ignored and the transmit signal is fed to the receiver input circuitry via a multiplexer. In the internal wrap mode, WRAP can be checked by observing the signal amplitude at the equalization pins, EQ + and EQ –. Equalization is active at this signal level, although the signal does not exhibit the high-frequency attenuation effects for which equalization is intended to compensate. During wrap mode, both XMT+ / XMT– are driven to a low state to prevent any dc current flowing in the isolation transformer. phantom driver and wire-fault detection The phantom-drive circuit under control of NSRT generates a dc voltage on both of the phantom-drive outputs, PHOUTA and PHOUTB. In order to maintain the phantom drive, NSRT is toggled by the TI380C30 at least once every 20 ms. A watchdog timer is included in the TI380C30 to remove the phantom drive if NSRT does not have the required transitions. The watchdog timer is normally not allowed to expire because it is being reinitialized at least every 20 ms. If there is a problem in the TI380C30 or its microcode resulting in failure to toggle NSRT, the timer expires in a maximum of 22 ms. If this happens, the phantom drive is deasserted and remains so until the next falling edge of NSRT. The watchdog timer requires no external-timing components. When the phantom drive is deasserted, the phantom-drive lines are actively pulled low, reaching a level of 1 V or less within 50 ms. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 phantom driver and wire-fault detection (continued) The dc voltage from PHOUTA and PHOUTB is superimposed on the transmit-signal pair to the trunk-coupling unit (TCU) to request that the station be inserted into the ring. This is achieved by connecting the transmit-signal pair to the center of the secondary winding of the transmit-isolation transformer. Since PHOUTA and PHOUTB are connected to the media side of the isolation transformer, they require extensive protection against line surges. A capacitor is connected between the two phantom lines to provide an ac path for the transmit signal, while PHOUTA and PHOUTB independently drive the dc voltage on each of the transmit lines allowing for independent wire-fault detection on each. frequency acquisition and REDY Unlike its predecessors, the TMS3805x family, the data-recovery PLL of the TI380C30 physical layer does not require constant frequency monitoring; neither is it necessary to recenter its frequency via the FRAQ control line. When the commprocessor asserts FRAQ, it initiates a reset of the clock-recovery PLL. The REDY signal is deasserted for the duration of this action and reasserted low when it is complete (a maximum of 3 µs later). This low-going transition of REDY is required by the commprocessor following the setting of FRAQ high to indicate to the PH that any frequency error that it could have detected has been corrected. power-down control The TI380C30 physical-layer interface can be disabled by the PWRDN signal. If PWRDN is taken low, all outputs of the physical-layer interface are in the high-impedance state and all internal logic is powered down, bringing power consumption to a very low level. Upon removing PWRDN, the device resets and initializes itself. This process could take up to 2 ms and care should be taken to ensure that the system does not require stable clocks during this period. user-accessible hardware registers and TI380C30-internal pointers The tables on the following pages show how to access internal data via pointers and how to address the registers in the host interface. The SIFACL register, which directly controls device operation, is described in detail. The adapter-internal pointers table is defined only after TI380C30 initialization and until the OPEN command is issued. These pointers are defined by the TI380C30 software (microcode), and this table describes the release 2.x software. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 ADVANCE INFORMATION The phantom voltage is detected by the TCU, causing the external wrap path from the transmitter outputs back to the receiver inputs to be broken and the ring to be broken. A signal connection is established from the ring to the receiver inputs and from the transmitter outputs to the ring. The return current from the dc-phantom voltage on the transmit pair is returned to the station via the receive pair. This provides some measure of wire-fault detection on the receive lines. The phantom-drive outputs are current limited to prevent damage if short circuited. They detect either an abnormally high or an abnormally low load current at either output corresponding to a short or an open circuit in the ring or TCU wiring. Either type of fault results in the wire-fault indicator output (WFLT) to be driven low. The logic state of WFLT is high when the phantom drive is not active. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 Adapter-Internal Pointers for Token Ring † ADDRESS DESCRIPTION > 00.FFF8‡ > 00.FFFA‡ Pointer to software raw microcode level in chapter 0 Pointer to starting location of copyright notices. Copyright notices are separated by a > 0A character and terminated by a > 00 character in chapter 0. > 01.0A00 Pointer to burned-in address in chapter 1 > 01.0A02 Pointer to software level in chapter 1 > 01.0A04 Pointer to TI380C30 addresses in chapter 1: Pointer + 0 node address Pointer + 6 group address Pointer + 10 functional address > 01.0A06 ADVANCE INFORMATION Pointer to TI380C30 parameters in chapter 1: Pointer + 0 physical-drop number Pointer + 4 upstream neighbor address Pointer + 10 upstream physical-drop number Pointer + 14 last ring-poll address Pointer + 20 reserved Pointer + 22 transmit access priority Pointer + 24 source class authorization Pointer + 26 last attention code Pointer + 28 source address of the last received frame Pointer + 34 last beacon type Pointer + 36 last major vector Pointer + 38 ring status Pointer + 40 soft-error timer value Pointer + 42 ring-interface error counter Pointer + 44 local ring number Pointer + 46 monitor error code Pointer + 48 last beacon-transmit type Pointer + 50 last beacon-receive type Pointer + 52 last MAC-frame correlator Pointer + 54 last beaconing-station UNA Pointer + 60 reserved Pointer + 64 last beaconing-station physical-drop number > 01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter-generated MAC frames) in chapter 1 > 01.0A0A Pointer to LLC counters in chapter 1: Pointer + 0 MAX_SAPs Pointer + 1 open SAPs Pointer + 2 MAX_STATIONs Pointer + 3 open stations Pointer + 4 available stations Pointer + 5 reserved > 01.0A0C Pointer to 4- / 16-Mbps word flag. If zero, the adapter is set to run at 4 Mbps. If nonzero, the adapter is set to run at 16 Mbps. > 01.0A0E Pointer to total TI380C30 RAM found in 1K bytes in RAM allocation test in chapter 1. † This table describes the pointers for release 2.x of the TI380C30 software. ‡ This address valid only for microcode release 2.x 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 User-Access Hardware Registers 80x8x 16-BIT MODE: (SI / M = 1, S8 / SHALT = 0)† NORMAL MODE SBHE = 0 SRS2 = 0 WORD TRANSFERS BYTE TRANSFERS SRSX SRS0 SRS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PSEUDO-DMA MODE ACTIVE SBHE = 0 SRS2 = 0 SBHE = 0 SRS2 = 1 SBHE = 1 SRS2 = 0 SBHE = 0 SRS2 = 1 SBHE = 1 SRS2 = 0 SIFDAT MSB SIFDAT / INC MSB SIFADR MSB SIFCMD SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SIFDAT LSB SIFDAT / INC LSB SIFADR LSB SIFSTS SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB SDMADAT MSB DMALEN MSB SDMAADR MSB SDMAADX MSB SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SDMADAT LSB DMALEN LSB SDMAADR LSB SDMAADX LSB SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB ADVANCE INFORMATION † SBHE = 1 and SRS2 = 1 are not defined 80x8x 8-BIT MODE: (SI / M = 1, S8 / SHALT = 1) SRSX SRS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SRS1 NORMAL MODE SBHE = X SRS2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PSEUDO-DMA MODE ACTIVE SBHE = X SIFDAT LSB SIFDAT MSB SIFDAT / INC LSB SIFDAT / INC MSB SIFADR LSB SIFADR MSB SIFSTS SIFCMD SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB SDMADAT LSB SDMADAT MSB DMALEN LSB DMALEN MSB SDMAADR LSB SDMAADR MSB SDMAADX LSB SDMAADX MSB SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB 68xxx MODE: (SI / M = 0)‡ NORMAL MODE SUDS = 0 SLDS = 0 WORD TRANSFERS BYTE TRANSFERS SRSX SRS0 SRS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PSEUDO-DMA MODE ACTIVE SUDS = 0 SLDS = 0 SUDS = 0 SLDS = 1 SUDS = 1 SLDS = 0 SUDS = 0 SLDS = 1 SUDS = 1 SLDS = 0 SIFDAT MSB SIFDAT / INC MSB SIFADR MSB SIFCMD SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SIFDAT LSB SIFDAT / INC LSB SIFADR LSB SIFSTS SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB SDMADAT MSB DMALEN MSB SDMAADR MSB SDMAADX MSB SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SDMADAT LSB DMALEN LSB SDMAADR LSB SDMAADX LSB SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB ‡ 68xxx mode is always 16 bit. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SIF adapter-control register (SIFACL) The SIFACL register allows the host processor to control and to some extent reconfigure the TI380C30 under software control. SIFACL Register Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T E S T 0 T E S T 1 T E S T 2 — SWHLDA SWDDIR SWHRQ PSDMAEN ARESET CPHALT BOOT LBP SINTEN PEN NSEL OUT0 NSEL OUT1 RP – 0 R –u R –0 RS – 0 RW – 0 RP – b RP – b RW – 0 RW – 1 RP – p RP – 0 RP – 1 R R R ADVANCE INFORMATION Legend: R = W = P = S = –n = b = p = u = Read Write Write during ARESET = 1 only Set only Value after reset Value on BTSTRP Value on PRTYEN Indeterminate Bits 0 – 2: Value on TEST0 and TEST2 pins These bits are read only and reflect the value on the corresponding device pins. This allows the host S / W to determine speed configuration. If the network speed and type are software configurable, these bits are used to determine which configurations are supported by the network hardware. TEST0 TEST1 TEST2 L H X NC NC X H H L Description 16-Mbps token ring 4-Mbps token ring Reserved Bit 3: Reserved. Read data is indeterminate. Bit 4: SWHLDA — Software-Hold Acknowledge Allows the function of SHLDA / SBGR to be emulated from software control for pseudo-DMA mode. PSDMAEN SWHLDA SWHRQ 0† X X SWHLDA value in the SIFACL register cannot be set to a one. RESULT 1† 0 0 No pseudo-DMA request pending 1† 0 1 Indicates a pseudo-DMA request interrupt 1† 1 X Pseudo-DMA process in progress † The value on SHLDA / SBGR is ignored. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SIF adapter-control register (SIFACL) (continued) Bit 5: SWDDIR — Current SDDIR-Signal Value Contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software. 0 = Pseudo DMA from host system to TI380C30 1 = Pseudo DMA from TI380C30 to host system Bit 6: SWHRQ — Current SHRQ-Signal Value INTEL MODE (SI / M = H) 0 = System bus not requested 1 = System bus requested Bit 7: MOTOROLA MODE (SI / M = L) 1 = System bus not requested 0 = System bus requested PSDMAEN — Pseudo-System-DMA Enable Enables pseudo-DMA operation 0 = Normal bus-master DMA operation is possible. 1 = Pseudo-DMA operation selected. Operation dependent on the values of the SWHLDA and SWHRQ bits in the SIFACL register. Bit 8: ARESET — Adapter Reset Is a hardware reset of the TI380C30. This bit has the same effect as SRESET except that the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid). 0 = The TI380C30 operates normally. 1 = The TI380C30 is held in the reset condition. Bit 9: CPHALT — Communications-Processor Halt Controls the TI380C30 processor access to the internal TI380C30 buses. This prevents the TI380C30 from executing instructions before the microcode is downloaded. 0 = The TI380C30 processor can access the internal TI380C30 buses. 1 = The TI380C30 processor cannot access the internal-adapter buses. Bit 10: BOOT — Bootstrap CP Code Indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM or ROM/ PROM/ EPROM. This bit controls the operation of MCAS and MROMEN. 0 = ROM/ PROM/ EPROM memory in chapters 0 and 31 1 = RAM memory in chapters 0 and 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 ADVANCE INFORMATION Contains the current value on SHRQ / SBRQ when in Intel mode and the inverse of the value on SHRQ/ SBRQ in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is requested. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SIF adapter-control register (SIFACL) (continued) Bit 11: LBP — Local-Bus Priority Controls the priority levels of devices on the local bus. 0 = No external devices (such as TI380FPA) are used with the TI380C30. 1 = An external device (such as TI380FPA) is used with the TI380C30. This allows the external bus master to operate at the necessary priority on the local bus. If the system uses the TMS380SRA only, the bit must be set to 0. If the system uses both the TMS380SRA and the TI380FPA, the bit must be set to 1. Bit 12: SINTEN — System-Interrupt Enable Allows the host processor to enable or disable system-interrupt requests from the TI380C30. The system-interrupt request from the TI380C30 is on SINTR / SIRQ. The following equation shows how SINTR / SIRQ is driven. The table details the results of the states. SINTR/ SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT) ADVANCE INFORMATION PSDMAEN SWHRQ SWHLDA SINTEN SYSTEM INTERRUPT (SIFSTS REGISTER) 1† 1† 1 1 X X Pseudo DMA is active. 1 0 X X The TI380C30 generated a system interrupt for a pseudo DMA. RESULT 1† 0 0 X X Not a pseudo-DMA interrupt X X X 1 1 The TI380C30 generates a system interrupt. 0 X X 1 0 The TI380C30 does not generate a system interrupt. 0 X The TI380C30 cannot generate a system interrupt. 0 X X † The value on SHLDA / SBGR is ignored. Bit 13: PEN — Parity Enable Determines whether data transfers within the TI380C30 are checked for parity. 0 = Data transfers are not checked for parity. 1 = Data transfers are checked for correct odd parity. Bit 14 – 15: NSELOUT0, NSELOUT0 1 — Network-Selection Outputs Values control NSELOUT0 and NSELOUT1. These bits can be modified only while the ARESET bit is set. These bits can be used to software configure a TI380C30: NSELOUT0 should be connected to TEST0 (TEST1 should be left unconnected and TEST2 should be tied high). NSELOUT0 and NSELOUT1 are used to select network speed as shown in the table below: NSELOUT0 NSELOUT1 SELECTION 0 0 Reserved 0 1 16-Mbps token ring 1 0 Reserved 1 1 4-Mbps token ring At power up, these bits are set corresponding to 16-Mbps token ring (NSELOUT1 = 1, NSELOUT0 = 0). 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SIFACL control for pseudo-DMA operation Pseudo DMA operation is software controlled by using five bits in the SIFACL register. The logic model for the SIFACL-register control of pseudo-DMA operation is shown in Figure 5. Motorola Mode Host Interface SYSTEM_INTERRUPT (SIFSTS register) DMA Request M U X SINTR / SIRQ M U X SHRQ / SBRQ SHLDA / SBGR M U X DMA Grant ADVANCE INFORMATION Internal Signals SDDIR DMADIR ... SWHLDA SWDDIR SWHRQ . . . PSDMAEN SINTEN ... SIFACL Register Figure 5. Pseudo-DMA Logic Related to SIFACL Bits POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Maximum case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 8: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground. recommended operating conditions VDD Supply voltage ADVANCE INFORMATION TTL-level signal VIH High-level input voltage VIL IOH Low-level input voltage, TTL-level signal (see Note 9) High-level output current TTL outputs IOL TA High-level output current (see Note 10) TTL outputs OSCIN MIN NOM 4.75 5 2 2.4 RCLK, PXTAL, RCVR 2.6 – 0.3 Operating free-air temperature MAX UNIT 5.25 V VDD + 0.3 VDD + 0.3 V VDD + 0.3 0.8 V – 400 µA 2 mA 70 °C 0 NOTES: 9. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only. 10. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst case). electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS ‡ PARAMETER VOH VOL High-level output voltage, TTL-level signal (see Note 11) Low-level output voltage, TTL-level signal IO High impedance output current High-impedance II Input current, any input or input / output ICC Supply current Ci Input capacitance, any input VDD = MIN, VDD = MIN, IOH = MAX IOL = MAX VDD = MAX, VDD = MAX, VO = 2.4 V VO = 0.4 V VI = VSS to VDD VDD = MAX Normal mode Power-down mode VDD = 5 V f = 1 MHz, MIN TYP MAX 2.4 V 0.6 20 – 20 ± 20 200 V µA µA mA 20 Others at 0 V UNIT 15 pF Co Output capacitance, any output or input / output f = 1 MHz, Others at 0 V 15 pF ‡ For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions. NOTE 11: The following signals require an external pullup resistor: SRAS / SAS, SRDY / SDTACK, SRD / SUDS, SWR / SLDS, EXTINT0 – EXTINT3, and MBRQ. 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) receiver input (RCV+ and RCV–) VB TEST CONDITIONS MIN MAX VSB – 1 VSB + 1 UNIT Receiver-input bias voltage See Note 12 VT+ Rising-input threshold voltage VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 VT– Falling-input threshold voltage VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 – 50 VAT Asymmetry threshold voltage, ( VT+ + VT– ) VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 – 20 20 mV Vr(CM) Rising-input common-mode rejection [ VT+ (@VSB + 0.5 V) – VT+ (@VSB – 0.5 V) ] See Notes 12, 13, and Figure 6 – 30 30 mV Vf(CM) Falling-input common-mode rejection [ VT+ (@VSB + 0.5 V) – VT+ (@VSB – 0.5 V) ] See Notes 12, 13, and Figure 6 – 30 30 mV Both inputs at VSB, See Note 12 and Figure 6 – 10 10 15 60 – 15 –60 1.2 1.8 II(RCVR) Input under test at VSB + 1 V, Other input at VSB – 1 V, See Notes 12 and 13 and Figure 6 Receiver input current Rtst = 330 Ω, Input under test at VSB – 1 V, Other input at VSB + 1 V, See Note 12 IEQB RCV+ at 4 V, RCV– at 4 V, Equalizer bias current RCV– at 1 V or RCV+ at 1 V, See Figure 6 50 V mV mV µA mA VEQW Equalizer wrap voltage WRAP = low, See Figure 6 130 0 mV NOTES: 12. VSB is the self-bias voltage of the input pair RCV+ and RCV–. It is defined as VSB = (VSB+ +VSB –) ÷ 2 (where VSB+ is the self-bias voltage of RCV+; VSB – is the self-bias voltage of RCV–). The self-bias voltage of both pins is approximately VDD ÷ 2. 13. VICM is the common-mode voltage applied to RCV+ and RCV–. phantom driver (PHOUTA and PHOUTB) PARAMETER TEST CONDITIONS VOH High level output voltage High-level IOS IOL Short-circuit output current IOZH IOZL Off-state output current with high-level voltage applied Low-level output current Off-state output current with low-level voltage applied MIN MAX UNIT IOH = – 1 mA IOH = – 2 mA 4.1 V 3.8 V VO = 0 V VO = VDD –4 – 20 mA –1 – 10 mA VO = VDD VO = 0 V – 100 100 µA – 100 100 µA MIN MAX UNIT 0.15 kΩ wire fault ( WFLT ) (see Notes 14 and 15) PARAMETER RLS Phantom load resistance detected as short circuit RLO Phantom load resistance detected as open circuit 50 kΩ RLN Phantom load resistance dectected as normal 2.9 5.5 kΩ NOTES: 14. The wire-fault circuit recognizes a fault condition for any phantom-drive load resistance to ground of greater than RLO or any load resistance less than RLS. Any resistance in the range specified for RLN is not recognized as a wire fault. A fault condition on either PHOUTA or PHOUTB results in the WFLT signal being asserted (low). 15. Resistor (RLS, RLO, RLN) connected from output under test to ground, other output loaded with 4.1 Ω to ground. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 ADVANCE INFORMATION PARAMETER TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PLL characteristics PARAMETER VFILT TEST CONDITIONS MIN MAX tc(XT1) = 125 ns 1.8 4.0 TEST CONDITIONS MIN MAX 1.8 4.0 – 2.5 – 6.5 mA 0.4 1.3 mA Reference PLL operating filter voltage UNIT V crystal-oscillator characteristics PARAMETER VSB(XT1) Input self-bias voltage IOH(XT2) Output high-level current V(XT2) = VSB(XT1) V(XT1) = VSB(XT1) + 0.5 V IOL(XT2) Output low-level current V(XT2) = VSB(XT1) V(XT1) = VSB(XT1) – 0.5 V UNIT V timing parameters ADVANCE INFORMATION The timing parameters for the signals of TI380C30 are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among the various signals. The parameters are numbered for convenience. static signals The following table lists signals that are not allowed to change dynamically and therefore have no timing associated with them. They should be strapped high, low, or left unconnected as required. SIGNAL FUNCTION SI / M Host-processor select (Intel / Motorola) CLKDIV Reserved BTSTRP Default-bootstrap mode (RAM / ROM) PRTYEN Default-parity select (enabled / disabled) TEST0 Test pin indicates network type TEST1 NC TEST2 Test pin indicates network type TEST3 Test pin for TI manufacturing test † Test pin for TI manufacturing test † TEST4 TEST5 Test pin for TI manufacturing test † † For unit-in-place test 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 timing parameter symbology Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the signal names and other related terminology have been abbreviated as shown below: DR DRVR RS SRESET VDD VDDL, VDD DRN DRVR OSC OSCIN SCK SBCLK Lower-case subscripts are defined as follows: c cycle time r d delay time sk h hold time su w pulse duration (width) rise time skew setup time t transition time The following additional letters and phrases are defined as follows: High Z L Low Falling edge No longer high V Valid Rising edge No longer low POST OFFICE BOX 1443 High impedance • HOUSTON, TEXAS 77251–1443 ADVANCE INFORMATION H 31 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels are compatible with TTL devices. Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level at which the signal is said to be high is 2 V, as shown below. The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically 1.5 ns. 2 V (high) 0.8 V (low) ADVANCE INFORMATION test measurement The test-load circuit shown in Figure 6 represents the programmable load of the tester pin electronics that are used to verify timing parameters of TI380C30 output signals. IOL Test Point VLOAD 50 pF Test Point TTL Output Under Test XMT+ 50 pF 330 Ω Test Point XMT– 50 pF IOH (a) TTL-OUTPUT TEST LOAD (b) XMT+ and XMT– TEST LOAD IEQB EQ+ VLOAD VEQW 180 Ω EQ– (c) Iref TEST CIRCUIT Where: VLOAD (d) EQUALIZER TEST CIRCUIT = 1.5 V, typical dc-level verification or 0.7 V, typical timing verification Figure 6. Test and Load Circuits 32 330 Ω POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 switching characteristics over recommended range of supply voltage (unless otherwise noted) transmitter-drive characteristics PARAMETER VPP(XMT) XMT+ / XMT– XMT peak-to-peak peak to peak voltage (see Note 16) TEST CONDITIONS MIN VDD = 4.75 V, See Figures 6 and 7 8.2 MAX UNIT V VDD = 5.25 V, See Figures 6 and 7 10.3 NOTE 16: VPP(XMT) is determined by: VOH(XMT+) + VOH(XMT–) – VOL(XMT+) – VOL(XMT–) transmitter switching characteristics (see Figures 6 and 7) XMT+/XMT skew (see Note 17) XMT+/XMT– TEST CONDITIONS MIN MAX tsk(DRV) = – 1 ns tsk(DRV) = + 1 ns –3 +3 ns –3 +3 ns –2 +2 ns –2 +2 ns tsk(DRV) = – 1 ns tsk(DRV) = + 1 ns td(XMT– L) or td(XMT+ L) – td(XMT– H) XMT+/XMT asymmetry (see Note 18) XMT+/XMT– UNIT ADVANCE INFORMATION PARAMETER NOTES: 17. XMT+/XMT– skew is determined by: td(XMT+ H) – 18. XMT+/XMT– asymmetry is determined by: t t t t d(XMT H) d(XMT L) d(XMT– L) d(XMT– H) – 2 2 ) ) ) ) DRVR+ 2.4 V 1.5 V 0.45 V DRVR– 2.4 V 1.5 V 0.45 V tsk(DRV) tsk(DRV) VOH(XMT+) V50(XMT+) VOL(XMT+) XMT+ td(XMT+L) td(XMT+H) VOH(XMT–) V50(XMT–) VOL(XMT–) XMT– td(XMT– H) td(XMT– L) Figure 7. Transmitter Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 timing requirements over recommended range of supply voltage, tc(XT1) = 125 ns (see Figure 8) TEST CONDITIONS MIN TYP UNIT Cycle time of clock applied to XT1 Pulse duration, OSC32 high 10 ns tw(OSC32L) Pulse duration, OSC32 low 12 ns 16-Mbps mode 12 ns tw(PXTALL) (PXTALL) 125 MAX tc(XT1) tw(OSC32H) Pulse duration, duration PXTAL low tw(PXTALH) (PXTALH) duration PXTAL high Pulse duration, tw(RCLKL) (RCLKL) Pulse duration duration, RCLK low ns 4-Mbps mode 46 ns 16-Mbps mode 10 ns 4-Mbps mode 46 ns 16-Mbps mode 12 ns 4-Mbps mode 46 ns 16-Mbps mode 10 ns ADVANCE INFORMATION tw(RCLKH) (RCLKH) Pulse duration, duration RCLK high 4-Mbps mode 46 ns tsu(RCVR) th(RCVR) Setup time, RCVR valid to RCLK rising edge 16-Mbps mode 18 ns Hold time, RCVR valid after RCLK rising edge 16-Mbps mode 1 ns tw(PXTALH) tw(PXTALL) 2V PXTAL 0.8 V tw(OSC32H) tw(OSC32L) 2V OSC32 0.8 V tw(RCLKH) tw(RCLKL) 2V RCLK 0.8 V tsu(RCVR) th(RCVR) 2V RCVR 0.8 V Figure 8. PXTAL, RCLK, and RCVR Timing 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing 102†‡ 103 104 105 106† 107 108 109 MIN NOM MAX UNIT tr(VDD) td(VDDH-SCKV) Rise time, 1.2 V to minimum VDD-high level 1 ms Delay time, minimum VDD-high level to first valid SBCLK no longer high 1 ms td(VDDH-OSCV) tc(SCK) Delay time, minimum VDD-high level to first valid OSCIN high 1 ms 30.3 500 ns tw(SCKH) tw(SCKL) Pulse duration, SBCLK high 13 500 ns Pulse duration, SBCLK low 13 500 ns tt(SCK) tc(OSC) Transition time, SBCLK 2 ns tw(OSCH) ( ) tw(OSCL) ( ) Cycle time, SBCLK (see Note 19) Cycle time, OSCIN (see Note 20) 1 / OSCIN Pulse duration, OSCIN high (see Note 21) Pulse duration, OSCIN low (see Note 21) OSCIN = 64 MHz 5.5 OSCIN = 48 MHz 8 OSCIN = 32 MHz 8 OSCIN = 64 MHz 5.5 OSCIN = 48 MHz 8 OSCIN = 32 MHz 8 ns ns ns 110† 111† tt(OSC) td(OSCV-CKV) Transition time, OSCIN 3 ns Delay time, OSCIN valid to MBCLK1 and MBCLK2 valid 1 ms 117† 118† th(VDDH-RSL) tw(RSH) Hold time, SRESET low after VDD reaches minimum high level 119† 288† tw(RSL) tsu(RST) 289† th(RST) tM 5 ms Pulse duration, SRESET high 14 µs Pulse duration, SRESET low 14 µs Setup time, DMA size to SRESET high (Intel mode only) 10 ns Hold time, DMA size from SRESET high (Intel mode only) 10 ns CLKDIV = H 2tc(OSC) CLKDIV = L 2tc(OSC) One-eighth of a local-memory cycle ns † This specification is provided as an aid to board design. It is not assured during manufacturing testing. ‡ If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger difference: real value of parameter 101 or 102 minus the max value listed. NOTES: 19. SBCLK can be any value between 2 MHz and 33 MHz. This data sheet describes the system interface ( SIF ) timing parameters for the cases of SBCLK at 25 MHz and 33 MHz. 20. The value of OSCIN can be 64 MHz ±1%, 32 MHz ± 1%, or 48 MHz ± 1%. If OSCIN is used to generate PXTALIN, the OSCIN tolerance must be ± 0.01%. 21. This is to assure a ± 5% duty-cycle crystal, provided that OSCIN meets the recommended operating conditions for VIH and VIL . POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 ADVANCE INFORMATION NO. 100† 101†‡ TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 100 Minimum VDD-High Level VDD 103 106 106 104 101 105 SBCLK 102 107 110 108 OSCIN 110 109 ADVANCE INFORMATION MBCLK1 111 MBCLK2 118 117 119 SRESET 288 289 S8 / SHALT NOTE A: To represent the information in one illustration, nonactual phase and timebase characteristics are shown. Refer to specified parameters for precise information. Figure 9. Timing for Power Up, System Clocks, SYNCIN, and SRESET 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). MIN 1 Period of MBCLK1 and MBCLK2 2 Pulse duration, clock high 3 Pulse duration, clock low 4 Hold time, MBCLK2 low after MBCLK1 high 5 Hold time, MBCLK1 high after MBCLK2 high 6 Hold time, MBCLK2 high after MBCLK1 low 7 Hold time, MBCLK1 low after MBCLK2 low 8 Setup time, address / enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high MAX UNIT 4tM 2tM – 9 2tM – 9 ns tM – 9 tM – 9 ns tM – 9 tM – 9 ns tM – 9 tM – 14 ns tM – 14 13 ns ns ns ns ns 9 Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no longer high 10 Setup time, address on MADH0 – MADH7 before MBCLK1 no longer high 11 Setup time, MAL high before MBCLK1 no longer high 12 Setup time, address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low 0.5tM – 9 ns 13 Setup time, column address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no longer low 0.5tM – 9 ns 14 Setup time, status on MADH0 – MADH7 before MBCLK1 no longer low ns 120 Setup time, NMI valid before MBCLK1 low 0.5tM – 9 30 121 Hold time, NMI valid after MBCLK1 low 0 126 Delay time, MBCLK1 no longer low to MRESET valid 0 129 Hold time, column address / status after MBCLK1 no longer low Reference 4 Periods 8 Periods tM – 7 12 Periods 16 Periods ns ns ns ns 20 ns ns 20 Periods OSCIN (when CLKDIV = 1) OSCIN (when CLKDIV = 0) OSCOUT MBCLK1 † MBCLK2 † † MBCLK1 and MBCLK2 have no timing relationship to OSCOUT. MBCLK1 and MBCLK2 can start on any OSCIN rising edge, depending on when the memory cycle starts execution. Figure 10. Clock Waveforms After Clock Stabilization POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 ADVANCE INFORMATION NO. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 M8 M1 M2 M4 M3 M5 M6 M7 M8 M1 1 tM 3 MBCLK1 4 2 6 1 5 7 3 MBCLK2 8 MAX0, MAX2, MROMEN 2 12 ADD / EN Address 9 MAXPH, MAXPL, MADL0 – MADL7 13 Row Col ADVANCE INFORMATION 14 10 Address MADH0 – MADH7 Status 11 129 MAL 120 NMI 121 Valid 126 MRESET Valid Figure 11. Memory-Bus Timing: Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 memory-bus timing: clocks, MRAS, MCAS, and MAL to ADDRESS tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). MIN 15 Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer high 16 Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high 17 Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle 18 Pulse duration, MRAS low 19 MAX UNIT 1.5tM – 11.5 ns tM – 6.5 8tM ns ns Pulse duration, MRAS high 4.5tM – 5 3.5tM – 5 20 Setup time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status (MADH0 – MADH7) before MCAS no longer high 0.5tM – 9 ns 21 Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status (MADH0 – MADH7) after MCAS low tM – 5 ns 22 Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status (MADH0 – MADH7) after MRAS no longer high 2.5tM – 6.5 ns 23 Pulse duration, MCAS low ns 24 Pulse duration, MCAS high, refresh cycle follows read or write cycle 3tM – 9 2tM – 9 25 Hold time, row address on MAXL0 – MAXL7, MAXPH, and MAXPL after MAL low ns 26 Setup time, row address on MAXL0 – MAXL7, MAXPH, and MAXPL before MAL no longer high 1.5tM – 9 tM – 9 27 Pulse duration, MAL high Setup time, address / enable on MAX0, MAX2, and MROMEN before MAL no longer high tM – 9 tM – 9 ns 28 29 Hold time, address / enable of MAX0, MAX2, and MROMEN after MAL low Setup time, address on MADH0 – MADH7 before MAL no longer high 1.5tM – 9 tM – 9 ns 30 31 Hold time, address on MADH0 – MADH7 after MAL low 1.5tM – 9 ns POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns ns ADVANCE INFORMATION NO. ns ns ns ns 39 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 MAXPH, MAXPL, MADL0 – MADL7 Row Column Column Row 16 26 17 22 15 19 18 MRAS 21 20 24 23 MCAS 25 27 MAL 28 ADVANCE INFORMATION MAX0, MAX2, MROMEN 29 ADD / EN Address 21 30 31 20 MADH0 – MADH7 Address Status Address Status 22 Figure 12. Memory-Bus Timing: Clocks, MRAS, MCAS, and MAL to ADDRESS 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 memory-bus timing: read cycle tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). MIN 32 Access time, address / enable valid on MAX0, MAX2, and MROMEN to valid data / parity 33 Access time, address valid on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 to valid data / parity 35 Access time, MRAS low to valid data / parity 36 Hold time, valid data / parity after MRAS no longer low 37† Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7 and MADL0 – MADL7 after MRAS high (see Note 22) 38 Access time, MCAS low to valid data / parity 39 Hold time, valid data / parity after MCAS no longer low 40† Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 after MCAS high (see Note 22) 41 Delay time, MCAS no longer high to MOE low 42† Setup time, address / status in the high-impedance state on MAXPH, MAXPL, MADL0 – MADL7, and MADH0 – MADH7 before MOE no longer high 43 Access time, MOE low to valid data / parity 44 Pulse duration, MOE low 45 Delay time, MCAS low to MOE no longer low 46 Hold time, valid data / parity in after MOE no longer low 47† Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 after MOE high (see Note 22) 48† 48a† MAX UNIT 6tM – 23 ns 6tM – 23 ns 4.5tM – 21.5 ns 0 ns 2tM – 10.5 ns 3tM –23 ns 0 ns 2tM –13 ns tM +13 0 ns ns 2tM – 20 ns 2tM – 9 3tM – 9 ns 0 ns 2tM – 15 ns Setup time, address / status in the high-impedance state on MAXPH, MAXPL, MADL0 – MADL7, and MADH0 – MADH7, before MBEN no longer high 0 ns Setup time, address / status in the high-impedance state on MAXPH, MAXPL, MADL0 – MADL7, and MADH0 – MADH7 and before MBIAEN no longer high 0 ns 49 Access time, MBEN low to valid data / parity 49a Access time, MBIAEN low to valid data / parity 50 Pulse duration, MBEN low 50a Pulse duration, MBIAEN low 51 ns 2tM – 25 2tM – 25 ns ns 2tM – 9 2tM – 9 ns Hold time, valid data / parity after MBEN no longer low 0 ns 51a Hold time, valid data / parity after MBIAEN no longer low 0 ns 52† Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 after MBEN high (see Note 22) 2tM – 15 ns 52a† Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 after MBIAEN high 2tM – 15 ns 1.5tM – 12 3tM – 5 ns 53 Hold time, MDDIR high after MBEN high, read follows write cycle 54 Setup time, MDDIR low before MBEN no longer high ADVANCE INFORMATION NO. ns ns 55 Hold time, MDDIR low after MBEN high, write follows read cycle 3tM – 12 ns † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. NOTE 22: The data / parity that exists on the address lines will most likely reach the high-impedance state sometime later than the rising edge of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read. The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address, and does not represent the actual high-impedance period on the address bus. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 MAX0, MAX2, MROMEN Address / Enable Address Data / Parity 32 MAXPH, MAXPL, MADH0 – MADH7, MADL0 – MADL7 Address Address / Status Address 33 36 37 35 MRAS 38 39 40 MCAS ADVANCE INFORMATION 43 45 41 46 42 47 44 MOE 49a 48a 51a 52a 50a MBIAEN 49 51 48 52 MBEN 50 53 54 55 MDDIR Figure 13. Memory-Bus Timing: Read Cycle 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 memory-bus timing: write cycle tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). MIN 58 Setup time, MW low before MRAS no longer low 60 Setup time, MW low before MCAS no longer low 63 Setup time, valid data / parity before MW no longer high 64 Pulse duration, MW low 65 Hold time, data / parity out valid after MW high 66 Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low 67 Hold time, MRAS low to MW no longer low 69 Hold time, MCAS low to MW no longer low 70 Setup time, MBEN low before MW no longer high 71 Hold time, MBEN low after MW high 72 Setup time, MDDIR high before MBEN no longer high 73 Hold time, MDDIR high after MBEN high MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0 – MADH7, MADL0 – MADL7 Address / Enable MAX UNIT tM 1.5tM – 6.5 5.1 ns 2.5tM – 9 0.5tM – 10.5 7tM –11.5 ns 5.5tM – 9 4tM –11.5 ns 1.5tM – 13.5 0.5tM – 6.5 ns 2tM – 9 1.5tM – 12 ns ns ns ns ns ns ns ADVANCE INFORMATION NO. ns Address Address ADD / STS Data / Parity Out MRAS 58 MCAS 60 65 63 64 MW 69 67 66 70 71 MBEN 72 73 MDDIR Figure 14. Memory-Bus Timing: Write Cycle POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 memory-bus timing: DRAM-refresh timing tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). NO. MIN 15 Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer high 16 Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high 18 Pulse duration, MRAS low 19 Pulse duration, MRAS high 73a Setup time, MCAS low before MRAS no longer high 73b Hold time, MCAS low after MRAS low 73c Setup time, MREF high before MCAS no longer high 73d Hold time, MREF high after MCAS high ADVANCE INFORMATION Refresh Address MADL0 – MADL7 MAX UNIT 1.5tM – 11.5 tM – 6.5 ns 4.5tM – 5 3.5tM – 5 ns 1.5tM –11.5 4.5tM – 6.5 ns ns ns ns 14 ns tM – 9 ns Address 16 19 15 18 MRAS 73a 73b MCAS 73d 73c MREF Figure 15. Memory-Bus Timing: DRAM-Refresh Cycle XMATCH and XFAIL timing tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). NO. MIN 127 Delay time, status bit 7 high to XMATCH and XFAIL recognized 128 Pulse duration, XMATCH or XFAIL high MADH7 Status Bit 7 127 XMATCH, XFAIL Figure 16. XMATCH and XFAIL Timing 44 7tM 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 128 MAX UNIT ns ns TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 token ring: ring-interface timing 153 MIN 4 Mbps Period of RCLK (see Note 23) 154L Pulse duration duration, RCLK low 154H Pulse duration, duration RCLK high 16 Mbps ns 4 Mbps nominal: 62.5 ns 35 ns 8 ns 10 ns 4 ns 40 ns 16 Mbps 8 ns 4 Mbps 40 ns 16 Mbps 8 ns 4 Mbps 4 Mbps Period of OSCOUT and PXTALIN (see Note 23) ns ns Hold time, RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbps 165 31.25 15 Setup time, RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbps Pulse duration, duration ring-baud ring baud clock high ns 16 Mbps nominal: 15.625 ns 156 158H UNIT 46 16 Mbps nominal: 15.625 ns duration ring-baud ring baud clock low Pulse duration, MAX 125 4 Mbps nominal: 62.5 ns 155 158L TYP 16 Mbps (for PXTALIN only) 125 ns 31.25 ns ± 0.01 Tolerance of PXTALIN input frequency (see Note 23) ADVANCE INFORMATION NO. % NOTE 23: This parameter is not tested but is required by the IEEE 802.5 specification. 153 154H RCLK 154L 156 155 Valid RCVR 158H 158L OSCOUT, PXTALIN 1.5 V 165 Figure 17. Ring-Interface Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 token ring: transmitter timing NO. MIN Delay time, DRVR rising edge (1.8 V ) to DRVR falling edge (1 V ) or DRVR falling edge (1 V ) to DRVR rising edge (1.8 V ) MAX ±2 UNIT 159 tsk(DR) 160 td(DR)H† td(DR)L† Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V ) See Note 24 ns Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V ) See Note 24 ns td(DRN)H† t(DRN)L† Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V ) See Note 24 ns Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V ) See Note 24 ns 161 162 163 164 t d(DR)L DRVR / DRVR asymmetry )t d(DRN)H 2 – t d(DR)H )t ±1.5 d(DRN)L 2 ns ns † When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock-source is either RCLK or PXTALIN. NOTE 24: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164. ADVANCE INFORMATION RCLK or PXTALIN 2.6 V 1.5 V 0.6 V DRVR 2.4 V 1.5 V 0.6 V 160 161 159 159 2.4 V 1.5 V 0.6 V DRVR 162 163 Figure 18. Skew and Asymmetry From RCLK or PXTALIN to DRVR and DRVR 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x DIO read-cycle timing MIN MAX 33-MHz OPERATION MIN MAX UNIT 255 Delay time, SRDY low to either SCS or SRD high 15 15 ns 256 Pulse duration, SRAS high 30 30 ns 259† Hold time, SAD in the high-impedance state after SRD low (see Note 25) 0 0 ns 260 Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid before SRDY low 0 0 ns 261† Delay time, SRD or SCS high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SRD or SCS high (see Note 25) 264 35 35 ns 0 0 ns Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE valid to SRAS no longer high (see Note 26) 30 30 ns 265 Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE valid after SRAS low 10 10 ns 266a Setup time, SRAS high to SRD no longer high (see Note 26) 15 15 ns 267‡ Setup time, SRSX, SRS0 – SRS2 valid before SRD no longer high (see Note 25) 15 15 ns 268 Hold time, SRSX, SRS0 – SRS2 valid after SRD no longer low (see Note 26) 0 0 ns 272a Setup time, SRD, SWR, and SIACK high from previous cycle to SRD no longer high tc(SCK) tc(SCK) ns 273a Hold time, SRD, SWR, and SIACK high after SRD high tc(SCK) tc(SCK) ns 275 Delay time, SRD and SWR, or SCS high to SRDY high (see Note 25) 0 25 0 25 ns 279† Delay time, SRD and SWR, high to SRDY in the high-impedance state 0 tc(SCK) 0 tc(SCK) ns 282a Delay time, SDBEN low to SRDY low in a read cycle 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns 282R Delay time, SRD low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed 0 tc(SCK) + 3 0 tc(SCK) + 3 ns 283R Delay time, SRD high to SDBEN high (see Note 25) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns 286 Pulse duration, SRD high between DIO accesses (see Note 25) tc(SCK) tc(SCK) ADVANCE INFORMATION 25-MHz OPERATION NO NO. ns † This specification is provided as an aid to board design. It is not assured during manufacturing testing. ‡ It is the later of SRD and SWR or SCS low that indicates the start of the cycle. NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS, SRSX, SRS0 – SRS2, SBHE Valid † Valid 264 268 265 SRAS 256 266a 267 SIACK 272a 273a SWR 273a ADVANCE INFORMATION 272a SRD 273a 272a 286 High SDDIR 279 282R 283R SDBEN 275 282a SRDY ‡ 255 Hi-Z 261 260 SADH0 – SADH7, SADL0 – SADL7, SPH, SPL § 261a 259 Hi-Z Hi-Z Output Data Valid Hi-Z † In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must meet parameter 266a; SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. ‡ When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. § In 8-bit 80x8x mode DIO reads, the SADH0 – SADH7 contain don’t-care data. Figure 19. 80x8x DIO Read-Cycle Timing 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x DIO write-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 255 Delay time, SRDY low to either SCS or SWR high 15 15 ns 256 Pulse duration, SRAS high 30 30 ns 262 Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid before SCS or SWR no longer low 15 15 ns 263 Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid after SCS or SWR high 15 15 ns 264 Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE to SRAS no longer high (see Note 26) 30 30 ns 265 Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE after SRAS low 10 10 ns 266a Setup time, SRAS high to SWR no longer high (see Note 25) 15 15 ns 267† Setup time, SRSX, SRS0 – SRS2 before SWR no longer high (see Note 25) 15 15 ns 268 Hold time, SRSX, SRS0 – SRS2 valid after SWR no longer low (see Note 26) 0 0 ns 272a Setup time, SRD, SWR, and SIACK high from previous cycle to SWR no longer high tc(SCK) tc(SCK) ns 273a Hold time, SRD, SWR, and SIACK high after SWR high tc(SCK) tc(SCK) ns 276‡ Delay time, SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following access to the SIF (see TMS380 Second-Generation Token-Ring User’s Guide, SPWU005, subsection 3.4.1.1.1) 4000 4000 275 279§ Delay time, SWR or SCS high to SRDY high (see Note 25) 0 Delay time, SWR high to SRDY in the high-impedance state 0 Delay time, SWR low to SDDIR low (see Note 25) 0 tc(SCK) tc(SCK) / 2 + 4 0 280 0 tc(SCK) tc(SCK) / 2 + 4 If SIF register is ready (no waiting required) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 If SIF register is not ready (waiting required) 0 4000 0 4000 tc(SCK) / 2 + 4 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 tc(SCK) / 2 + 4 282b Delay time, SDBEN low to SRDY low (see TMS380 Second Generation Token-Ring g User’s Guide, SPWU005, subsection 3.4.1.1.1) 0 25 ns ns ns ns 282W Delay time, SDDIR low to SDBEN low 0 283W Delay time, SCS or SWR high to SDBEN no longer low 0 286 25 ADVANCE INFORMATION NO NO. 0 ns ns Pulse duration, SWR high between DIO accesses (see Note 25) tc(SCK) tc(SCK) ns † It is the later of SRD and SWR or SCS low that indicates the start of the cycle. ‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing. § This specification is provided as an aid to board design. It is not assured during manufacturing testing. NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must meet parameter 266a; SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS, SRSX, SRS0 – SRS2, SBHE Valid 264 268 265 SRAS 256 SIACK 266a 267 273a 272a SWR 273a 286 272a SRD 273a 272a ADVANCE INFORMATION 280 SDDIR 282W 283W SDBEN † 279 276 275 SRDY 282b 255 Hi-Z Hi-Z 263 262 SADH0 – SADH7, SADL0 – SADL7, Hi-Z Hi-Z Data SPH, SPL ‡ † When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. ‡ In 8-bit 80x8x-mode DIO writes, the value placed on SADH0 – SADH7 is a don’t care. Figure 20. 80x8x DIO Write-Cycle Timing 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x interrupt-acknowledge-cycle timing: first SIACK pulse NO. 286 Pulse duration, SIACK high between DIO accesses (see Note 25) 287 Pulse duration, SIACK low on first pulse of two pulses 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX tc(SCK) tc(SCK) UNIT MAX tc(SCK) tc(SCK) ns ns NOTE 25: The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles. SRD, SWR, SCS 286 287 First SIACK Second ADVANCE INFORMATION Figure 21. 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse 80x8x interrupt-acknowledge-cycle timing: second SIACK pulse NO NO. 255 Delay time, SRDY low to SCS high 259† 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 15 15 ns Hold time, SAD in the high-impedance state after SIACK low (see Note 25) 0 0 ns 260 Setup time, output data valid before SRDY low 0 0 ns 261† Delay time, SIACK high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SIACK high (see Note 25) 272a Setup time, inactive data strobe high to SIACK no longer high 273a Hold time, inactive data strobe high after SIACK high 275 Delay time, SIACK high to SRDY high (see Note 25) 276‡ Delay time, SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following access to the SIF 279† Delay time, SIACK high to SRDY in the high-impedance state 0 0 0 tc(SCK) tc(SCK) / 2 + 4 ns Delay time, SDBEN low to SRDY low in a read cycle tc(SCK) tc(SCK) / 2 + 4 0 282a 282R Delay time, SIACK low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed 0 tc(SCK) + 3 0 tc(SCK) + 3 ns 35 0 35 0 tc(SCK) tc(SCK) ns tc(SCK) tc(SCK) 0 25 0 4000 ns ns ns 25 ns 4000 ns ns 283R Delay time, SIACK high to SDBEN high (see Note 25) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns † This specification is provided as an aid to board design. It is not assured during manufacturing. ‡ This specification has been characterized to meet stated value. It is not assured during manufacturing. NOTE 25: The inactive chip select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip select in interrupt-acknowledge cycles. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS, SRSX, SRS0 – SRS2, SBHE Only SCS needs to be inactive. All others are don’t care. SIACK 272a 273a 272a 273a 272a 273a SWR SRD SDDIR High 279 ADVANCE INFORMATION 282R 283R SDBEN 275 276 SRDY † 282a Hi-Z 255 Hi-Z 261 259 260 261a SADH0 – SADH7, Output Data Valid Hi-Z SADL0 – SADL7, SPH, SPL ‡ † SRDY is an active-low bus ready signal. It must be asserted before data output. ‡ In 8-bit 80x8x-mode DIO writes, the value placed on SADH0 – SADH7 is a don’t care. Hi-Z Figure 22. 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x-mode bus-arbitration timing, SIF takes control MIN 33-MHz OPERATION MAX MIN UNIT MAX 208a Setup time, asynchronous signal SBBSY and SHLDA before SBCLK no longer high to assure recognition on that cycle 10 10 ns 208b Hold time, asynchronous signal SBBSY and SHLDA after SBCLK low to assure recognition on that cycle 10 10 ns 212 Delay time, SBCLK low to SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid 224a Delay time, SBCLK low in cycle I2 to SOWN low 224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read 230 Delay time, SBCLK high to SHRQ high 241 Delay time, SBCLK high in TX cycle to SRD and SWR high, bus acquisition 241a† Hold time, SRD and SWR in the high-impedance state after SOWN low, bus acquisition 20 0 tc(SCK) – 15 20 ns 15 ns 28 23 ns 20 15 ns 25 25 ns 20 0 tc(SCK) – 15 ns ADVANCE INFORMATION 25-MHz OPERATION NO. † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 ADVANCE INFORMATION I1 I2 TX T1 SBCLK 208a SBBSY, SHLDA SIF Outputs: 208b 230 SHRQ 241 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SRD, SWR 241a 212 SBHE 212 SADH0 – SADH7, SADL0 – SADL7, SPH, SPL Address Valid 224c Write SDDIR Read 224a SOWN † † While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled. Figure 23. 80x8x-Mode Bus-Arbitration Timing, SIF Takes Control Template Release Date: 7–11–94 ( T4) SIF Inputs: SIF Master TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE Bus Exchange SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 54 User Master TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x-mode DMA read-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 205 Setup time, SADL0 – SADL7, SADH0 – SADH7, SPH, and SPL valid before SBCLK in T3 cycle no longer high 10 10 ns 206 Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 10 10 ns 207a Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH, and SPL valid after SRD high 0 0 ns 207b Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH, and SPL valid after SDBEN no longer low 0 0 ns 208a Setup time, asynchronous signal SRDY before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous signal SRDY after SBCLK low to assure recognition on this cycle 10 10 ns 212 Delay time, SBCLK low to address valid 20 20 ns 214† Delay time, SBCLK low in T1 cycle to SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in the high-impedance state 20 15 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 ns 216a Hold time, SALE or SXAL low after SRD high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid after SALE or SXAL low tw(SCKH) – 15 223R Delay time, SBCLK low in T4 cycle to SRD high (see Note 27) 225R Delay time, SBCLK low in T4 cycle to SDBEN high 226† Delay time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in the high-impedance state to SRD low 0 227R Delay time, SBCLK low in T2 cycle to SRD low 0 229† Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in the high-impedance state after SBCLK low in T1 cycle 0 0 ns 231 Pulse duration, SRD low 2tc(SCK) – 25 2tc(SCK) – 25 ns 233 Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid before SALE, SXAL no longer high 10 10 ns 237R Delay time, SBCLK high in the T2 cyle to SDBEN low 247 Setup time, data valid before SRDY low if parameter 208a not met 20 0 0 25 tc(SCK) / 2 – 4 16 0 tw(SCKH) – 15 0 16 ns 25 tc(SCK) / 2 – 4 0 16 0 ns ns 11 ns ns 15 11 0 ns 11 0 15 ADVANCE INFORMATION NO NO. ns ns ns † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. NOTE 27: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 ADVANCE INFORMATION T1 T3 T4 T1 SBCLK Hi-Z SRAS 212 SBHE † Valid High SWR 227R SRD ‡ 223R 218 216 217 217 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SXAL 226 216 216a SALE 212 233 SADH0–SADH7, SADL0–SADL7, SPH, SPL § 214 Address Extended Address 207a 205 233 218 212 206 Data 229 Address 247¶ 218 208a 207b SRDY 237R 208b 225R SDBEN † SDDIR Low † In 8-bit 80x8x mode, SBHE / SRNW is a don’t care input during DIO and an inactive (high) output during DMA. ‡ Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. § In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 221; i.e., held after T4 high. ¶ If parameter 208A is not met, then valid data must be present before SRDY goes low. Figure 24. 80x8x-Mode DMA Read-Cycle Timing Template Release Date: 7–11–94 TWAIT V T2 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE TX SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 56 T4 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x-mode DMA write-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 208a Setup time, asynchronous signal SRDY before SBCLK no longer high to assure recognition on that cycle 10 10 ns 208b Hold time, asynchronous signal SRDY after SBCLK low to assure recognition on that cycle 10 10 ns 212 Delay time, SBCLK low to SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid 20 20 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 20 ns 216a Hold time, SALE or SXAL low after SWR high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 219 Delay time, SBCLK low in T2 cycle to output data and parity valid 221 Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid after SWR high 223W Delay time, SBCLK low to SWR high 225W Delay time, SBCLK high in T4 cycle to SDBEN high 225WH Hold time, SDBEN low after SWR, SUDS, and SLDS high 227W Delay time, SBCLK low in T2 cycle to SWR low 233 Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid before SALE, SXAL no longer high 237W Delay time, SBCLK high in T1 cycle to SDBEN low tw(SCKH) – 15 0 25 tc(SCK) / 2 – 4 0 tw(SCKH) – 15 29 tc(SCK) – 12 0 tc(SCK) / 2 – 4 tc(SCK) – 12 16 tc(SCK) / 2 – 7 POST OFFICE BOX 1443 25 29 0 16 0 ns 10 0 • HOUSTON, TEXAS 77251–1443 ns 11 ns 11 ns ns 15 10 16 ns ns tc(SCK) / 2 – 7 20 ns ADVANCE INFORMATION NO NO. ns ns 11 ns 57 ADVANCE INFORMATION T3 T4 T1 SBCLK 212 SBHE † Valid High SRD 223W 227W SWR 216 217 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 217 SXAL 216 216a SALE 212 SADL0 – SADH7, SADH0 – SADL7, SPH, SPL ‡ 233 212 218 233 218 221 219 Address Output Data Extended Address 208a SRDY 225W 237W 208b SDBEN SDDIR 225WH High † In 8-bit 80x8x mode, SBHE / SRNW is a don’t care input during DIO and an inactive (high) output during DMA. ‡ In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 221; i.e., held after T4 high. § In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever the increment of the DMA address register carries beyond the least significant 16 bits. Figure 25. 80x8x-Mode DMA Write-Cycle Timing Template Release Date: 7–11–94 TWAIT V T2 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE T1 SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 58 TX§ T4 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x-mode bus-arbitration timing, SIF returns control 25-MHz OPERATION NO. MIN 33-MHz OPERATION MAX MIN UNIT MAX 220† Delay time, SBCLK low in I1 cycle to SADH0 – SADH7, SADL0 – SADL7, SPL, SPH, SRD, and SWR in the high-impedance state 35 35 ns 223b† Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state 45 45 ns 224b Delay time, SBCLK low in cycle I2 to SOWN high 15 ns 224d Delay time, SBCLK low in cycle I2 to SDDIR high 27 22 ns 230 Delay time, SBCLK high in cycle I1 to SHRQ low 20 15 ns 240† Setup time, SRD, SWR, and SBHE in the high-impedance state before SOWN no longer low 0 20 0 0 0 ns † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. T3 Bus Exchange T4 I1 User Master I2 (T1) ADVANCE INFORMATION SIF Master (T2) SBCLK SHLDA SIF Outputs: 230 SHRQ ‡ 220 SRD, SWR Hi-Z 240 223b SBHE SIF Hi-Z 240 220 SADH0 – SADH7, SADL0 – SADL7, SPH, SPL Hi-Z SIF 224d Write SDDIR Read 224b SOWN § ‡ In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus-transfer it controls. § While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled. Figure 26. 80x8x-Mode Bus-Arbitration Timing, SIF Returns Control POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 80x8x-mode bus-release timing 25-MHz OPERATION NO. MIN MAX 33-MHz OPERATION MIN UNIT MAX 208a Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure recognition 10 10 ns 208b Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition 10 10 ns 208c Hold time, SBRLS low after SOWN high 0 0 ns T(W or 2) T3 T4 T1 T2 SBCLK † 208a SBRLS ‡ 208b ADVANCE INFORMATION SOWN 208c † Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition. ‡ The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system interface releases the bus before starting another. Figure 27. 80x8x-Mode Bus-Release Timing 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx DIO read-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 255 Delay time, SDTACK low to either SCS, SUDS, or SLDS high 15 15 ns 259† Hold time, SAD in the high-impedance state after SUDS or SLDS low (see Note 25) 0 0 ns 260 Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL valid before SDTACK low 0 0 ns 261† Delay time, SCS, SUDS, or SLDS high to SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in the high-impedance state (see Note 25) 261a Hold time, output data valid after SUDS or SLDS no longer low (see Note 25) 0 0 ns 267 Setup time, register address before SUDS or SLDS no longer high (see Note 25) 15 15 ns 268 Hold time, register address valid after SUDS or SLDS no longer low (see Note 26) 0 0 ns 272 Setup time, SRNW before SUDS or SLDS no longer high (see Note 25) 12 12 ns 273 Hold time, SRNW after SUDS or SLDS high 0 ns 273a Hold time, SIACK high after SUDS or SLDS high 275 Delay time, SCS, SUDS, or SLDS high to SDTACK high (see Note 25) 276‡ Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 279† Delay time, SUDS or SLDS high to SDTACK in the high-impedance state 0 tc(SCK) 0 tc(SCK) ns 282a Delay time, SDBEN low to SDTACK low 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns 282R Delay time, SUDS or SLDS low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, SPWU005, subsection 3.4.1.1.1), provided the previous cycle completed 0 tc(SCK) + 3 0 tc(SCK) + 3 ns 283R Delay time, SUDS or SLDS high to SDBEN high (see Note 25) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns 286 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 26) 35 0 tc(SCK) 35 tc(SCK) 0 25 0 4000 tc(SCK) tc(SCK) ns ns 25 ns 4000 ns ns † This specification is provided as an aid to board design. It is not assured during manufacturing testing. ‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing. NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 ADVANCE INFORMATION NO NO. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS, SRSX, SRS0, SRS1 Valid 267 268 SIACK 273a SRNW 272 273 SUDS, SLDS 286 SDDIR High 279 282R ADVANCE INFORMATION 283R SDBEN 276 SDTACK † Hi-Z 275 282a 255 Hi-Z 261 259 260 261a SADH0 – SADH7, SADL0 – SADL7, Output Data Valid Hi-Z SPH, SPL † SDTACK is an active-low bus-ready signal. It must be asserted before data output. Figure 28. 68xxx DIO Read-Cycle Timing 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Hi-Z TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx DIO write-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 255 Delay time, SDTACK low to either SCS, SUDS or SLDS high 15 15 ns 262 Setup time, write data valid before SUDS or SLDS no longer low 15 15 ns 263 Hold time, write data valid after SUDS or SLDS high 15 15 ns 267† Setup time, register address before SUDS or SLDS no longer high (see Note 25) 15 15 ns 268 Hold time, register address valid after SUDS or SLDS no longer low (see Note 26) 0 0 ns 272 Setup time, SRNW before SUDS or SLDS no longer high (see Note 25) 12 12 ns 272a Setup time, inactive SUDS or SLDS high to active data strobe no longer high tc(SCK) tc(SCK) ns 273 Hold time, SRNW after SUDS or SLDS high 273a Hold time, inactive SUDS or SLDS high after active data strobe high 275 Delay time, SCS, SUDS or SLDS high to SDTACK high (see Note 25) 276‡ Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 279§ Delay time, SUDS or SLDS high to SDTACK in the high-impedance state 0 tc(SCK) 0 tc(SCK) ns 280 Delay time, SUDS or SLDS low to SDDIR low (see Note 25) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns If SIF register is ready (no waiting required) 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 282b Delay time, SDBEN low to SDTACK low ((see TMS380 Second Generation TokenRing User’s Guide, SPWU005, subsection 3.4.1.1.1) If SIF register is not ready (waiting required) 0 4000 0 4000 tc(SCK) / 2 + 4 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 tc(SCK) / 2 + 4 0 0 tc(SCK) ns tc(SCK) 0 25 0 4000 ns 25 ns 4000 ns ns 282W Delay time, SDDIR low to SDBEN low 0 283W Delay time, SUDS or SLDS high to SDBEN no longer low 0 286 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 25) tc(SCK) 0 tc(SCK) ns ns ns † It is the later of SRD and SWR or SCS low that indicates the start of the cycle. ‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing. § This specification is provided as an aid to board design. It is not assured during manufacturing testing. NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 ADVANCE INFORMATION NO NO. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS SRSX, SRS0, SRS1 Valid 267 268 SIACK 273a 272 273 SRNW 286 272a SUDS, SLDS † 273a 280 SDDIR High ADVANCE INFORMATION 282W 283W SDBEN ‡ 279 276 275 255 SDTACK § Hi-Z 282b Hi-Z 263 262 SADH0 – SADH7, SADL0 – SADL7, Hi-Z Data Hi-Z SPH, SPL † For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events referenced to a data strobe edge use the later occurring edge. Events defined by two data strobes, edges, such as parameter 286, are measured between latest and earlier edges. ‡ When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. § SDTACK is an active-low bus ready signal. It must be asserted before data output. Figure 29. 68xxx DIO Write-Cycle Timing 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx interrupt-acknowledge-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 255 Delay time, SDTACK low to either SCS or SUDS, or SIACK high 15 15 ns 259† Hold time, SAD in the high-impedance state after SIACK no longer high (see Note 25) 0 0 ns 260 Setup time, output data valid before SDTACK no longer high 0 0 ns 261† Delay time, SIACK high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SCS or SIACK no longer low (see Note 25) 267§ Setup time, register address before SIACK no longer high (see Note 25) 272a Setup time, inactive high SIACK to active data strobe no longer high 273a Hold time, inactive SRNW high after active data strobe high 275 Delay time, SCS or SRNW high to SDTACK high (see Note 25) 276‡ Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 0 4000 279† Delay time, SIACK high to SDTACK in the high-impedance state 0 282a Delay time, SDBEN low to SDTACK low in a read cycle 282R Delay time, SIACK low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, SPWU005, subsection 3.4.1.1.1), provided the previous cycle completed 283R Delay time, SIACK high to SDBEN high (see Note 25) 286 Pulse duration, SIACK high between DIO accesses (see Note 25) 35 35 ns 0 0 ns 15 15 ns tc(SCK) tc(SCK) ns tc(SCK) 0 25 tc(SCK) 0 ns 25 ns 0 4000 ns 0 0 tc(SCK) tc(SCK) / 2 + 4 ns 0 tc(SCK) tc(SCK) / 2 + 4 0 tc(SCK) + 3 0 tc(SCK) + 3 ns ns 0 tc(SCK) / 2 + 4 0 tc(SCK) / 2 + 4 ns tc(SCK) tc(SCK) ns † This specification is provided as an aid to board design. It is not assured during manufacturing testing. ‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing. § It is the later of SRD and SRD or SCS low that indicates the start of the cycle. NOTE 25: The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 ADVANCE INFORMATION NO NO. TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 SCS, SRSX, SRS0, SRS1, SBHE Only SCS needs to be Inactive. All others are don’t care. 267 SIACK 286 272a SRNW 273a SLDS 286 SDDIR High 279 282R ADVANCE INFORMATION 283R SDBEN 275 276 282a Hi-Z SDTACK † 259 255 Hi-Z 261 260 261a SADH0 – SADH7, SADL0 – SADL7, SPH, SPL ‡ Hi-Z Output Data Valid Hi-Z † SDTACK is an active-low bus ready signal. It must be asserted before data output. ‡ Internal logic drives SDTACK high and verifies that it has reached a valid-high level before making it a 3-state signal. Figure 30. 68xxx Interrupt-Acknowledge-Cycle Timing 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx-mode bus-arbitration timing, SIF takes control NO. 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX UNIT MAX 208a Setup time, asynchronous input SBGR before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SBGR after SBCLK low to assure recognition on this cycle 10 10 ns 212 Delay time, SBCLK low to address valid 0 20 0 20 ns 224a Delay time, SBCLK low in cycle I2 to SOWN low (see Note 28) 0 20 0 15 ns 224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read 28 23 ns 230 Delay time, SBCLK high to either SHRQ low or SBRQ high 20 15 ns 241 Delay time, SBCLK high in TX cycle to SUDS and SLDS high 25 25 ns 241a Hold time, SUDS, SLDS, SRNW, and SAS in the high-impedance state after SOWN low, bus aquisition tc(SCK–15) tc(SCK–15) ns POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE INFORMATION † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. NOTE 28: Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. 67 ADVANCE INFORMATION SIF Master I2 TX T1 T2 SBCLK 208b 208a SBGR SBERR, SDTACK, SBBSY SIF Outputs: 230 230 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SBRQ † 208a 208b SAS, SLDS, SUDS 241 Output Input 241 Read SRNW Write SADH0 – SADH7, SADL0 – SADL7, SPH, SPL 212 Hi-Z SIF 224c Write SDDIR Read 224a SOWN ‡ 241a † In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer it controls. ‡ While the system-interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled. Figure 31. 68xxx-Mode Bus-Arbitration Timing, SIF Takes Control Template Release Date: 7–11–94 I1 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE SIF Inputs: Bus Exchange ( T4) SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68 User Master TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx-mode DMA read-cycle timing MIN MAX 33-MHz OPERATION MIN MAX UNIT 205 Setup time, input data valid before SBCLK in T3 cycle no longer high 10 10 ns 206 Hold time, input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 10 10 ns 207a Hold time, input data valid after data strobe no longer low 0 0 ns 207b Hold time, input data valid after SDBEN no longer low 0 0 ns 208a Setup time, asynchronous input SDTACK before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SDTACK after SBCLK low to assure recognition on this cycle 10 10 ns 209 Pulse duration, SAS, SUDS, and SLDS high 210 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active 16 11 ns 212 Delay time, SBCLK low to address valid 20 20 ns 214† Delay time, SBCLK low in T2 cycle to SAD high impedance 20 15 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 20 ns 216a Hold time, SALE or SXAL low after SUDS and SAS high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 222 Delay time, SBCLK high to SAS low 223R Delay time, SBCLK low in T4 cycle to SUDS, SLDS, and SAS high (see Note 27) 225R Delay time, SBCLK low in T4 cycle to SDBEN high 229† Hold time, SAD in the high-impedance state after SBCLK low in T4 cycle 0 0 ns 233 Setup time, address valid before SALE or SXAL no longer high 10 10 ns 233a Setup time, address valid before SAS no longer high 237R Delay time, SBCLK high in the T2 cycle to SDBEN low 247 Setup time, data valid before SDTACK low if parameter 208a not met tc(SCK)+ tw(SCKL) – 18 tw(SCKH) – 15 0 tc(SCK)+ tw(SCKL) – 18 ns 0 25 tc(SCK) / 2 – 4 20 16 0 tw(SCKH) – 15 0 16 tw(SCKL) – 15 ns 25 tc(SCK) / 2 – 4 15 0 ns ns ns 11 ns ns 11 0 ns 11 tw(SCKL) – 15 16 ADVANCE INFORMATION 25-MHz OPERATION NO NO. ns ns † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. NOTE 27: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 ADVANCE INFORMATION T1 S1 T2 S2 S3 T3 S4 S5 T4 S6 T1 S7 SBCLK 222 SAS † 209 223R 210 SUDS, SLDS 209 218 217 High POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SRNW 217 216 SXAL 216 218 216a SALE 229 212 233a 212 233 SADL0 – SADH7, SADH0 – SADL7, SPH, SPL 233 206 205 214 207a Address Data In 247‡ Extended Address Hi-Z 207b 208a SDTACK §¶ 208b SDDIR 237R 225R SDBEN † † On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data may be removed when either the read strobe or SDBEN becomes no longer active. ‡ If parameter 208a is not met, then valid data must be present before SDTACK goes low. § Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. ¶ All VSS pins should be routed to minimize inductance to system ground. Figure 32. 68xxx-Mode DMA Read-Cycle Timing Template Release Date: 7–11–94 TX TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE T4 SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 70 TWAIT V TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx-mode DMA write-cycle timing 25-MHz OPERATION 33-MHz OPERATION MIN MIN MAX MAX UNIT 208a Setup time, asynchronous input SDTACK before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SDTACK after SBCLK low to assure recognition on this cycle 10 10 ns 209 Pulse duration, SAS, SUDS, and SLDS high 211 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active 211a Delay time, output data valid to SUDS and SLDS no longer high 212 Delay time, SBCLK low to address valid 20 20 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 20 ns 216a Hold time, SALE or SXAL low after SUDS and SAS high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 219 Delay time, SBCLK low in T2 cycle to output data and parity valid 221 Hold time, output data, parity valid after SUDS and SLDS high 222 Delay time, SBCLK high to SAS low 223W Delay time, SBCLK low to SUDS, SLDS, and SAS high 225W Delay time, SBCLK high in T4 cycle to SDBEN high 225WH Hold time, SDBEN low after SUDS and SLDS high 233 Setup time, address valid before SALE or SXAL no longer high 233a Setup time, address valid before SAS no longer high 237W Delay time, SBCLK high in T1 cycle to SDBEN low tc(SCK)+ tw(SCKL) – 18 tc(SCK)+ tw(SCKL) – 18 25 tw(SCKL) – 15 tw(SCKH) – 15 25 tw(SCKL) – 15 25 tc(SCK) / 2 – 4 0 tw(SCKH) – 15 tc(SCK) – 12 25 tc(SCK) / 2 – 4 tc(SCK) – 12 16 0 16 tc(SCK) / 2 – 7 • HOUSTON, TEXAS 77251–1443 ns ns 11 ns 11 ns ns ns tw(SCKL) – 15 16 ns 15 10 tw(SCKL) – 15 ns ns tc(SCK) / 2 – 7 10 POST OFFICE BOX 1443 ns 29 20 ns ns 0 29 0 ns ADVANCE INFORMATION NO NO. ns 11 ns 71 ADVANCE INFORMATION T2 T3 T4 T1 SBCLK 222 211 223W SAS 209 233a SUDS, SLDS 218 216 211a 217 SRNW POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Low 217 218 SXAL 216 216a SALE 212 212 233 233 221 219 SADL0 – SADH7, SADH0 – SADL7, SPL, SPH Address Output Data Extended Address 208a SDTACK †‡ 208b 225W SDDIR 237W 225WH SDBEN † All VSS terminals should be routed to minimize inductance to system ground. ‡ On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN becomes no longer active. § In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever the increment of the DMA address register carries beyond the least significant 16 bits. Figure 33. 68xxx-Mode DMA Write-Cycle Timing Template Release Date: 7–11–94 T1 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE TX§ T4 SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 72 TWAIT V TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx-mode bus-arbitration timing, SIF returns control 25-MHz OPERATION NO. MIN MAX 25-MHz OPERATION MIN UNIT MAX 220† Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the high-impedance state, bus release 35 35 ns 223b† Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state 45 45 ns 224b Delay time, SBCLK low in cycle I2 to SOWN high 15 ns 224d Delay time, SBCLK low in cycle I2 to SDDIR high 27 22 ns 230 Delay time, SBCLK high to either SHRQ low or SBRQ high 20 15 ns 240† Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance state before SOWN no longer low 0 0 20 0 0 ns ADVANCE INFORMATION † This specification has been characterized to meet stated value. It is not assured during manufacturing testing. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 ADVANCE INFORMATION User T1 I2 SBCLK SBGR SDTACK SIF Outputs: 230 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SBRQ † 220 240 SAS, SUDS, SLDS 240 223b Read Hi-Z SRNW Write 220 SADH0 – SADH7, SADL0 – SADL7, SPH, SPL SIF Hi-Z 224d Write SDDIR Read 224b SOWN † In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer it controls. Figure 34. 68xxx-Mode Bus-Arbitration Timing, SIF Returns Control Template Release Date: 7–11–94 Bus Exchange I1 T4 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL LAYER INTERFACE SIF Inputs: T3 SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 74 SIF Master T2 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 68xxx-mode bus-release and error timing 25-MHz OPERATION NO. MIN MAX 33-MHz OPERATION MIN UNIT MAX 208a Setup time, asynchronous input before SBCLK no longer high to assure recognition 10 10 ns 208b Hold time, asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to assure recognition 10 10 ns 208c Hold time, SBRLS low after SOWN high 0 0 ns 236 Setup time, SBERR low before SDTACK no longer high if parameter 208a not met 30 30 ns T(W or 2) T3 T4 T1 T2 SBCLK † 208a 208b SOWN 208c 208a SBERR § 236 SDTACK † Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition. ‡ The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of SBRLS, it completes any internally-started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system interface releases the bus before starting another. § If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed, regardless of the value of SDTACK. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface then releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA-bus cycle on the system bus. When SBERR is properly asserted and BERETRY is zero, however, the system interface releases the bus upon completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not defined after a system-bus error. Figure 35. 68xxx-Mode Bus-Release and Error Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 75 ADVANCE INFORMATION 208b SBRLS ‡ TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 T1 T(W or 2) T3 TH T4 T1 SBCLK SDTACK SBERR SHALT Figure 36. 68xxx-Mode Bus Halt and Retry, Normal Completion With Delayed Start † † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown. ADVANCE INFORMATION T1 T2 T3 T4 THB THE T1 SBCLK SDTACK SBERR SHALT SOWN Figure 37. 68xxx-Mode Bus Halt and Retry, Rerun Cycle With Delayed Start † † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown. 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TI380C30 INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS016A – NOVEMBER 1994 – REVISED JULY 1995 MECHANICAL DATA PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 132 89 88 133 0,27 0,17 0,08 M ADVANCE INFORMATION 0,50 0,13 NOM 176 45 1 44 Gage Plane 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040134 / B 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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