SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
FEATURES
D Industry-Standard Pin-Out
D Enable Functions for Each Driver
D High Current Drive Capability of ±4 A
D Unique BiPolar and CMOS True Drive Output
D
D
D
D
D
D
D
DESCRIPTION
The UCC27423/4/5 family of high-speed dual MOSFET
drivers can deliver large peak currents into capacitive
loads.Three standard logic options are offered –
dual-inverting, dual-noninverting and one-inverting and
one-noninverting driver. The thermally enhanced 8-pin
PowerPADTM MSOP package (DGN) drastically lowers
the thermal resistance to improve long-term reliability.
It is also offered in the standard SOIC-8 (D) or PDIP-8
(P) packages.
Stage Provides High Current at MOSFET
Miller Thresholds
TTL/CMOS Compatible Inputs Independent of
Supply Voltage
20-ns Typical Rise and 15-ns Typical Fall
Times with 1.8-nF Load
Typical Propagation Delay Times of 25 ns with
Input Falling and 35 ns with Input Rising
4-V to 15-V Supply Voltage
Dual Outputs Can Be Paralleled for Higher
Drive Current
Available in Thermally Enhanced MSOP
PowerPADTM Package with 4.7°C/W θjc
Rated From –40°C to 105°C
APPLICATIONS
D Switch Mode Power Supplies
D DC/DC Converters
D Motor Controllers
D Line Drivers
D Class D Switching Amplifiers
Using a design that inherently minimizes shoot-through
current, these drivers deliver 4-A of current where it is
needed most at the Miller plateau region during the
MOSFET switching transition. A unique BiPolar and
MOSFET hybrid output stage in parallel also allows
efficient current sourcing and sinking at low supply
voltages.
The UCC27423/4/5 provides enable (ENBL) functions
to have better control of the operation of the driver
applications. ENBA and ENBB are implemented on pins
1 and 8 which were previously left unused in the industry
standard pin-out. They are internally pulled up to Vdd for
active high logic and can be left open for standard
operation.
BLOCK DIAGRAM
8
ENBB
7
OUTA
6
VDD
5
OUTB
ENBA 1
INVERTING
INA 2
VDD
NON−INVERTING
INVERTING
GND 3
INB 4
NON−INVERTING
UDG−01063
PowerPADt is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
Copyright 2003, Texas Instruments Incorporated
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1
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
ORDERING INFORMATION
OUTPUT
CONFIGURATION
TEMPERATURE RANGE
TA = TJ
PACKAGED DEVICES
SOIC-8 (D)
MSOP-8 PowerPAD
(DGN)}
PDIP-8 (P)
Dual inverting
−40°C to +105°C
UCC27423D
UCC27423DGN
UCC27423P
Dual nonInverting
−40°C to +105°C
UCC27424D
UCC27424DGN
UCC27424P
One inverting,
one noninverting
−40°C to +105°C
UCC27425D
UCC27425DGN
UCC27425P
† D (SOIC−8) and DGN (PowerPAD−MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,
UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
‡ The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which
is the ground of the device.
D, DGN, OR P PACKAGE
(TOP VIEW)
D, DGN, OR P PACKAGE
(TOP VIEW)
D, DGN, OR P PACKAGE
(TOP VIEW)
UCC27425
UCC27424
UCC27423
ENBA 1
8 ENBB
ENBA 1
8 ENBB
ENBA 1
8 ENBB
INA 2
7 OUTA
INA 2
7 OUTA
INA 2
7 OUTA
GND 3
6 VDD
INB 4
GND 3
5 OUTB
6 VDD
INB 4
(DUAL INVERTING)
GND 3
5 OUTB
6 VDD
INB 4
(DUAL NON−INVERTING)
5 OUTB
(ONE INVERTING AND
ONE NON−INVERTING)
power dissipation rating table
PACKAGE
SUFFIX
Θjc (°C/W)
Θja (°C/W)
Power Rating (mW)
TA = 70°C See Note 1
Derating Factor Above
70°C (mW/5C) See
Note 1
SOIC-8
D
42
84 – 160}
344−655 See Note 2
6.25 − 11.9 See Note 2
PDIP-8
P
49
110
500
9
MSOP PowerPAD-8
See Note 3
DGN
4.7
50 − 59}
1370
17.1
Notes: 1. 125°C operating junction temperature is used for power rating calculations
2. The range of values indicates the effect of pc−board. These values are intended to give the system designer an indication of the
best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc−board where possible
in order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to Technical
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made
Easy, Texas Instruments Literature No. SLMA004.
3. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
Table 1. Input/Output Table
INPUTS (VIN_L, VIN_H)
2
ENBA
ENBB
INA
H
H
H
H
H
UCC27423
UCC27424
INB
OUTA
OUTB
OUTA
L
L
H
H
L
H
H
L
H
H
L
L
H
H
H
H
L
L
X
X
UCC27425
OUTB
OUTA
L
L
H
L
L
H
H
H
H
H
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
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OUTB
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
Output current (OUTA, OUTB) DC, IOUT_DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 A
Pulsed, (0.5 µs), IOUT_PULSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A
Input voltage (INA, INB), VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V or VDD+0.3 (whichever is larger)
Enable voltage (ENBA, ENBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V or VDD+0.3 (whichever is larger)
Power dissipation at TA = 25°C (DGN package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W
(D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
(P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mW
Junction operating temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature (soldering, 10 sec.), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V, TA = −40°C to 105°C,TA = TJ, (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Input (INA, INB)
VIN_H, logic 1 input threshold
2
V
VIN_L, logic 0 input threshold
Input current
0 V <= VIN <= VDD
−10
1
V
10
µA
330
450
mV
22
40
mV
30
35
Ω
45
Ω
2.5
Ω
4.0
Ω
0
Output (OUTA, OUTB)
Output current
VOH, high-level output voltage
VOL, low-level output level
Output resistance high
Output resistance low
Latch-up protection
VDD = 14 V,
See Note 1,
VOH = VDD – VOUT,
See Note 2
4
IOUT = −10 mA
IOUT = 10 mA
TA = 25°C,
See Note 3
IOUT = −10 mA,
VDD = 14 V,
25
TA = full range,
See Note 3
IOUT = −10 mA,
VDD = 14 V,
18
TA = 25°C,
See Note 3
IOUT = 10 mA,
VDD = 14 V,
1.9
TA = full range
See Note 3
IOUT = 10 mA,
VDD = 14 V,
1.2
See Note 1
500
2.2
A
mA
NOTES: 1. Ensured by design. Not tested in production.
2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of
the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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3
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V, TA = −40°C to 105°C,TA = TJ, (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
CLOAD = 1.8 nF,(1)
CLOAD = 1.8 nF,(1)
20
40
15
40
CLOAD = 1.8 nF,(1)
CLOAD = 1.8 nF,(1)
25
40
35
50
2.4
2.9
UNITS
Switching Time
tR, rise time (OUTA, OUTB)
tF, fall time (OUTA, OUTB)
tD1, delay, IN rising (IN to OUT)
tD2, delay, IN falling (IN to OUT)
ns
Enable (ENBA, ENBB)
VIN_H, high-level input voltage
VIN_L, low-level input voltage
LO to HI transition
1.7
HI to LO transition
Hysteresis
RENBL, enable impedance
tD3, propagation delay time(4)
tD4, propagation delay time(4)
VDD = 14 V,
CLOAD = 1.8 nF(1)
CLOAD = 1.8 nF(1)
ENBL = GND
INA = 0 V,
INA = 0 V,
1.1
1.8
2.2
0.15
0.55
0.90
75
100
140
30
60
100
150
INB = 0 V
900
1350
INB = HIGH
750
1100
INA = HIGH,
INB = 0 V
750
1100
INA = HIGH,
INB = HIGH
600
900
INA = 0 V,
INB = 0 V
300
450
INA = 0 V,
INB = HIGH
750
1100
INA = HIGH,
INB = 0 V
750
1100
INA = HIGH,
INB = HIGH
1200
1800
INA = 0 V,
INB = 0 V
600
900
INA = 0 V,
INB = HIGH
1050
1600
INA = HIGH,
INB = 0 V
450
700
INA = HIGH,
INB = HIGH
900
1350
INA = 0 V,
INB = 0 V
300
450
INA = 0 V,
INB = HIGH
450
700
INA = HIGH,
INB = 0 V
450
700
INA = HIGH,
INB = HIGH
600
900
V
V
kΩ
ns
Overall
UCC27423
IDD, static operating current,
VDD = 15 V,
ENBA = ENBB = 15 V
UCC27424
UCC27425
IDD, disabled, VDD = 15 V,
ENBA = ENBB = 0 V
All
µA
A
NOTES: 1. Ensured by design. Not production.
2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors.
3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of
the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
4. See Figure 2.
4
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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
(a)
(b)
+5V
90%
90%
INPUT
INPUT
10%
10%
0V
tD1
tf
tD2
tF
90%
90%
tF
tF
16V
90%
tD1
OUTPUT
tD2
OUTPUT
10%
10%
0V
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5V
ENBx
VIN_L
VIN_H
0V
tD3
tD4
VDD
90%
90%
tR
OUTx
tF
10%
0V
Figure 2. Switching Waveform for Enable to Output
NOTE:
The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the
power MOSFET transition through the Miller regions of operation.
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5
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
Terminal Functions
TERMINAL
FUNCTION
NO.
NAME
I/O
1
ENBA
I
Enable input for the driver A with logic compatible threshold and hysteresis. The driver
output can be enabled and disabled with this pin. It is internally pulled up to VDD with
100-kΩ resistor for active high operation. The output state when the device is disabled
will be low regardless of the input state.
2
INA
I
Input A. Input signal of the A driver which has logic compatible threshold and hysteresis.
If not used, this input should be tied to either VDD or GND. It should not be left floating.
3
GND
−
Common ground. This ground should be connected very closely to the source of the
power MOSFET which the driver is driving.
4
INB
I
Input B. Input signal of the A driver which has logic compatible threshold and hysteresis.
If not used, this input should be tied to either VDD or GND. It should not be left floating.
5
OUTB
O
Driver output B. The output stage is capable of providing 4-A drive current to the gate of
a power MOSFET.
6
VDD
I
Supply. Supply voltage and the power input connection for this device.
7
OUTA
O
Driver output A. The output stage is capable of providing 4-A drive current to the gate of
a power MOSFET.
8
ENBB
I
Enable input for the driver B with logic compatible threshold and hysteresis. The driver
output can be enabled and disabled with this pin. It is internally pulled up to VDD with
100-kΩ resistor for active high operation. The output state when the device is disabled
will be low regardless of the input state.
APPLICATION INFORMATION
General Information
High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family.
A leading application is the need to provide a high power buffer stage between the PWM output of the control
IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is
utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also
have the need to simultaneously drive multiple devices which can present an extremely large load to the control
circuitry.
Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire
to minimize the effect of high frequency switching noise by placing the high current driver physically close to
the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers
at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the
UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external
driver can help by moving the heat from the controller to an external package.
6
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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
Input Stage
The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages; yet it is equally compatible
with 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse
current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal
with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input
signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages
to the drivers function as a digital gate, and they are not intended for applications where a slow changing input
voltage is used to generate a switching output when the logic threshold of the input section is reached. While
this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal
at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power
device, then an external resistance can be added between the output of the driver and the load device, which
is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the
devoce package, as discussed in the section on Thermal Considerations.
Output Stage
Inverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel
MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external
N-channel MOSFETs.
Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The
pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance
is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage
of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot
due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes
are not required.
The UCC27423 family delivers 4-A of gate drive where it is most needed during the MOSFET switching
transition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFET
hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFET
during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. [1]
Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied
at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where
the current peaked up and then settled down to a steady-state value. The noted current measurements are
made at a time of 200 ns after the input pulse is applied, after the initial transient.
The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped
around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to
sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V.
VDD
UCC27423
ENBA
INPUT
1
2
3
4
ENBB
INA
GND
INB
OUTA
VDD
OUTB
8
DSCHOTTKY
10 Ω
7
C2
1 µF
6
5
C3
100 µF
+
VSUPPLY
5.5 V
VSNS
1 µF
CER
100 µF
AL EL
RSNS
0.1 Ω
UDG−01065
Figure 3.
8
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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V
with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V.
VDD
UCC27423
ENBA
1
ENBB
INPUT
2
INA
OUTA
3 GND
4
8
DSCHOTTKY
C2
1 µF
VDD 6
INB
OUTB
10 Ω
7
5
C3
100µF
+
DADJ
5.5 V
VSNS
1 µF
CER
100µF
AL EL
RSNS
0.1Ω
UDG−01066
Figure 4.
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients
which may turn the device back ON.
Parallel Outputs
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in
Figure 4.
VDD
INPUT
UCC27423
ENBA
1
ENBB
2
INA
3 GND
4
INB
OUTA
8
7
VDD 6
OUTB
CLOAD
5
1 µF
CER
2.2µF
UDG−01067
Figure 5.
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9
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
Operational Waveforms and Circuit Layout
Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.
The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear
rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the
driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.
Figure 6.
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.
It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground
on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load
with copper trace as wide as possible. These connections should also be made with a small enclosed loop area
to minimize the inductance.
VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from:
IOUT = Qg x f, where f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise
problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should
be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively
low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel
combination of capacitors should present a low impedance characteristic for the expected current levels in the
driver application.
10
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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
Drive Current and Power Requirements
The UCC27423/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of
several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the
device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating
frequency of the power device. A MOSFET is used in this discussion because it is the most common type of
switching device used in high frequency power conversion equipment.
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.
When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that
is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
E + 1 CV 2, where C is the load capacitor and V is the bias voltage feeding the driver.
2
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
P+2
1 CV 2f, where f is the switching frequency.
2
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as:
P = 10 nF x (12)2 x (300 kHz) = 0.432 W
With a 12-V supply, this would equate to a current of:
I + P + 0.432 W + 0.036 A
V
12 V
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the
IDD current that is due to the IC internal consumption should be considered. With no load the IC current draw
is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to
that expected.
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11
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance
plus the added charge needed to swing the drain of the device between the ON and OFF states. Most
manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, one can determine the power that must be
dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following
equation for power:
P+C
V2
f + Qg
f
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate
at a specific bias voltage.
Enable
UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs
incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100-kΩ
resistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when
ENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver
and therefore can be left open for standard operation. The output states when the drivers are disabled is low
regardless of the input state. See the truth table of Table 1 for the operation using enable logic.
Enable input are compatible with both logic signals and slow changing analog signals. They can be directly
driven or a power−up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and
ENBB control input A and input B respectively.
12
www.ti.com
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
THERMAL INFORMATION
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range
the package must allow for the efficient removal of the heat produced while keeping the junction temperature
within rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a range
of application requirements.
As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power
rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also
given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,
switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer
a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the Θjc down to 4.7°C/W. Data is presented in Reference 3
to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the
standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over
that available in the D or P packages, and is shown to more than double the power capability of the D and P
packages. Note that the PowerPAD is not directly connected to any leads of the package. However, it is
electrically and thermally connected to the substrate which is the ground of the device.
References
1. Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFET
Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive
Circuits, by Bill Andreycak, Texas Instruments Literature No. SLUA105
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
4. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
Related Products
Product
Description
Packages
UCC37323/4/5
Dual 4-A Low-Side Drivers
MSOP-8 PowerPAD, SOIC-8, PDIP-8
UCC37321/2
Single 9-A Low-Side Driver with Enable
MSOP-8 PowerPAD, SOIC-8, PDIP-8
TPS2811/12/13
Dual 2-A Low-Side Drivers with Internal Regulator
TSSOP-8, SOIC-8, PDIP-8
TPS2814/15
Dual 2-A Low-Side Drivers with Two Inputs per Channel
TSSOP-8, SOIC-8, PDIP-8
TPS2816/17/18/19
Single 2-A Low-Side Driver with Internal Regulator
5-Pin SOT−23
TPS2828/29
Single 2-A Low-Side Driver
5-Pin SOT−23
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13
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY (VDD = 8.0 V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 4.5 V)
100
80
80
10 nF
IDD − Supply Current − mA
IDD − Supply Current − mA
100
60
4.7 nF
40
2.2 nF
20
10 nF
4.7 nF
60
40
2.2 nF
1 nF
20
1 nF
470 pF
0
0
470 pF
0
500 K
1M
1.5 M
0
2M
1M
f - Frequency − Hz
Figure 7
Figure 8
2M
SUPPLY CURRENT
vs
FREQUENCY (VDD = 15 V)
150
100
10 nF
IDD − Supply Current − mA
200
4.7 nF
2.2 nF
50
1 nF
150
10 nF
4.7 nF
100
2.2 nF
50
1 nF
470 pF
470 pF
0
0
0
500 K
1M
1.5 M
2M
f - Frequency − Hz
0
500 K
1M
f - Frequency − Hz
Figure 9
14
1.5 M
f - Frequency − Hz
SUPPLY CURRENT
vs
FREQUENCY (VDD = 12 V)
IDD − Supply Current − mA
500 K
Figure 10
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1.5 M
2M
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (CLOAD = 4.7 nF)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (CLOAD = 2.2 nF)
90
160
80
140
2 MHz
IDD − Supply Current − mA
IDD − Supply Current − mA
70
60
50
1 MHz
40
30
500 kHz
20
120
2 MHz
100
1 MHz
80
60
500 kHz
40
200 kHz
200 kHz
20
10
100 kHz
100/50 kHz
0
50/20 kHz
0
6
4
8
12
10
14
16
4
9
VDD − Supply Voltage − V
Figure 11
19
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27423)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27424)
0.9
0.60
0.8
0.55
Input = VDD
Input = VDD
VDD − Supply Voltage − V
IDD − Supply Current − mA
14
VDD − Supply Voltage − V
0.7
0.6
0.5
0.4
0.50
Input = 0 V
0.45
0.40
0.35
Input = 0 V
0.3
0.30
4
6
8
10
12
14
16
VDD − Supply Voltage − V
Figure 13
4
6
8
10
12
VDD − Supply Voltage − V
14
16
Figure 14
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15
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
RISE TIME/FALL TIME
vs
TEMPERATURE (UCC27423)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27425)
25
0.75
0.70
tr
tr/tf − Rise/Fall Time − ms
IDD − Supply Current − mA
20
0.65
Input = VDD
0.60
0.55
0.50
Input = 0 V
0.45
15
tf
10
5
0.40
0.35
0
0.30
4
6
8
10
12
14
16
−50
0
50
100
150
TJ − Temperature − °C
VDD − Supply Voltage − V
Figure 16
Figure 15
RISE TIME
vs
SUPPLY VOLTAGE
FALL TIME
vs
SUPPLY VOLTAGE
0.6
0.6
0.6
0.5
10 nF
10 nF
0.4
0.3
tr − Fall Time − ms
tr − Rise Time − ms
0.6
4.7 nF
0.2
2.2 nF
0.4
4.7 nF
0.3
2.2 nF
1 nF
0.2
1 nF
0.1
0.1
470 pF
470 pF
0
0
4
6
8
10
12
14
16
4
6
8
10
12
VDD − Supply Voltage − V
VDD − Supply Voltage − V
Figure 17
16
0.5
Figure 18
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14
16
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
DELAY TIME (tD1)
vs
SUPPLY VOLTAGE (UCC27423)
30
38
28
36
26
10 nF
34
10 nF
24
22
tD2 − Delay Time − ns
tD1 − Delay Time − ns
DELAY TIME (tD2)
vs
SUPPLY VOLTAGE (UCC27423)
4.7 nF
20
18
2.2 nF
16
32
4.7 nF
30
28
2.2 nF
26
470 pF
24
1 nF
470 pF
14
22
1 nF
12
20
4
6
8
10
12
14
16
4
6
8
Figure 19
14
16
Figure 20
ENABLE RESISTANCE
vs
TEMPERATURE
ENABLE THRESHOLD AND HYSTERESIS
vs
TEMPERATURE
150
140
ENBL − ON
2.5
RENBL − Enable Resistance − Ω
Enable threshold and hysteresis − V
12
VDD − Supply Voltage − V
VDD − Supply Voltage − V
3.0
10
2.0
1.5
1.0
ENBL − OFF
130
120
110
100
90
80
70
0.5
60
ENBL − HYSTERESIS
0
−50
−25
0
25
50
75
TJ − Temperature − °C
100
125
50
−50
−25
0
25
50
75
100
125
TJ − Temperature − °C
Figure 21
Figure 22
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17
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
IN = GND
ENBL = VDD
VDD − Supply Voltage − V
1 V/div
VDD − Supply Voltage − V
1 V/div
IN = GND
ENBL = VDD
VDD
VDD
OUT
0V
0V
OUT
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 23
Figure 24
OUTPUT BEHAVIOR
vs
VDD (INVERTING)
OUTPUT BEHAVIOR
vs
VDD (INVERTING)
VDD
OUT
IN = VDD
ENBL = VDD
VDD − Supply Voltage − V
1 V/div
VDD − Supply Voltage − V
1 V/div
IN = VDD
ENBL = VDD
OUT
0V
0V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 26
Figure 25
18
VDD
www.ti.com
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
IN = VDD
ENBL = VDD
VDD − Supply Voltage − V
1 V/div
VDD − Supply Voltage − V
1 V/div
IN = VDD
ENBL = VDD
VDD
VDD
OUT
OUT
0V
0V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 27
Figure 28
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
IN = GND
ENBL = VDD
VDD
OUT
0V
VDD − Supply Voltage − V
1 V/div
VDD − Supply Voltage − V
1 V/div
IN = GND
ENBL = VDD
VDD
OUT
0V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 29
Figure 30
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19
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
INPUT THRESHOLD
vs
TEMPERATURE
VON − Input Threshold Voltage − V
2.0
1.9
VDD = 15 V
1.8
1.7
1.6
1.5
VDD = 10 V
VDD = 4.5 V
1.4
1.3
1.2
−50
−25
0
25
50
75
TJ − Temperature − °C
Figure 31
20
www.ti.com
100
125
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°− 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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21
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
MECHANICAL DATA
DGN (MSOP)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
Thermal Pad
(See Note F)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°−ā 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073271/A 04/98
NOTES: A.
B.
C.
D.
E.
F.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
Falls within JEDEC MO-187
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device. The exposed pad dimension is 1.3 mm x 1.7 mm. However, the tolerances can be
+1.05/−0.05 mm (+ 41 / −2 mils) due to position and mold flow variation.
G. For additional information on the PowerPADt package and how to take advantage of its heat dissipating abilities, refer to Technical
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made
Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
PowerPADt is a trademark of Texas Instruments Incorporated.
22
www.ti.com
SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004
MECHANICAL DATA
P (PDIP)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
www.ti.com
23
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