TI UCD7100PWPRG4

UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense
FEATURES
•
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•
•
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DESCRIPTION
Adjustable Current Limit Protection
3.3-V, 10-mA Internal Regulator
DSP/µC Compatible Inputs
Single ±4-A TrueDrive™ High Current Driver
10-ns Typical Rise and Fall Times with 2.2-nF
Loads
25-ns Input-to-Output Propagation Delay
25-ns Current Sense to Output Delay
Programmable Current Limit Threshold
Digital Output Current Limit Flag
4.5-V to 15-V Supply Voltage Range
Rated from -40°C to 105°C
Lead(Pb)-Free Packaging
APPLICATIONS
•
•
•
•
Digitally Controlled Power Supplies
DC/DC Converters
Motor Controllers
Line Drivers
The UCD7100 is a member of the UCD7K family of
digital control compatible drivers for applications
utilizing digital control techniques or applications requiring fast local peak current limit protection.
The UCD7100 is a low-side ±4-A high-current
MOSFET gate driver. It allows the digital power
controllers such as UCD9110 or UCD9501 to
interface to the power stage in single ended topologies. It provides a cycle-by-cycle current limit
function with programmable threshold and a digital
output current limit flag which can be monitored by
the host controller. With a fast 25-ns cycle-by-cycle
current limit protection, the driver can turn off the
power stage in the unlikely event that the digital
system can not respond to a failure situation in time.
For fast switching speeds, the UCD7100 output stage
uses the TrueDrive™ output architecture, which delivers rated current of ±4 A into the gate of a
MOSFET during the Miller plateau region of the
switching transition. It also includes a 3.3-V, 10-mA
linear regulator to provide power to the digital controller.
TYPICAL APPLICATION DIAGRAMS
VIN
VOUT
Bias
Winding
Digital Controller
AN1
AGND
VDD
UCD7100PWP
3
3V3
PWMA
2
IN
INT
5
CLF
PWMB
VDD 14
OUT 12
6 ILIM
CS 8
4 AGND
Communication
2
AN2
AN3
Isolation
Amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
DESCRIPTION (CONT.)
The UCD7K driver family is compatible with standard 3.3 volt I/O ports of DSPs, Microcontrollers, or ASICs.
UCD7100 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-14 packages.
CONNECTION DIAGRAMS
VDD
CLF
ILIM
PVDD
PVDD
OUT
OUT
PGND
PGND
CS
AGND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
3V3
VDD
IN
3V3
AGND
CLF
ILIM
NC
IN
RGY−14 PACKAGE
(BOTTOM VIEW)
PWP−14 PACKAGE
(TOP VIEW)
2
3
4
5
6
1
7
NC
8
CS
NC − No internal connection
9
PGND
PGND
OUT
OUT
14
13 12 11 10
PVDD
PVDD
ORDERING INFORMATION
Packaged Devices (1) (2) (3)
(1)
(2)
(3)
2
Temperature Range
110-V HV Startup Circuit
PowerPAD™ HTSSOP-14
(PWP)
QFN-14 (RGY)
-40°C to 105°C
No
UCD7100PWP
UCD7100RGYT
HTSSOP-14 (PWP) and QFN-14 (RGY) packages are available taped and reeled. Add R suffix to device type (e.g. UCD7100PWPR) to
order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RGY packages. Standard pack
quantity for the UCD7100RGYT is 250 devices.
These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
QFN packaging is not yet available.
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
ABSOLUTE MAXIMUM RATINGS
(1) (2)
SYMBOL
VDD
PARAMETER
UCD7100
Supply Voltage
16
Quiescent
20
Switching, TA = 25°C, TJ = 125°C, VDD = 12 V
200
IDD
Supply Current
VOUT
Output Gate Drive VoltOUT
age
IOUT(sink)
IOUT(source)
Output Gate Drive Current
mA
-1 V to VDD
A
-4.0
-0.3 to 3.6
ILIM
-0.3 to 3.6
Digital I/O’s
IN, CLF
-0.3 to 3.6
Power Dissipation
TA = 25°C, TJ = 125°C, (PWP-14)
W
Junction Operating Temperature
-55 to 150
Tstr
Storage Temperature
-65 to 150
CDM
TSOL
(1)
(2)
ESD Rating
V
2.67
TJ
HBM
V
4.0
OUT
ISET, CS
Analog Input
UNIT
Human body model
2000
Change device model
500
Lead Temperature (Soldering, 10 sec)
°C
V
°C
+300
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage, VDD
Supply bypass capacitance
MIN
TYP
MAX
UNIT
4.25
12
14.5
V
1
Reference bypass capacitance
0.22
Operating junction temperature
-40
µF
105
°C
3
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = -40°C to 105°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY SECTION
Supply current, OFF
VDD = 4.2 V
200
400
µA
Supply current
Outputs not switching IN = LOW
1.5
2.5
mA
LOW VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON
4.25
4.5
4.75
VDD UVLO OFF
4.05
4.25
4.45
VDD UVLO hysteresis
150
250
350
3.267
3.3
3.333
3.234
3.3
3.366
V
mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point
TA = 25°C
3V3 over temperature
3V3 load regulation
ILOAD = 1 mA to 10 mA, VDD = 5 V
1
6.6
3V3 line regulation
VDD = 4.75 V to 12 V, ILOAD = 10 mA
1
6.6
Short circuit current
VDD = 4.75 to 12 V
11
20
35
3V3 OK threshold, ON
3.3 V rising
2.9
3.0
3.1
3V3 OK threshold, OFF
3.3 V falling
2.7
2.8
2.9
V
mV
mA
V
INPUT SIGNAL
HIGH, positive-going input threshold
voltage (VIT+)
1.65
2.08
LOW negative-going input threshold
voltage (VIT-)
1.16
1.5
0.6
0.8
Input voltage hysteresis, (VIT+ VIT-)
Frequency
2
V
MHz
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold
0.466
0.50
0.536
ILIM maximum current limit threshold ILIM = 3.3 V
ILIM = OPEN
0.975
1.025
1.075
ILIM current limit threshold
ILIM = 0.75 V
0.700
0.725
0.750
ILIM minimum current limit threshold
ILIM = 0.25 V
0.21
0.23
0.25
CLF output high level
CS > ILIM , ILOAD = -7 mA
2.64
CLF output low level
CS ≤ ILIM, ILOAD = 7 mA
Propagation delay from IN to CLF
IN rising to CLF falling after a current limit event
0.66
V
V
mV
V
10
20
ns
25
50
mV
CURRENT SENSE COMPARATOR
Bias voltage
Includes CS comp offset
5
Input bias current
–1
uA
Propagation delay from CS to OUTx
ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV
25
40
Propagation delay from CS to CLF
ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV
25
50
35
75
ns
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance
4
IN = low, resistance from CS to AGND
10
Ω
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = -40°C to 105°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVERS
Source current
Sink current
(1)
(1)
Source current (1)
VDD = 12 V, IN = high, OUT = 5 V
4
VDD = 12 V, IN = low, OUT = 5 V
4
VDD = 4.75 V, IN = high, OUT = 0
2
3
Sink current
(1)
VDD = 4.75 V, IN = low, OUT = 4.75 V
Rise time, tR
(1)
A
CLOAD = 2.2 nF, VDD = 12 V
10
20
Fall time, tF (1)
CLOAD = 2.2 nF, VDD = 12 V
10
15
Output with VDD < UVLO
VDD = 1.0 V, ISINK = 10 mA
0.8
1.2
V
Propagation delay from IN to OUTx,
tD1
CLOAD = 2.2 nF, VDD = 12 V, CLK rising
20
35
ns
(1)
ns
Ensured by design. Not 100% tested in production.
VIT+
INPUT
VIT−
tF
tF
90%
tD1
tD2
OUTPUT
10%
NOTE:
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that
dominate the power MOSFET transition through the Miller regions of operation.
5
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
FUNCTIONAL BLOCK DIAGRAM
14 PVDD
VDD 1
13 PVDD
3V3 Regulator
&
Reference
UVLO
11 OUT
IN 2
3V3 3
10 PGND
AGND 4
25 mV
Q SD
Q
+
R
ILIM 6
N/C 7
Figure 1. UCD7100
6
9
PGND
8
CS
+
CLF 5
12 OUT
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
TERMINAL FUNCTIONS
UCD7100
PIN
NAME
I/O
1
VDD
I
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to
15 V. Bypass the pin with at least 4.7 µF of capacitance.
2
2
IN
I
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
3
3
3V3
O
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
of current. Place 0.22-µF of ceramic capacitance from the pin to ground.
4
4
AGND
-
Analog ground return.
5
5
CLF
O
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the UCD7K device receives the next rising edge on the IN pin.
6
6
ILIM
I
Current limit threshold set pin. The current limit threshold can be set to any value between
0.25 V and 1.0 V.
7
7
NC
-
No Connection.
8
8
CS
I
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
the power stage by implementing cycle-by-cycle current limiting.
9
9
PGND
-
Power ground return. Connect the two PGNDs together. These ground pins should be
connected very closely to the source of the power MOSFET.
10
10
PGND
-
Power ground return. Connect the two PGNDs together. These ground pins should be
connected very closely to the source of the power MOSFET.
11
11
OUT
O
The high-current TrueDrive™ driver output. Connect the two OUT pins together.
12
12
OUT
O
The high-current TrueDrive™ driver output. Connect the two OUT pins together.
13
13
PVDD
I
Supply pin provides power for the output drivers. It is not connected internally to the VDD
supply rail. Connect the two PVDD pins together.
14
14
PVDD
I
Supply pin provides power for the output drivers. It is not connected internally to the VDD
supply rail. Connect the two PVDD pins together.
HTSSOP
-14 PIN #
DFN-14
PIN #
1
FUNCTION
7
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
APPLICATION INFORMATION
The UCD7100 is part of a family of digital compatible
drivers targeting applications utilizing digital control
techniques or applications that require local fast peak
current limit protection.
Supply
The UCD7K devices accept an input range of 4.5 V
to 15 V. The device has an internal precision linear
regulator that produces the 3V3 output from this VDD
input. A separate pin, PVDD, not connected internally
to the VDD supply rail provides power for the output
drivers. In all applications the same bus voltage
supplies the two pins. It is recommended that a low
value of resistance be placed between the two pins
so that the local capacitance on each pin forms low
pass filters to attenuate any switching noise that may
be on the bus.
Although quiescent VDD current is low, total supply
current will be higher, depending on the gate drive
output current required by the switching frequency.
Total VDD current is the sum of quiescent VDD current
and the average OUT current. Knowing the operating
frequency and the MOSFET gate charge (QG), average OUT current can be calculated from:
IOUT = QG x f, where f is frequency.
For high-speed circuit performance, a VDD bypass
capacitor is recommended to prevent noise problems.
A 4.7-µF ceramic capacitor should be located close to
the VDD to ground connection. A larger capacitor with
relatively low ESR should be connected to the PVDD
pin, to help deliver the high current peaks to the load.
The capacitors should present a low impedance
characteristic for the expected current levels in the
driver application. The use of surface mount
components for all bypass capacitors is highly recommended.
Reference / External Bias Supply
All devices in the UCD7K family are capable of
supplying a regulated 3.3-V rail to power various
types of external loads such as a microcontroller or
an ASIC. The onboard linear voltage regulator is
capable of sourcing up to 10 mA of current. For
normal operation, place a minimum of 0.22 µF of
ceramic capacitance from the reference pin to
ground.
Input
The IN pin is a high impedance digital input capable
of accepting 3.3-V logic level signals up to 2 MHz.
There is an internal Schmitt Trigger comparator which
isolates the internal circuitry from any external noise.
8
If limiting the rise or fall times to the power device is
desired, then an external resistance can be added
between the output of the driver and the load device,
which is generally a power MOSFET gate. The
external resistor may also help remove power dissipation from the package.
Current Sensing and Protection
A very fast current limit comparator connected to the
CS pin is used to protect the power stage by
implementing cycle-by-cycle current limiting.
The current limit threshold is equal to the lesser of
the positive inputs at the current limit comparator.
The current limit threshold can be set to any value
between 0.25 V and 1.0 V by applying the desired
threshold voltage to the current limit (ILIM) pin. When
the CS level is greater than the ILIM voltage minus
25 mV, the output of the driver is forced low and the
current limit flag (CLF) is set high. The CLF signal is
latched high until the UCD7K device receives the
next rising edge on the IN pin.
When the CS voltage is below ILIM, the driver output
will follow the PWM input. The CLF digital output flag
can be monitored by the host controller to determine
when a current limit event occurs and to then apply
the appropriate algorithm to obtain the desired current
limit profile.
One of the main benefits of this local protection
feature is that the UCD7K devices can protect the
power stage if the software code in the digital
controller becomes corrupted and hangs up. If the
controller’s PWM output stays high, the local current
sense circuit will turn off the driver output when an
over-current condition occurs. The system would
likely go into a retry mode because; most DSP and
microcontrollers have on-board watchdog, brown-out,
and other supervisory peripherals to restart the device in the event that it is not operating properly. But
these peripherals typically do not react fast enough to
save the power stage. The UCD7K’s local current
limit comparator provides the required fast protection
for the power stage.
The CS threshold is 25 mV below the ILIM voltage.
This way, if the user attempts to command zero
current (ILIM < 25 mV) while the CS pin is at ground,
for example at start-up, the CLF flag latches high until
the IN pin receives a pulse. At start-up it is necessary
to ensure that the ILIM pin always greater than the
CS pin for the handshaking to work as described
below. If for any reason the CS pin comes to within
25 mV of the ILIM pin during start-up, then the CLF
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
flag is latched high and the digital controller must poll
the UCD7K device, by sending it a narrow IN pulse. If
the fault condition is not present the IN pulse resets
the CLF signal to low indicating that the UCD7K
device is ready to process power pulses.
drain voltage is swinging between the voltage levels
dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with
current supplied or removed by the driver device. See
Reference [1]
Handshaking
Drive Current and Power Requirements
The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the
digitally controlled power supply. At start-up the CLF
flag is held high until all the internal and external
supply voltages of the UCD7K device are within their
operating range. Once the supply voltages are within
acceptable limits, the CLF goes low and the device
will process input drive signals. The micro-controller
should monitor the CLF flag at start-up and wait for
the CLF flag to go LOW before sending power pulses
to the UCD7K device.
The UCD7K family of drivers can deliver high current
into a MOSFET gate for a period of several hundred
nanoseconds. High peak current is required to turn
the device ON quickly. Then, to turn the device OFF,
the driver is required to sink a similar amount of
current to ground. This repeats at the operating
frequency of the power device. A MOSFET is used in
this discussion because it is the most common type
of switching device used in high frequency power
conversion equipment.
Driver Output
The high-current output stage of the UCD7K device
family is capable of supplying ±4-A peak current
pulses and swings to both VDD and GND. The driver
outputs follows the state of the IN pin provided that
the VDD and 3V3 voltages are above their respective
under-voltage lockout threshold.
The drive output utilizes Texas Instruments’
TrueDrive™ architecture, which delivers rated current
into the gate of a MOSFET when it is most needed
during the Miller plateau region of the switching
transition providing efficiency gains.
TrueDrive™ consists of pullup/ pulldown circuits
using bipolar and MOSFET transistors in parallel. The
peak output current rating is the combined current
from the bipolar and MOSFET transistors. The output
resistance is the RDS(on) of the MOSFET transistor
when the voltage on the driver output is less than the
saturation voltage of the bipolar transistor. This hybrid
output stage also allows efficient current sourcing at
low supply voltages.
Each output stage also provides a very low
pedance to overshoot and undershoot due to
body diode of the external MOSFET. This means
in many cases, external-schottky-clamp diodes
not required.
imthe
that
are
Reference [1] discusses the current required to drive
a power MOSFET and other capacitive-input
switching devices.
When a driver device is tested with a discrete,
capacitive load it is a fairly simple matter to calculate
the power that is required from the bias supply. The
energy that must be transferred from the bias supply
to charge the capacitor is given by:
E 1 CV2
2
(1)
where C is the load capacitor and V is the bias
voltage feeding the driver.
There is an equal amount of energy transferred to
ground when the capacitor is discharged. This leads
to a power loss given by the following:
P 1 CV2 f
2
(2)
where f is the switching frequency.
This power is dissipated in the resistive elements of
the circuit. Thus, with no external resistor between
the driver and gate, this power is dissipated inside the
driver. Half of the total power is dissipated when the
capacitor is charged, and the other half is dissipated
when the capacitor is discharged. An actual example
using the conditions of the previous gate drive
waveform should help clarify this.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the
control circuitry. Proper drive is required for efficient,
reliable operation. The UCD7K drivers have been
optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the
switching transition. This interval occurs while the
9
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the
power loss can be calculated as:
P 10 nF 122 300 kHz 0.432 W
(3)
With a 12-V supply, this would equate to a current of:
I P 0.432 W 0.036 A
V
12 V
(4)
The actual current measured from the supply was
0.037 A, and is very close to the predicted value. But,
the IDD current that is due to the device internal
consumption should be considered. With no load the
device current drawn is 0.0027 A. Under this condition the output rise and fall times are faster than
with a load. This could lead to an almost insignificant,
yet measurable current due to cross-conduction in the
output stages of the driver. However, these small
current differences are buried in the high frequency
switching spikes, and are beyond the measurement
capabilities of a basic lab setup. The measured
current with 10-nF load is close to the value expected.
The switching load presented by a power MOSFET
can be converted to an equivalent capacitance by
examining the gate charge required to switch the
device. This gate charge includes the effects of the
input capacitance plus the added charge needed to
swing the drain of the device between the ON and
OFF states. Most manufacturers provide specifications that provide the typical and maximum gate
charge, in nC, to switch the device under specified
conditions. Using the gate charge QG, one can
determine the power that must be dissipated when
charging a capacitor. This is done by using the
equivalence QG = CEFF x V to provide the following
equation for power:
P C V2 f Q G V f
(5)
This equation allows a power designer to calculate
the bias power required to drive a specific MOSFET
gate at a specific bias voltage.
10
Thermal Information
The useful range of a driver is greatly affected by the
drive power requirements of the load and the thermal
characteristics of the device package. In order for a
power driver to be useful over a particular temperature range the package must allow for the efficient
removal of the heat produced while keeping the
junction temperature within rated limits. The UCD7K
family of drivers is available in PowerPAD™ TSSOP
and QFN/DFN packages to cover a range of application requirements. Both have the exposed pads to
relieve thermal dissipation from the semiconductor
junction.
As illustrated in Reference [2], the PowerPAD™
packages offer a leadframe die pad that is exposed at
the base of the package. This pad is soldered to the
copper on the PC board (PCB) directly underneath
the device package, reducing the ΘJC down to
4.7°C/W. The PC board must be designed with
thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference [3].
Note that the PowerPAD™ is not directly connected
to any leads of the package. However, it is electrically
and thermally connected to the substrate which is the
ground of the device.
Circuit Layout Recommendations
In a power driver operating at high frequency, it is a
significant challenge to get clean waveforms without
much overshoot/undershoot and ringing. The low
output impedance of these drivers produces
waveforms with high di/dt. This tends to induce
ringing in the parasitic inductances. Utmost care must
be used in the circuit layout. It is advantageous to
connect the driver IC as close as possible to the
leads. The driver device layout has the analog ground
on the opposite side of the output, so the ground
should be connected to the bypass capacitors and
the load with copper trace as wide as possible. These
connections should also be made with a small enclosed loop area to minimize the inductance.
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
VIN
VOUT
Bias Supply
Bias
Winding
UCD7100PWP
1 VDD
3 3V3
1
VDS
2
UCD91xx
with
CLA
Peripheral
PVDD 14
VDS
PVDD 13
IN
2
4 AGND
5 CLF
CS
OUT 12
OUT 11
6 ILIM
FB
7
NC
PGND 10
PGND 9
CS 8
2
CS
COMMUNICATION
(Programming & Status Reporting)
2
Isolation
Amplifier
Figure 2. Isolated Forward Converter
11
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
~
VAC
−
+
~
Bias
Supply
UCD7100PWP
1
VDD
3 3V3
Signal
Conditioning
Amplifier
PFC_ISENSE
UCD9501
Digital
Controller
VDS
PVDD 14
VDS
PVDD 13
2 IN
4 AGND
OUT 12
OUT 11
CS
5 CLF
FB
6 ILIM
PGND 10
PGND 9
7 NC
CS 8
CS
COMMUNICATION
(Programming & Status Reporting)
Signal
Conditioning
Amplifier
Figure 3. PFC Boost Front-End Power Supply
12
VOUT
UCD7100
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SLUS651A – MARCH 2005 – REVISED MAY 2005
TYPICAL CHARACTERISTICS
UVLO THRESHOLDS
vs
TEMPERATURE
3V3 REFERENCE VOLTAGE
vs
TEMPERATURE
3.36
5.0
UVLO on
4.5
3.34
UVLO on
3V3 − Reference Voltage − V
VUVLO − UVLO Thresholds − V
4.0
3.5
3.0
2.5
2.0
1.5
3.32
3.30
3.28
1.0
3.26
0.5
0.0
−50
UVLO on
3.24
−25
0
25
50
75
100
125
−50
−25
0
t − Temperature − °C
Figure 4.
Figure 5.
3V3 SHORT CIRCUIT CURRENT
vs
TEMPERATURE
INPUT THRESHOLDS
vs
TEMPERATURE
125
100
125
Input Rising
22.5
2.0
VINPUT − Input Voltage − V
ISHORT_CKT − Short Circuit Current − mA
100
2.5
23.0
22.0
VDD = 4.75 V
21.5
VDD = 12 V
21.0
1.5
Input Falling
1.0
0.5
20.5
20.0
−50
25
50
75
t − Temperature − °C
0.0
−25
0
25
50
75
t − Temperature − °C
Figure 6.
100
125
−50
−25
0
25
50
75
TJ − Temperature − °C
Figure 7.
13
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
TYPICAL CHARACTERISTICS (continued)
OUTPUT RISE TIME AND FALL TIME
vs
TEMPERATURE (VDD = 12 V)
RISE TIME
vs
SUPPLY VOLTAGE
65
18.0
tR = Rise Time
55
CLOAD = 10 nF
14.0
12.0
10.0
tR − Rise Time − ns
tR, tF − Rise and Fall Times − ns
16.0
tF = Fall Time
8.0
6.0
45
CLOAD = 4.7 nF
35
25
CLOAD = 2.2 nF
4.0
15
2.0
CLOAD = 1 nF
0.0
5
−50
−25
0
25
50
75
100
5
125
TJ − Temperature − °C
7.5
10
12.5
15
VDD − Supply Voltage − V
Figure 8.
Figure 9.
FALL TIME
vs
SUPPLY VOLTAGE
PROPAGATION DELAY RISING
vs
SUPPLY VOLTAGE
20
45
tF − Fall Time − ns
35
tPD − Propagation Delay, Rising − ns
40
CLOAD = 10 nF
30
25
CLOAD = 4.7 nF
20
CLOAD = 2.2 nF
15
10
CLOAD = 4.7 nF
5
CLOAD = 2.2 nF
CLOAD = 1 nF
10
CLOAD = 1 nF
0
5
5
14
CLOAD = 10 nF
15
7.5
10
12.5
15
5
7.5
10
12.5
VDD − Supply Voltage − V
VDD − Supply Voltage − V
Figure 10.
Figure 11.
15
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY FALLING
vs
SUPPLY VOLTAGE
DEFAULT CURRENT LIMIT THRESHOLD
vs
TEMPERATURE
0.54
0.53
VCS − Current Limit Threshold − V
tPD − Propagation Delay, Falling − ns
25
CLOAD = 10 nF
20
15
CLOAD = 4.7 nF
10
CLOAD = 2.2 nF
0.52
0.51
0.50
0.49
0.48
0.47
CLOAD = 1 nF
5
0.46
5
7.5
10
12.5
15
−50
−25
25
50
75
Figure 12.
Figure 13.
CS TO OUTx PROPAGATION DELAY
vs
TEMPERATURE
CS TO CLF PROPAGATION DELAY
vs
TEMPERATURE
100
125
50
40
45
35
tPD − CS to CLF Propagation Delay − ns
tPD − CS to OUTx Propagation Delay − ns
0
TJ − Temperature − °C
VDD − Supply Voltage − V
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
TJ − Temperature − °C
TJ − Temperature − °C
Figure 14.
Figure 15.
100
125
15
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
TYPICAL CHARACTERISTICS (continued)
IN TO OUT PROPAGATION DELAY
vs
TEMPERATURE
START-UP BEHAVIOR AT VDD = 12 V (INPUT TIED TO 3V3)
35
VDD (2 V/div)
tPD − Propagation Delay − ns
30
25
20
15
3V3 (2 V/div)
10
5
OUTx (2 V/div)
0
−50
−25
0
25
50
75
100
125
t − Time − 40 µs/div
TJ − Temperature − °C
Figure 16.
Figure 17.
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT TIED TO
3V3)
START-UP BEHAVIOR AT VDD = 12 V (INPUT SHORTED
TO GND)
VDD (2 V/div)
VDD (2 V/div)
3V3 (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
Figure 18.
16
t − Time − 40 µs/div
Figure 19.
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
TYPICAL CHARACTERISTICS (continued)
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT SHORTED
TO GND)
OUTPUT RISE AND FALL TIME (VDD = 12 V, CLOAD = 10
NF)
Output Voltage − 2 V/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
Figure 20.
t − Time − 40 ns/div
Figure 21.
17
UCD7100
www.ti.com
SLUS651A – MARCH 2005 – REVISED MAY 2005
REFERENCES
1. Power Supply Seminar SEM–1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
RELATED PRODUCTS
PRODUCT
(1)
(2)
(3)
(4)
DESCRIPTION
Dual Low Side ±4-A Drivers with Independent CS
3V3, CS (1) (2)
UCD7201
Dual Low Side ±4-A Drivers with Common CS
3V3, CS (1) (2)
UCD7230
±4A Synchronous Buck Driver with CS
3V3, CS (1) (2)
UCD7500
Single Low Side ±4-A Driver with CS and 110-V High Voltage Startup
3V3, CS,
HVS110 (1) (2) (3)
UCD7600
Dual Low Side ±4-A Drivers with Independent CS and 110-V High Voltage Startup
3V3, CS,
HVS110 (1) (2) (3)
UCD7601
Dual Low Side ±4-A Drivers with Common CS and 110-V High Voltage Startup
3V3, CCS,
HVS110 (1) (4) (3)
UCD9110
Digital Power Controller for High Performance Single-loop Applications
UCD9501
Digital Power Controller for High Performance Multi-loop Applications
3V3 = 3.3V linear regulator.
CS = current sense and current limit function.
HVS110 = 110-V high voltage startup circuit.
CCS = common current sense and current limit function.
REVISION HISTORY
DATE
3/4/05
18
FEATURES
UCD7200
REVISION
SLUS651
CHANGE DESCRIPTION
Initial release
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCD7100PWP
ACTIVE
HTSSOP
PWP
14
UCD7100PWPR
ACTIVE
HTSSOP
PWP
UCD7100PWPRG4
ACTIVE
HTSSOP
UCD7100RGYR
PREVIEW
QFN
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PWP
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
RGY
14
1000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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