FREESCALE 33394

Freescale Semiconductor,Order
Inc.
this document from Analog Marketing
Rev. 2.5, 11/2002
33394
MULTI–OUTPUT
POWER SUPPLY
The 33394 is a multi–output power supply integrated circuit with high
speed CAN transceiver. The IC incorporates a switching pre–regulator
operating over a wide input voltage range from +4.0V to +26.5V (with
transients up to 45V).
The switching regulator has an internal 3.0A current limit and runs in both
buck mode or boost mode to always supply a pre–regulated output followed
by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V
@ 120mA; VDDL / 2.6V (User scalable between 3.3V – 1.25V) @ 400mA
typically, using an external NPN pass transistor. The Keep Alive regulator
VKAM (scalable) @ 50mA; FLASH memory programming voltage VPP /
5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V
(tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to
supply 125mA clamped to 17V.
Additional features include Active Reset circuitry watching VDDH,
VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT),
Power Sequencing circuitry guarantees the core supply voltages never
exceed their limits or polarities during system power up and power down.
A high speed CAN transceiver physical layer interfaces between the
microcontroller CMOS outputs and differential bus lines. The CAN driver is
short circuit protected and tolerant of loss of battery or ground conditions.
33394 is designed specifically to meet the needs of modules, which use
the MPC565 microcontroller, though it will also support others from the
MPC5XX family of Motorola microcontrollers.
Features:
• Wide operating input voltage range: +4.0V to +26.5V (+45V transient).
•
•
•
•
•
•
SEMICONDUCTOR
TECHNICAL DATA
44–Lead HSOP
DH SUFFIX
CASE 1291
44–Lead QFN
FC SUFFIX
CASE 1310
(BOTTOM VIEW)
Provides all regulated voltages for MPC5XX MCUs and other ECU’s
logic and analog functions.
Accurate power up/down sequencing.
Provides necessary MCU support monitoring and fail–safe support.
Provides three 5.0 V buffer supplies for internal & external (short–circuit
protected) sensors.
Includes step–down/step–up switching regulator to provide supply
voltages during different battery conditions.
Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by
means of Serial Peripheral Interface.
INV
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
DO
SCLK
DI
CS
PIN CONNECTIONS
GND
SW2G
BOOT
SW1
SW1
SW1
VBAT
VBAT
KA_VBAT
VIGN
VKAM
1
QFN
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
Freescale Semiconductor, Inc...
Switch Mode Power Supply with
Multiple Linear Regulators and
High Speed CAN Transceiver
TOP VIEW
VBAT
VBAT
KA_VBAT
VIGN
VKAM
/SLEEP
VKAM_FB
HRT
VSEN
CANH
REGON
CANL
WAKEUP
GND
VREF1
CANTXD
VPP_EN
CANRXD
VPP
/PORESET
VDD3_3
/HRESET
VDD3_3FB
/PRERESET
VDDL_X
VDDL_FB
VDDL_B
VDDL_FB
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
1
HSOP
SW1
SW1
SW1
BOOT
SW2G
GND
INV
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
DO
SCLK
DI
CS
/SLEEP
HRT
CANH
CANL
GND
54–Lead SOICW–EP
DWB SUFFIX
CASE 1377
PIN CONNECTIONS
GND
CANL
CANH
HRT
/SLEEP
N/C
CS
DI
SCLK
DO
N/C
VREF3
VREF2
VDDH
VPRE_S
VPRE
VCOMP
INV
GND
SW2G
BOOT
N/C
SW1
SW1
SW1
SW1
SW1
1
SOICW
CANTXD
CANRXD
/PORESET
/HRESET
/PRERESET
N/C
VDDL_FB
VDDL_B
VDDL_X
VDD3_3FB
VDD3_3
VPP
VPP_EN
VREF1
WAKEUP
REGON
VSEN
VKAM_FB
VKAM
VIGN
N/C
KA_VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
This document contains information on a new product. Specifications
and information herein are subject to change without notice.
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
1
Freescale Semiconductor,
Inc.
33394
To Q3
Lf1
6.8 H
Dp1
+
+
Figure 1. 33394DH – Simplified Block Diagram and Typical Application
m
VBAT
+
1, 2
Cf2
100 F
Cf1
10 F
Dp2
m
m
Buck
Control
Logic
VIGN
Boost
4
OFF
10 nF
VKAM
2.6 V
+
Freescale Semiconductor, Inc...
10 nF
5
22 k
m
VKAM_FB
22 F
6
20 k
VSEN
7
41
Low–Side
Drive
40
VKAM
Keep–Alive
Adj. Volt.
60 mA
I–Lim
40 k
–
+
Vbg
+
–
VREF1
+
10 nF
10
m
VPP
5.0 V/3.3 V
+
10 nF
12
m
14
10 nF 47 F
Q2
MJD31C
VDDL
2.6 V
+
m
110R
/PRERESET
47 F
VKAM
2.6 V
Notes:
Notes:
Notes:
Notes:
2
10 k
Rc3
430R
Cc2
35
Enable
CANRXD
Sleep
VREF1
5.0 V
100 mA
LDO
T–Lim, I–Lim
VDDH
5.0 V
400 mA
LDO
T–Lim, I–Lim
CAN
Wakeup
Logic
VDDH
5.0 V
+
34
m
10 nF
47 F
Vbg
VPP
5.0 V/3.3 V
150 mA
LDO
T–Lim, I–Lim
VREF2
5.0 V
100 mA
LDO
T–Lim, I–Lim
Band Gap
Reference
VDD3_3
3.3 V
120 mA
LDO, Pass
T–Lim, I–Lim
VREF3
5.0 V
100 mA
LDO
T–Lim, I–Lim
Standby
Control
VREF2
33
m
5.0 V
+
10 nF
18
Sleep
/PORESET
10 k
VREF3
32
m
5.0 V
+
10 nF
1.0 F
16 Bit
SPI
Control
Fault Rep.
20
10 k
Rc2
100 k
Cc1
VPRE
VPRE_S
36
VDDL_B VDDL Drive
Adj. Volt.
VDDL_X
40 mA
16 VDDL_FB Dual Pass
T–Lim
17
/HRESET 19
100R
Cc3
3.3 nF
INV
37
15
Q3
MJD31C
MTD20N03HDL
GND
VCOMP 1.0 nF
VQ3
VPRE
Q1
38
m
13
VDD3_FB
+
SW2G
1.0 F
47 F
VDD3_3
3.3 V
10 nF
11
D1
11.7 k 100 pF
VSEN
VBAT Volt.
125 mA
T–Lim, I–Lim
1.0 F
VPP_EN
+
39
+
–
9
5.0 V
m
BOOT
High–Side
Drive
REGON
8
WAKEUP
C1
100 F
Cb
100 nF
Feed
Forward
Ramp
Generator
3
Control
VPRE
5.6 V
D2
42–44
Oscillator
KA_VBAT
4.7 k
m
SW1
–
ON
L1
47 H
Reset
Detection
VDDH,
VDD3_3,
VDDL
31
30
29
28
DO
SCLK
DI
CS
VDDH
5.0 V
/SLEEP
27
High–Speed CAN
Transceiver
HRT
POR Timer
26
47 k
m
1.0 F
21
CANRXD
22
23
24
25
CANL
CANH
CANTXD
120 R
GND
1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins).
2.VDDL and VKAM are adjustable to support current microprocessor technology (1.25 V to 3.3 V) by means of an external resistor divider.
3. When the 33394 CAN transceiver is not used, CANL and CANH pins can be shorted together.
4. Dp1 = reverse battery protection diode. Dp2 = load dump protection diode. Dp1, Dp2 can be ommitted in those applications which do not require such protection.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
Freescale Semiconductor, Inc...
PIN FUNCTION DESCRIPTION (44–HSOP Package)
PIN NO.
NAME
1
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
2
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
3
KA_VBAT
4
VIGN
Turn–On control through ignition switch (with internal protection diode)
5
VKAM
VDDL tracking Keep Alive Memory (Standby) supply
6
VKAM_FB
VKAM output feedback
7
VSEN
Switched battery output
8
REGON
Regulator “Hold On” input
9
WAKEUP
CAN wake up event output
10
VREF1
11
VPP_EN
DESCRIPTION
Keep alive supply (with internal protection diode)
VDDH tracking linear regulator 1
VPP enable
12
VPP
13
VDD3_3
14
VDD3_3FB
15
VDDL_X
VDDL optional external pass transistor base drive, operating in Boost Mode only
16
VDDL_B
VDDL external pass transistor base drive
17
VDDL_FB
18
/PRERESET
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDDL output feedback
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
19
/HRESET
20
/PORESET
Open drain / HRESET (Hardware Reset) output
21
CANRXD
CAN receive data (DOUT)
22
CANTXD
CAN transmit data (DIN)
23
GND
Ground
24
CANL
CAN differential bus drive low line
25
CANH
CAN differential bus drive high line
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
26
HRT
27
/SLEEP
Hardware Reset Timer pin (programmed with external capacitor and resistor)
28
CS
SPI chip select
29
DI
SPI serial data in
30
SCLK
Sleep Mode & Power Down control
SPI clock input
31
DO
32
VREF3
SPI serial data out
VDDH tracking linear regulator 3
33
VREF2
VDDH tracking linear regulator 2
34
VDDH
5.0 V regulated supply output
35
VPRE_S
36
VPRE
37
VCOMP
Switching pre–regulator output sense
Switching pre–regulator output
Switching pre–regulator compensation (error amplifier output)
38
INV
Switching pre–regulator error amplifier inverting input
39
GND
Ground
40
SW2G
External power switch (MOSFET) gate drive — Boost regulator
41
BOOT
Bootstrap capacitor
42
SW1
Source of the internal power switch (n–channel MOSFET)
43
SW1
Source of the internal power switch (n–channel MOSFET)
44
SW1
Source of the internal power switch (n–channel MOSFET)
NOTE: The exposed pad of the 44 HSOP package is electrically and thermally connected with the IC ground.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
3
Freescale Semiconductor,
Inc.
33394
PIN FUNCTION DESCRIPTION (44–QFN Package)
Freescale Semiconductor, Inc...
PIN NO.
NAME
DESCRIPTION
1
GND
2
SW2G
Ground
External power switch (MOSFET) gate drive — Boost Reg.
3
BOOT
Bootstrap capacitor
4
SW1
Source of the internal power switch (n–channel MOSFET)
5
SW1
Source of the internal power switch (n–channel MOSFET)
6
SW1
Source of the internal power switch (n–channel MOSFET)
7
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
8
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
9
KA_VBAT
Keep alive battery supply (with internal protection diode)
10
VIGN
Turn on control through ignition switch (with internal protection diode)
11
VKAM
VDDL tracking Keep Alive Memory (Standby) supply
12
VKAM_FB
VKAM output feedback
13
VSEN
Switched battery output
14
REGON
Regulator “Hold On” input
15
WAKEUP
CAN wake up event output
16
VREF1
17
VPP_EN
18
VPP
VDDH tracking linear regulator 1
VPP enable
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
19
VDD3_3
20
VDD3_3FB
21
VDDL_X
VDDL optional external pass transistor base drive, operating in Boost Mode only
22
VDDL_B
VDDL external pass transistor base drive
23
VDDL_FB
24
/PRERESET
25
/HRESET
26
/PORESET
27
CANRXD
CAN receive data (DOUT)
28
CANTXD
CAN transmit data (DIN)
29
GND
Ground
30
CANL
CAN differential bus drive low line
31
CANH
CAN differential bus drive high line
32
HRT
33
/SLEEP
34
CS
SPI chip select
35
DI
SPI serial data in
36
SCLK
37
DO
38
VREF3
VDDH tracking linear regulator 3
39
VREF2
VDDH tracking linear regulator 2
40
VDDH
5.0 V regulated supply output
41
VPRE_S
42
VPRE
43
VCOMP
44
INV
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDDL output feedback
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
Open drain / HRESET (Hardware Reset) output
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
Hardware Reset Timer pin (programmed with external capacitor and resistor)
Sleep Mode & Power Down control
SPI clock input
SPI serial data out
Switching pre–regulator output sense
Switching pre–regulator output
Switching pre–regulator compensation (error amplifier output)
Switching pre–regulator error amplifier inverting input
NOTE: The exposed pad of the 44 QFN package is electrically and thermally connected with the IC ground.
4
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
PIN FUNCTION DESCRIPTION (54 SOICW–EP Package)
Freescale Semiconductor, Inc...
PIN NO.
NAME
DESCRIPTION
1
GND
Ground
2
CANL
CAN differential bus drive low line
3
CANH
CAN differential bus drive high line
4
HRT
5
/SLEEP
6
N/C
No Connect
7
CS
SPI chip select
8
DI
SPI serial data in
9
SCLK
10
DO
SPI serial data out
11
N/C
No Connect
12
VREF3
VDDH tracking linear regulator 3
13
VREF2
VDDH tracking linear regulator 2
14
VDDH
5.0 V regulated supply output
15
VPRE_S
16
VPRE
17
VCOMP
18
INV
Switching pre–regulator error amplifier inverting input
19
GND
Ground
20
SW2G
External power switch (MOSFET) gate drive — Boost regulator
21
BOOT
Bootstrap capacitor
23
SW1
Source of the internal power switch (n–channel MOSFET)
24
SW1
Source of the internal power switch (n–channel MOSFET)
25
SW1
Source of the internal power switch (n–channel MOSFET)
26
SW1
Source of the internal power switch (n–channel MOSFET)
27
SW1
Source of the internal power switch (n–channel MOSFET)
28
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
29
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
30
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
31
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
32
VBAT
Battery supply to IC (external reverse battery protection needed in some applications)
33
KA_VBAT
Hardware Reset Timer pin (programmed with external capacitor and resistor)
Sleep Mode & Power Down control
SPI clock input
Switching pre–regulator output sense
Switching pre–regulator output
Switching pre–regulator compensation (error amplifier output)
Keep alive supply (with internal protection diode)
34
N/C
35
VIGN
No Connect
Turn–On control through ignition switch (with internal protection diode)
36
VKAM
VDDL tracking Keep Alive Memory (Standby) supply
37
VKAM_FB
VKAM output feedback
38
VSEN
Switched battery output
39
REGON
Regulator “Hold On” input
40
WAKEUP
CAN wake up event output
41
VREF1
42
VPP_EN
43
VPP
44
VDD3_3
45
VDD3_3FB
46
VDDL_X
VDDL optional external pass transistor base drive, operating in Boost Mode only
47
VDDL_B
VDDL external pass transistor base drive
48
VDDL_FB
49
N/C
50
/PRERESET
51
/HRESET
52
/PORESET
53
CANRXD
CAN receive data (DOUT)
54
CANTXD
CAN transmit data (DIN)
VDDH tracking linear regulator 1
VPP enable
5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
3.3 V regulated supply output, base drive for optional external pass transistor
VDD3_3 output feedback
VDDL output feedback
No Connect
Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
Open drain / HRESET (Hardware Reset) output
Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
NOTE: The exposed pad of the 54 SOICW–EP package is electrically and thermally connected with the IC ground.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
5
Freescale Semiconductor,
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1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur.
Voltage parameters are absolute voltages referenced to ground.)
Freescale Semiconductor, Inc...
Parameter
Min.
Max.
Unit
Supply Voltage (VBAT), Load Dump
–0.3
+45
V
Supply Voltage (KA_VBAT, VIGN), Load Dump
–18
+45
V
Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM)
–0.3
+5.8
V
Supply Voltages (VREF1, VREF2, VREF3, VSEN)
–2.0
+18
V
CANL, CANH (0<VBAT<18 VDC no time limit)
–18
+26.5
V
ESD Voltage
Human Body Model all pins
Machine Model all pins
(Note 1)
(Note 2)
–2.0
–200
+2.0
+200
kV
V
CANLesd, CANHesd
(Note 1)
–4.0
+4.0
kV
CANLesd, CANHesd
(Note 2)
–200
+200
V
CANLtransient, CANHtransient
(Note 3)
–200
+200
V
/SLEEP
–18
+45
V
REGON, VPP_EN, /HRESET, /PORESET, /PRERESET, HRT, DO, DI, CS, SCLK
–0.3
+7.0
V
CANTXD, CANRXD
–0.3
+7.0
V
Operational Package Temperature [Ambient Temperature]
–40
+125
°C
Storage Temperature
–65
+150
°C
8.3
5.0
5.0
W
W
W
260
_C
Power Dissipation (TA = 125_C)
44 HSOP
44 QFN
54 SOICW–EP
(Note 4)
(Note 4)
(Note 4)
Lead Soldering Temperature
(Note 5)
Maximum Junction Temperature
+150
°C
RθJA, Thermal Resistance, Junction to Ambient (44 HSOP)
(Note 6)
41
°C/W
RθJC, Thermal Resistance, Junction to Case (44 HSOP)
(Note 7)
0.2
°C/W
RθJB, Thermal Resistance, Junction to Base (44 HSOP)
(Note 8)
3
°C/W
RθJA, Thermal Resistance, Junction to Ambient (44 QFN)
(Note 6)
77
°C/W
RθJC, Thermal Resistance, Junction to Case (44 QFN)
(Note 7)
1.7
°C/W
RθJB, Thermal Resistance, Junction to Base (44 QFN)
(Note 8)
5.0
°C/W
RθJA, Thermal Resistance, Junction to Ambient (54 SOICW–EP)
(Note 6)
52
°C/W
RθJC, Thermal Resistance, Junction to Case (54 SOICW–EP)
(Note 7)
1.2
°C/W
RθJB, Thermal Resistance, Junction to Base (54 SOICW–EP)
(Note 8)
8.1
°C/W
1. Human body model: C = 100 pF, R = 1.5 kΩ.
2. Machine model: C = 200 pF, R = 10 Ω and L = 0.75 µH. In case of a discharge from pin CANL to pin GND: – 100 V < CANL transient < +100
V; in case of a discharge from pin CANH to Vcc: –150 V < CANH transient < +150 V.
3. The waveforms of the applied transients is in accordance with ”ISO 7637 part 1” test pulses 1, 2, 3a and 3b.
4. Maximum power dissipation at indicated junction temperature.
5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering
time/temperature limits.
6. Thermal resistance measured in accordance with EIA/JESD51–2.
7. Theoretical thermal resistance from the die junction to the exposed pad.
8. Thermal resistance measured in accordance with JESD51–8.
2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted)
Parameter
Supply Voltages (VBAT, KA_VBAT)
Switching Regulator Output Current (IVPRE)
(Note 1)
Value
Unit
4.0 to 26.5
V
0 to 1.2
A
VDDH Output Current
0 to 400
mA
VDD3_3 Output Current
0 to 120
mA
VDDL_B Pass Transistor Base Drive Current
0 to 40
mA
VPP Output Current
0 to 150
mA
VREF Output Current
0 to 100
mA
VSEN Output Current
0 to 125
mA
VKAM Standby Output Current (normal mode of operation)
0 to 60
mA
VKAM Standby Output Current (standby mode of operation)
0 to 12
mA
1. See Typical Application Diagram in Figure 1.
6
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33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
6.2
V
DC CHARACTERISTICS:
GENERAL
Start Up Voltage
VBATstart
Power Dissipation, VBAT = 13.3 V (Buck Mode)
Undervoltage Shut Down
1.8
VBATUV
Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V;
IVKAM = 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V
3.4
IVBAT(sleep)
750
Battery Input Current, Keep Alive Mode
VIGN = 0; IVKAM = –10 mA
Power On Current, Regulator ON with no load on VDDH, VDD3_3,
VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V
Freescale Semiconductor, Inc...
Battery Input Current, VPRE = –1.0 A, VBAT = 4.5 V
Battery Input Current, VPRE = –1.0 A, VBAT = 9 V
Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V
Battery Input Current, VPRE = –1.0 A, VBAT = 18 V
IVBAT(no load)
IVBAT(4.5)
2.2
W
3.9
V
1000
µA
12
mA
27
mA
3.0
A
IVBAT(9)
1.5
A
IVBAT(13.3)
1.2
A
IVBAT(18)
1.1
A
MODE CONTROL
VIGN Input Voltage Threshold, REGON = 0 V
VBAT = 13.3 V; Battery Voltage = 14 V
VIH
VIL
VIGN Hysteresis
2.8
1.7
3.15
2.0
3.4
2.3
V
0.7
1.0
1.5
V
VIGN Pull–Down Current, REGON = 0V
VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V
RPD
40
100
150
µA
REGON Input High Voltage Threshold
VIH
1.3
1.65
2.1
V
REGON Input Low Voltage Threshold
VIL
0.8
1.35
1.5
V
REGON Input Voltage Threshold Hysteresis
VIhys
0.2
0.3
0.4
V
REGON Pull–Down Current, REGON = VDDH to VIL(min)
RPD
10
20
50
µA
/SLEEP Input High Voltage Threshold
VIH
1.7
2.2
2.6
V
/SLEEP Input Low Voltage Threshold
VIL
1.4
1.9
2.2
V
/SLEEP Input Voltage Threshold Hysteresis
VIhys
0.2
0.3
0.4
V
/SLEEP Pull–Down Current, /SLEEP = VDDH to VIL(min)
RPD
10
20
50
µA
VPP_EN Input High Voltage Threshold
VIH
1.3
1.65
2.1
V
VIL
0.8
1.35
1.5
V
RPD
10
20
50
µA
VPP_EN Input Voltage Low Threshold
VPP_EN Pull–Down Current, VPP_EN = VDDH to VIL(min)
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
7
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VPRE
5.4
5.6
5.8
V
DC CHARACTERISTICS:
BUCK CONVERTER
Buck Converter Output Voltage, VBAT = 7.5V to 18V; ILOAD=500mA
Buck to Boost Mode Threshold Voltage
(Note 1)
VBATthd
6.7
V
Boost to Buck Mode Threshold Voltage
(Note 1)
VBATthu
7.2
V
(Note 1)
BVDSS
50
V
IDSW1
–2.75
A
SW1 Drain–Source Current Limit
IscSW1
–2.5
SW1 Drain–Source On–Resistance; ID = 1.0 A, VBAT = 9.0 V
RDS(on)
N–channel power MOSFET SW1
SW1 Drain–Source Breakdown Voltage
SW1 Continuous Drain Current
–3.0
–3.5
A
300
mΩ
Freescale Semiconductor, Inc...
Error Amplifier (Design Information Only)
Input Offset Voltage
(Note 1)
VOS
20
mV
DC Open Loop Gain
(Note 1)
AVOL
80
dB
Unity Gain Bandwidth
(Note 1)
BW
1.5
MHz
Output Voltage Swing — High Level
(Note 1)
VOH
4.2
V
Output Voltage Swing — Low Level
(Note 1)
VOL
0.4
V
Output Source Current
(Note 1)
IOUT
1.0
mA
Output Sink Current
(Note 1)
IOUT
200
µA
Ramp Generator
Sawtooth Peak Voltage
(Note 1)
VOSC
3.5
V
Sawtooth Peak–to–Peak Voltage
(Note 1)
VOSCp–p
3.0
V
Boost Converter Output Voltage, VBAT = 4.5 V to 6.0 V
(Note 1)
VPRE
6.6
V
SW2G Output Voltage, Power MOSFET On
(Note 1)
Vg
VPRE
V
SW2G Source Continuous Current
(Note 1)
Isource
TBD
mA
BOOST CONVERTER
External Power MOSFET Gate Drive SW2G
SW2G Sink Continuous Current
5.9
6.0
Isink
200
300
400
mA
Freq
180
200
220
kHz
AC CHARACTERISTICS:
BUCK CONVERTER
Oscillator Frequency
SW1 Switch Turn–ON Time
(Note 1)
tT–ON
TBD
ns
SW1 Switch Turn–OFF Time
(Note 1)
tT–OFF
TBD
ns
SW2G Switch Turn–ON Time, Cgate = pF
(Note 1)
tT–ON
TBD
ns
SW2G Switch Turn–OFF Time, Cgate = pF
(Note 1)
tT–OFF
TBD
ns
OFF Time
(Note 1)
tOFF
1.25
µs
Duty cycle
(Note 1)
d
75
%
NOTE:
1. Guaranteed by design but not production tested.
8
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VDDH
4.9
5.0
5.1
V
VDDH Load Regulation, VBAT = 13.3 V; IVDDH = 0 to –400 mA;
LoadRgVDDH
–40
40
mV
VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; IVDDH = –400 mA;
LineRgVDDH
–20
20
mV
450
mV
DC CHARACTERISTICS:
VDDH
VDDH Output Voltage, IVDDH = –400 mA;
VDDH Drop Out Voltage, VPRE – VDDH, IVDDH = –400 mA;
Decrease VBAT until Resets asserted
VDOV
VDDH Output Current, VBAT = 4.0 V to 26.5 V
IVDDH
VDDH Short Circuit Current, VDDH = 0 V
Freescale Semiconductor, Inc...
VDDH Maximum Allowed Feedback Current
(Power Up Sequence Guaranteed)
ISC
–400
–750
(Note 1)
(Note 2)
VDDH Reset Voltage, Range of VDDH where Resets must remain
asserted
mA
–440
mA
135
µA
VVDDH_HRST
0.5
4.8
V
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
VDD3_3
VDD3_3 Output Voltage, IVDD3_3 = –120 mA;
VDD3_3
3.21
VDD3_3 Load Regulation, VBAT = 13.3 V; IVDD3_3 = 0 to –120 mA
LoadRgVDD3
–40
VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; IVDD3_3 = –120mA
LineRgVDD3
–20
VDD3_3 Drop Out Voltage, VPRE – VDD3_3
IVDD3_3 = –120 mA; Decrease VBAT until Resets asserted
VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V
VDD3_3 Maximum Allowed Feedback Current
(Power Up Sequence Guaranteed)
VDOV
IVDD3_3
VDD3_3 Short Circuit Current, VDD3_3 = 0 V
3.3
ISC
V
40
mV
20
mV
2.04
V
–120
–320
(Note 1)
(Note 2)
VDD3_3 Reset Voltage
Range of VDD3_3 where Resets must remain asserted
3.36
mA
–130
mA
135
µA
VVDD3_HRST
0.5
3.1
V
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
VDDLREF
1.242
1.292
V
VDDL Load Regulation, VBAT = 13.3 V; IVDDL_B = 0 to –40 mA
LoadRgVDDL
–1.6
0
%
VDDL Line Regulation
VBAT = 4.0 V to 26.5 V; IVDDL_B = –40 mA
LineRgVDDL
–0.8
0.8
%
1.3
V
VDDL
–5%
V
0.187
V
VDDL
VDDL Feedback Reference Voltage, pin VDDL_FB
IVDDL_B = 0 to –40 mA
VDDL Drop Out Voltage, VPRE – VDDL
IVDDL = –400 mA; VBAT decreases until Resets asserted
1.267
VDOV
VDDL Reset Voltage,
Range of VDDL where Resets must remain asserted
(Note 1)
VVDDL_HRST
VDDL Susceptibility to Feeding Back
(Power Up Sequence Guaranteed)
(Note 3)
VDDLREF
VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V
VDDL_B Drive Short Circuit Current
VDDL_B = 0V, VBAT = 7.5V to 26.5V
IVDDL_B
IscVDDL_B
VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V
VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6V
0.5
–40
–100
IVDDL_B
IscVDDL_X
–40
–100
VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V
IVDDL_FB
0
NOTE:
1. Guaranteed by design but not production tested.
2. Maximum allowed current flowing back into the regulator output.
3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
mA
–45
mA
mA
–45
mA
2.0
µA
9
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VKAMREF
1.242
1.267
1.292
V
VKAM Load Regulation, VBAT = 13.3 V; IVKAM = –0 to –50 mA
LoadRgVKAM
–1.6
0
%
VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; IVKAM = –50 mA
LineRgVKAM
–0.8
0.8
%
VTVKAM
–1.6
0.8
%
VKAM
0.675
VVKAM_HRST
0.5
DC CHARACTERISTICS:
VKAM
VKAM Feedback Reference Voltage, pin VKAM_FB
Normal Mode (switcher running), IVKAM = 0 to –50mA
VKAM Tracking to VDDL Voltage, VDDL – VKAM
VBAT = 4.0 V to 26.5 V; IVKAM = 0 to –50 mA, IVDDL = 0 to –400mA
VKAM Feedback Voltage — Power Down Mode
3.0 V ≤ Battery Voltage ≤ 26.5 V, IVKAM = –12 mA
Freescale Semiconductor, Inc...
VKAM Reset Voltage (/PORESET)
Range of VKAM where Resets must remain asserted
VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V
VKAM Output Current (Sleep Mode and when VBAT ≤ 4.0 V)
VKAM Short Circuit Current, VKAM = 0 V
IVKAM
VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V
IVKAM_FB
VKAM Output Capacitance Required, Capacitor Initial Tolerance 10%
VKAM
–5%
–50
IVKAM(sleep)
ISC
V
mA
–12
–140
V
mA
–50
mA
0
2.0
µA
22
100
µF
VPP
VPP 5.0V Output Voltage (Default), IVPP = –150 mA
VPP5
4.86
5.0
5.12
V
VPP 3.3 V Output Voltage (Programmed by SPI)
IVPP = –150 mA
VPP3
3.22
3.3
3.38
V
VPP Load Regulation, VBAT = 13.3 V; IVPP = 0 to –150 mA
LoadRgVPP
–0.8
0.8
%
VPP Line Regulation, VBAT = 4.0 V to 26.5 V; IVPP = –150 mA
LineRgVPP
–0.4
0.4
%
VPP Tracking to VDDH Voltage, VDDH – VPP,
VBAT = 4.0 V to 26.5 V; IVPP = 0 to –150 mA;
IVDDH = 0 to –400 mA
VTVPP
–0.8
0.8
%
VPP Drop Out Voltage, VPRE — VPP (VPP set to default 5.0V)
IVPP = –150 mA; Decrease VBAT until VPP is out of specification
(less than 4.86 V)
VDOV
0.4
V
VPP Output Current, VBAT = 4.0 V to 26.5 V
IVPP
VPP Short Circuit Current, VPP = 0 V
–150
mA
ISC
–360
–165
mA
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
NOTE:
1. Guaranteed by design but not production tested.
10
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VREF
4.86
5.0
5.12
V
VREF Load Regulation, VBAT = 13.3 V; IVREF = 0 to –100 mA
LoadRgVREF
–40
40
mV
VREF Line Regulation, VBAT = 4.0 V to 26.5 V; IVREF = –100 mA
LineRgVREF
–20
20
mV
VTVREF
–40
20
mV
0.4
V
DC CHARACTERISTICS:
VREF1, 2, 3
VREF Output Voltage, IVREF = –100 mA
Freescale Semiconductor, Inc...
VREF Tracking to VDDH Voltage, VDDH – VREF,
VBAT = 4.0 V to 26.5 V, IVREF = 0 to –100 mA;
IVDDH = 0 to –400 mA
VREF Drop Out Voltage, VPRE–VREF
IVREF = –100 mA; Decrease VBAT until VREF is out of specification
(less than 4.86 V)
VDOV
VREF Output Current, VBAT = 4.0 V to 26.5 V
IVREF
VREF Short Circuit Current, VREF = –2.0 V
ISC
VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V
IstbVREF
VREF Leakage Current, VREF disabled, VREF = –2.0 V
–100
–260
mA
–110
mA
40
mA
ILKVREF
–2.0
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
mA
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
0.2
V
21
V
–140
mA
40
mA
VSEN
VSEN Saturation Voltage, IVSEN = 0 to –125 mA, VBAT= 8 to 16 V
VSENsat
VSEN Output Voltage Limit, IVSEN = 0 to –125mA, VBAT= 16 to 26.5V
VSENlimit
16
VSEN Short Circuit Current, VSEN = –2.0 V
IscVSEN
–290
VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V
IstbVSEN
VSEN Leakage Current, VSEN disabled, VSEN = –2.0 V
ILKVSEN
17
200
µA
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
NOTE:
1. Guaranteed by design but not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
11
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
5.2
V
DC CHARACTERISTICS:
SUPERVISORY OUTPUTS
Reset Voltage Thresholds
/HRESET to follow /PRERESET by 0.7 µs
VDDH Reset Upper Threshold Voltage
(Note 1)
VDDH Reset Lower Threshold Voltage
(Note 1)
VDD3_3 Reset Upper Threshold Voltage
(Note 1)
VDD3_3 Reset Lower Threshold Voltage
(Note 1)
VDDL Reset Upper Threshold Voltage
(Notes 1, 4)
VDDL Reset Lower Threshold Voltage
(Notes 1, 4)
4.8
V
3.43
3.17
V
V
1.35
1.2
V
V
Freescale Semiconductor, Inc...
/PORESET Voltage Threshold
VKAM Reset Upper Threshold Voltage
(Notes 2, 5)
VKAM Reset Lower Threshold Voltage
(Notes 2, 5)
1.35
1.2
V
V
/PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage
(Note 3)
7.0
V
/PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current,
Vreset< 0.4 V
1.0
mA
/PRERESET, /HRESET, /PORESET Low–Level Output Voltage,
IOL = 1.0 mA
0.5
V
/PRERESET /HRESET /PORESET Leakage Current
15
µA
WAKEUP High–Level Output Voltage, IOH = –800µA
VDDH–0.8
V
WAKEUP Low–Level Output Voltage, IOL = 1.6 mA
HRT Voltage Threshold
0.4
2.49
2.53
V
2.57
V
HRT Sink Current
1.0
mA
HRT Leakage Current
5.0
µA
HRT Saturation Voltage, HRT Current = 1 mA
0.4
V
AC CHARACTERISTICS:
SUPERVISORY OUTPUTS
/PORESET Delay
Delay time from VKAM in regulation and stable to the release of
/PORESET
7.0
10
15
ms
Reset Delay Time
Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset
(/PORESET, /PRERESET)
10
20
50
µs
/HRESET Delay Time
Time From /PRERESET low to /HRESET low
0.5
0.7
1.0
µs
VDDH, VDDL, VREF Power Up Sequence
Max Power Up Sequence Time Dependent on Output Load
Characteristics.
(Note 3)
800
µs
NOTE:
1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET.
2. VKAM regulator output supervised by /PORESET.
3. Guaranteed by design but not production tested.
4. Measured at the VDDL_FB pin.
5. Measured at the VKAM_FB pin.
12
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
CAN Transceiver (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL)
CAN Transceiver Supply Current (dominant), VCANTXD = 0V
IDD(CAN)
30
50
70
mA
CAN Transceiver Supply Current (recessive), VCANTXD = VDDH
IDD(CAN)
2.5
5
10
mA
High–Level Input Voltage Threshold (recessive), Vdiff<0.5V
VIH
1.4
2.0
V
Low–Level Input Voltage Threshold (dominant), Vdiff>1.0V
VIL
0.8
1.4
V
High–Level Input Current, VCANTXD = VDDH
IIH
–5
0
+5
µA
Low–Level Input Current, VCANTXD = 0V
IIL
–10
–15
–30
µA
CANTXD Pull–up Current, VCANTXD = 0V to VIH(max)
IPU
–10
–60
µA
10
pF
VDDH
V
V
Transmitter Data Input CANTXD
Freescale Semiconductor, Inc...
CANTXD Input Capacitance
(Note 1)
CI(TXD)
5
Receiver Data Output CANRXD
High–Level Output Voltage
VCANTXD = VDDH, ICANRXD = –0.8 mA
VOH
VDDH
–0.8
Low–Level Output Voltage, VCANTXD = 0, ICANRXD = 1.6 mA
VOL
0.4
High–Level Output Current, VCANRXD = 0.7VDDH
IOH
–800
µA
Low–Level Output Current, VCANRXD = 0.4V
IOL
1.6
mA
BUS Lines CANH, CANL
Output Voltage CANH (recessive)
VCANTXD = VDDH; RL = open
VCANH(r)
2.0
2.5
3.0
V
Output Voltage CANL (recessive)
VCANTXD = VDDH; RL = open
VCANL(r)
2.0
2.5
3.0
V
100
µA
Output Current CANH (recessive)
VCANTXD = VDDH; VCANH, VCANL = 2.5V
IO(CANH)(r)
Output Current CANL (recessive)
VCANTXD = VDDH; VCANH, VCANL = 2.5V
IO(CANL)(r)
–100
Output Voltage CANH (dominant), VCANTXD = 0V
VCANH(d)
2.75
3.5
4.5
V
Output Voltage CANL (dominant), VCANTXD = 0V
VCANL(d)
0.5
1.5
2.25
V
Differential Output Voltage (dominant) VCANH(d) – VCANL(d)
VCANTXD = 0V
VOdiff(d)
1.5
2.0
3.0
V
Differential Output Voltage (recessive) VCANH(r) – VCANL(r)
VCANTXD = VDDH
VOdiff(r)
0
0.5
V
Differential Input Common Mode Voltage Range
µA
VCM
–2.0
7.0
V
VRXDdiff(th)
0.5
0.75
1.0
V
VIdiff(hys)
0.10
0.2
0.30
V
Short Circuit Output Current CANH
VCANH = – 8.0V, VCANTXD = 0V
ISC(CANH)
–70
–200
mA
Short Circuit Output Current CANL
VCANL = VBAT = 18V, VCANTXD = 0V
ISC(CANL)
70
200
mA
Differential Receiver Threshold Voltage (recessive)
VCANTXD = VDDH, VCANRXD < 0.4V, – 2.0V < VCM < 7.0V
Differential Receiver Input Voltage Hysteresis
Loss of Ground — see Figure 11. Refer to Figure 10 for loading considerations.
Output Leakage Current CANH, VCANH = –18V
IOLKG(CANH)
–2.0
2.0
mA
Output Leakage Current CANHL, VCANL = –18V
IOLKG(CANL)
–2.0
2.0
mA
IILKG(CANH)
–800
800
µA
IILKG(CANL)
–800
800
µA
Loss of Battery — see Figure 12. Refer to Figure 10 for loading considerations.
Input Leakage Current CANH, VCANH = 6.0V
Input Leakage Current CANHL, VCANL = 6.0V
NOTE:
1. Guaranteed by design but not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
13
Freescale Semiconductor,
Inc.
33394
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
CAN Transceiver (Continued) (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL)
CANH,CANL impedance
CANH Common Mode Input Resistance
Ri(CM)CANH
5.0
25
50
kΩ
CANL Common Mode Input Resistance
Ri(CM)CANL
5.0
25
50
kΩ
CANH, CANL Common Mode Input Resistance Mismatch
100(RiCANH – Ri(CM)CANL )/[ (RiCANH + Ri(CM)CANL )/2]
Ri(CM)MCAN
–3.0
3.0
%
RI(dif)
25
50
75
kΩ
Freescale Semiconductor, Inc...
Differential Input Resistance
CANH Input Capacitance, VCANTXD = VDDH
(Note 1)
CI(CANH)
7.5
20
pF
CANL Input Capacitance, VCANTXD = VDDH
(Note 1)
CI(CANL)
7.5
20
pF
Differential Input Capacitance, CINCANH – CINCANL,
VCANTXD = VDDH
CI(CANdif)
3.75
10
pF
(Note 1)
Thermal Shutdown
Thermal Shutdown Junction Temperature
(Note 1)
TSDIS
150
190
°C
Thermal Shutdown Hysteresis
(Note 1)
TSHYS
5.0
20
°C
AC CHARACTERISTICS:
CAN Transceiver
Timing Characteristics
See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load RL = 60 Ω differential.
Delay CANTXD to Bus Active, CL = 3nF
tonTXD
50
ns
Delay CANTXD to Bus Inactive, CL = 10pF
toffTXD
80
ns
Delay CANTXD to CANRXD, Bus Active, CL = 3nF
tonRXD
120
ns
Delay CANTXD to CANRXD, Bus Inactive, CL = 10pF
toffRXD
190
ns
NOTE:
1. Guaranteed by design but not production tested.
VDDH (5V)
CANTxD
0V
CANH = 3.5V (Dominant bit)
CANH (Recessive bit)
Vdiff
CANL (Recessive bit)
2.5 V
CANL = 1.5V (Dominant bit)
0.9 V
Vdiff
0.5 V
VDDH (5V)
CANRxD
0.7VDDH
0.3VDDH
0V
tonTxD
tonRxD
toffTxD
toffRxD
Figure 2. CAN Delay Timing Waveform
14
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3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
VOH
4.2
Typ.
Max.
Unit
DC CHARACTERISTICS:
SPI
DO Output High Voltage, IOH = –100 µA
DO Output Low Voltage, IOL = 1.6 mA
VOL
DO Tri–state Leakage Current, CS = 0
IDOLkg
–10
VIH
2.7
CS, SCLK, DI Input High Voltage
CS, SCLK, DI Input Low Voltage
CS, SCLK, DI Input Voltage Threshold Hysteresis
CS, SCLK, DI Pull–Down Current,
CS, SCLK, DI = VDDH to VIL(min)
V
0.4
V
10
µA
3.1
3.5
V
VIL
1.7
2.1
2.5
V
VIhys
0.8
1.0
1.2
V
ISPI_PD
10
20
50
µA
AC CHARACTERISTICS:
Freescale Semiconductor, Inc...
SPI
NOTES: MPC565 QSMCM/ SPI set for CPHA = 0 & CPOL = 0. *Assumes MPC565 SCLK rise and fall times of 30 ns, DO load = 200pF
–
Transfer Frequency
fop
dc
5.00
MHz
1
2
SCLK Period
tsck
200
–
ns
Enable Lead Time
tlead
105
–
ns
3
4
Enable Lag Time
tlag
50
–
ns
SCLK High Time*
tsckhs
70
–
ns
5
SCLK Low Time*
tsckls
70
–
ns
6
SDI Input Setup Time
tsus
16
–
ns
7
SDI Input Hold Time
ths
20
–
ns
8
SDO Access Time
ta
–
75
ns
9
SDO Disable Time
tdis
–
100
ns
10
SDO Output Valid Time
tvs
–
75
ns
11
SDO Output Hold Time
tho
0
–
ns
12
Rise Time (Design Information)
(Note 1)
tro
–
30
ns
13
Fall Time (Design Information)
(Note 1)
tfo
–
30
ns
14
CS Negated Time
(Note 1)
tcsn
500
–
ns
NOTE:
1. Guaranteed by design but not production tested.
3
14
20% and 70% of Vdd typ.
CS
2
4
1
SCLK
5
8
10
DO
LSB OUT
6
DI
DATA
MSB OUT
DON’T
CARE
12 13
7
LSB IN
9
11
DATA
MSB IN
Figure 3. SPI Timing Diagram
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DATA
15
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4. FUNCTIONAL DESCRIPTION
The 33394 is an integrated buck regulator/linear supply
specifically designed to supply power to the Motorola
MPC55x/MPC56x microprocessors. A detailed functional
description of the Buck Regulator, Linear Regulators, Power
Up/Down Sequences, Thermal Shutdown Protection, Can
Transceiver Reset Functions and Reverse Battery Function
are given below. Block diagram of the 33394 is given in Figure
1. The 33394 is packaged in a 44 pin HSOP, 54 pin SOICW
and the 44 pin QFN.
Freescale Semiconductor, Inc...
4.1. Input Power Source (VBAT, KA_VBAT & VIGN)
The VBAT and KA_VBAT pins are the input power source
for the 33394. The VBAT pins must be externally protected
from vehicle level transients greater than +45 V and reverse
battery. See typical application diagram in Figure 1. The VBAT
pins directly supply the pre–regulator switching power supply.
All power to the linear regulators (except VKAM in the power
down mode) is supplied from VBAT through the switching
regulator. VKAM power is supplied through VBAT input pins
and switching regulator when the 33394 is awake. When the
microprocessor is in a power down mode (no VDDH or VDDL
supply), the current requirement on VKAM falls to less than 12
mA. During this period the VKAM current is supplied from the
reverse battery protected KA_VBAT input.
The KA_VBAT supply pin is the power source to the Keep
Alive Memory regulator (VKAM) in power down mode. Power
is continuously supplied regardless of the state of the ignition
switch (VIGN input). The KA_VBAT input is reverse battery
protected but requires external load dump protection (refer to
Figure 1).
The VIGN pin is used as a control input to the 33394. The
regulation circuits will function and draw current from VBAT
when VIGN is high (active) or REGON is high (active) or on
CAN bus activity (WAKEUP active). To keep the VIGN input
from floating, a 10k pull–down resistor to GND should be
used. The VIGN pin has a 3.0 V threshold and 1.0 volt of
hysteresis. VIGN is designed to operate up to +26.5 volt
battery while providing reverse battery and +45 volt load dump
protection. The input requires ESD, and transient protection.
See Figure 1 for external component required.
W
4.2. Switching Regulator Functional Description
A block diagram of the internal switching regulator is shown
in Figure 4. The switching regulator incorporates circuitry to
implement a Buck or a Buck/Boost regulator with additional
external components. A high voltage, low RDS(on) power
MOSFET is included on chip to minimize the external
components required to implement a Buck regulator. The
power MOSFET is a sense FET to implement current limit. For
low voltage operation, a low side driver is provided that is
capable of driving external logic level MOSFETs. This allows
a switching regulator utilizing Buck/Boost topology to be
implemented. Two independent control schemes are utilized
in the switching regulator.
In Buck mode, voltage mode pulse–width modulation
(PWM) control is used. The switcher output voltage divided by
an internal resistor divider is sensed by an Error Amplifier and
compared with the bandgap reference voltage. The PWM
Comparator uses the output signal from the Error Amplifier as
the threshold level. The PWM Comparator compares the
sawtooth voltage from the Ramp Generator with the output
signal from the Error Amplifier thus creating a PWM signal to
the control logic block. The Error Amplifier inverting input and
16
output are brought out to enable the control loop to be
externally compensated. The compensation technique is
described in paragraph 5.2.3. Buck Converter Feedback
Compensation in the Application Information section. In
order to improve line rejection, feed forward is implemented in
the ramp generator. The feed forward modifies the ramp slope
in proportion to the VBAT voltage in a manner to keep the loop
gain constant, thus simplifying loop compensation. At startup,
a soft start circuit lowers the current limit value to prevent
potentially destructive in–rush current.
In Boost mode, pulse–frequency modulation (PFM) control
is utilized. The duty cycle is set to 75% and the switching
action is stopped either by the Boost Comparator, sensing the
switcher output voltage VPRE, or by the Current Limit circuit
when the switching current reaches its predetermined limit
value. This control method requires no external components.
The selection of the control method is determined by the
control logic based on the VBAT input voltage.
4.2.1. Switching Transistor (SW1)
The internal switching transistor is an n–channel power
MOSFET. The RDS(on) of this internal power FET is
approximately 0.25 ohm at +125_C. The 33394 has a nominal
instantaneous current limit of 3.0 A (well below the saturation
current of the MOSFET and external surface mounted
inductor) in order to supply 1.2 A of current for the linear
regulators that are connected to the VPRE pin (see Figure 1).
The input to the drain of the internal N—channel MOSFET
must be protected by an external series blocking diode, for
reverse battery protection (see Figure 1).
4.2.2. Bootstrap Pin (BOOT)
An external bootstrap 0.1 µF capacitor connected between
SW1 and the BOOT pin is used to generate a high voltage
supply for the high side driver circuit of the buck controller. The
capacitor is pre charged to approximately 10V while the
internal FET is off. On switching, the SW1 pin is pulled up to
VBAT, causing the BOOT pin to rise to approximately
VBAT+10V — the highest voltage stress on the 33394.
4.2.3. External MOSFET Gate Drive (SW2G)
This is an output for driving an external FET for boost mode
operation. Due to the fact that the gate drive supply voltage is
VPRE the external power MOSFET should be a logic level
device. It also has to have a low RDS(on) for acceptable
efficiency. During buck mode, this gate output is held low.
4.2.4. Compensation (INV, VCOMP)
The PWM error amplifier inverting input and output are
brought out to allow the loop to be compensated. The
recommended compensation network is shown in Figure 18
and its Bode plot is in Figure 19. The use of external
compensation components allows optimization of the buck
converter control loop for the maximum bandwidth. Refer to
the paragraph 5.2.3. Buck Converter Feedback
Compensation in the Application Information section for
further details of the buck controller compensation.
4.2.5. Switching Regulator Output Voltage (VPRE)
The output of the switching regulator is brought into the chip
at the VPRE pin. This voltage is required for both the switching
regulator control and as the supply voltage for all the linear
regulators.
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4.2.6. Switching Regulator Output Voltage Sense
(VPRE_S)
This is the switching regulator output voltage sense input.
The switcher output voltage VPRE is divided by an internal
resistor divider and compared with the bandgap reference
voltage (see Figure 4).
Refer to Section 5 Application Information for detailed
description of the switching regulator operation.
BOOT
SW1
VBAT
VPRE
SOFT
START
BOOTSTRAP
CURRENT
LIMIT
HS
DRIVER
VPRE
SWITCHER
MODE
ENABLE
Freescale Semiconductor, Inc...
Vbg
LS
DRIVER
BUCK &
BOOST
CONTROL
LOGIC
40 k
PWM
COMP +
THERMAL
LIMIT
E/A
–
FEED
FORWARD
RAMP
GENERATOR
VPRE
SW2G
VPRE_S
–
+
INV
Vbg
1.25 V
11.7 k
VCOMP
Vbg
SWITCHER
OSCILLATOR
200 kHz
Vbg
+
VPRE –
COMP
Vbg
1.25 V
BOOST
COMP
+
–
Vbg
1.25 V
Figure 4. Switching Regulator Block Diagram
4.3. Voltage Regulator (VDDH)
The VDDH output is a linearly regulated +5.0 +/– 0.10V
voltage supply capable of sourcing a maximum of 400 mA
steady state current from VPRE (+5.6 V) for VBAT voltages
from +4.0 V to +26.5 V (+45V transient). This regulator
incorporates current limit short circuit protection and thermal
shut down protection. The voltage output is stable under all
load/line conditions. However, the designer must consider
ripple and high frequency filtering as well as regulator
response, when choosing external components. See Table 1
in the Applications Information section for recommended
output capacitor parameters.
NOTE :
Backfeeding into the VDDH output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDDH Regulator Section for the maximum
allowed backfed current into the VDDH output.
4.4. Tracking Voltage Regulator (VPP)
This linearly regulated +5.0 V/+3.3 V (SPI selectable)
voltage supply is capable of sourcing 150 mA of steady state
current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to
+26.5 V (up to +45V transient). It tracks the VDDH or VDD3_3
output, and incorporates current limit short circuit protection
and over temperature shut down protection. This output is
intended for FLASH memory programming and includes a
dedicated enable pin (VPP_EN). The regulator enable can
also be controlled through the SPI interface but requires both
the VPP_EN pin and the SPI bit (EN_VPP bit) to be high to
enable. The selection of tracking VDDH or VDD3_3 is
controlled by the VPP_V bit in the SPI. Logic “1” selects VDDH
(default), logic “0” selects VDD3_3. The voltage output is
stable under all load/line conditions. However, the designer
must consider ripple and high frequency filtering as well as
regulator response when choosing external components. See
Table 1 for recommended output capacitor parameters.
The VPP tracking regulator should not be used in parallel
with the VDDH regulator, because this arrangement can
corrupt the proper power sequencing of the IC.
4.5. Tracking Voltage Regulator (VREFn)
The outputs of the VREF1, VREF2, VREF3 linear regulators
are 100 mA at +5.0 V. They track the VDDH output. The power
supplies are designed to supply power to sensors that are
located external to the module. These regulators may be
enabled or disabled via the SPI, which also provides fault
reporting for these regulators. They are protected for short to
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DATA
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battery (+18 V) and short to –2.0 V. Precautions must be taken
to protect the VREF pins from exposure to transients. See
Table 1 for recommended output capacitor parameters.
Applications Information section for recommended output
capacitor parameters.
NOTES:
4.5.1. VREF Over Temperature Latch Off Feature
Freescale Semiconductor, Inc...
If either the VREF1, VREF2 or VREF3 outputs is shorted to
ground for any duration of time, an over temperature shut
down circuit disables the output source transistor once the
local die temperature exceeds +150°C to +190°C. The output
transistor remains off until the locally sensed temperature is
5°C to 20°C. below the trip off temperature. The output(s) will
periodically turn on and off until either the die temperature
decreases or until the fault condition is removed. If one of
these outputs goes into over—temperature shutdown, it will
not impact the operation of any of the other outputs (assuming
that no other package thermal or VPRE current limit
specifications are violated). Fault information is reported
through the SPI communication interface (see Figure 8).
4.6. Voltage Regulator (VDD3_3)
This linearly regulated +3.3 V +/–0.06 V voltage supply is
capable of sourcing 120 mA of steady state current from
VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V
transient). This regulator incorporates current limit short
circuit protection and thermal protection. When no external
pass transistor is used the VDD3_3 and the VDD3_3FB pins
must be shorted together — see Figure 22. The current
capability of the VDD3_3 output can be increased by means
of an external pass transistor — see Figure 1. When the
external pass transistor is used the VDD3_3 internal short
circuit current limit does not provide the short circuit
protection. The voltage output is stable under all load/line
conditions. However, the designer must consider ripple and
high frequency filtering as well as regulator response when
choosing external components. See Table 1 in the
Applications Information section for recommended output
capacitor parameters.
1. The use of an EXTERNAL pass device allows the power
dissipation of the 33394 to be reduced by approximately 50%
and thereby allows the use of a thermally efficient package
such as an HSOP 44 or QFN 44. The base drive control
signal (VDDL_B) is provided by on chip circuitry. The
regulated output voltage sense signal is fed back into the on
chip differential amplifier through pin VDDL_FB. The
collector of this external pass device should be connected to
VPRE to minimize power dissipation and adequately supply
400 mA. Proper thermal mounting considerations must be
accounted for in the PCB design.
2. Backfeeding into the VDDL output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDDL Regulator Section for the maximum
allowed backfed current into the VDDL output.
4.8. Keep–Alive/Standby Supply (VKAM)
This linearly regulated Keep Alive Memory voltage supply
tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is
capable of sourcing 50 mA of steady state current from VPRE
during normal microprocessor operation and 12 mA through
KA_VBAT pin during stand–by/sleep mode. The VKAM
regulator output incorporates a current limit short circuit
protection. The output requires a specific range of capacitor
values to be stable under all load/line conditions. See Table 1
in the Applications Information section for recommended
output capacitor parameters.
NOTE :
The source current for the VKAM supply output depends on
the sleep/wake state of the 33394.
4.9. Switched Battery Output (VSEN)
NOTE :
Backfeeding into the VDD3_3 output can cause problems
during the power up sequence. Refer to the Electrical
Characteristics VDD3_3 Regulator Section for the maximum
allowed backfed current into the VDD3_3 output.
4.7. Voltage Regulator (VDDL)
The output voltage of the VDDL linear regulator is
adjustable by means of an external resistor divider.
This linearly regulated +/–2% core voltage supply uses an
external pass transistor and is capable of sourcing 40 mA
base drive current typically (see application circuit, Figure 1)
of steady state current. The collector of the external NPN pass
transistor is connected to VPRE (+5.6 V) for a VBAT voltage
from +7.5 V to +26.5 V (+45V transient). The voltage output is
stable under all load/line conditions. However, the designer
must consider ripple and high frequency filtering as well as
regulator response when choosing external components.
Also, the dynamic load characteristics of the microprocessor,
relative to CPU clock frequency changes must be considered.
An additional external pass transistor, for VDDL regulation in
the Boost mode, can be added between protected battery
voltage (see Figure 1) and VDDL, with its base driven by
VDDL_X. In that arrangement the 33394’s core voltage supply
operates over the whole input voltage range VBAT = +4.0 V
to +26.5 V (up to +45V transient). See Table 1 in the
18
This is a saturated switch output, which tracks the VBAT and
is capable of sourcing 125 mA of steady state current from
VBAT. This regulator will track the voltage VBAT to less than
200 mV, and its output voltage is clamped at +17 V. The gate
voltage of the internal N—channel MOSFET is provided by a
charge pump from VBAT. There is an internal gate–to–source
voltage clamp. This regulator is short circuit protected and has
independent over—temperature protection. If this output is
shorted and goes into thermal shutdown, the normal operation
of all other voltage outputs is not impacted. This output is
controlled by the SPI VSEN bit.
NOTE:
A short to VBAT on VREF1, VREF2, VREF3 or VSEN will
not result in additional current being drawn from the battery
under normal (+8 V to +18 V) voltage levels. Under jumpstart
condition (VBAT = +26.5 V) and during load dump condition,
the device will survive this condition, but additional current
may be drawn from the battery.
4.9.1. VSEN Over Temperature Latch Off Feature
If the VSEN output is shorted to ground for any duration of
time, an over temperature shut down circuit disables the
output source transistor once the local die temperature
exceeds +150°C to +190°C. The output transistor remains off
until the locally sensed temperature drops 5°C to 20°C below
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the trip–off temperature. The output will periodically turn on
and off until either the die temperature decreases or until the
fault condition is removed. If the VSEN output goes into
over—temperature shutdown, it does not impact the operation
of any of the other outputs (assuming that no other package
thermal or VPRE current limit specifications are violated).
Fault information is reported through the SPI communication
interface (see Figure 8).
Freescale Semiconductor, Inc...
4.10. Resets To Microprocessor
/PORESET – Power On Reset, /PRERESET — Pre Reset,
/HRESET– Hardware Reset. All the Reset pins are open drain
‘active low’ outputs, capable of sinking 1.0 mA current and
able to withstand +7.0 V. See Figure 1 and Figure 20 for
recommended pull–up resistor values and their connection.
The /PORESET pin is pulled up to the VKAM voltage by a
pull up resistor. It is connected to the microprocessor Power
On Reset (POR) pin, and is normally high. During initial battery
connect the /PORESET is held to ground by the 33394. After
the VKAM supply is in regulation and an internal 10 ms timer
has expired, the /PORESET is released. If VKAM goes out of
regulation the device will first pull the /PORESET and
/PRERESET followed by a 0.7 µs delay then /HRESET. By
/HRESET low VDDH, VDD3_3 and VDDL will start a power
down sequence. When the fault is removed a standard power
up sequence is initiated. The VKAM linear regulator output
must be out of regulation for greater than 20 µs before
/PORERSET and /PRERESET (with /HRESET 0.7 µs
delayed) are pulled low. If a fault occurs on VKAM in the
Key–Off Mode (when the VIGN is off) and the fault is then
removed the VKAM will regulate but /PORESET will not be
released until Key–On (asserting VIGN pin) allows the 10 ms
timer to run.
The Reset signals (/PRERESET, /HRESET) are not
asserted when the 33394 enters Sleep Mode by asserting the
/SLEEP pin. When exiting out of Sleep Mode the 33394
asserts the Resets (/PRERESET, /HRESET) during the power
up sequence.
The /PRERESET and /HRESET pins are pulled up to the
VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to
section 5. Application Information, paragraph 5.3.
Selecting Pull–Up Resistors for detailed description of
these two connection scenarios. The 33394 monitors the main
supply voltages VDDH, VDD3_3 and VDDL. If any of these
voltages falls out of regulation limits the /PRERESET will be
pulled down followed by the /HRESET after 0.7 µs delay, and
the power down sequence will be initiated. There are several
different scenarios how to connect the /PRERESET and
/HRESET pins to the microprocessor. Typically the
/PRERESET pin will be connected to the IRQ0 pin of the
microprocessor, and the /HRESET to the microprocessor
/HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL
linear regulator outputs must be out of regulation for greater
than 20 µs before /PRERESET (with /HRESET 0.7 µs
delayed) are pulled low.
4.11. Hardware Reset Timer (HRT)
The HRT pin is used to set the delay between VDDH,
VDD3_3 and VDDL active and stable and the release of the
/HRESET and /PRERESET outputs. An external resistor and
capacitor is used to program the timer. To minimize quiescent
current during power down modes, the RC timer current
should be drawn from one of the VDD supplies (see Figure 1).
The threshold on the HRT pin has zero temperature coefficient
and is set at 2.5 V.
4.12. Power Up/Down Sequencing
The 33394 power up sequence is specifically designed to
meet the power up and power down requirements of the
MPC565 microprocessor. The MPC565 processor requires
that VDDH remain within 3.1 volts of VDDL during power up
and can not lag VDDL by more than 0.5 volts. This condition
is met by the 33394 regardless of load impedance. It is critical
to note that the 33394 under normal conditions is designed to
supply VKAM prior to the power up sequence on VDDH,
VDD3_3 and VDDL. During power up and power down
sequencing /PRERESET and /HRESET are held low. Power
up and power down sequencing is implemented in six steps.
During this process the reference voltage for VDDH, VDD3_3
and VDDL is ramped up in six steps. Minimum power up/down
time is dependent on the internal clock and is 800 µs.
Maximum power up/down time is also dependent on load
impedance. During the power up/down cycle, voltage level
requirements for each step of VDDH, VDD3_3 and VDDL
must be met before the supply may advance to the next
voltage level. Hence VDDH and VDDL will remain within the
3.1/0.5 V window. Figure 6 illustrates a typical power up and
down sequence.
4.13. Regulator Enable Function (REGON)
This feature allows the microcontroller to select the delayed
shut down of the 33394 device. It holds off the activation of the
Reset signals, to the microcontroller, after the VIGN signal has
transitioned and signals the request to shutdown the VDDH,
VDD3_3, VDDL, VSEN and the VREFn supplies. This allows
the microcontroller to delay a variable amount of time, after
sensing that the VIGN signal has transitioned and signaled the
request to shutdown the regulated supplies. This time can be
used to store data to EPROM memory, schedule an orderly
shutdown of peripherals, etc. The microcontroller can then
drive the REGON signal, to the 33394, to the low logic state,
to turn off the regulators (except for the VKAM supply).
4.14. Regulator Shutdown Function (/SLEEP)
This feature allows for an external control element (e.g.
microprocessor) to shut down the 33394 regulators, even if
the VIGN signal (or REGON) is active, by asserting the
/SLEEP pin from high to low (falling edge transition). In this
case the 33394 initiates the power down sequence, but the
Reset signals (/PRERESET, /HRESET) are not asserted. This
allows the microprocessor to continue to execute code when
it is supplied only from the Keep Alive supply VKAM. When the
microprocessor exits sleep state by pulling /SLEEP pin high
the Resets (/PRERESET, /HRESET) are asserted during the
power up sequence.
The /SLEEP pin has an internal pull down, therefore when
its functionality is not used this pin can be either pulled up to
VKAM, VBAT, pulled down to ground or left open.
The /SLEEP pin should not be pulled up to VDDH.
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DATA
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Freescale Semiconductor,
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33394
Output
MPC56X
Supply Input
* VDD3_3 = 3.3V (not used by MPC56x)
VDDH = 5.0V
VDDH, VDDA,
VFLASH5
VDD3_3 = 3.3V*
VDDH
VDD3_3
VDDL
NVDDL, QVDDL,
VDD, VDDSYN, 2.6V
VDDF
VDDL = 2.6V
2
VIGN
6
4
8
9
10
VKAM = 2.6V
VKAM
1
3
KAPWR,
VDDSRAM1,2,3
VDDRTC
2.6V
/PORESET
2.6V
5.0V
11
7
PORESET
10ms
/PRERESET
IRQ0
2.6V
5
Freescale Semiconductor, Inc...
/HRESET
0.7ms
HRT DELAY
0.7ms
HRT DELAY
HRT DELAY
0.7ms
HRESET
Figure 5. 33394 Timing Diagram
1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms.
2 VIGN is applied, 33394 starts power up sequence.
3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay
programmable by an external capacitor and resistor, HRT pin).
4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated.
5 /HRESET is asserted 0.7 ms after /PRERESET
6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released
(with an HRT delay).
7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET
with 0.7 ms delay) are asserted – see Note 1.
8 33394 initiates power down sequence.
9 Fault on VKAM removed, the 33394 initiates the start up sequence.
10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT
delay).
11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed.
VDDH = 5.0 V
VDD3_3 = 3.3 V
LESS THAN 3.1 V
0V
POWER UP SEQUENCE
VDDL = 2.6 V*
POWER DOWN SEQUENCE
*NOTE: VDDL = 2.6 V for MPC565
Figure 6. 33394 Power Up/Down Sequence
* VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.
20
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pin be in a logic low state whenever the chip select pin (CS)
makes any transition. For this reason, it is recommended
though not necessary, that the SCLK pin is commanded to a
low logic state as long as the device is not accessed (CS in
logic low state). When CS is in a logic low state, any signal at
the SCLK and DI pin is ignored and the DO is tri—stated (high
impedance).
4.15. SPI Interface to Microcontroller (Serial
Peripheral Interface)
The pins specified for this function are: DI (Data Input), DO
(Data Output), CS (Chip Select) and SCLK. Refer to Figure 3
for the 33394 SPI timing information. The delay, which is
needed from CS leading edge active to the first SCLK leading
edge transition (0 to 1) is approximately 125 ns. The SCLK
rate is a maximum of 5.0 MHz. The SPI function will provide
control of such 33394 features as VREFn regulator turn on/off,
VREFn fault reporting and CAN wake up feature activation.
Refer to Figure 7 & Figure 8 for the data and status bit
assignments for the 16 bit SPI data word exchange.
4.15.3. DI (Data Input) Pin
The DI pin is used for serial data input. This information is
latched into the input register on the rising edge of SCLK. A
logic high state present on DI will program a specific function
(see Figure 7 for the data bits assignments for the 16 bit SPI
data word exchange.). The change will happen with the falling
edge of the CS signal. To program the specific function of the
33394 a 16 bit serial stream of data is required to be entered
into the DI pin starting with LSB. For each rising edge of the
SCLK while CS is logic high, a data bit instruction is loaded into
the shift register per the data bit DI state. The shift register is
full after 16 bits of information have been entered. To preserve
data integrity, care should be taken to not transition DI as
SCLK transitions from a low to high logic state.
Freescale Semiconductor, Inc...
4.15.1. CS (Chip Select) Pin
The system MCU selects the 33394 to be communicated
with through the use of the CS pin. Whenever the pin is in a
logic high state, data can be transferred from the MCU to the
33394 and vice versa. Clocked—in data from the MCU is
transferred to the 33394 shift register and latched in on the
falling edge of the CS signal. On the rising edge of the CS
signal, output status information is transferred from the output
status register into the device’s shift register. Whenever the
CS pin goes to a logic high state, the DO pin output is enabled
allowing information to be transferred from the 33394 to the
MCU. To avoid any spurious data, it is essential that the
transition of the CS signal occur only when SCLK is in a logic
low state.
4.15.4. DO (Data Output) Pin
The serial output (DO) pin is the output from the shift
register. The DO pin remains tri—state until the CS pin goes
to a logic high state. See Figure 8 for the status bits
assignments for the 16–bit SPI data word exchange. The CS
positive transition will make LSB status available on DO pin.
Each successive positive SCLK will make the next bit status
available. The DI/DO shifting of data follows a
first—in—first—out protocol with both input and output words
transferring the Least Significant Bit (LSB) first.
4.15.2. SCLK (System Clock) Pin
The shift clock pin (SCLK) clocks the internal shift registers
of the 33394. The serial input (DI) data is latched into the input
shift register on the rising edge of the SCLK. The serial output
pin (DO) shifts data information out of the shift register also on
the rising edge of the SCLK signal. It is essential that the SCLK
33394 SPI Registers:
Serial Input Data/Control
Default Value
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
1
1
1
1
1
1
1
1
Name
Bit Definitions:
Bit 15 to 8 = 0
Default Value
Bit
Name
7
6
5
4
3
2
1
0 (LSB)
WKUP
CAN_EN
VPP_V
EN_VPP
VSEN
VREF3
VREF2
VREF1
Bit Definitions:
Bit 7 — WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity
Bit 6 — CAN_EN: Enables CAN receiver, will draw small current during power off
Bit 5 — VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V
Bit 4 — EN_VPP: – Used to turn the VPP regulator off and on from the MCU
Bit 3 — VSEN: – Used to turn the VSEN regulator off and on from the MCU
Bit 2 — VREF3: – Used to turn the VREF3 regulator off and on from the MCU
Bit 1 — VREF2: – Used to turn the VREF2 regulator off and on from the MCU
Bit 0 — VREF1: – Used to turn the VREF1 regulator off and on from the MCU
Figure 7. SPI Input Data/ Control Register
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Freescale Semiconductor,
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33394 SPI Registers:
Serial Output Data/Status
Default Value
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Default Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0 (LSB)
VSEN–T
VREF3–T
VREF2–T
VREF1–T
VSEN–I
VREF3–I
VREF2–I
VREF1–I
Name
Bit Definitions:
Bit 15 to 8 = 0
Freescale Semiconductor, Inc...
Name
Bit Definitions:
Bit 7 — VSEN–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 6 — VREF3–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 5 — VREF2–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 4 — VREF1–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists
Bit 2 — VREF3–I: – Will be set (1), if a current limit condition exists
Bit 1 — VREF2–I: – Will be set (1), if a current limit condition exists
Bit 0 — VREF1–I: – Will be set (1), if a current limit condition exists
NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal
Figure 8. SPI Output Data/ Status Register
4.16. CAN Transceiver
The CAN protocol is defined in terms of ’dominant’ and
’recessive’ bits. When the digital input (CANTXD) is a logic ”0”
(negated level, dominant bit), CANH goes to +3.5 V (nominal)
and CANL goes to +1.5 V (nominal). The digital output will also
be negated. When the digital input is logic ”1” (asserted level,
recessive bit), CANH and CANL are set to +2.5 V (nominal).
The corresponding digital output is also asserted.
4.16.1. CAN Network Topology
There are two 120 Ω (only two), terminations between the
CANH and CANL outputs. The majority of the time, the module
controller will contain one of the terminations. The other
termination should be as close to the other ”end” of the CAN
Bus as possible. The termination provides a total of 60 Ω
differential resistive impedance for generation of the voltage
difference between CANH and CANL. Current flows out of
CANH, through the termination, and then through CANL and
back to ground. The CAN bus is not defined in terms of the bus
capacitance. A filter capacitor of 220 pF to 470 pF may be
required. The maximum capacitive load on the CAN bus is
then 15 nF (not a lumped capacitance but distributed through
the network cabling). Refer to Figure 9.
Common Mode Choke
2.2 mH
PCM
CANH
Max : 31 Remotes
470 pF*
120
Vehicle Term.
470 pF*
W
120
W
CANL
470 pF*
470 pF*
*Optional
Figure 9. CAN Load Characteristics
4.16.2. CAN Transceiver Functional Description
A block diagram of the CAN transceiver is shown in Figure
10. A summary of the network topology is shown in Figure 9.
The transceiver has wake up capability controlled by the state
of the SPI bit WKUP. This allows 33394 to enter a low power
mode and be awakened by CAN bus activity. When activity is
22
sensed on the CAN bus pins, the 33394 will perform a power
up sequence and will provide the microprocessor with
indication (WAKEUP pin high) that wake up occurred from a
CAN message. The 33394 may be placed back in low
quiescent mode by pulling the /SLEEP pin from high to low.
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The Wake–up function can be disabled through SPI by setting
the WKUP bit to 0.
The CAN transceiver of the 33394 is designed for
communications speeds up to 1.0 Mbps. The use of a
common mode choke may be required in some applications.
When the 33394 CAN transceiver physical interface is not
used in the system design, the CAN bus driver pins CANH and
CANL should be shorted together.
4.16.3. CANH
CANH is an output driver stage that sources current on the
CANH output. It’s output follows CANL, but in the opposite
polarity. The output is short circuit protected. In the event that
battery or ground is lost to the module, the CANH transmitter’s
output stage is disabled.
Freescale Semiconductor, Inc...
4.16.4. CANL
CANL is an output driver stage that sinks current on the
CANL output. The sink type output is short circuit protected.
In the event that battery or ground is lost to the module, the
CANL transmitter’s output stage is disabled.
4.16.5. CANTXD
input drives the outputs to a differential (dominant) voltage,
where the CANH output is +3.5 V and the CANL output is +1.5
V. A logic ‘1’ input drives the outputs to their idle (recessive)
state, where the CANH and CANL outputs are +2.5 V. An
internal pull–up to VDDH shall guarantee a logic ”1” input level
if this input is left open. On power–up, or in the event of a
thermal shutdown, this input must be toggled high and then
low to clear the thermal fault latch. The faulted CAN bus
output(s) will remain disabled until the thermal fault latch is
cleared. The CAN bus data rate is determined by the data rate
of CANTXD.
4.16.6. CANRXD
This is a CMOS compatible output used to send data from
the CAN bus pins, CANH and CANL, to the microprocessor.
When the voltage differential between CANH and CANL is
under the differential input voltage threshold (recessive state),
CANRXD is logic ‘1’. When the voltage differential between
CANH and CANL is over the voltage threshold (dominant
state), CANRXD is logic ‘0’. In standby mode, input voltage
threshold remains the same. There is a minimum of 0.1 V of
hysteresis between the high and low (and vice versa)
transition points.
CANTXD input comes from the microcontroller and drives
that state of the CAN bus pins, CANH and CANL. A logic ‘0’
OverTemp
Sense &
Hysteresis
VDDH
VDDH
CAN_EN
10 µA
CANTXD
CANH
Complimentary
High/Low Side
Drivers w/
Current Limit
CANL
0.8 – 2.0 V
W
25 k
0.5 – 1.0 V
+
–
CANRXD
AWAKE
CAN_EN
CANRXD
5k
W
5k
W
+
–
2.5 V
W
25 k
Figure 10. CAN Transceiver Block Diagram
4.16.7. CAN Over Temperature Latch Off Feature
If the CANH or CANL output is shorted to ground or battery
for any duration of time, an over temperature shut down circuit
disables the output stage. The output stage remains latched
off until the CANTXD input is toggled from a logic ’1’ to a logic
’0’ to clear the over temperature shutdown latch. Thermal
shutdown does not impact the remaining functionality of the
IC.
4.16.8. CAN Loss of Assembly Ground
The definition of a loss of ground condition at the device
level is that all pins of the IC (excluding transmitter outputs) will
see very low impedance to VBAT. The loss of ground is shown
on the module level in Figure 11. The nomenclature is suited
to a test environment. In the application, a loss of ground
condition results in all I/O pins floating to battery voltage. In
this condition, the CAN bus must not source enough current
to corrupt the bus.
4.16.9. CAN Loss of Assembly Battery
The loss of battery condition at the IC level is that the power
input pins of the IC see infinite impedance to the battery supply
voltage (depending upon the application) but there is some
undefined impedance looking from these pins to ground. In
this condition, the CAN bus must not sink enough current to
corrupt the bus. Refer to Figure 12.
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DATA
23
Freescale Semiconductor,
Inc.
33394
ICANH
Battery
16 V
VBAT
51
W
CANH
51
CANL
POWER
OAK
W
43
W
VDD3_3
W
VDDL
43
68
Freescale Semiconductor, Inc...
W
–2V
+
–2V
–
ICANL
VIGN
CANL
POWER
OAK
+
GND
+
+6V
–
W
VDDH
43
W
VDD3_3
W
VDDL
43
68
–
+
+6V
–
GND
Figure 11. CAN Loss of Ground Test Circuit
24
CANH
VBAT
ICANL
VIGN
VDDH
ICANH
Battery
Figure 12. CAN Loss of Battery Test Circuit
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Freescale Semiconductor, Inc...
5. APPLICATION INFORMATION
This section provides information on external components
that are required by the 33394. The IC is designed to operate
in an automotive environment. Conducted immunity and
radiated emissions requirements have been addressed
during the design. However, the IC requires some external
protection.
Protection is required for all pins connected directly to
battery. The module designer should use an MOV or another
transient voltage suppressor in all cases, when the load
dump transition exceeds + 45 volts with respect to ground.
Protection should also include a reverse battery protection
diode (or relay) and input filter. This is required to protect the
33394 from ESD and +/– 300V ignition transients. Typical
configurations are shown in Figure 1. Outputs and inputs
connected directly to connector pins require module level
ESD protection.
reasonable for most of practical applications. Then the ESR
of the output capacitor has to satisfy the following condition:
5.1. Selecting Components for Linear Regulators
This level of ESR requires a relatively large capacitance. In
order to maintain the linear regulator stability and to satisfy
large load current steps requirements the solid tantalum
capacitor 100µF/10V with ESR = 200 mΩ. One device that
meets these requirements is the TPSC107K010S020
tantalum capacitor from the AVX Corporation.
The output capacitor of the linear regulator serves two
different purposes. It maintains the linear regulator loop
stability, and it provides an energy reservoir to supply current
during very fast load transients. This is especially true when
supplying highly modulated loads like microcontrollers and
other high–speed digital circuits. Due to the limited
bandwidth of the linear regulators, the output capacitor is
selected to limit the ripple voltage caused by these abrupt
changes in the load current. During the fast load current
transients, the linear regulator output capacitor alone
controls the initial output voltage deviation. Hence, the output
capacitor’s equivalent series resistance (ESR) is the most
critical parameter.
The outputs, which do not experience such severe
conditions (the VREF e.g.), use the output capacitor mainly
for stability purpose, and therefore its capacitance value can
be significantly smaller. The typical output capacitor
parameters are: C = 1.0 µF; ESR = 2.0 ohms. When a
ceramic 1 µF capacitor is used, the ESR can be provided by
a discrete serial resistor (see Figure 20).
The following example shows how to determine the output
capacitance for a heavily loaded output supplying digital
circuits.
5.1.1. Selecting the Output Capacitor Example:
The output capacitance must be selected to provide
sufficiently low ESR. The selected capacitor must have an
adequate voltage, temperature and ripple current rating for
the particular application.
In order to calculate the proper output capacitor
parameters, several assumptions will be made.
1) During the very fast load current transients, the linear
regulator can not supply the required current fast enough,
and therefore for a certain time the entire load current is
supplied by the output capacitor. 2) The capacitor’s
equivalent series inductance (ESL) is neglected. These
assumptions can greatly simplify the calculations, and are
ESR
v DDVIoo
Where:
∆Vo is the maximum allowed linear regulator voltage drop
caused by the load current transient.
∆Io is the maximum current transient, which can occur due to
the abrupt step in the linear regulator load current.
In this example the VDDH output with the 400 mA load step
is considered with the maximum voltage drop of 100mV. This
gives the output capacitor’s maximum ESR value of:
ESR
DVESR + ESR
mV + 250 mW
+ 100
400 mA
DIo + 200 mW
400 mA
+ 80 mV
In the next step, the voltage drop associated with the
capacitance can be calculated:
A 5 ms
DVC + DIo C Dt + 0.4100
mF + 20
mV
Where:
C is the output capacitance.
Dt is the linear regulator response time.
∆Io is the maximum current transient, which can occur due to
the abrupt step in the linear regulator load current.
Assuming that the capacitor ESL is negligible, the total
voltage drop in the voltage regulator output caused by the
current fast transient can be calculated as:
DVtotal + DVESR ) DVC + 80
mV
) 20 mV + 100 mV
A ceramic capacitor with capacitance value 10nF should
be placed in parallel to provide filtering for the high frequency
transients caused by the switching regulator.
Properly sized decoupling ceramic capacitor close to the
microprocessor supply pin should be used as well. Table 1
shows the suggested output capacitors for the 33394 IC
linear regulator outputs.
Other factors to consider when selecting output capacitors
include key off timing for memory retention. Though the
VKAM is not a heavily loaded output, the VKAM output
capacitor has to have a sufficiently large capacitance value to
supply current to the microcontroller for a certain time after
battery voltage is disconnected.
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Table 1. Linear Regulator Output Capacitor Examples
SMD tantalum
Output
Value/Rating
VDDH
100uF/10V
TPSC107K010S0200
VPP
33uF/10V
TPSB336K010S0650
VDD3_3
68uF/6.3V
TPSC686K006S0200
VDDL
100uF/6.3V
TPSC107K006S0150
VREFx
10uF/16V
THJB106K016S
VKAM*
100uF/6.3V
TPSC107K006S0150
5.2. Switching Regulator Operation
Freescale Semiconductor, Inc...
Part n. (AVX Corp.)
The 33394 switching regulator circuit consists of two basic
switching converter topologies. One is the typical voltage
mode PWM step–down or buck regulator, which provides
pre–regulated VPRE voltage (+5.6 V) during normal
operating conditions.
During cold start–up, when the car battery is weak, the
input voltage for the 33394 can fall below the lower operating
limit of the step–down converter. Under such conditions, the
step–up or boost converter provides the required value of the
VPRE voltage. The following paragraphs describe the basic
principles of the two converters operation.
inductor input voltage is clamped one forward diode drop
below ground. The inductor current during the off time is:
iL(off)
toff is the off–time of the power switch.
iL(off) is the inductor current during the off time.
Vfwrd is forward voltage drop across the rectifier.
During the steady state operation iL(on) = iL(off) = ∆IL, and
Vin/Vo = d
One switching cycle of the step–down converter operation
has two distinct parts: the power switch on state and the off
state. When the power switch is on, one inductor terminal is
connected to the input voltage Vin, and the other inductor
terminal is the output voltage Vo. During this part of the
switching period the rectifier (catch diode) is back biased,
and the current ramps up through the inductor to the output:
Where:
iL(on)
+
* Vo)
ton
L
Where:
Vin is the input voltage.
T is switching period, T = 1/f.
f is the frequency of operation.
Two relations give the ripple voltage in the output capacitor
Co. The first describes ripple voltage caused by current
variation upon the output capacitance Co:
+ 8CoDIL
f
The other is caused by current variations over the output
capacitor equivalent series resistance ESR:
+
Vo is the output voltage.
iL(on) is the inductor current during the on–time.
L is the inductance of the inductor L.
During the on time, current ramping through the inductor
stores energy in the inductor core.
During the off time of the power switch, the input voltage
source Vin is disconnected from the circuit. The energy
stored in the core forces current to continue to flow in the
same direction, the rectifier is forward biased and the
26
d is the duty cycle, and d = ton/T.
VppCo
ton is the on–time of the power switch.
toff
Where:
Buck Mode
(Vin
)
+ (Vo * Vfwd
L
VppESR
DIL RESR
Practically, the ESR contributes predominantly to the buck
converter ripple voltage:
VppESR >>VppCo
The inductor peak current can be calculated as follows:
IpkL
+ Io ) 12 DIL
Where:
Io is the average output current.
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IQ
IL
Q
L
DIL
+
+
ID
Vin
VO
CO
D
RLOAD
–
ILO
L
ILOAD
CO
–ID
RLOAD
Vout
–
POWER SWITCH ON
Freescale Semiconductor, Inc...
IQ
+
+
Vin
IO
IL
VD
Vfwd
ILO
+
ILOAD
+
CO
VD(fwd)
RLOAD
VCo
Vout
ton
–
POWER SWITCH OFF
toff
t
T
Figure 13. Basic Buck Converter Operation and its Waveforms
Boost Mode
The operation of the boost converter also consists of two
parts, when the power switch is on and off. When the power
switch turns on, the input voltage source is placed directly
across the inductor, and the current ramps up linearly
through the inductor as described by:
iL(on)
+ Vin L ton
iL(off)
+ (Vo * VLin)
Where:
toff is the off–time of the power switch.
Vo is the output voltage.
During the steady state operation iL(on) = iL(off) = ∆IL, and
Where:
d
ton is the on–time of the power switch.
+ Vo V*oVin
Vin is the input voltage.
Where:
iL(on) is the inductor current during the on–time.
d is the duty cycle, and d = ton/T.
L is the inductance of the inductor L.
T is switching period, T = 1/f.
The current ramping across the inductor stores energy
within the core material. In order to maintain steady–state
operation, the amount of energy stored during each switching
cycle, times the frequency of operation must be higher (to
cover the losses) than the power demands of the load:
f is the frequency of operation.
Psto
+ 12 LI pk f u Pout
The ripple voltage of the boost converter can be described
as:
VppCo
2
When the power switch turns off again, the inductor voltage
flies back above the input voltage and is clamped by the
forward biased rectifier at the output voltage.
The current ramps down through the inductor to the output
until the new on time begins or, in case of discontinuous
mode of operation, until the energy stored in the inductor core
drops to zero.
toff
+ CIoo
(Vo
* Vin)
Vo
f
Where:
VppCo is the ripple caused by output current.
The portion of the output ripple voltage caused by the ESR
of the output capacitor is:
VppESR
+ (Io
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Vo
Vin
) 12 DIL)
RESR
27
Freescale Semiconductor,
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33394
Where Io is the average output current.
IpkL
The inductor peak current is given by the following
equation:
IL
ID
L
D
Vo
Vin
) 12 DIL
DIL
+
+
IQ
Q
+ Io
IL
VO
RLOAD
CO
Vin
–
ID
IO
+
Freescale Semiconductor, Inc...
+
L
ION
Vin
Vout
ILOAD
CO
IQ
RLOAD
–
POWER SWITCH ON
VQ
IL
+
IOFF
+
VIN
Vout
ILOAD
CO
RLOAD
VCo
ton
–
POWER SWITCH OFF
toff
t
T
Figure 14. Basic Boost Converter Operation and its Waveforms
5.2.1. Switching Regulator Component Selection
The selection of the external inductor L2 and capacitor C2
values (see Figure 15) is a compromise between the two
modes of operation of the switching regulator, the pre
regulated voltage VPRE and the dropout voltage of the linear
regulators. Ideal equations describing the peak—peak
inductor current ripple, peak—peak output voltage ripple and
peak inductor current are shown below. Since the switching
regulator will work mostly in the buck mode, the inductor and
the switcher input and output capacitor were selected for
optimum buck controller performance, but also taking into
account the restriction placed by adopting the boost
converter as well.
IQ
VRDS(on)
VRL
IL
Vfwd2
Q1
RDS(on)
RL
L
D2
ESR
D1
Vin
Vfwd1
Q2
+
VO
CO
–
Figure 15. 33394 Switcher Topology
The following example shows a procedure for determining
the component values. The VPRE output is set to regulate to
28
Vin(typ) = 13.5 V
Io = 1.2
VPRE = 5.6 V (+6 V in the boost mode)
f = 200 kHz
Vfwd1 = Vfwd2 = 0.5 V
Maximum allowed output voltage ripple in the buck mode
Vpp(max) = 0.2 V/2 = 0.1 V (to allow for process and
temperature variations).
5.2.1.1. Selecting the Inductor
RLOAD
+
5.6 V and the linear regulators require a minimum of 0.4 V
dropout voltage. This leaves a ±0.2 V window for the
peak—to–peak output voltage ripple. Assuming the following
conditions:
In order to select the proper inductance value, the inductor
ripple current ∆IL has to be determined. The usual ratio of ∆IL
to output current Io is:
∆IL = 0.3 Io
As described in the previous section, and taking into
account the 33394 switcher topology (see Figure 15), the
inductor ripple current can be estimated as:
DIL +
(Vin
* Vo * Vfwd2)
L
)
Vo Vfwd2
Vin f
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33394
After substitution, the calculated inductance value is L = 45
µH, which gives 47 µH standard component value.
The peak–to peak ripple current value is: ∆IL = 0.345 A.
The peak inductor current is given by:
ILpk = 0.5∆IL + Io = 0.5x0.345 + 1.2 = 1.37[A]
The inductor saturation current is given by the upper value
of the 33394 internal switch current limit Ilim(max) = 3.0 A.
Considering also the inductor serial resistance, these
requirements are met, for example by the PO250.473T
inductor from Pulse Engineering, Inc.
Freescale Semiconductor, Inc...
5.2.1.2. Selecting the Catch Diode D1
The rectifier D1 current capability has to be greater than
calculated average current value.
The maximum reverse voltage stress placed upon this
rectifier D1 is given by maximum input voltage (maximum
transient battery voltage). These requirements are met, for
example by the HSM350 (3 A, 50 V) schottky diode from
Microsemi, Inc.
VppESR = ∆IL x RESR = 0.345 x 0.08 = 28 [mV]
One device that meets both, the low ESR, and the
temperature stability requirements is, for example, the
TPSV107K020R0085 tantalum capacitor from AVX Corp.
Boost Converter Power Capability
The boost converter with selected components has to be
able to deliver the required power.
Due to the nature of this non–compensated PFM control
technique, the Boost converter output ripple voltage is higher
than if it utilized a typical PWM control method. Therefore the
switcher output voltage level is set higher than in the Buck
mode (in the Boost mode VPRE = +6 V), in order to maintain
a sufficient dropout voltage for the 5–volt linear regulators
(VDDH, VREFs) and to avoid unwanted Resets to the
microcontroller.
The most stringent conditions for the 33394 boost
converter occur with the lowest input voltage:
Vin(min) = 3.5 V
Io = 0.8 A
5.2.1.3. Selecting the Output Capacitor
Vpre = +6 V
The output capacitor Co should be a low ESR part,
therefore the 100 µF tantalum capacitor with 80 mΩ ESR was
chosen.
f = 200 kHz
From the formula for calculating the ripple voltage:
VRES
IL
Vfwd2
RD
L
D2
Vfwd1 = Vfwd2 = 0.5 V
d = 0.75, duty cycle is fixed at 75% in boost mode
IL
ILIM
I01
I02
+
ESR
Q2
IQ
VO
+
Vin
RLOAD
IL1
IL2
L1 > L2
DIL1 < DIL2
IO1 > IO2
CO
T
–
t
Figure 16. 33394 Switcher Topology – Boost Mode
The input voltage drop associated with the resistance of
the internal switch Q1 and inductor series resistance can be
estimated as:
VD
[ Ipk(min)
RD
+ 2.5 A
0.35
W + 0.875
V
Where:
VD is the voltage dissipated on the major parasitic
resistances, RDSon of the internal power switch and inductor
series resistance RL.
For the worst case conditions:
RD = RDSon(max) + RL = 0.25 + 0.1 = 0.35[Ω]
Ipk(min) is the minimum internal power switch current limit
value.
Then the equation for calculating ∆IL can be modified as
follows:
VD
DIL + Vin *
L
* 0.875
+ 3.5
47 10 *
6
+ 125[mA]
) Vfwd2) * (Vin * VD)] d +
(Vo ) Vfwd2) f
[(6 ) 0.5) * (3.5 * 0.875)] 0.75
(6 ) 0.5) 0.2 10
[(Vo
6
Then the maximum average input current can be
calculated as:
IinAve
+ Ipk(min) * 12 DIL + 2.5 * 0.125
+ 2.43[A]
2
Finally, the boost converter power capability has to be
higher than the required output power or:
Pin(max)
h u Pout
Where Pin(max) is the boost converter maximum input power:
h is the boost converter efficiency, in our case h is
estimated to be h = 85%, and includes switching losses of the
external power switch Q2 (MOSFET) inductor and capacitors
AC losses, and output rectifier D2 (schottky) switching
losses.
Pout is the boost converter output power, which includes
power loss of the output rectifier D2:
+ (Vo ) Vfwd2) Io + (6 ) 0.5) 0.8 + 5.2[W]
Pin + (Vin * VD) IinAve h +
+ (3.5 * 0.875) 2.43 0.85 + 5.42[W]
Pout
As can be seen, the boost converter input power capability
meets the required criteria.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
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29
Freescale Semiconductor, Inc...
Freescale Semiconductor,
Inc.
33394
5.2.1.4. Selecting the Power MOSFET Q2
5.2.2. Input Filter Selection
The boost converter maximum output voltage plus the
voltage drop across the output schottky rectifier D2 gives the
MOSFET’s maximum drain–source voltage stress:
BVdsQ2>Vo+Vfwd2 = 6 V+0.5 V, as can be seen, the
breakdown voltage parameter is not critical.
The more important in our case is the Q2 current handling
capability. The external power MOSFET has to withstand
higher currents than the upper current limit of the 33394:
Since the switcher will work in the Boost mode only during
cold crank condition, the 33394 EMC (electromagnetic
compatibility) performance is not of concern during this mode
of operation. Therefore, only the Buck mode of operation is
important for selecting the appropriate input filter. For the
Buck converter topology (see Figure 13) the low impedance
3rd order filter (C3, L2, C4 and C26 in the Application
Schematic Diagram Figure 20) offers a good solution. It can
be seen from the Buck converter current waveforms that
comparatively high current pulses are drawn from the
converter’s input source. The filter inductance must be kept
minimal and the capacitor, which is placed right next to the
power switch, must be sized large enough to provide
sufficient energy reservoir for proper switcher operation.
The ESR of this input capacitor combination C4, C26 has
to be sufficiently low to reduce the switching ripple of the
switcher input node VBAT. There are three main reasons to
keep the voltage ripple of the VBAT pin at its minimum. First,
it is the EMC (electromagnetic compatibility) performance of
the switcher in the normal operating mode (buck mode).
Second, it allows a smooth transition between the boost and
buck mode of operation. Third, it helps to avoid entering an
undervoltage condition too early. A practical way to achieve
sufficiently low ESR of the switcher input capacitor, even at
low temperature extremes, is to use several high value
ceramic capacitors in parallel with a large electrolytic
capacitor. These capacitors should be physically placed as
close to the VBAT pins as possible.
IDQ2>3A
In order to keep the power dissipation of the 33394 boost
converter to its minimum, a very low RDSon power MOSFET
has to be selected. Moreover, due to the fact that the 33394
external MOSFET gate driver is supplied from VPRE, in
order to assure proper switching of Q2 a logic level device
has to be selected.
Last but not least, the Q2 package has to suitable for the
harsh automotive environment with low thermal resistance.
These requirements are met, for example by the
MTD20N03HDL power MOSFET from ON Semiconductor.
5.2.1.5. Selecting the Boost Converter Output
Rectifier D2
Criteria similar to that of selecting the power MOSFET was
used to select the boost converter output rectifier. Its reverse
breakdown voltage is not a critical parameter:
VrD2>Vo=6 V
The D2 rectifier has to withstand higher peak current than
is the 33394 internal switch upper current limit Ilim(max).
The most important parameter is its forward voltage drop,
which has to be minimal. This parameter is also crucial for the
proper 33394 switcher functionality, and especially for proper
transition between the buck and boost modes.
Finally, its switching speed, forward and reverse recovery
parameters play a significant role when selecting the output
rectifier D2.
These requirements are met, for example by the HSM350
schottky rectifier from Microsemi, Inc.
5.2.3. Buck Converter Feedback Compensation
A typical control loop of the buck regulator is shown in
Figure 17. The loop consists of a power processing block —
the modulator in series with an error–detecting block — the
Error (Feedback) Amplifier. In principle, a portion of the
output voltage (VPRE of the 33394 switcher) is compared to
a reference voltage (Vbg) in the Error Amplifier and the
difference is amplified and inverted and used as a control
input for the modulator to keep the controlled variable (output
voltage VPRE) constant.
Vin
Gain Block
(Modulator)
Vin
+
S
G
Vout
–
+
PWM
Signal
Ramp
–
+
Vout
To Load
MODULATOR
H
Zf
Feedback
Block
Vout/Vin = G/(1 + GH)
–
+
Zin
Reference
Voltage
ERROR FEEDBACK AMPLIFIER
Figure 17. The Buck Converter Control Loop
30
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
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33394
C2
R2
80
CLOSED LOOP (overall)
60
C3
R3
R1
– E/A
+
R
VCOMP
U1
Ref
fp(LC)
ERROR
AMPLIFIER
40
GAIN (dB)
VPRE_S
C1
fp2
fp1
20
fZ1 A1
MODULATOR
0
A2
fZ2
Ifxo
–20
ADC
1
10
100
1000
10 k
100 k
1M
100 k
1M
f (Hz)
90
MODULATOR
0
+ 2p Ǹ1LC
o
This double pole exhibits a —40dB per decade rolloff and
a —180 degree phase shift.
Another point of interest in the modulator’s transfer
function is the zero caused by the ESR of the output
capacitor Co and the capacitance of the output capacitor
itself:
fz(ESR)
–60
+ DVVine
Where Ve is the maximum change of the Error Amplifier
voltage to change the duty cycle from 0 to 100 percent (Ve =
2.6 V at Vbat =14 V).
As can be seen from Figure 19, the buck converter
modulator transfer function has a double complex pole
caused by the output L–C filter. Its corner frequency can be
calculated as:
fp(LC)
fZ(ESR)
–40
1
+ 2pRESR
Co
The ESR zero causes +20dB per decade gain increase,
and +90 degree phase shift.
Once the open loop transfer function is determined, the
appropriate compensation can be applied in order to obtain
the required closed loop cross over frequency and phase
margin (~60 degree) — refer to Figure 18 and Figure 19.
Figure 19 shows the 33394 Switching Regulator modulator
gain–phase plot, E/A gain–phase plot, closed loop
gain–phase plot, and the E/A compensation circuit. The
frequency fxo is the required cross–over frequency of the
buck regulator.
In order to achieve the best performance (the highest
bandwidth) and stability of the voltage–mode controlled buck
PWM regulator the two–pole–two–zero type of compensation
was selected — see Figure 19 for the compensated Error
Amplifier Bode plot, and Figure 18 for the compensation
network. The two compensating zeros and their positive
phase shift (2 x +90 degree) associated with this type of
compensation can counteract the negative phase shift
caused by the double pole of the modulator’s output filter.
PHASE (deg)
Freescale Semiconductor, Inc...
Figure 18. Error Amplifier Two–Pole–Two–Zero
Compensation Network
The process of determining the right compensation
components starts with analysis of the open loop (modulator)
transfer function, which has to be determined and plotted into
the Bode plot (see Figure 19). The modulator DC gain can be
determined as follows:
–90
ERROR AMPLIFIER
–180
–270
CLOSED LOOP (overall)
–360
1
10
100
1000
10 k
f (Hz)
Figure 19. Bode Plot of the Buck Regulator
The frequency of the compensating poles and zeros can
be calculated from the following expressions:
+ 2pR12C2
1
fz2 +
[ 2pR11C3
2p(R1 ) R3)C3
1
fp1 +
2pR3C3
C ) C2
fp2 + 1
[ 1
fz1
2pR2C1C2
2pR2C1
and the required absolute gain is:
+ RR21
+ R2(R1 ) R3) [ R2
A1
A2
R1R3
R3
Refer to Application Schematic Diagram (Figure 20) and
Table 2 for the 33394 switcher component values.
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
31
Freescale Semiconductor,
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33394
Table 2.
Part number
(Figure 18)
Application diagram
part number (Figure 1)
Component value
R1
33394 internal resistor
39.6kΩ
R2
R2
100kΩ
R3
R1
430Ω
C1
C6
100pF
C2
C7
1.0nF
C3
C5
3.3nF
Where R is the HRT timer pull–up resistor,
C is the HRT timer capacitor
VB is the pull–up voltage,
Vth is the HRT timer threshold voltage (Vth = 2.5V
nominal value),
VSAT is the saturation voltage of the internal pull–down
transistor.
If the HRT timer pull–up resistor is connected to VDDH
(see Figure 1) and the resistor value is ≥ 47 k , therefore the
VSAT can be neglected, the formula for calculating the time
delay can be simplified to:
W
Freescale Semiconductor, Inc...
5.3. Selecting Pull–Up Resistors
All the Resets (/PORESET, /PRERESET and /HRESET)
are open drain outputs, which can sink a maximum of 1 mA
drain current. This determines the pull–up resistor minimum
value. VKAM should be used as the pull–up source for the
/PORESET output. /PORESET is pulled low only during
initial battery connect or when VKAM is below 2.5 volts (for
VDDL = 2.6 V).
To select the /PRERESET and /HRESET pull–up resistor
connections, consider current draw during sleep modes. For
example, the pull up resistor on /PRERESET and /HRESET
should receive its source from VDDL, if the sleep mode or low
power mode of the module is initiated primarily by the state of
the VIGN pin. Refer to Figure 20 for recommended pull–up
resistor values.
Another way to connect the /PRERESET and /HRESET
pull–up resistors is to connect them to the VKAM output
together with the /PORESET pull–up resistor (see Figure 1).
This is the preferable solution when the sleep or low power
mode is initiated primarily by the microprocessor. In that
case, when the 33394 is shut down by pulling the /SLEEP pin
down, all three Resets (/PORESET, /PRERESET and
/HRESET) stay high. Since they are pulled–up to the supply
voltage (VKAM) they draw no current from the VKAM and the
module quiescent current is minimized.
5.4. Selecting Hardware Reset Timer Components
The HRT input sets the delay time from VDDH, VDD3_3
and VDDL stable to the release of /PRERESET and
/HRESET. When sizing the delay time the module design
engineer must consider capacitor leakage, printed board
leakage and HRT pin leakage. Resistor selection should be
low enough to make the leakage currents negligible. The
Hardware Reset (/HRESET) delay can be calculated as
follows:
Delay time:
tD
32
+ * RC
*
tD
+ 0.7
RC
5.5. Selecting the VKAM Resistor Divider
The VKAM linear regulator output voltage is divided by an
external resistor divider and compared with the bandgap
reference voltage (Vbg) in the input of the VKAM error
amplifier. The resistor divider can be designed according to
the following formula:
VKAM
+ VKAMref
ǒ) Ǔ
1
Rupper
Rlower
VKAMref = 1.267 V
Where VKAMref is the bandgap reference voltage.
Since the VKAM feedback pin (VKAM_FB) input current is
only a few nA, the resistor value can be selected sufficiently
high in order to minimize the quiescent current of the module.
See Figure 20 for the VKAM resistor divider recommended
values.
5.6. Selecting the VDDL Resistor Divider
The VDDL regulator resistor divider is designed according
to the same formula as described in the paragraph above
(see Figure 20).
VDDL
+ VDDLref
ǒ) Ǔ
1
Rupper
Rlower
Where VDDLref = 1.267 V
Nonetheless, the actual resistor values should be chosen
several decades lower than in the previous example. This is
due to the fact that the VDDL linear regulator needs to be
pre–loaded by a minimum of 10 mA current in order to
guarantee stable operation. See Figure 20 for the VDDL
resistor divider recommended values.
*
(VB VSAT) Vth
]
(VB VSAT)
ln[
*
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
D2 *
MURS320T3 Q3
JP1
+Battery
L2
6.8uH
1
Vbat
2
VDDH
2
+
C3
1.0uF/50V
C4
100uF/35V
+ C2
D3
SS25
SW1
DIP–2
R1
430R
C29
1.0uF/50V
1.0uF/50V
C26
C28
VKAM
10nF
R4
22k
+
C23
10nF
C24
22uF
R6
20k
VREF1
VPP_EN
C8
10nF
C9
1.0uF
VDDL_X
VDDL_B
VDDL_FB
R19
2.0R
CANRXD
CANTXD
VPP
VBAT
VBAT
VBAT
VBAT
VBAT
KA_VBAT
N/C
VIGN
VKAM
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
VDDL_FB
N/C
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
SW1
SW1
SW1
SW1
SW1
N/C
BOOT
SW2G
GND
INV
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
N/C
DO
SCLK
DI
CS
N/C
/SLEEP
HRT
CANH
CANL
GND
MC33394DWB
VSEN
REGON
WAKEUP
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VPRE
C30
37
DO
36
R10 4.7k
SCLK
35
R11 4.7k
DI
34
R12 4.7k
CS
C22
10uF
37
36
35
34
VREF2
C15
10nF
R20
2.0R
VREF3
R15
47k
R8
120R
R17
10k
C11
10nF
C14
1.0uF
/SLEEP
C25 *
R16
10k
+
C10
47uF
/PORESET
+
/HRESET
/PRERESET
C21
10nF
R9 4.7k
VDDH
10nF
VPRE_S
C13
10uF
+3.3V
C7
1.0nF
R22
100k
+
C12
10nF
C6
100pF
BOOT
U1
VIGN
R3
4.7k
C1
100nF
CANL
R14
4.7k
C5 100uF/16V
3.3nF
Q1
MMSF3300R2
R13
18R
VPP_EN
IGN
VDDH
C18
1.0uF
C27 *
C16
1.0uF
C17
10nF
R21
2.0R
R18
10k
VKAM
Q3
VPRE
Q2
MJD31C
+Battery
GND
+Battery
GND
+Battery
GND
+Battery
GND
VKAM
/SLEEP
VPP
WAKEUP
VSEN
IGN
+3.3V
REGON
/PORESET
/PRERESET
CANH
/HRESET
CANL
CANRXD
VREF2
CANTXD
VREF1
CS
VREF3
DI
VPP_EN
SCLK
VDDH
DO
VDDL
GND
VDDL = 2.6V
J1
VDDL_B
Q3
MJD31C
VDDL_X
VDDL
R5
110R
VDDL_FB
+
C15
10nF
C20
47uF
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Freescale Semiconductor, Inc...
D1
20BQ030
L1
47uH
1
CANH
1
2
R7
100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 20. 33394 Application Circuit Schematic Diagram
Table 3. 33394 Evaluation Board Performance
Parameter
Value
(TA = 25_C, Vin = 14V)
V
Load
[mV]
[mA]
Line Regulation
(Vin = 5.2V to 26.5V)
DV
Load Regulation
(Vin = 14 V)
[mV]
Load
[mA]
DV
[mV]
Load
[mA]
VDDH
5.028
400
10
400
18
0 to 400
VPP
5.026
150
10
150
5
0 to 150
VREF1
5.023
100
8
100
8
0 to 100
VREF2
5.022
100
8
100
10
0 to 100
VREF3
5.021
100
6
100
11
0 to 100
VDD3_3
3.307
120
5
120
7
0 to 120
VDDL
2.667
400
5
400
10
0 to 400
VKAM
2.638
60
2
60
14
0 to 60
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
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Freescale Semiconductor,
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33394
Freescale Semiconductor, Inc...
Table 4. 33394DWB Evaluation Board Bill of Material
Item
Qty.
1
1
C1
Part Designator
100nF/16V, Ceramic X7R
Value/ Rating
Any manufacturer
Part Number/ Manufacturer
2
1
C2
100µF/20V
TPSV107K020R0085, AVX Corp.
3
3
C3,C26,C29
1.0µF/50V
C1812C105K5RACTR, Kemet
4
1
C4
100µF/35V
UUB1V101MNR1GS, Nichicon
5
1
C5
3.3nF, Ceramic X7R
Any manufacturer
6
1
C6
100pF, Ceramic X7R
Any manufacturer
7
1
C7
1.0nF, Ceramic X7R
Any manufacturer
8
10
C8,C11,C12,C15,C17,C19,C21,C23,C28,C30
10nF, Ceramic X7R
Any manufacturer
9
4
C9,C14,C16,C18
1.0µF, Ceramic X7R
Any manufacturer
10
2
C20,C10
47µF/10V, Tantalum
TPSC476K010R0350, AVX Corp.
11
1
C13
10µF/16V, Tantalum
TPSB106K016R0800, AVX Corp.
12
1
C22
10µF/6.3V, Tantalum
TPSA106K006R1500, AVX Corp.
13
1
C24
22µF/6.3V, Tantalum
TPSA226K006R0900, AVX Corp.
14
2
C25,C27
470pF, Ceramic X7R
Any manufacturer
15
1
D1
30V/2A Schottky
20BQ030, International Rectifier
16
1
D2
200V/3A Diode
MURS320T3, ON Semiconductor
17
1
D3
50V/2A Schottky
SS25, General Semiconductor
18
1
JP1
2–pin, 0.2 (5.1mm)
Terminal Block
19
1
J1
34–pin, 0.1 x 0.1
PCB Header Connector
20
1
L1
47µH
P0250.473T, Pulse Engineering
21
1
L2
6.8µH
P0751.682T, Pulse Engineering
22
1
Q1
30V/11.5A, Mosfet
MMSF3300R2, ON Semiconductor
23
2
Q2,Q3
100V/3A, BJT
MJD31C, ON Semiconductor
24
1
R1
430R, Resistor 0805
Any manufacturer
25
1
R2
100k, Resistor 0805
Any manufacturer
26
6
R3,R9,R10,R11,R12,R14
4.7k, Resistor 0805
Any manufacturer
27
1
R4
22k, Resistor 0805, 1%
Any manufacturer
28
1
R5
110R, Resistor 0805, 1%
Any manufacturer
29
1
R6
20k, Resistor 0805, 1%
Any manufacturer
30
1
R7
100R, Resistor 0805, 1%
Any manufacturer
31
1
R8
120R, Resistor 0805
Any manufacturer
32
1
R13
18R, Resistor 0805
Any manufacturer
33
1
R15
47k, Resistor 0805
Any manufacturer
34
3
R16,R17,R18
10k, Resistor 0805
Any manufacturer
35
3
R19,R20,R21
2.0R, Resistor 0805
Any manufacturer
36
1
SW1
2–Position DIP Switch
BD02, C&K Components
37
1
TP1
Test Point, 0.038
240–333, Farnell
38
1
U1
Integrated Circuit
33394DWB/ Motorola
34
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
m
1.0 F/
50 V
SW1
DIP–2
VPP_EN
m
1.0 F/50 V C3
R14
4.7k
R3
4.7 k
m
6.8 H
MURS320T3
C29
L2
2
m
m
+
C23
10 nF
C1
100 nF
C24
100 F
m
R4
22 k
12
13
14
15
16
17
18
19
20
21
22
+
C9
1.0 F
m
5.0V @ 150mA VPP
+
C12
10 nF
VKAM_FB
VSEN
REGON
WAKEUP
VREF1
VPP_EN PC33394FC
VPP
VDD3_3
VDD3_3FB
VDDL_X
VDDL_B
C13
33 F
VPRE
Q2
MJD31C
+3.3V
m
+
+
C30
33 F/16 V
m
R1
430R
U1
44
43
42
41
40
39
38
37
36
35
34
INV
VCOMP
VPRE
VPRE_S
VDDH
VREF2
VREF3
DO
SCLK
DI
CS
C6
100 pF
C7
1.0 nF
R2 100 k
VPRE
5.0V @ 400 mA
VDDH
C10
47 F
m
+
C11
10 nF
5.0V @ 100 mA
VREF2
C14
1.0 F
m
+
C15
10 nF
47 k
C18
1.0 F
m
120R
R19
10R
37
36
35
VKAM
R16
10 k
R17
10 k
R18
10 k
C25 *
R9
4.7 k
DO
R10
4.7 k
SCLK
R11
4.7 k
DI
R12
4.7 k
CS
VREF3
C27 *
C16
1.0 F
m
5.0V @ 100 mA
+
C17
10 nF
VPRE
Q3
MJD31C
2.6V @ 400 mA
VDDL
C19
10 nF
Q4
VDDL_B
Q4
MJD31C
VDDL_X
VDDL
+
C20
100 F
m
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+BATTERY
GND
+BATTERY
GND
+BATTERY
GND
+BATTERY
GND
VKAM
/SLEEP
VPP
WAKEUP
VSEN
IGN
+3.3V
REGON
/PDRESET
/PRERESET
CANH
/HRESET
CANL
CANRXD
VREF2
CANTXD
VREF1
CS
VREF3
DI
VPP_EN
SCLK
VDDH
DO
VDDL
GND
34
J1
C2
100 F/
20 V
OPTIONAL
OUTPUT
FILTER
L3
1
2
R15 VDDH
+
C22
47 mF
R13
23
24
25
26
27
28
29
30
31
32
33
m
VPRE_S
C5
3.3 nF
Q1
MTD20N03HDL
18R
R6
20 k
C8
10 nF
m
D1
20BQ030
2
47 H
D3
SS25
100 F/ C4 1.0 F/ C26
50 V
35 V
5.0V @ 100mA VREF1
Freescale Semiconductor, Inc...
+
L1
1
VIGN
2.6V VKAM
C28
10 nF
C21
10 nF
VBAT
11
10
9
8
7
6
5
4
3
2
1
VDDH
1
VKAM
VIGN
KA_VBAT
VBAT
VBAT
SW1
SW1
SW1
BOOT
SW2G
GND
+BATTERY
1
2
VDDL_FB
/PRERESET
/HRESET
/PORESET
CANRXD
CANTXD
GND
CANL
CANH
HRT
/SLEEP
JP1
Q4
*
D2
R5
110R
VDDL_FB
R7
100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 21. 33394 Application Circuit with Increased 3.3V Output Current Capability
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
35
Freescale Semiconductor,
Inc.
33394
Freescale Semiconductor, Inc...
Table 5. 33394FC Evaluation Board Bill of Material
Item
Qty.
1
1
C1
Part Designator
100nF/16V, Ceramic X7R
Value/ Rating
Any manufacturer
Part Number/ Manufacturer
2
1
C2
100µF/20V
TPSV107K020R0085, AVX Corp.
3
3
C3,C26,C29
1.0µF/50V
C1812C105K5RACTR, Kemet
4
1
C4
100µF/35V
UUB1V101MNR1GS, Nichicon
5
1
C5
1.5nF, Ceramic X7R
Any manufacturer
6
1
C6
100pF, Ceramic X7R
Any manufacturer
7
1
C7
1.0nF, Ceramic X7R
Any manufacturer
8
9
C8,C11,C12,C15,C17,C19,C21,C23,C28
10nF, Ceramic X7R
Any manufacturer
9
1
C18
1.0µF, Ceramic X7R
Any manufacturer
10
3
C9,C14,C16
1.0µF/35V Tantalum
TPSA105K035R3000, AVX Corp.
11
2
C10,C22
47µF/10V Tantalum
TPSC476K010R0350, AVX Corp.
12
1
C13
33µF/10V Tantalum
TPSB336K010R0500, AVX Corp.
13
1
C20
100µF/6.3V Tantalum
TPSC107K006R0150, AVX Corp.
14
1
C24
22µF/6.3V, Tantalum
TPSA226K006R0900, AVX Corp.
15
2
C27,C25
470pF, Ceramic X7R
Any manufacturer
16
1
C30
33µF/16V
TPSC336K016R0300, AVX Corp.
17
1
D1
30V/ 2A Schottky
20BQ030, International Rectifier
18
1
D2
200V/3A Diode
MURS320T3, ON Semiconductor
19
1
D3
SS25
SS25, General Semiconductor
20
1
JP1
2–pin, 0.2 (5.1mm)
Terminal Block
21
1
J1
34–pin, 0.1 x 0.1
PCB Header Connector
22
1
L1
47µH
P0250.473T, Pulse Engineering
23
1
L2
6.8µH
P0751.682T, Pulse Engineering
24
1
L3
Ferrite Bead
HF30ACC575032/ TDK
25
1
Q1
30V/20A Mosfet
MTD20N03HDL, ON Semiconductor
26
3
Q2,Q3,Q4
100V/3A BJT
MJD31C, ON Semiconductor
27
1
R1
680R, Resistor 0805
Any manufacturer
28
1
R2
100k, Resistor 0805
Any manufacturer
29
6
R3,R9,R10,R11,R12,R14
4.7k, Resistor 0805
Any manufacturer
30
1
R4
22k, Resistor 0805, 1%
Any manufacturer
31
1
R5
110R, Resistor 0805, 1%
Any manufacturer
32
1
R6
20k, Resistor 0805, 1%
Any manufacturer
33
1
R7
100R, Resistor 0805, 1%
Any manufacturer
34
1
R8
120R, Resistor 0805
Any manufacturer
35
1
R13
18R, Resistor 0805
Any manufacturer
36
1
R15
47k, Resistor 0805
Any manufacturer
37
3
R16,R17,R18
10k, Resistor 0805
Any manufacturer
38
1
R19
10R, Resistor 0805
Any manufacturer
39
1
SW1
2–Position DIP Switch
BD02, C&K Components
40
1
TP1
Test Point
240–333, Farnell
41
1
U1
Integrated Circuit
MC33394DWB/ Motorola
36
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
1
C1
100µF +
S1
ON
OFF
2
3
R5
4.7k
C5
10nF
4
VKAM = 2.6V @ 60mA
5
+
C6
10nF
C7
47µF
6
R2
22k
7
R1
20k
8
9
VREF1 = 5V @ 100mA
10
+
C8
10nF
C9
1.0µF
VPP = 5V @ 150mA
12
Freescale Semiconductor, Inc...
+
C17
47µF
C16
10nF
11
VDDH
3.3V @ 120mA
C10
10nF
C11
47µF
14
15
VPRE
Q1
MJD44H11
16
VDDL = 2.6V @ 600mA
17
+
C12
10nF
13
+
C13
100µF
R4
22R
/PRERESET
R3
20R
18
/HRESET
19
/PORESET 20
R6 10k
VKAM
R7 10k
21
22
VBAT
SW1
VBAT
SW1
SW1
KA_VBAT
VIGN
BOOT
VKAM
SW2G
GND
VKAM_FB
INV
VSEN
REGON
VCOMP
VPRE
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
PC33394
Input voltage +7V to +26.5V
VPRE_S
VDDH
VREF2
VREF3
DO
VDDL_X
SCLK
VDDL_B
DI
VDDL_FB
CS
/PRERESET
/HRESET
/SLEEP
HRT
L1
47µF
44
+
43
Cb
100nF
42
41
330nF
40
CANH
CANRXD
CANL
CANTXD
GND
D1
MBRS340T
C2
100µF
BAV99
Cf3
3.3nF
39
38
Rf3
430R
Rf2
100k
Cf1
100pF
Cf2
1nF
37
36
35
VDDH = 5V @ 400mA
34
+
VREF2 = 5V @ 100mA
33
+
32 VREF3 = 5V @ 100mA C18
1.0µF
+
31 C20
C21
10nF
1.0µF
30
C14
100µF
C19
10nF
C15
10nF
29
28
27
Rt
47k
26
VDDH
25
/PORESET
VPRE = 5.6V
24
Ct
1.0 µF
60R
23
R8 10k
Figure 22. 33394 Buck–Only Application
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
37
Freescale Semiconductor,
Inc.
33394
+12V @ 100mA
+
D3
+
C23
47µF
Input voltage +10V to +26.5V
1
C1
100µF +
S1
ON
2
SW1
C5
10nF
KA_VBAT
SW1
4
5
+
C6
10nF
C7
47µF
6
R2
22k
7
R1
20k
8
9
VREF1 = 5V @ 100mA
10
+
C8
10nF
C9
1.0µF
VPP = 5V @ 150mA
12
+
C17
47µF
C16
10nF
11
VDDH
3.3V @ 120mA
13
+
C10
10nF
C11
47µF
14
15
VPRE
Q1
MJD31C
16
VDDL = 2.6V @ 400mA
17
+
C13
100µF
R4
22R
/PRERESET
R3
20R
18
/HRESET
19
/PORESET 20
R6 10k
VKAM
R7 10k
21
22
VIGN
BOOT
VKAM
SW2G
GND
VKAM_FB
INV
VSEN
REGON
VCOMP
VPRE
WAKEUP
VREF1
VPP_EN
VPP
VDD3_3
VDD3_3FB
PC33394
3
R5
4.7k
VKAM = 2.6V @ 60mA
Freescale Semiconductor, Inc...
VBAT
44
C22
47µF
–12V @ 100mA
VPRE = 5.6V
43
T1
OFF
C12
10nF
SW1
VBAT
D3
VPRE_S
VDDH
VREF2
VREF3
DO
VDDL_X
SCLK
VDDL_B
DI
VDDL_FB
CS
/PRERESET
/HRESET
/SLEEP
HRT
/PORESET
CANH
CANRXD
CANL
CANTXD
GND
42
+
Cb
100nF
41
D1
MBRS340T
C2
100µF
Rf3
430R
40
39
Cf3
3.3nF
38
37
Rf2
100k
Cf1
100pF
Cf2
1nF
36
35
VDDH = 5V @ 400mA
34
+
VREF2 = 5V @ 100mA
33
+
32 VREF3 = 5V @ 100mA C18
1.0µF
+
31 C20
C21
10nF
1.0µF
30
C14
100µF
C19
10nF
C15
10nF
29
28
27
Rt
47k
26
VDDH
25
24
Ct
1.0 µF
60R
23
R8 10k
Figure 23. 33394 Flyback Converter Provides Symmetrical Voltages
38
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
PACKAGE DIMENSIONS
DH SUFFIX
44–LEAD HSOP
PLASTIC PACKAGE
CASE 1291–01
ISSUE O
PIN ONE ID
h
X 45 _
E3
E2
E5
44
4X
D1
D3
e
42X
1
D2
4X
22
23
EXPOSED
HEATSINK AREA
B
E1
E
bbb
M
E4
A
22X
BOTTOM VIEW
C B
Y
H
DATUM
PLANE
ÇÇÇÇ
ÉÉÉ
ÇÇÇÇ
ÉÉÉ
ÇÇÇÇ
b1
A A2
c1
c
C
SEATING
PLANE
b
aaa
C A
SECTION W–W
GAUGE
PLANE
bbb C
M
L1
q
W
W
L
A1
Freescale Semiconductor, Inc...
0.325
D
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS –A– AND –B– TO BE DETERMINED AT
DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
(1.600)
MILLIMETERS
MIN
MAX
3.000
3.400
0.025
0.125
2.900
3.100
15.800 16.000
11.700 12.600
0.900
1.100
–––
1.000
13.950 14.450
10.900 11.100
2.500
2.700
6.400
7.300
2.700
2.900
–––
1.000
0.840
1.100
0.350 BSC
0.220
0.350
0.220
0.320
0.230
0.320
0.230
0.280
0.650 BSC
–––
0.800
q
0_
8_
aaa
0.200
bbb
0.100
DIM
A
A1
A2
D
D1
D2
D3
E
E1
E2
E3
E4
E5
L
L1
b
b1
c
c1
e
h
DETAIL Y
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
39
Freescale Semiconductor,
Inc.
33394
PACKAGE DIMENSIONS
FC SUFFIX
44–LEAD QFN
PLASTIC PACKAGE
CASE 1310–01
ISSUE D
PIN 1
INDEX AREA
0.1 C
9
A
2X
M
0.1 C
G
0.1 C
2X
1.0 1.00
0.8 0.75
0.05 C
9
(0.325)
(0.65)
0.05
0.00
C
5
SEATING PLANE
Freescale Semiconductor, Inc...
DETAIL G
VIEW ROTATED 90 ° CLOCKWISE
M
B
0.1 C A B
6.85
6.55
DETAIL M
PIN 1 IDENTIFIER
34
EXPOSED DIE
ATTACH PAD
44
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF–PQFP–N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER
LEADS AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES,
MAXIMUM DRAFT ANGLE IS 12°.
1
33
6.85
6.55
0.1 C A B
0.65
23
44X
0.75
0.50
40X
11
22
N
12
44X
0.37
0.23
VIEW M–M
0.1
M
C A B
0.05
M
C
(45 ° )
(3.53)
44X
0.065
0.015
0.60
0.24
0.60
0.24
(0.25)
DETAIL N
DETAIL N
CORNER CONFIGURATION OPTION
PREFERRED CORNER CONFIGURATION
4
4
°
3.4
3.3
DETAIL T
(90 )
BACKSIDE
PIN 1 INDEX
0.475
0.425
2X 0.39
0.31
R 0.25
0.15
40
2X
0.1
0.0
DETAIL M
DETAIL M
DETAIL T
PREFERRED BACKSIDE PIN 1 INDEX
BACKSIDE PIN 1 INDEX OPTION
PREFERRED BACKSIDE PIN 1 INDEX
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
PACKAGE DIMENSIONS
DWB SUFFIX
54–LEAD SOICW–EP
PLASTIC PACKAGE
CASE 1377–01
ISSUE B
10.3
5
7.6
7.4
9
C
B
2.65
2.35
52X
1
54
0.65
Freescale Semiconductor, Inc...
PIN 1 INDEX
4
9
B
27
18.0
17.8
CL
B
28
A
5.15
54X
2X 27 TIPS
0.3
SEATING
PLANE
0.10 A
A B C
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
NOT EXCEED 0.25 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD SHALL NOT LESS THAN
0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES
OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTER–LEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
A
R0.08 MIN
C
C
0 ° MIN
0.25
GAUGE PLANE
(1.43)
A
8°
0°
6.6
5.9
0.9
0.5
SECTION B–B
0.1
0.0
0.30 A B C
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
(0.29)
4.8
4.3
0.30 A B C
0.30
0.25
BASE METAL
(0.25)
0.38
0.22
6
0.13
M
PLATING
A B C
8
SECTION A–A
ROTATED 90_ CLOCKWISE
VIEW C–C
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
41
Freescale Semiconductor,
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33394
Freescale Semiconductor, Inc...
NOTES
42
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor,
Inc.
33394
Freescale Semiconductor, Inc...
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT
DATA
43
Freescale Semiconductor, Inc...
Freescale Semiconductor,
Inc.
33394
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
◊
MC33394/D