Order this document from Analog Marketing Rev. P_2.4, 07/2002 The PC33394 is a multi–output power supply integrated circuit with high speed CAN transceiver. The IC incorporates a switching pre–regulator operating over a wide input voltage range from +4.0V to +26.5V (with transients up to 45V). The switching regulator has an internal 3.0A current limit and runs in both buck mode or boost mode to always supply a pre–regulated output followed by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V @ 120mA; VDDL / 2.6V (User scalable between 3.3V – 1.25V) @ 400mA typically, using an external NPN pass transistor. The Keep Alive regulator VKAM (scalable to track VDDL) @ 50mA; FLASH memory programming voltage VPP / 5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V (tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to supply 125mA clamped to 17V. Additional features include Active Reset circuitry watching VDDH, VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT), Power Sequencing circuitry guarantees the core supply voltages never exceed their limits or polarities during system power up and power down. A high speed CAN transceiver physical layer interfaces between the microcontroller CMOS outputs and differential bus lines. The CAN driver is short circuit protected and tolerant of loss of battery or ground conditions. PC33394 is designed specifically to meet the needs of modules, which use the MPC565 microcontroller, though it will also support others from the MPC5XX family of Motorola microcontrollers. Features: • Wide operating input voltage range: +4.0V to +26.5V (+45V transient). • • • • • • MULTI–OUTPUT POWER SUPPLY SEMICONDUCTOR TECHNICAL DATA 44–Lead HSOP DH SUFFIX CASE 1291 44–Lead QFN FC SUFFIX CASE 1310 (BOTTOM VIEW) Provides all regulated voltages for MPC5XX MCUs and other ECU’s logic and analog functions. Accurate power up/down sequencing. 54–Lead SOICW–EP DWB SUFFIX CASE 1377 Provides necessary MCU support monitoring and fail–safe support. Provides three 5.0 V buffer supplies for internal & external (short–circuit protected) sensors. Includes step–down/step–up switching regulator to provide supply voltages during different battery conditions. Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by means of Serial Peripheral Interface. $)1 1*(+ 1+1+- 6. 1# 1- ! 1- ! * .'& $ . PIN CONNECTIONS QFN 1&(6! 1. ) - "*) 2& 0+ 1- ! 1++6 ) 1++ 16 16! 1'63 1'6 ") .2" **/ .2 .2 .2 1/ 1/ &61/ 1$") 1&( 1/ 1/ &61/ 1$") 1&( .' + 1&(6! #-/ 1. ) )# - "*) )' 2& 0+ ") 1- ! )/3 1++6 ) )-3 1++ +*- . / 16 #- . / 16! +- - . / 1'63 1'6! 1'6 1'6! +- - . / #- . / +*- . / )-3 )/3 HSOP .2 .2 .2 **/ .2" ") $)1 1*(+ 1+1+- 6. 1# 1- ! 1- ! * .'& $ . .' + #-/ )# )' ") PIN CONNECTIONS ") )' )# #-/ .' + ) . $ .'& * ) 1- ! 1- ! 1# 1+- 6. 1+1*(+ $)1 ") .2" **/ ) .2 .2 .2 .2 .2 SOICW )/3 )-3 +*- . / #- . / +- - . / ) 1'6! 1'6 1'63 16! 16 1++ 1++6 ) 1- ! 2& 0+ - "*) 1. ) 1&(6! 1&( 1$") ) &61/ 1/ 1/ 1/ 1/ 1/ This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola, Inc. 2002 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 1 PC33394 /E, Figure 1. PC33394DH – Simplified Block Diagram and Typical Application '< # F 1/ < ! < ! F .2 A EDJHEB EEIJ D! 1&( 1 D! A 1&(6! ! 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D! ! +*-/?C;H ! #?=> .F;;:) /H7DI9;?L;H 1 #-/ * .'& $ . .' + 1# 1 A D! )' )# )/3 ") $D J>?I 9ED<?=KH7J?ED J>; :;L?9; 97D EF;H7J; M?J> 7 C?D?CKC ?DFKJ LEBJ7=; 1/ E< 1 LEBJ7=; 7J + 1/ F?DI 1' 7D: 1&( 7H; 7:@KIJ78B; JE IKFFEHJ 9KHH;DJ C?9HEFHE9;IIEH J;9>DEBE=O 1 1 1 8O C;7DI E< 7D ;NJ;HD7B H;I?IJEH :?L?:;H 2>;D J>; + ) JH7DI9;?L;H ?I DEJ KI;: )' 7D: )# F?DI 97D 8; I>EHJ;: JE=;J>;H F H;L;HI; 87JJ;HO FHEJ;9J?ED :?E:; F BE7: :KCF FHEJ;9J?ED :?E:; F F 97D 8; ECC?JJ;: ?D J>EI; 7FFB?97J?EDI M>?9> :E DEJ H;GK?H; IK9> FHEJ;9J?ED MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 PIN FUNCTION DESCRIPTION (44–HSOP Package) PIN NO. NAME DESCRIPTION 1 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 2 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 3 KA_VBAT 4 VIGN Turn–On control through ignition switch (with internal protection diode) 5 VKAM VDDL tracking Keep Alive Memory (Standby) supply 6 VKAM_FB VKAM output feedback 7 VSEN Switched battery output Keep alive supply (with internal protection diode) 8 REGON Regulator “Hold On” input 9 WAKEUP CAN wake up event output 10 VREF1 11 VPP_EN VDDH tracking linear regulator 1 VPP enable 12 VPP 13 VDD3_3 14 VDD3_3FB 15 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only 16 VDDL_B VDDL external pass transistor base drive 17 VDDL_FB 18 /PRERESET 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL output feedback Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) 19 /HRESET 20 /PORESET Open drain / HRESET (Hardware Reset) output 21 CANRXD CAN receive data (DOUT) 22 CANTXD CAN transmit data (DIN) 23 GND Ground 24 CANL CAN differential bus drive low line 25 CANH CAN differential bus drive high line Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. 26 HRT 27 /SLEEP Hardware Reset Timer pin (programmed with external capacitor and resistor) 28 CS SPI chip select 29 DI SPI serial data in 30 SCLK Sleep Mode & Power Down control SPI clock input 31 DO 32 VREF3 SPI serial data out VDDH tracking linear regulator 3 33 VREF2 VDDH tracking linear regulator 2 34 VDDH 5.0 V regulated supply output 35 VPRE_S 36 VPRE 37 VCOMP Switching pre–regulator output sense Switching pre–regulator output Switching pre–regulator compensation (error amplifier output) 38 INV Switching pre–regulator error amplifier inverting input 39 GND Ground 40 SW2G External power switch (MOSFET) gate drive — Boost regulator 41 BOOT Bootstrap capacitor 42 SW1 Source of the internal power switch (n–channel MOSFET) 43 SW1 Source of the internal power switch (n–channel MOSFET) 44 SW1 Source of the internal power switch (n–channel MOSFET) MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 3 PC33394 PIN FUNCTION DESCRIPTION (44–QFN Package) PIN NO. 4 NAME DESCRIPTION 1 GND 2 SW2G Ground External power switch (MOSFET) gate drive — Boost Reg. 3 BOOT Bootstrap capacitor 4 SW1 Source of the internal power switch (n–channel MOSFET) 5 SW1 Source of the internal power switch (n–channel MOSFET) 6 SW1 Source of the internal power switch (n–channel MOSFET) 7 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 8 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 9 KA_VBAT Keep alive battery supply (with internal protection diode) 10 VIGN Turn on control through ignition switch (with internal protection diode) 11 VKAM VDDL tracking Keep Alive Memory (Standby) supply 12 VKAM_FB VKAM output feedback 13 VSEN Switched battery output 14 REGON Regulator “Hold On” input 15 WAKEUP CAN wake up event output 16 VREF1 17 VPP_EN 18 VPP 19 VDD3_3 20 VDD3_3FB 21 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only 22 VDDL_B VDDL external pass transistor base drive 23 VDDL_FB 24 /PRERESET 25 /HRESET 26 /PORESET 27 CANRXD CAN receive data (DOUT) 28 CANTXD CAN transmit data (DIN) VDDH tracking linear regulator 1 VPP enable 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL output feedback Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) Open drain / HRESET (Hardware Reset) output Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. 29 GND Ground 30 CANL CAN differential bus drive low line 31 CANH CAN differential bus drive high line 32 HRT 33 /SLEEP 34 CS SPI chip select 35 DI SPI serial data in 36 SCLK 37 DO 38 VREF3 VDDH tracking linear regulator 3 39 VREF2 VDDH tracking linear regulator 2 40 VDDH 5.0 V regulated supply output 41 VPRE_S 42 VPRE 43 VCOMP 44 INV Hardware Reset Timer pin (programmed with external capacitor and resistor) Sleep Mode & Power Down control SPI clock input SPI serial data out Switching pre–regulator output sense Switching pre–regulator output Switching pre–regulator compensation (error amplifier output) Switching pre–regulator error amplifier inverting input MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 PIN FUNCTION DESCRIPTION (54–SOICW–EP Package) PIN NO. NAME 1 GND Ground DESCRIPTION 2 CANL CAN differential bus drive low line 3 CANH CAN differential bus drive high line 4 HRT 5 /SLEEP 6 N/C No Connect 7 CS SPI chip select 8 DI SPI serial data in 9 SCLK 10 DO SPI serial data out 11 N/C No Connect 12 VREF3 VDDH tracking linear regulator 3 13 VREF2 VDDH tracking linear regulator 2 14 VDDH 5.0 V regulated supply output 15 VPRE_S 16 VPRE 17 VCOMP 18 INV Switching pre–regulator error amplifier inverting input 19 GND Ground 20 SW2G External power switch (MOSFET) gate drive — Boost regulator 21 BOOT Bootstrap capacitor 23 SW1 Source of the internal power switch (n–channel MOSFET) 24 SW1 Source of the internal power switch (n–channel MOSFET) 25 SW1 Source of the internal power switch (n–channel MOSFET) 26 SW1 Source of the internal power switch (n–channel MOSFET) 27 SW1 Source of the internal power switch (n–channel MOSFET) 28 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 29 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 30 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 31 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 32 VBAT Battery supply to IC (external reverse battery protection needed in some applications) 33 KA_VBAT 34 N/C Hardware Reset Timer pin (programmed with external capacitor and resistor) Sleep Mode & Power Down control SPI clock input Switching pre–regulator output sense Switching pre–regulator output Switching pre–regulator compensation (error amplifier output) Keep alive supply (with internal protection diode) No Connect 35 VIGN Turn–On control through ignition switch (with internal protection diode) 36 VKAM VDDL tracking Keep Alive Memory (Standby) supply 37 VKAM_FB VKAM output feedback 38 VSEN Switched battery output 39 REGON Regulator “Hold On” input 40 WAKEUP CAN wake up event output 41 VREF1 42 VPP_EN VDDH tracking linear regulator 1 43 VPP 44 VDD3_3 45 VDD3_3FB 46 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only 47 VDDL_B VDDL external pass transistor base drive 48 VDDL_FB 49 N/C 50 /PRERESET 51 /HRESET 52 /PORESET 53 CANRXD CAN receive data (DOUT) 54 CANTXD CAN transmit data (DIN) VPP enable 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL output feedback No Connect Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) Open drain / HRESET (Hardware Reset) output Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 5 PC33394 1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur. Voltage parameters are absolute voltages referenced to ground.) Value Parameter Unit Min. Max. Supply Voltage (VBAT), Load Dump –0.3 +45 V Supply Voltage (KA_VBAT, VIGN), Load Dump –18 +45 V Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM) –0.3 +5.8 V Supply Voltages (VREF1, VREF2, VREF3, VSEN) –2.0 +18 V CANL, CANH 0<VBAT<18 VDC no time limit –18 +26.5 V –2.0 –200 +2.0 +200 kV V ESD Voltage Human Body Model all pins Machine Model all pins (Note 1) (Note 2) CANLesd, CANHesd (Note 1) –4.0 +4.0 kV CANLesd, CANHesd (Note 2) –200 +200 V CANLtransient, CANHtransient (Note 3) –200 +200 V /SLEEP –18 +45 V REGON, VPP_EN, /HRESET, /PORESET, /PRERESET, HRT, DO, DI, CS, SCLK –0.3 +7.0 V CANTXD, CANRXD –0.3 +7.0 V Operational Package Temperature [Ambient Temperature] –40 +125 °C Storage Temperature –65 +150 °C 8.3 5.0 W W Power Dissipation (TA = 125C) 44 HSOP 44 QFN (Note 4) (Note 4) Lead Soldering Temperature (Note 5) Maximum Junction Temperature 260 C +150 °C RθJA, Thermal Resistance, Junction to Ambient (44 HSOP) (Note 6) 41 °C/W RθJC, Thermal Resistance, Junction to Case (44 HSOP) (Note 7) 0.2 °C/W RθJB, Thermal Resistance, Junction to Base (44 HSOP) (Note 8) 3 °C/W RθJA, Thermal Resistance, Junction to Ambient (44 QFN) (Note 6) 77 °C/W RθJC, Thermal Resistance, Junction to Case (44 QFN) (Note 7) 1.7 °C/W RθJB, Thermal Resistance, Junction to Base (44 QFN) (Note 8) 5.0 °C/W RθJC, Thermal Resistance, Junction to Case (54 SOICW–EP) (Note 7) 1.2 °C/W RθJB, Thermal Resistance, Junction to Base (54 SOICW–EP) (Note 8) 8,1 °C/W 1. Human body model: C = 100 pF, R = 1.5 kΩ. 2. Machine model: C = 200 pF, R = 10 Ω and L = 0.75 µH. In case of a discharge from pin CANL to pin GND: – 100 V < CANL transient < +100 V; in case of a discharge from pin CANH to Vcc: –150 V < CANH transient < +150 V. 3. The waveforms of the applied transients is in accordance with ”ISO 7637 part 1” test pulses 1, 2, 3a and 3b. 4. Maximum power dissipation at indicated junction temperature. 5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering time/temperature limits. 6. Thermal resistance measured in accordance with EIA/JESD51–2. 7. Theoretical thermal resistance from the die junction to the exposed pad. 8. Thermal resistance measured in accordance with JESD51–8. 2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted) Parameter Supply Voltages (VBAT, KA_VBAT) Switching Regulator Output Current (IVPRE) (Note 1) Value Unit 4.0 to 26.5 V 0 to 1.2 A VDDH Output Current 0 to 400 mA VDD3_3 Output Current 0 to 120 mA VDDL_B Pass Transistor Base Drive Current 0 to 40 mA VPP Output Current 0 to 150 mA VREF Output Current 0 to 100 mA VSEN Output Current 0 to 125 mA VKAM Standby Output Current (normal mode of operation) 0 to 60 mA VKAM Standby Output Current (standby mode of operation) 0 to 12 mA 1. See Typical Application Diagram in Figure 1. 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: GENERAL Start Up Voltage VBATstart 6.0 Power Dissipation, VBAT = 13.3 V (Buck Mode) Undervoltage Shut Down Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V; IVKAM = 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V 1.8 VBATUV 3.4 IVBAT(sleep) 750 Battery Input Current, Keep Alive Mode VIGN = 0; IVKAM = –10 mA Power On Current, Regulator ON with no load on VDDH, VDD3_3, VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V Battery Input Current, VPRE = –1.0 A, VBAT = 4.5 V Battery Input Current, VPRE = –1.0 A, VBAT = 9 V Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V Battery Input Current, VPRE = –1.0 A, VBAT = 18 V IVBAT(no load) IVBAT(4.5) 2.2 V W 3.8 V 1000 µA 12 mA 27 mA 3.0 A IVBAT(9) 1.5 A IVBAT(13.3) 1.2 A IVBAT(18) 1.1 A MODE CONTROL VIGN Input Voltage Threshold, REGON = 0 V VBAT = 13.3 V; Battery Voltage = 14 V VIH VIL VIGN Hysteresis 2.8 1.7 3.15 2.0 3.4 2.3 V 0.7 1.0 1.5 V VIGN Pull–Down Current, REGON = 0V VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V RPD 40 100 150 µA REGON Input High Voltage Threshold VIH 1.3 1.65 2.1 V REGON Input Low Voltage Threshold VIL 0.8 1.35 1.5 V REGON Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V REGON Pull–Down Current, REGON = VDDH to VIL(min) RPD 10 20 50 µA /SLEEP Input High Voltage Threshold VIH 1.7 2.2 2.6 V /SLEEP Input Low Voltage Threshold VIL 1.4 1.9 2.2 V /SLEEP Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V /SLEEP Pull–Down Current, /SLEEP = VDDH to VIL(min) RPD 10 20 50 µA VPP_EN Input High Voltage Threshold VIH 1.3 1.65 2.1 V VPP_EN Input Voltage Low Threshold VIL 0.8 1.35 1.5 V VPP_EN Pull–Down Current, VPP_EN = VDDH to VIL(min) RPD 10 20 50 µA MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 7 PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit VPRE 5.4 5.6 5.8 V DC CHARACTERISTICS: BUCK CONVERTER Buck Converter Output Voltage, VBAT = 7.5V to 18V; ILOAD=500mA Buck to Boost Mode Threshold Voltage (Note 1) VBATthd 6.7 V Boost to Buck Mode Threshold Voltage (Note 1) VBATthu 7.2 V (Note 1) N–channel power MOSFET SW1 SW1 Drain–Source Breakdown Voltage BVDSS 50 V SW1 Continuous Drain Current IDSW1 –2.75 A SW1 Drain–Source Current Limit IscSW1 –2.5 SW1 Drain–Source On–Resistance; ID = 1.0 A, VBAT = 9.0 V RDS(on) –3.0 –3.5 A 300 mΩ Error Amplifier (Design Information Only) Input Offset Voltage (Note 1) VOS 20 mV DC Open Loop Gain (Note 1) AVOL 80 dB Unity Gain Bandwidth (Note 1) BW 1.5 MHz Output Voltage Swing — High Level (Note 1) VOH 4.2 V Output Voltage Swing — Low Level (Note 1) VOL 0.4 V Output Source Current (Note 1) IOUT 1.0 mA Output Sink Current (Note 1) IOUT 200 µA Ramp Generator Sawtooth Peak Voltage (Note 1) VOSC 3.5 V Sawtooth Peak–to–Peak Voltage (Note 1) VOSCp–p 3.0 V Boost Converter Output Voltage, VBAT = 4.5 V to 6.0 V (Note 1) VPRE 6.6 V SW2G Output Voltage, Power MOSFET On (Note 1) Vg SW2G Source Continuous Current (Note 1) Isource BOOST CONVERTER External Power MOSFET Gate Drive SW2G SW2G Sink Continuous Current 5.9 6.0 VPRE V TBD Isink 200 Freq 180 mA 300 400 mA 200 220 kHz AC CHARACTERISTICS: BUCK CONVERTER Oscillator Frequency SW1 Switch Turn–ON Time (Note 1) tT–ON TBD ns SW1 Switch Turn–OFF Time (Note 1) tT–OFF TBD ns SW2G Switch Turn–ON Time, Cgate = pF (Note 1) tT–ON TBD ns SW2G Switch Turn–OFF Time, Cgate = pF (Note 1) tT–OFF TBD ns OFF Time (Note 1) tOFF 1.25 µs Duty cycle (Note 1) d 75 % NOTES: 1. Guaranteed by design but not production tested. 8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit 5.0 5.1 V 40 mV 20 mV 450 mV DC CHARACTERISTICS: VDDH VDDH Output Voltage, IVDDH = –400 mA; VDDH 4.9 VDDH Load Regulation, VBAT = 13.3 V; IVDDH = 0 to –400 mA; LoadRgVDDH –40 VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; IVDDH = –400 mA; LineRgVDDH –20 VDDH Drop Out Voltage, VPRE – VDDH, IVDDH = –400 mA; Decrease VBAT until Resets asserted VDOV VDDH Output Current, VBAT = 4.0 V to 26.5 V IVDDH VDDH Short Circuit Current, VDDH = 0 V VDDH Maximum Allowed Feedback Current (Power Up Sequence Guaranteed) ISC –400 –750 (Note 1) (Note 2) VDDH Reset Voltage, Range of VDDH where Resets must remain asserted mA –440 mA 135 µA VVDDH_HRST 0.5 4.8 V Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C VDD3_3 3.21 3.36 V VDD3_3 Load Regulation, VBAT = 13.3 V; IVDD3_3 = 0 to –120 mA LoadRgVDD3 –40 40 mV VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; IVDD3_3 = –120mA LineRgVDD3 –20 20 mV 2.04 V VDD3_3 VDD3_3 Output Voltage, IVDD3_3 = –120 mA; VDD3_3 Drop Out Voltage, VPRE – VDD3_3 IVDD3_3 = –120 mA; Decrease VBAT until Resets asserted VDOV VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V IVDD3_3 VDD3_3 Short Circuit Current, VDD3_3 = 0 V VDD3_3 Maximum Allowed Feedback Current (Power Up Sequence Guaranteed) 3.3 ISC –120 –320 (Note 1) (Note 2) VDD3_3 Reset Voltage Range of VDD3_3 where Resets must remain asserted mA –130 mA 135 µA VVDD3_HRST 0.5 3.1 V Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C VDDLREF 1.225 1.275 V VDDL Load Regulation, VBAT = 13.3 V; IVDDL_B = 0 to –40 mA LoadRgVDDL –1.6 0 % VDDL Line Regulation VBAT = 4.0 V to 26.5 V; IVDDL_B = –40 mA LineRgVDDL –0.8 0.8 % 1.3 V VDDL –5% V 0.187 V VDDL VDDL Feedback Reference Voltage, pin VDDL_FB IVDDL_B = 0 to –40 mA VDDL Drop Out Voltage, VPRE – VDDL IVDDL = –400 mA; VBAT decreases until Resets asserted 1.25 VDOV VDDL Reset Voltage, Range of VDDL where Resets must remain asserted (Note 1) VVDDL_HRST VDDL Susceptibility to Feeding Back (Power Up Sequence Guaranteed) (Note 3) VDDLREF VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V VDDL_B Drive Short Circuit Current VDDL_B = 0V, VBAT = 7.5V to 26.5V VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V 0.5 IVDDL_B IscVDDL_B –40 –100 IVDDL_B mA –45 –40 mA mA VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6V IscVDDL_X –100 –45 mA VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V IVDDL_FB 0 2.0 µA NOTES: 1. Guaranteed by design but not production tested. 2. Maximum allowed current flowing back into the regulator output. 3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 9 PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit VKAMREF 1.242 1.267 1.292 V VKAM Load Regulation, VBAT = 13.3 V; IVKAM = –0 to –50 mA LoadRgVKAM –1.6 0 % VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; IVKAM = –50 mA LineRgVKAM –0.8 0.8 % VTVKAM –1.6 0.8 % VKAM 0.675 VVKAM_HRST 0.5 DC CHARACTERISTICS: VKAM VKAM Feedback Reference Voltage, pin VKAM_FB Normal Mode (switcher running), IVKAM = 0 to –50mA VKAM Tracking to VDDL Voltage, VDDL – VKAM VBAT = 4.0 V to 26.5 V; IVKAM = 0 to –50 mA, IVDDL = 0 to –400mA VKAM Feedback Voltage — Power Down Mode 3.0 V ≤ Battery Voltage ≤ 26.5 V, IVKAM = –12 mA VKAM Reset Voltage (/PORESET) Range of VKAM where Resets must remain asserted VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V VKAM Output Current (Sleep Mode and when VBAT ≤ 4.0 V) VKAM Short Circuit Current, VKAM = 0 V VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V V VKAM –5% V IVKAM –50 mA IVKAM(sleep) –12 mA ISC –140 –50 mA IVKAM_FB 0 2.0 µA 22 100 µF VKAM Output Capacitance Required, Capacitor Initial Tolerance 10% VPP VPP 5.0V Output Voltage (Default), IVPP = –150 mA VPP5 4.86 5.0 5.12 V VPP 3.3 V Output Voltage (Programmed by SPI) IVPP = –150 mA VPP3 3.22 3.3 3.38 V VPP Load Regulation, VBAT = 13.3 V; IVPP = 0 to –150 mA LoadRgVPP –0.8 0.8 % VPP Line Regulation, VBAT = 4.0 V to 26.5 V; IVPP = –150 mA LineRgVPP –0.4 0.4 % VPP Tracking to VDDH Voltage, VDDH – VPP, VBAT = 4.0 V to 26.5 V; IVPP = 0 to –150 mA; IVDDH = 0 to –400 mA VTVPP –0.8 0.8 % VPP Drop Out Voltage, VPRE — VPP (VPP set to default 5.0V) IVPP = –150 mA; Decrease VBAT until VPP is out of specification (less than 4.86 V) VDOV 0.4 V VPP Output Current, VBAT = 4.0 V to 26.5 V IVPP VPP Short Circuit Current, VPP = 0 V –150 mA ISC –360 –165 mA Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C NOTES: 1. Guaranteed by design but not production tested. 10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. 5.0 Unit DC CHARACTERISTICS: VREF1, 2, 3 VREF Output Voltage, IVREF = –100 mA VREF 4.86 5.12 V VREF Load Regulation, VBAT = 13.3 V; IVREF = 0 to –100 mA LoadRgVREF –40 40 mV VREF Line Regulation, VBAT = 4.0 V to 26.5 V; IVREF = –100 mA LineRgVREF –20 20 mV VTVREF –40 20 mV 0.4 V VREF Tracking to VDDH Voltage, VDDH – VREF, VBAT = 4.0 V to 26.5 V, IVREF = 0 to –100 mA; IVDDH = 0 to –400 mA VREF Drop Out Voltage, VPRE–VREF IVREF = –100 mA; Decrease VBAT until VREF is out of specification (less than 4.86 V) VDOV VREF Output Current, VBAT = 4.0 V to 26.5 V IVREF VREF Short Circuit Current, VREF = –2.0 V ISC –100 –260 VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V IstbVREF VREF Leakage Current, VREF disabled, VREF = –2.0 V ILKVREF –2.0 mA –110 mA 40 mA mA Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C 0.2 V 21 V VSEN VSEN Saturation Voltage, IVSEN = 0 to –125 mA, VBAT= 8 to 16 V VSENsat VSEN Output Voltage Limit, IVSEN = 0 to –125mA, VBAT= 16 to 26.5V VSENlimit 16 VSEN Short Circuit Current, VSEN = –2.0 V IscVSEN –290 –140 mA VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V IstbVSEN 40 mA VSEN Leakage Current, VSEN disabled, VSEN = –2.0 V ILKVSEN 200 µA 17 Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C NOTES: 1. Guaranteed by design but not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 11 PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit 5.2 V DC CHARACTERISTICS: SUPERVISORY OUTPUTS Reset Voltage Thresholds /HRESET to follow /PRERESET by 0.7 µs VDDH Reset Upper Threshold Voltage (Note 1) VDDH Reset Lower Threshold Voltage (Note 1) VDD3_3 Reset Upper Threshold Voltage (Note 1) VDD3_3 Reset Lower Threshold Voltage (Note 1) VDDL Reset Upper Threshold Voltage (Notes 1, 4) VDDL Reset Lower Threshold Voltage (Notes 1, 4) 4.8 V 3.43 3.17 V V 1.35 1.2 V V /PORESET Voltage Threshold VKAM Reset Upper Threshold Voltage (Notes 2, 5) VKAM Reset Lower Threshold Voltage (Notes 2, 5) 1.35 1.2 V V /PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage (Note 3) 7.0 V /PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current, Vreset< 0.4 V 1.0 mA /PRERESET, /HRESET, /PORESET Low–Level Output Voltage, IOL = 1.0 mA 0.4 V /PRERESET /HRESET /PORESET Leakage Current 10 µA WAKEUP High–Level Output Voltage, IOH = –800µA VDDH–0.8 V WAKEUP Low–Level Output Voltage, IOL = 1.6 mA 0.4 V 2.57 V HRT Sink Current 1.0 mA HRT Leakage Current 5.0 µA HRT Saturation Voltage, HRT Current = 1 mA 0.4 V HRT Voltage Threshold 2.49 2.53 AC CHARACTERISTICS: SUPERVISORY OUTPUTS /PORESET Delay Delay time from VKAM in regulation and stable to the release of /PORESET 7.0 10 15 ms Reset Delay Time Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset (/PORESET, /PRERESET) 10 20 50 µs /HRESET Delay Time Time From /PRERESET low to /HRESET low 0.5 0.7 1.0 µs VDDH, VDDL, VREF Power Up Sequence Max Power Up Sequence Time Dependent on Output Load Characteristics. (Note 3) 800 µs NOTES: 1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET. 2. VKAM regulator output supervised by /PORESET. 3. Guaranteed by design but not production tested. 4. Measured at the VDDL_FB pin. 5. Measured at the VKAM_FB pin. 12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: CAN Transceiver (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL) CAN Transceiver Supply Current (dominant), VCANTXD = 0V IDD(CAN) 30 50 70 mA CAN Transceiver Supply Current (recessive), VCANTXD = VDDH IDD(CAN) 2.5 5 10 mA High–Level Input Voltage Threshold (recessive), Vdiff<0.5V VIH 1.4 2.0 V Low–Level Input Voltage Threshold (dominant), Vdiff>1.0V VIL 0.8 1.4 V High–Level Input Current, VCANTXD = VDDH IIH –5 0 +5 µA Low–Level Input Current, VCANTXD = 0V IIL –10 –15 –30 µA IPU –10 –60 µA 10 pF VDDH V Transmitter Data Input CANTXD CANTXD Pull–up Current, VCANTXD = 0V to VIH(max) CANTXD Input Capacitance (Note 1) CI(TXD) 5 Receiver Data Output CANRXD High–Level Output Voltage VCANTXD = VDDH, ICANRXD = –0.8 mA VOH VDDH –0.8 Low–Level Output Voltage, VCANTXD = 0, ICANRXD = 1.6 mA VOL 0.4 V High–Level Output Current, VCANRXD = 0.7VDDH IOH –800 µA Low–Level Output Current, VCANRXD = 0.4V IOL 1.6 mA BUS Lines CANH, CANL Output Voltage CANH (recessive) VCANTXD = VDDH; RL = open VCANH(r) 2.0 2.5 3.0 V Output Voltage CANL (recessive) VCANTXD = VDDH; RL = open VCANL(r) 2.0 2.5 3.0 V 100 µA Output Current CANH (recessive) VCANTXD = VDDH; VCANH, VCANL = 2.5V IO(CANH)(r) Output Current CANL (recessive) VCANTXD = VDDH; VCANH, VCANL = 2.5V IO(CANL)(r) –100 Output Voltage CANH (dominant), VCANTXD = 0V VCANH(d) 2.75 3.5 4.5 V Output Voltage CANL (dominant), VCANTXD = 0V VCANL(d) 0.5 1.5 2.25 V Differential Output Voltage (dominant) VCANH(d) – VCANL(d) VCANTXD = 0V VOdiff(d) 1.5 2.0 3.0 V Differential Output Voltage (recessive) VCANH(r) – VCANL(r) VCANTXD = VDDH VOdiff(r) 0 0.5 V 7.0 V 1.0 V Differential Input Common Mode Voltage Range µA VCM –2.0 VRXDdiff(th) 0.5 0.75 Differential Receiver Input Voltage Hysteresis VIdiff(hys) 0.10 0.2 0.30 V Short Circuit Output Current CANH VCANH = – 8.0V, VCANTXD = 0V ISC(CANH) –70 –200 mA Short Circuit Output Current CANL VCANL = VBAT = 18V, VCANTXD = 0V ISC(CANL) 70 200 mA Differential Receiver Threshold Voltage (recessive) VCANTXD = VDDH, VCANRXD < 0.4V, – 2.0V < VCM < 7.0V Loss of Ground — see Figure 11. Refer to Figure 10 for loading considerations. Output Leakage Current CANH, VCANH = –18V IOLKG(CANH) –2.0 2.0 mA Output Leakage Current CANHL, VCANL = –18V IOLKG(CANL) –2.0 2.0 mA Loss of Battery — see Figure 12. Refer to Figure 10 for loading considerations. Input Leakage Current CANH, VCANH = 6.0V IILKG(CANH) –800 800 µA Input Leakage Current CANHL, VCANL = 6.0V IILKG(CANL) –800 800 µA NOTES: 1. Guaranteed by design but not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 13 PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit 5.0 25 50 kΩ 25 DC CHARACTERISTICS: CAN Transceiver (Continued) (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL) CANH,CANL impedance CANH Common Mode Input Resistance Ri(CM)CANH CANL Common Mode Input Resistance Ri(CM)CANL 5.0 CANH, CANL Common Mode Input Resistance Mismatch 100(RiCANH – Ri(CM)CANL )/[ (RiCANH + Ri(CM)CANL )/2] Ri(CM)MCAN –3.0 RI(dif) 25 Differential Input Resistance CANH Input Capacitance, VCANTXD = VDDH (Note 1) CANL Input Capacitance, VCANTXD = VDDH (Note 1) Differential Input Capacitance, CINCANH – CINCANL, VCANTXD = VDDH 50 kΩ 3.0 % 50 75 kΩ 7.5 20 pF CI(CANL) 7.5 20 pF CI(CANdif) 3.75 10 pF CI(CANH) (Note 1) Thermal Shutdown Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C AC CHARACTERISTICS: CAN Transceiver Timing Characteristics See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load RL = 60 Ω differential. Delay CANTXD to Bus Active, CL = 3nF tonTXD 50 ns Delay CANTXD to Bus Inactive, CL = 10pF toffTXD 80 ns Delay CANTXD to CANRXD, Bus Active, CL = 3nF tonRXD 120 ns Delay CANTXD to CANRXD, Bus Inactive, CL = 10pF toffRXD 190 ns NOTES: 1. Guaranteed by design but not production tested. 1# 1 )/N 1 )# 1 EC?D7DJ 8?J )# -;9;II?L; 8?J 1:?<< )' -;9;II?L; 8?J 1 )' 1 EC?D7DJ 8?J 1 1:?<< 1 )-N 1# 1# JED/N JED-N 1# 1 1 JE<</N JE<<-N Figure 2. CAN Delay Timing Waveform 14 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the PC33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. DO Output High Voltage, IOH = –100 µA VOH 4.2 DO Output Low Voltage, IOL = 1.6 mA VOL DO Tri–state Leakage Current, CS = 0 IDOLkg –10 VIH 2.7 3.1 Max. Unit DC CHARACTERISTICS: SPI CS, SCLK, DI Input High Voltage CS, SCLK, DI Input Low Voltage CS, SCLK, DI Input Voltage Threshold Hysteresis CS, SCLK, DI Pull–Down Current, CS, SCLK, DI = VDDH to VIL(min) V 0.4 V 10 µA 3.5 V VIL 1.7 2.1 2.5 V VIhys 0.8 1.0 1.2 V ISPI_PD 10 20 50 µA AC CHARACTERISTICS: SPI NOTES: MPC565 QSMCM/ SPI set for CPHA = 0 & CPOL = 0. *Assumes MPC565 SCLK rise and fall times of 30 ns, DO load = 200pF – Transfer Frequency fop dc 5.00 MHz 1 SCLK Period tsck 200 – ns 2 Enable Lead Time tlead 105 – ns 3 Enable Lag Time tlag 50 – ns 4 SCLK High Time* tsckhs 70 – ns 5 SCLK Low Time* tsckls 70 – ns 6 SDI Input Setup Time tsus 16 – ns 7 SDI Input Hold Time ths 20 – ns 8 SDO Access Time ta – 75 ns 9 SDO Disable Time tdis – 100 ns 10 SDO Output Valid Time tvs – 75 ns tho 0 – ns tro – 30 ns 11 SDO Output Hold Time 12 Rise Time (Design Information) 13 Fall Time (Design Information) (Note 1) tfo – 30 ns 14 CS Negated Time (Note 1) tcsn 500 – ns (Note 1) NOTES: 1. Guaranteed by design but not production tested. 3 14 7D: E< 1:: JOF . 2 4 1 .'& 5 8 10 * '. *0/ 6 $ / (. *0/ *)/ - 12 13 7 '. $) 9 11 / (. $) Figure 3. SPI Timing Diagram MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 15 PC33394 4. FUNCTIONAL DESCRIPTION The PC33394 is an integrated buck regulator/linear supply specifically designed to supply power to the Motorola MPC55x/MPC56x microprocessors. A detailed functional description of the Buck Regulator, Linear Regulators, Power Up/Down Sequences, Thermal Shutdown Protection, Can Transceiver Reset Functions and Reverse Battery Function are given below. Block diagram of the PC33394 is given in Figure 1. The PC33394 is packaged in a 44 pin HSOP, 54 pin SOICW and the 44 pin QFN. 4.1. Input Power Source (VBAT, KA_VBAT & VIGN) The VBAT and KA_VBAT pins are the input power source for the PC33394. The VBAT pins must be externally protected from vehicle level transients greater than +45 V and reverse battery. See typical application diagram in Figure 1. The VBAT pins directly supply the pre–regulator switching power supply. All power to the linear regulators (except VKAM in the power down mode) is supplied from VBAT through the switching regulator. VKAM power is supplied through VBAT input pins and switching regulator when the PC33394 is awake. When the microprocessor is in a power down mode (no VDDH or VDDL supply), the current requirement on VKAM falls to less than 12 mA. During this period the VKAM current is supplied from the reverse battery protected KA_VBAT input. The KA_VBAT supply pin is the power source to the Keep Alive Memory regulator (VKAM) in power down mode. Power is continuously supplied regardless of the state of the ignition switch (VIGN input). The KA_VBAT input is reverse battery protected but requires external load dump protection (refer to Figure 1). The VIGN pin is used as a control input to the PC33394. The regulation circuits will function and draw current from VBAT when VIGN is high (active) or REGON is high (active) or on CAN bus activity (WAKEUP active). To keep the VIGN input from floating, the PC33394 has an internal current sink of 100 µA, 3.0 V threshold and 1.0 volt of hysteresis. VIGN is designed to operate up to +26.5 volt battery while providing reverse battery and +45 volt load dump protection. The input requires ESD, and transient protection. See Figure 1 for external component required. 4.2. Switching Regulator Functional Description A block diagram of the internal switching regulator is shown in Figure 4. The switching regulator incorporates circuitry to implement a Buck or a Buck/Boost regulator with additional external components. A high voltage, low RDS(on) power MOSFET is included on chip to minimize the external components required to implement a Buck regulator. The power MOSFET is a sense FET to implement current limit. For low voltage operation, a low side driver is provided that is capable of driving external logic level MOSFETs. This allows a switching regulator utilizing Buck/Boost topology to be implemented. Two independent control schemes are utilized in the switching regulator. In Buck mode, voltage mode pulse–width modulation (PWM) control is used. The switcher output voltage divided by an internal resistor divider is sensed by an Error Amplifier and compared with the bandgap reference voltage. The PWM Comparator uses the output signal from the Error Amplifier as the threshold level. The PWM Comparator compares the sawtooth voltage from the Ramp Generator with the output signal from the Error Amplifier thus creating a PWM signal to the control logic block. The Error Amplifier inverting input and 16 output are brought out to enable the control loop to be externally compensated. The compensation technique is described in paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section. In order to improve line rejection, feed forward is implemented in the ramp generator. The feed forward modifies the ramp slope in proportion to the VBAT voltage in a manner to keep the loop gain constant, thus simplifying loop compensation. At startup, a soft start circuit lowers the current limit value to prevent potentially destructive in–rush current. In Boost mode, pulse–frequency modulation (PFM) control is utilized. The duty cycle is set to 75% and the switching action is stopped either by the Boost Comparator, sensing the switcher output voltage VPRE, or by the Current Limit circuit when the switching current reaches its predetermined limit value. This control method requires no external components. The selection of the control method is determined by the control logic based on the VBAT input voltage. 4.2.1. Switching Transistor (SW1) The internal switching transistor is an n–channel power MOSFET. The RDS(on) of this internal power FET is approximately 0.25 ohm at +125C. The PC33394 has a nominal instantaneous current limit of 3.0 A (well below the saturation current of the MOSFET and external surface mounted inductor) in order to supply 1.2 A of current for the linear regulators that are connected to the VPRE pin (see Figure 1). The input to the drain of the internal N—channel MOSFET must be protected by an external series blocking diode, for reverse battery protection (see Figure 1). 4.2.2. Bootstrap Pin (BOOT) An external bootstrap 0.1 µF capacitor connected between SW1 and the BOOT pin is used to generate a high voltage supply for the high side driver circuit of the buck controller. The capacitor is pre charged to approximately 10V while the internal FET is off. On switching, the SW1 pin is pulled up to VBAT, causing the BOOT pin to rise to approximately VBAT+10V — the highest voltage stress on the PC33394. 4.2.3. External MOSFET Gate Drive (SW2G) This is an output for driving an external FET for boost mode operation. Due to the fact that the gate drive supply voltage is VPRE the external power MOSFET should be a logic level device. It also has to have a low RDS(on) for acceptable efficiency. During buck mode, this gate output is held low. 4.2.4. Compensation (INV, VCOMP) The PWM error amplifier inverting input and output are brought out to allow the loop to be compensated. The recommended compensation network is shown in Figure 18 and its Bode plot is in Figure 19. The use of external compensation components allows optimization of the buck converter control loop for the maximum bandwidth. Refer to the paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section for further details of the buck controller compensation. 4.2.5. Switching Regulator Output Voltage (VPRE) The output of the switching regulator is brought into the chip at the VPRE pin. This voltage is required for both the switching regulator control and as the supply voltage for all the linear regulators. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 resistor divider and compared with the bandgap reference voltage (see Figure 4). Refer to Section 5 Application Information for detailed description of the switching regulator operation. 4.2.6. Switching Regulator Output Voltage Sense (VPRE_S) This is the switching regulator output voltage sense input. The switcher output voltage VPRE is divided by an internal **/ .2 1/ 1+.*!/ ./-/ **/./-+ 0-- )/ '$($/ #. -$1 1+- .2$/# (* )' 18= 0& **./ *)/-*' '*"$ /# -(' '$($/ '. -$1 - +2( *(+ ! !*-2- -(+ " ) -/*- 1+.2" 1+- 6. A $)1 18= 1 A 1*(+ 18= .2$/# *.$''/* A#P 18= 1+*(+ 18= 1 **./ *(+ 18= 1 Figure 4. Switching Regulator Block Diagram 4.3. Voltage Regulator (VDDH) The VDDH output is a linearly regulated +5.0 +/– 0.10V voltage supply capable of sourcing a maximum of 400 mA steady state current from VPRE (+5.6 V) for VBAT voltages from +4.0 V to +26.5 V (+45V transient). This regulator incorporates current limit short circuit protection and thermal shut down protection. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response, when choosing external components. See Table 1 for recommended output capacitor parameters. 4.4. Tracking Voltage Regulator (VPP) This linearly regulated +5.0 V/+3.3 V (SPI selectable) voltage supply is capable of sourcing 150 mA of steady state current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (up to +45V transient). It tracks the VDDH or VDD3_3 output, and incorporates current limit short circuit protection and over temperature shut down protection. This output is intended for FLASH memory programming and includes a dedicated enable pin (VPP_EN). The regulator enable can also be controlled through the SPI interface but requires both the VPP_EN pin and the SPI bit (EN_VPP bit) to be high to enable. The selection of tracking VDDH or VDD3_3 is MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA controlled by the VPP_V bit in the SPI. Logic “1” selects VDDH (default), logic “0” selects VDD3_3. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. See Table 1 for recommended output capacitor parameters. The VPP tracking regulator should not be used in parallel with the VDDH regulator, because this arrangement can corrupt the proper power sequencing of the IC. 4.5. Tracking Voltage Regulator (VREFn) The outputs of the VREF1, VREF2, VREF3 linear regulators are 100 mA at +5.0 V. They track the VDDH output. The power supplies are designed to supply power to sensors that are located external to the module. These regulators may be enabled or disabled via the SPI, which also provides fault reporting for these regulators. They are protected for short to battery (+18 V) and short to –2.0 V. Precautions must be taken to protect the VREF pins from exposure to transients. See Table 1 for recommended output capacitor parameters. 4.5.1. VREF Over Temperature Latch Off Feature If either the VREF1, VREF2 or VREF3 outputs is shorted to ground for any duration of time, an over temperature shut 17 PC33394 down circuit disables the output source transistor once the local die temperature exceeds +150°C to +190°C. The output transistor remains off until the locally sensed temperature is 5°C to 20°C. below the trip off temperature. The output(s) will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If one of these outputs goes into over—temperature shutdown, it will not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). 4.8. Tracking Keep–Alive/Standby Supply (VKAM) This linearly regulated Keep Alive Memory voltage supply tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is capable of sourcing 50 mA of steady state current from VPRE during normal microprocessor operation and 12 mA through KA_VBAT pin during stand–by/sleep mode. The VKAM regulator output incorporates a current limit short circuit protection. The output requires a specific range of capacitor values to be stable under all load/line conditions. See Table 1 for recommended output capacitor parameters. NOTE : 4.6. Voltage Regulator (VDD3_3) This linearly regulated +3.3 V +/–0.06 V voltage supply is capable of sourcing 120 mA of steady state current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V transient). This regulator incorporates current limit short circuit protection and thermal protection. When no external pass transistor is used the VDD3_3 and the VDD3_3FB pins must be shorted together — see Figure 22. The current capability of the VDD3_3 output can be increased by means of an external pass transistor — see Figure 1. When the external pass transistor is used the VDD3_3 internal short circuit current limit does not provide the short circuit protection. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. See Table 1 for recommended output capacitor parameters. 4.7. Voltage Regulator (VDDL) The output voltage of the VDDL linear regulator is adjustable by means of an external resistor divider. This linearly regulated +/–2% core voltage supply uses an external pass transistor and is capable of sourcing 40 mA base drive current typically (see application circuit, Figure 1) of steady state current. The collector of the external NPN pass transistor is connected to VPRE (+5.6 V) for a VBAT voltage from +7.5 V to +26.5 V (+45V transient). The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. Also, the dynamic load characteristics of the microprocessor, relative to CPU clock frequency changes must be considered. An additional external pass transistor, for VDDL regulation in the Boost mode, can be added between protected battery voltage (see Figure 1) and VDDL, with its base driven by VDDL_X. In that arrangement the PC33394’s core voltage supply operates over the whole input voltage range VBAT = +4.0 V to +26.5 V (up to +45V transient). See Table 1 for recommended output capacitor parameters. The source current for the VKAM supply output depends on the sleep/wake state of the PC33394. 4.9. Switched Battery Output (VSEN) This is a saturated switch output, which tracks the VBAT and is capable of sourcing 125 mA of steady state current from VBAT. This regulator will track the voltage VBAT to less than 200 mV, and its output voltage is clamped at +17 V. The gate voltage of the internal N—channel MOSFET is provided by a charge pump from VBAT. There is an internal gate–to–source voltage clamp. This regulator is short circuit protected and has independent over—temperature protection. If this output is shorted and goes into thermal shutdown, the normal operation of all other voltage outputs is not impacted. This output is controlled by the SPI VSEN bit. NOTE: A short to VBAT on VREF1, VREF2, VREF3 or VSEN will not result in additional current being drawn from the battery under normal (+8 V to +18 V) voltage levels. Under jumpstart condition (VBAT = +26.5 V) and during load dump condition, the device will survive this condition, but additional current may be drawn from the battery. 4.9.1. VSEN Over Temperature Latch Off Feature If the VSEN output is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150°C to +190°C. The output transistor remains off until the locally sensed temperature drops 5°C to 20°C below the trip–off temperature. The output will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If the VSEN output goes into over—temperature shutdown, it does not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). 4.10. Resets To Microprocessor NOTE: The use of an EXTERNAL pass device allows the power dissipation of the PC33394 to be reduced by approximately 50% and thereby allows the use of a thermally efficient package such as an HSOP 44 or QFN 44. The base drive control signal (VDDL_B) is provided by on chip circuitry. The regulated output voltage sense signal is fed back into the on chip differential amplifier through pin VDDL_FB. The collector of this external pass device should be connected to VPRE to minimize power dissipation and adequately supply 400 mA. Proper thermal mounting considerations must be accounted for in the PCB design. 18 /PORESET – Power On Reset, /PRERESET — Pre Reset, /HRESET– Hardware Reset. All the Reset pins are open drain ‘active low’ outputs, capable of sinking 1.0 mA current and able to withstand +7.0 V. See Figure 1 and Figure 20 for recommended pull–up resistor values and their connection. The /PORESET pin is pulled up to the VKAM voltage by a pull up resistor. It is connected to the microprocessor Power On Reset (POR) pin, and is normally high. During initial battery connect the /PORESET is held to ground by the PC33394. After the VKAM supply is in regulation and an internal 10 ms timer has expired, the /PORESET is released. If VKAM goes out of regulation the device will first pull the /PORESET and MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 /PRERESET followed by a 0.7 µs delay then /HRESET. By /HRESET low VDDH, VDD3_3 and VDDL will start a power down sequence. When the fault is removed a standard power up sequence is initiated. The VKAM linear regulator output must be out of regulation for greater than 20 µs before /PORERSET and /PRERESET (with /HRESET 0.7 µs delayed) are pulled low. If a fault occurs on VKAM in the Key–Off Mode (when the VIGN is off) and the fault is then removed the VKAM will regulate but /PORESET will not be released until Key–On (asserting VIGN pin) allows the 10 ms timer to run. The Reset signals (/PRERESET, /HRESET) are not asserted when the PC33394 enters Sleep Mode by asserting the /SLEEP pin. When exiting out of Sleep Mode the PC33394 asserts the Resets (/PRERESET, /HRESET) during the power up sequence. The /PRERESET and /HRESET pins are pulled up to the VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to section 5. Application Information, paragraph 5.3. Selecting Pull–Up Resistors for detailed description of these two connection scenarios. The PC33394 monitors the main supply voltages VDDH, VDD3_3 and VDDL. If any of these voltages falls out of regulation limits the /PRERESET will be pulled down followed by the /HRESET after 0.7 µs delay, and the power down sequence will be initiated. There are several different scenarios how to connect the /PRERESET and /HRESET pins to the microprocessor. Typically the /PRERESET pin will be connected to the IRQ0 pin of the microprocessor, and the /HRESET to the microprocessor /HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL linear regulator outputs must be out of regulation for greater than 20 µs before /PRERESET (with /HRESET 0.7 µs delayed) are pulled low. and can not lag VDDL by more than 0.5 volts. This condition is met by the PC33394 regardless of load impedance. It is critical to note that the PC33394 under normal conditions is designed to supply VKAM prior to the power up sequence on VDDH, VDD3_3 and VDDL. During power up and power down sequencing /PRERESET and /HRESET are held low. Power up and power down sequencing is implemented in six steps. During this process the reference voltage for VDDH, VDD3_3 and VDDL is ramped up in six steps. Minimum power up/down time is dependent on the internal clock and is 800 µs. Maximum power up/down time is also dependent on load impedance. During the power up/down cycle, voltage level requirements for each step of VDDH, VDD3_3 and VDDL must be met before the supply may advance to the next voltage level. Hence VDDH and VDDL will remain within the 3.1/0.5 V window. Figure 6 illustrates a typical power up and down sequence. 4.11. Hardware Reset Timer (HRT) This feature allows for an external control element (e.g. microprocessor) to shut down the PC33394 regulators, even if the VIGN signal (and REGON) is active, by asserting the /SLEEP pin from high to low. In this case the PC33394 initiates the power down sequence, but the Reset signals (/PRERESET, /HRESET) are not asserted. This allows the microprocessor to continue to execute code when it is supplied only from the Keep Alive supply VKAM. When the microprocessor exits sleep state by pulling /SLEEP pin high the Resets (/PRERESET, /HRESET) are asserted during the power up sequence. The /SLEEP pin has an internal pull down, therefore when its functionality is not used this pin can be either pulled up to VKAM, VBAT, pulled down to ground or left open. The /SLEEP pin should not be pulled up to VDDH. The HRT pin is used to set the delay between VDDH, VDD3_3 and VDDL active and stable and the release of the /HRESET and /PRERESET outputs. An external resistor and capacitor is used to program the timer. To minimize quiescent current during power down modes, the RC timer current should be drawn from one of the VDD supplies (see Figure 1). The threshold on the HRT pin has zero temperature coefficient and is set at 2.5 V. 4.12. Power Up/Down Sequencing The PC33394 power up sequence is specifically designed to meet the power up and power down requirements of the MPC565 microprocessor. The MPC565 processor requires that VDDH remain within 3.1 volts of VDDL during power up MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 4.13. Regulator Enable Function (REGON) This feature allows the microcontroller to select the delayed shut down of the PC33394 device. It holds off the activation of the Reset signals, to the microcontroller, after the VIGN signal has transitioned and signals the request to shutdown the VDDH, VDD3_3, VDDL, VSEN and the VREFn supplies. This allows the microcontroller to delay a variable amount of time, after sensing that the VIGN signal has transitioned and signaled the request to shutdown the regulated supplies. This time can be used to store data to EPROM memory, schedule an orderly shutdown of peripherals, etc. The microcontroller can then drive the REGON signal, to the PC33394, to the low logic state, to turn off the regulators (except for the VKAM supply). 4.14. Regulator Shutdown Function (/SLEEP) 19 PC33394 MC33394 MPC56X 1# 1 1# 1 1!'.# 1'1$ 1.4) 1! 16 1 1# 16 1' 1' 1 1$") 1&( 1 1&( +*- . / &+2- 1.-( 1-/ 1 1 CI +- - . / +*- . / $-, 1 #- . / I #-/ '4 I #-/ '4 #-/ '4 I #- . / Figure 5. PC33394 Timing Diagram 1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms. 2 VIGN is applied, PC33394 starts power up sequence. 3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay programmable by an external capacitor and resistor, HRT pin). 4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated. 5 /HRESET is asserted 0.7 s after /PRERESET 6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released (with an HRT delay). 7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET with 0.7 s delay) are asserted – see Note 1. 8 PC33394 initiates power down sequence. 9 Fault on VKAM removed, the PC33394 initiates the start up sequence. 10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT delay). 11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed. 1# 1 16 1 ' .. /#) 1 1 +*2 - 0+ . ,0 ) 1' 1 +*2 - *2) . ,0 ) )*/ 1' 1 <EH (+ Figure 6. PC33394 Power Up/Down Sequence * VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V. 20 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 the SCLK pin be in a logic low state whenever the chip select pin (CS) makes any transition. For this reason, it is recommended though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed (CS in logic low state). When CS is in a logic low state, any signal at the SCLK and DI pin is ignored and the DO is tri—stated (high impedance). 4.15. SPI Interface to Microcontroller (Serial Peripheral Interface) The pins specified for this function are: DI (Data Input), DO (Data Output), CS (Chip Select) and SCLK. Refer to Figure 3 for the PC33394 SPI timing information. The delay, which is needed from CS leading edge active to the first SCLK leading edge transition (0 to 1) is approximately 125 ns. The SCLK rate is a maximum of 5.0 MHz. The SPI function will provide control of such PC33394 features as VREFn regulator turn on/off, VREFn fault reporting and CAN wake up feature activation. Refer to Figure 7 & Figure 8 for the data and status bit assignments for the 16 bit SPI data word exchange. 4.15.3. DI (Data Input) Pin The DI pin is used for serial data input. This information is latched into the input register on the rising edge of SCLK. A logic high state present on DI will program a specific function (see Figure 7 for the data bits assignments for the 16 bit SPI data word exchange.). The change will happen with the falling edge of the CS signal. To program the specific function of the PC33394 a 16 bit serial stream of data is required to be entered into the DI pin starting with LSB. For each rising edge of the SCLK while CS is logic high, a data bit instruction is loaded into the shift register per the data bit DI state. The shift register is full after 16 bits of information have been entered. To preserve data integrity, care should be taken to not transition DI as SCLK transitions from a low to high logic state. 4.15.1. CS (Chip Select) Pin The system MCU selects the PC33394 to be communicated with through the use of the CS pin. Whenever the pin is in a logic high state, data can be transferred from the MCU to the PC33394 and vice versa. Clocked—in data from the MCU is transferred to the PC33394 shift register and latched in on the falling edge of the CS signal. On the rising edge of the CS signal, output status information is transferred from the output status register into the device’s shift register. Whenever the CS pin goes to a logic high state, the DO pin output is enabled allowing information to be transferred from the PC33394 to the MCU. To avoid any spurious data, it is essential that the transition of the CS signal occur only when SCLK is in a logic low state. 4.15.4. DO (Data Output) Pin The serial output (DO) pin is the output from the shift register. The DO pin remains tri—state until the CS pin goes to a logic high state. See Figure 8 for the status bits assignments for the 16–bit SPI data word exchange. The CS positive transition will make LSB status available on DO pin. Each successive positive SCLK will make the next bit status available. The DI/DO shifting of data follows a first—in—first—out protocol with both input and output words transferring the Least Significant Bit (LSB) first. 4.15.2. SCLK (System Clock) Pin The shift clock pin (SCLK) clocks the internal shift registers of the PC33394. The serial input (DI) data is latched into the input shift register on the rising edge of the SCLK. The serial output pin (DO) shifts data information out of the shift register also on the rising edge of the SCLK signal. It is essential that PC33394 SPI Registers: Serial Input Data/Control Default Value 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 Name Bit Definitions: Bit 15 to 8 = 0 Default Value Bit Name 7 6 5 4 3 2 1 0 (LSB) WKUP CAN_EN VPP_V EN_VPP VSEN VREF3 VREF2 VREF1 Bit Definitions: Bit 7 — WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity Bit 6 — CAN_EN: Enables CAN receiver, will draw small current during power off Bit 5 — VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V Bit 4 — EN_VPP: – Used to turn the VPP regulator off and on from the MCU Bit 3 — VSEN: – Used to turn the VSEN regulator off and on from the MCU Bit 2 — VREF3: – Used to turn the VREF3 regulator off and on from the MCU Bit 1 — VREF2: – Used to turn the VREF2 regulator off and on from the MCU Bit 0 — VREF1: – Used to turn the VREF1 regulator off and on from the MCU Figure 7. SPI Input Data/ Control Register MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 21 PC33394 PC33394 SPI Registers: Serial Output Data/Status Default Value 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Default Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (LSB) VSEN–T VREF3–T VREF2–T VREF1–T VSEN–I VREF3–I VREF2–I VREF1–I Name Bit Definitions: Bit 15 to 8 = 0 Name Bit Definitions: Bit 7 — VSEN–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 6 — VREF3–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 5 — VREF2–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 4 — VREF1–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists Bit 2 — VREF3–I: – Will be set (1), if a current limit condition exists Bit 1 — VREF2–I: – Will be set (1), if a current limit condition exists Bit 0 — VREF1–I: – Will be set (1), if a current limit condition exists NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal Figure 8. SPI Output Data/ Status Register 4.16. CAN Transceiver The CAN protocol is defined in terms of ’dominant’ and ’recessive’ bits. When the digital input (CANTXD) is a logic ”0” (negated level, dominant bit), CANH goes to +3.5 V (nominal) and CANL goes to +1.5 V (nominal). The digital output will also be negated. When the digital input is logic ”1” (asserted level, recessive bit), CANH and CANL are set to +2.5 V (nominal). The corresponding digital output is also asserted. 4.16.1. CAN Network Topology There are two 120 Ω (only two), terminations between the CANH and CANL outputs. The majority of the time, the module PCM CANH controller will contain one of the terminations. The other termination should be as close to the other ”end” of the CAN Bus as possible. The termination provides a total of 60 Ω differential resistive impedance for generation of the voltage difference between CANH and CANL. Current flows out of CANH, through the termination, and then through CANL and back to ground. The CAN bus is not defined in terms of the bus capacitance. A filter capacitor of 220 pF to 470 pF may be required. The maximum capacitive load on the CAN bus is then 15 nF (not a lumped capacitance but distributed through the network cabling). Refer to Figure 9. ECCED (E:; >EA; C# Max : 31 Remotes F! Vehicle Term. F! CANL F! F! *FJ?ED7B Figure 9. CAN Load Characteristics 4.16.2. CAN Transceiver Functional Description A block diagram of the CAN transceiver is shown in Figure 10. A summary of the network topology is shown in Figure 9. The transceiver has wake up capability controlled by the state of the SPI bit WKUP. This allows PC33394 to enter a low power mode and be awakened by CAN bus activity. When 22 activity is sensed on the CAN bus pins, the PC33394 will perform a power up sequence and will provide the microprocessor with indication (WAKEUP pin high) that wake up occurred from a CAN message. The PC33394 may be placed back in low quiescent mode by pulling the /SLEEP pin MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 input drives the outputs to a differential (dominant) voltage, where the CANH output is +3.5 V and the CANL output is +1.5 V. A logic ‘1’ input drives the outputs to their idle (recessive) state, where the CANH and CANL outputs are +2.5 V. An internal pull–up to VDDH shall guarantee a logic ”1” input level if this input is left open. On power–up, or in the event of a thermal shutdown, this input must be toggled high and then low to clear the thermal fault latch. The faulted CAN bus output(s) will remain disabled until the thermal fault latch is cleared. The CAN bus data rate is determined by the data rate of CANTXD. from high to low. The Wake–up function can be disabled through SPI by setting the WKUP bit to 0. The CAN transceiver of the PC33394 is designed for communications speeds up to 500 Kbps. The use of a common mode choke may be required in some applications. When the PC33394 CAN transceiver physical interface is not used in the system design, the CAN bus driver pins CANH and CANL should be shorted together. 4.16.3. CANH CANH is an output driver stage that sources current on the CANH output. It’s output follows CANL, but in the opposite polarity. The output is short circuit protected. In the event that battery or ground is lost to the module, the CANH transmitter’s output stage is disabled. 4.16.6. CANRXD This is a CMOS compatible output used to send data from the CAN bus pins, CANH and CANL, to the microprocessor. When the voltage differential between CANH and CANL is under the differential input voltage threshold (recessive state), CANRXD is logic ‘1’. When the voltage differential between CANH and CANL is over the voltage threshold (dominant state), CANRXD is logic ‘0’. In standby mode, input voltage threshold remains the same. There is a minimum of 0.1 V of hysteresis between the high and low (and vice versa) transition points. 4.16.4. CANL CANL is an output driver stage that sinks current on the CANL output. The sink type output is short circuit protected. In the event that battery or ground is lost to the module, the CANL transmitter’s output stage is disabled. 4.16.5. CANTXD CANTXD input comes from the microcontroller and drives that state of the CAN bus pins, CANH and CANL. A logic ‘0’ *L;H/;CF .;DI; #OIJ;H;I?I 1# 1# )6 ) µ )/3 )# ECFB?C;DJ7HO #?=>'EM .?:; H?L;HI M KHH;DJ '?C?J )' 1 A )-3 2& )6 ) )-3 1 A A 1 A Figure 10. CAN Transceiver Block Diagram 4.16.7. CAN Over Temperature Latch Off Feature If the CANH or CANL output is shorted to ground or battery for any duration of time, an over temperature shut down circuit disables the output stage. The output stage remains latched off until the CANTXD input is toggled from a logic ’1’ to a logic ’0’ to clear the over temperature shutdown latch. Thermal shutdown does not impact the remaining functionality of the IC. 4.16.8. CAN Loss of Assembly Ground The definition of a loss of ground condition at the device level is that all pins of the IC (excluding transmitter outputs) will see very low impedance to VBAT. The loss of ground is shown MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA on the module level in Figure 11. The nomenclature is suited to a test environment. In the application, a loss of ground condition results in all I/O pins floating to battery voltage. In this condition, the CAN bus must not source enough current to corrupt the bus. 4.16.9. CAN Loss of Assembly Battery The loss of battery condition at the IC level is that the power input pins of the IC see infinite impedance to the battery supply voltage (depending upon the application) but there is some undefined impedance looking from these pins to ground. In this condition, the CAN bus must not sink enough current to corrupt the bus. Refer to Figure 12. 23 PC33394 7JJ;HO 1 $)# 1/ )# )' POWER OAK 1 1# 16 1 1' ") Figure 11. CAN Loss of Ground Test Circuit 24 )# 1/ $)' 1$") $)# 7JJ;HO $)' 1$") )' POWER OAK 1 1# 16 1 1' ") Figure 12. CAN Loss of Battery Test Circuit MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 5. APPLICATION INFORMATION This section provides information on external components that are required by the PC33394. The IC is designed to operate in an automotive environment. Conducted immunity and radiated emissions requirements have been addressed during the design. However, the IC requires some external protection. Protection is required for all pins connected directly to battery. The module designer should use an MOV or another transient voltage suppressor in all cases, when the load dump transition exceeds + 45 volts with respect to ground. Protection should also include a reverse battery protection diode (or relay) and input filter. This is required to protect the PC33394 from ESD and +/– 300V ignition transients. Typical configurations are shown in Figure 1. Outputs and inputs connected directly to connector pins require module level ESD protection. 5.1. Selecting Components for Linear Regulators The output capacitor of the linear regulator serves two different purposes. It maintains the linear regulator loop stability, and it provides an energy reservoir to supply current during very fast load transients. This is especially true when supplying highly modulated loads like microcontrollers and other high–speed digital circuits. Due to the limited bandwidth of the linear regulators, the output capacitor is selected to limit the ripple voltage caused by these abrupt changes in the load current. During the fast load current transients, the linear regulator output capacitor alone controls the initial output voltage deviation. Hence, the output capacitor’s equivalent series resistance (ESR) is the most critical parameter. The outputs, which do not experience such severe conditions (the VREF e.g.), use the output capacitor mainly for stability purpose, and therefore its capacitance value can be significantly smaller. The typical output capacitor parameters are: C = 1.0 µF; ESR = 2.0 ohms. When a ceramic 1 µF capacitor is used, the ESR can be provided by a discrete serial resistor (see Figure 20). The following example shows how to determine the output capacitance for a heavily loaded output supplying digital circuits. 5.1.1. Selecting the Output Capacitor Example: The output capacitance must be selected to provide sufficiently low ESR. The selected capacitor must have an adequate voltage, temperature and ripple current rating for the particular application. In order to calculate the proper output capacitor parameters, several assumptions will be made. 1) During the very fast load current transients, the linear regulator can not supply the required current fast enough, and therefore for a certain time the entire load current is supplied by the output capacitor. 2) The capacitor’s equivalent series inductance (ESL) is neglected. These assumptions can greatly simplify the calculations, and are MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA reasonable for most of practical applications. Then the ESR of the output capacitor has to satisfy the following condition: ESR Vo Io Where: ∆Vo is the maximum allowed linear regulator voltage drop caused by the load current transient. ∆Io is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. In this example the VDDH output with the 400 mA load step is considered with the maximum voltage drop of 100mV. This gives the output capacitor’s maximum ESR value of: ESR 100 mV 250 m 400 mA This level of ESR requires a relatively large capacitance. In order to maintain the linear regulator stability and to satisfy large load current steps requirements the solid tantalum capacitor 100µF/10V with ESR = 200 mΩ. One device that meets these requirements is the TPSC107K010S020 tantalum capacitor from the AVX Corporation. VESR ESR Io 200 m 400 mA 80 mV In the next step, the voltage drop associated with the capacitance can be calculated: VC Io t 0.4 A 5 s 20 mV 100 F C Where: C is the output capacitance. t is the linear regulator response time. ∆Io is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. Assuming that the capacitor ESL is negligible, the total voltage drop in the voltage regulator output caused by the current fast transient can be calculated as: Vtotal VESR VC 80 mV 20 mV 100 mV A ceramic capacitor with capacitance value 10nF should be placed in parallel to provide filtering for the high frequency transients caused by the switching regulator. Properly sized decoupling ceramic capacitor close to the microprocessor supply pin should be used as well. Table 1 shows the suggested output capacitors for the PC33394 IC linear regulator outputs. Other factors to consider when selecting output capacitors include key off timing for memory retention. Though the VKAM is not a heavily loaded output, the VKAM output capacitor has to have a sufficiently large capacitance value to supply current to the microcontroller for a certain time after battery voltage is disconnected. 25 PC33394 Table 1. Linear Regulator Output Capacitor Examples SMD tantalum Output Ou pu Value/Rating Part n. (AVX Corp.) VDDH 100uF/10V TPSC107K010S0200 VPP 33uF/10V TPSB336K010S0650 VDD3_3 68uF/6.3V TPSC686K006S0200 VDDL 100uF/6.3V TPSC107K006S0150 VREFx 10uF/16V THJB106K016S VKAM* 100uF/6.3V TPSC107K006S0150 5.2. Switching Regulator Operation The PC33394 switching regulator circuit consists of two basic switching converter topologies. One is the typical voltage mode PWM step–down or buck regulator, which provides pre–regulated VPRE voltage (+5.6 V) during normal operating conditions. During cold start–up, when the car battery is weak, the input voltage for the PC33394 can fall below the lower operating limit of the step–down converter. Under such conditions, the step–up or boost converter provides the required value of the VPRE voltage. The following paragraphs describe the basic principles of the two converters operation. Buck Mode One switching cycle of the step–down converter operation has two distinct parts: the power switch on state and the off state. When the power switch is on, one inductor terminal is connected to the input voltage Vin, and the other inductor terminal is the output voltage Vo. During this part of the switching period the rectifier (catch diode) is back biased, and the current ramps up through the inductor to the output: iL(on) (Vin Vo) ton L Where: ton is the on–time of the power switch. Vin is the input voltage. Vo is the output voltage. iL(on) is the inductor current during the on–time. L is the inductance of the inductor L. During the on time, current ramping through the inductor stores energy in the inductor core. During the off time of the power switch, the input voltage source Vin is disconnected from the circuit. The energy stored in the core forces current to continue to flow in the same direction, the rectifier is forward biased and the 26 inductor input voltage is clamped one forward diode drop below ground. The inductor current during the off time is: iL(off) (Vo Vfwd) toff L Where: toff is the off–time of the power switch. iL(off) is the inductor current during the off time. Vfwrd is forward voltage drop across the rectifier. During the steady state operation iL(on) = iL(off) = ∆IL, and Vin/Vo = d Where: d is the duty cycle, and d = ton/T. T is switching period, T = 1/f. f is the frequency of operation. Two relations give the ripple voltage in the output capacitor Co. The first describes ripple voltage caused by current variation upon the output capacitance Co: IL VppCo 8Co f The other is caused by current variations over the output capacitor equivalent series resistance ESR: VppESR IL RESR Practically, the ESR contributes predominantly to the buck converter ripple voltage: VppESR >>VppCo The inductor peak current can be calculated as follows: IpkL Io 1 IL 2 Where: Io is the average output current. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 $, $ 1* * -'* $'* ' $, $'* * 1?D $* $' ' , 1?D $' $' $ -'* 1EKJ +*2 - .2$/# *) 1 1<M: $'* $'* * 1<M: -'* 1EKJ +*2 - .2$/# *!! 1E JED JE<< J / Figure 13. Basic Buck Converter Operation and its Waveforms Boost Mode The operation of the boost converter also consists of two parts, when the power switch is on and off. When the power switch turns on, the input voltage source is placed directly across the inductor, and the current ramps up linearly through the inductor as described by: V ton iL(on) in L iL(off) (Vo Vin) toff L Where: toff is the off–time of the power switch. Vo is the output voltage. During the steady state operation iL(on) = iL(off) = ∆IL, and Where: V Vin d o Vo ton is the on–time of the power switch. Vin is the input voltage. Where: iL(on) is the inductor current during the on–time. d is the duty cycle, and d = ton/T. L is the inductance of the inductor L. T is switching period, T = 1/f. The current ramping across the inductor stores energy within the core material. In order to maintain steady–state operation, the amount of energy stored during each switching cycle, times the frequency of operation must be higher (to cover the losses) than the power demands of the load: f is the frequency of operation. Psto 1 LI 2pk f Pout 2 When the power switch turns off again, the inductor voltage flies back above the input voltage and is clamped by the forward biased rectifier at the output voltage. The current ramps down through the inductor to the output until the new on time begins or, in case of discontinuous mode of operation, until the energy stored in the inductor core drops to zero. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA The ripple voltage of the boost converter can be described as: (Vo Vin) I VppCo o Vo f Co Where: VppCo is the ripple caused by output current. The portion of the output ripple voltage caused by the ESR of the output capacitor is: V VppESR (Io o 1 IL) RESR Vin 2 27 PC33394 Where Io is the average output current. IpkL Io The inductor peak current is given by the following equation: $' $ ' 1?D $' $, , Vo 1 I Vin 2 L $' 1* * -'* $ $* ' $*) 1?D 1EKJ $, $'* -'* * +*2 - .2$/# *) $' 1, $*!! 1$) 1EKJ $'* -'* * 1E JED +*2 - .2$/# *!! JE<< J / Figure 14. Basic Boost Converter Operation and its Waveforms 5.2.1. Switching Regulator Component Selection The selection of the external inductor L2 and capacitor C2 values (see Figure 15) is a compromise between the two modes of operation of the switching regulator, the pre regulated voltage VPRE and the dropout voltage of the linear regulators. Ideal equations describing the peak—peak inductor current ripple, peak—peak output voltage ripple and peak inductor current are shown below. Since the switching regulator will work mostly in the buck mode, the inductor and the switcher input and output capacitor were selected for optimum buck controller performance, but also taking into account the restriction placed by adopting the boost converter as well. $, 1-.ED 1-' $' 1<M: , -.ED -' ' 1?D 1<M: , 1* Vin(typ) = 13.5 V Io = 1.2 VPRE = 5.6 V (+6 V in the boost mode) f = 200 kHz Vfwd1 = Vfwd2 = 0.5 V Maximum allowed output voltage ripple in the buck mode Vpp(max) = 0.2 V/2 = 0.1 V (to allow for process and temperature variations). 5.2.1.1. Selecting the Inductor -'* .- 5.6 V and the linear regulators require a minimum of 0.4 V dropout voltage. This leaves a ±0.2 V window for the peak—to–peak output voltage ripple. Assuming the following conditions: In order to select the proper inductance value, the inductor ripple current ∆IL has to be determined. The usual ratio of ∆IL to output current Io is: ∆IL = 0.3 Io * As described in the previous section, and taking into account the PC33394 switcher topology (see Figure 15), the inductor ripple current can be estimated as: Figure 15. PC33394 Switcher Topology The following example shows a procedure for determining the component values. The VPRE output is set to regulate to 28 IL (Vin Vo Vfwd2) Vo Vfwd2 L Vin f MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 VppESR = ∆IL x RESR = 0.345 x 0.08 = 28 [mV] After substitution, the calculated inductance value is L = 45 µH, which gives 47 µH standard component value. One device that meets both, the low ESR, and the temperature stability requirements is, for example, the TPSV107K020R0085 tantalum capacitor from AVX Corp. The peak–to peak ripple current value is: ∆IL = 0.345 A. The peak inductor current is given by: Boost Converter Power Capability ILpk = 0.5∆IL + Io = 0.5x0.345 + 1.2 = 1.37[A] The boost converter with selected components has to be able to deliver the required power. Due to the nature of this non–compensated PFM control technique, the Boost converter output ripple voltage is higher than if it utilized a typical PWM control method. Therefore the switcher output voltage level is set higher than in the Buck mode (in the Boost mode VPRE = +6 V), in order to maintain a sufficient dropout voltage for the 5–volt linear regulators (VDDH, VREFs) and to avoid unwanted Resets to the microcontroller. The most stringent conditions for the PC33394 boost converter occur with the lowest input voltage: The inductor saturation current is given by the upper value of the PC33394 internal switch current limit Ilim(max) = 3.0 A. Considering also the inductor serial resistance, these requirements are met, for example by the PO250.473T inductor from Pulse Engineering, Inc. 5.2.1.2. Selecting the Catch Diode D1 The rectifier D1 current capability has to be greater than calculated average current value. The maximum reverse voltage stress placed upon this rectifier D1 is given by maximum input voltage (maximum transient battery voltage). These requirements are met, for example by the HSM350 (3 A, 50 V) schottky diode from Microsemi, Inc. Vin(min) = 3.5 V Io = 0.8 A 5.2.1.3. Selecting the Output Capacitor Vpre = +6 V The output capacitor Co should be a low ESR part, therefore the 100 µF tantalum capacitor with 80 mΩ ESR was chosen. f = 200 kHz Vfwd1 = Vfwd2 = 0.5 V From the formula for calculating the ripple voltage: 1- . $' 1<M: - ' 1?D , $, d = 0.75, duty cycle is fixed at 75% in boost mode $' .- $'$( $ $ 1* -'* $' $' ' ' $' $' $* $* * / J Figure 16. PC33394 Switcher Topology – Boost Mode The input voltage drop associated with the resistance of the internal switch Q1 and inductor series resistance can be estimated as: VD Ipk(min) RD 2.5 A 0.35 0.875 V Where: VD is the voltage dissipated on the major parasitic resistances, RDSon of the internal power switch and inductor series resistance RL. For the worst case conditions: RD = RDSon(max) + RL = 0.25 + 0.1 = 0.35[Ω] Ipk(min) is the minimum internal power switch current limit value. Then the equation for calculating ∆IL can be modified as follows: MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA V VD [(Vo Vfwd2) (Vin VD)] d IL in L (Vo Vfwd2) f 3.5 0.875 47 10 6 [(6 0.5) (3.5 0.875)] 0.75 (6 0.5) 0.2 10 6 125[mA] Then the maximum average input current can be calculated as: IinAve Ipk(min) 1 IL 2.5 0.125 2.43[A] 2 2 Finally, the boost converter power capability has to be higher than the required output power or: Pin(max) Pout Where Pin(max) is the boost converter maximum input power: 29 PC33394 h is the boost converter efficiency, in our case h is estimated to be h = 85%, and includes switching losses of the external power switch Q2 (MOSFET) inductor and capacitors AC losses, and output rectifier D2 (schottky) switching losses. Pout is the boost converter output power, which includes power loss of the output rectifier D2: Pout (Vo Vfwd2) Io (6 0.5) 0.8 5.2[W] Pin (Vin VD) IinAve (3.5 0.875) 2.43 0.85 5.42[W] As can be seen, the boost converter input power capability meets the required criteria. 5.2.1.4. Selecting the Power MOSFET Q2 The boost converter maximum output voltage plus the voltage drop across the output schottky rectifier D2 gives the MOSFET’s maximum drain–source voltage stress: BVdsQ2>Vo+Vfwd2 = 6 V+0.5 V, as can be seen, the breakdown voltage parameter is not critical. The more important in our case is the Q2 current handling capability. The external power MOSFET has to withstand higher currents than the upper current limit of the PC33394: IDQ2>3A In order to keep the power dissipation of the PC33394 boost converter to its minimum, a very low RDSon power MOSFET has to be selected. Moreover, due to the fact that the PC33394 external MOSFET gate driver is supplied from VPRE, in order to assure proper switching of Q2 a logic level device has to be selected. Last but not least, the Q2 package has to suitable for the harsh automotive environment with low thermal resistance. These requirements are met, for example by the MTD20N03HDL power MOSFET from ON Semiconductor. 5.2.1.5. Selecting the Boost Converter Output Rectifier D2 Criteria similar to that of selecting the power MOSFET was used to select the boost converter output rectifier. Its reverse breakdown voltage is not a critical parameter: VrD2>Vo=6 V The D2 rectifier has to withstand higher peak current than is the PC33394 internal switch upper current limit Ilim(max). The most important parameter is its forward voltage drop, which has to be minimal. This parameter is also crucial for the proper PC33394 switcher functionality, and especially for proper transition between the buck and boost modes. Finally, its switching speed, forward and reverse recovery parameters play a significant role when selecting the output rectifier D2. These requirements are met, for example by the HSM350 schottky rectifier from Microsemi, Inc. 5.2.2. Input Filter Selection Since the switcher will work in the Boost mode only during cold crank condition, the PC33394 EMC (electromagnetic compatibility) performance is not of concern during this mode of operation. Therefore, only the Buck mode of operation is important for selecting the appropriate input filter. For the Buck converter topology (see Figure 13) the low impedance 3rd order filter (C3, L2, C4 in the Application Schematic Diagram Figure 20) offers a good solution. It can be seen from the Buck converter current waveforms that comparatively high current pulses are drawn from the converter’s input source. The filter inductance must be kept minimal and the capacitor, which is placed right next to the power switch, must be sized large enough to provide sufficient energy reservoir for proper switcher operation. 5.2.3. Buck Converter Feedback Compensation A typical control loop of the buck regulator is shown in Figure 17. The loop consists of a power processing block — the modulator in series with an error–detecting block — the Error (Feedback) Amplifier. In principle, a portion of the output voltage (VPRE of the PC33394 switcher) is compared to a reference voltage (Vbg) in the Error Amplifier and the difference is amplified and inverted and used as a control input for the modulator to keep the controlled variable (output voltage VPRE) constant. 1?D "7?D BE9A (E:KB7JEH 1?D " # !;;:879A BE9A 1?D1EKJ " "# 1EKJ 1EKJ +2( .?=D7B -7CF /E 'E7: (*0'/*5< 5?D -;<;H;D9; 1EBJ7=; --*- ! & (+'$!$ - Figure 17. The Buck Converter Control Loop 30 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 - 1+- 6. - - '*. '**+EL;H7BB -;< 1*(+ 0 <F' --*(+'$!$ - "$): - <5 (*0'/*- <F <F <5 $<NE Figure 18. Error Amplifier Two–Pole–Two–Zero Compensation Network The process of determining the right compensation components starts with analysis of the open loop (modulator) transfer function, which has to be determined and plotted into the Bode plot (see Figure 19). The modulator DC gain can be determined as follows: 1 fp(LC) 2 LCo This double pole exhibits a —40dB per decade rolloff and a —180 degree phase shift. Another point of interest in the modulator’s transfer function is the zero caused by the ESR of the output capacitor Co and the capacitance of the output capacitor itself: 1 fz(ESR) 2RESRCo The ESR zero causes +20dB per decade gain increase, and +90 degree phase shift. Once the open loop transfer function is determined, the appropriate compensation can be applied in order to obtain the required closed loop cross over frequency and phase margin (~60 degree) — refer to Figure 18 and Figure 19. Figure 19 shows the PC33394 Switching Regulator modulator gain–phase plot, E/A gain–phase plot, closed loop gain–phase plot, and the E/A compensation circuit. The frequency fxo is the required cross–over frequency of the buck regulator. In order to achieve the best performance (the highest bandwidth) and stability of the voltage–mode controlled buck PWM regulator the two–pole–two–zero type of compensation was selected — see Figure 19 for the compensated Error Amplifier Bode plot, and Figure 18 for the compensation network. The two compensating zeros and their positive phase shift (2 x +90 degree) associated with this type of compensation can counteract the negative phase shift caused by the double pole of the modulator’s output filter. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA A A ( A ( < #P (*0'/*- +#. :;= V V ADC out d in Vin Ve Where Ve is the maximum change of the Error Amplifier voltage to change the duty cycle from 0 to 100 percent (Ve = 2.6 V at Vbat =14 V). As can be seen from Figure 19, the buck converter modulator transfer function has a double complex pole caused by the output L–C filter. Its corner frequency can be calculated as: <5 .- --*-(+'$!$ - '*. '**+EL;H7BB A < #P Figure 19. Bode Plot of the Buck Regulator The frequency of the compensating poles and zeros can be calculated from the following expressions: 1 fz1 2R2C2 1 1 fz2 2(R1 R3)C3 2R1C3 1 fp1 2R3C3 C C2 1 fp2 1 2R2C1C2 2R2C1 and the required absolute gain is: A1 R2 R1 R2(R1 R3) R 2 R1R3 R3 Refer to Application Schematic Diagram (Figure 20) and Table 2 for the PC33394 switcher component values. A2 31 PC33394 Table 2. /HRESET. When sizing the delay time the module design engineer must consider capacitor leakage, printed board leakage and HRT pin leakage. Resistor selection should be low enough to make the leakage currents negligible. Part number (Figure 18) Application diagram part number (Figure 1) Component value R1 PC33394 internal resistor 39.6kΩ R2 R2 100kΩ 5.5. Selecting the VKAM Resistor Divider R3 R1 430Ω C1 C6 100pF C2 C7 1.0nF C3 C5 3.3nF The VKAM linear regulator output voltage is divided by an external resistor divider and compared with the bandgap reference voltage (Vbg) in the input of the VKAM error amplifier. The resistor divider can be designed according to the following formula: 5.3. Selecting Pull–Up Resistors All the Resets (/PORESET, /PRERESET and /HRESET) are open drain outputs, which can sink a maximum of 1 mA drain current. This determines the pull–up resistor minimum value. VKAM should be used as the pull–up source for the /PORESET output. /PORESET is pulled low only during initial battery connect or when VKAM is below 2.5 volts (for VDDL = 2.6 V). To select the /PRERESET and /HRESET pull–up resistor connections, consider current draw during sleep modes. For example, the pull up resistor on /PRERESET and /HRESET should receive its source from VDDL, if the sleep mode or low power mode of the module is initiated primarily by the state of the VIGN pin. Refer to Figure 20 for recommended pull–up resistor values. Another way to connect the /PRERESET and /HRESET pull–up resistors is to connect them to the VKAM output together with the /PORESET pull–up resistor (see Figure 1). This is the preferable solution when the sleep or low power mode is initiated primarily by the microprocessor. In that case, when the PC33394 is shut down by pulling the /SLEEP pin down, all three Resets (/PORESET, /PRERESET and /HRESET) stay high. Since they are pulled–up to the supply voltage (VKAM) they draw no current from the VKAM and the module quiescent current is minimized. VKAM Vbg 1 Rupper Rlower Vbg = 1.25 V Where Vbg is the bandgap reference voltage. Since the VKAM feedback pin (VKAM_FB) input current is only a few nA, the resistor value can be selected sufficiently high in order to minimize the quiescent current of the module. See Figure 20 for the VKAM resistor divider recommended values. 5.6. Selecting the VDDL Resistor Divider The VDDL regulator resistor divider is designed according to the same formula as described in the paragraph above (see Figure 20). VDDL Vbg 1 Rupper Rlower Nonetheless, the actual resistor values should be chosen several decades lower than in the previous example. This is due to the fact that the VDDL linear regulator needs to be pre–loaded by a minimum of 10 mA current in order to guarantee stable operation. See Figure 20 for the VDDL resistor divider recommended values. 5.4. Selecting Hardware Reset Timer Components The HRT input sets the delay time from VDDH, VDD3_3 and VDDL stable to the release of /PRERESET and 32 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 7JJ;HO 1 Vbat 2 VDDH D1 20BQ030 L1 47uH 1 2 + C3 1.0uF/50V C4 100uF/35V + C2 D3 SS25 SW1 DIP–2 R14 15k R1 430R C29 1.0uF/50V U1 VIGN R3 4.7k C1 100nF 1.0uF/50V C26 C28 VKAM 10nF R4 22k + C23 10nF C24 22uF R6 20k VREF1 VPP_EN C8 10nF C9 1.0uF VDDL_X VDDL_B VDDL_FB R19 2.0R CANRXD CANTXD VPP VBAT VBAT VBAT VBAT VBAT KA_VBAT N/C VIGN VKAM VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB N/C /PRERESET /HRESET /PORESET CANRXD CANTXD SW1 SW1 SW1 SW1 SW1 N/C BOOT SW2G GND INV VCOMP VPRE VPRE_S VDDH VREF2 VREF3 N/C DO SCLK DI CS N/C /SLEEP HRT CANH CANL GND MC33394DWB VSEN REGON WAKEUP 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VPRE 37 R9 4.7k DO 36 R10 4.7k SCLK 35 R11 4.7k DI 34 R12 4.7k CS C22 10uF 37 36 35 34 R17 10k C11 10nF VREF2 C14 1.0uF /SLEEP C15 10nF R20 2.0R VREF3 R15 47k R8 120R C25 * R16 10k + C10 47uF /PORESET + /HRESET /PRERESET C21 10nF VDDH 10nF VPRE_S C13 10uF +3.3V C7 1.0nF C30 + C12 10nF C6 100pF R22 100k CANL VPP_EN IGN C5 100uF/16V 3.3nF Q1 MMSF3300R2 R13 18R BOOT 1 2 L2 6.8uH CANH JP1 D2 * MURS320T3 Q3 VDDH C18 100nF C27 * C16 1.0uF C17 10nF R21 2.0R R18 10k VKAM Q3 VPRE Q2 MJD31 7JJ;HO ") 7JJ;HO ") 7JJ;HO ") 7JJ;HO ") 1&( .' + 1++ 2& 0+ 1. ) $") 1 - "*) +*- . / +- - . / )# #- . / )' )-3 1- ! )/3 1- ! . 1- ! $ 1++6 ) .'& 1# * 1' ") VDDL = 2.6V Q3 MJD31 VDDL_X VDDL R5 110R VDDL_FB + C15 10nF C20 47uF 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J1 VDDL_B R7 100R CON/34 )EJ;I ?I 7 FHEJ;9J?ED :?E:; 7=7?DIJ H;L;HI; 87JJ;HO <7KBJ 9ED:?J?ED $D J>EI; 7FFB?97J?EDI M>?9> :E DEJ H;GK?H; J>?I JOF; E< FHEJ;9J?ED :?E:; 97D 8; ECC?JJ;: )EJ;I 7F79?JEHI 7H; EFJ?ED7B 7D: C7O 8; KI;: <EH ) JH7D9;?L;H ;L7BK7J?ED Figure 20. PC33394 Application Circuit Schematic Diagram Table 3. PC33394 Evaluation Board Performance Parameter Value (TA = 25C, Vin = 14V) Line Regulation (Vin = 5.2V to 26.5V) Load Regulation (Vin = 14 V) V [mV] Load [mA] [mV] Load [mA] V [mV] Load [mA] VDDH 5.028 400 10 400 18 0 to 400 VPP 5.026 150 10 150 5 0 to 150 VREF1 5.023 100 8 100 8 0 to 100 VREF2 5.022 100 8 100 10 0 to 100 VREF3 5.021 100 6 100 11 0 to 100 VDD3_3 3.307 120 5 120 7 0 to 120 VDDL 2.667 400 5 400 10 0 to 400 VKAM 2.638 60 2 60 14 0 to 60 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33 PC33394 Table 4. PC33394DWB Evaluation Board Bill of Material Item Qty. 1 2 C1,C18 Part Designator 100nF/16V, Ceramic X7R Value/ Rating Any manufacturer Part Number/ Manufacturer 2 1 C2 100uF/16V TPSD107K016R0125, AVX Corp. 3 3 C3,C26,C29 1.0uF/50V C1812C105K5RACTR, Kemet 4 1 C4 100uF/35V UUB1V101MNR1GS, Nichicon 5 1 C5 3.3nF, Ceramic X7R Any manufacturer 6 1 C6 100pF, Ceramic X7R Any manufacturer 7 1 C7 1.0nF, Ceramic X7R Any manufacturer 8 10 C8,C11,C12,C15,C17,C19,C21,C23,C28,C30 10nF, Ceramic X7R Any manufacturer 9 3 C9,C14,C16 1.0uF, Ceramic X7R Any manufacturer 10 2 C20,C10 47uF/10V, Tantalum TPSC476K010R0350, AVX Corp. 11 1 C13 10uF/16V, Tantalum TPSB106K016R0800, AVX Corp. 12 1 C22 10uF/6.3V, Tantalum TPSA106K006R1500, AVX Corp. 13 1 C24 22uF/6.3V, Tantalum TPSA226K006R0900, AVX Corp. 14 2 C25,C27 470pF, Ceramic X7R Any manufacturer 15 1 D1 30V/2A Schottky 20BQ030, International Rectifier 16 1 D2 200V/3A Diode MURS320T3, ON Semiconductor 17 1 D3 50V/2A Schottky SS25, General Semiconductor 18 1 JP1 2–pin, 0.2 (5.1mm) Terminal Block 19 1 J1 34–pin, 0.1 x 0.1 PCB Header Connector 20 1 L1 47uH PO250.473T, Pulse Engineering 21 1 L2 6.8uH PO751.682T, Pulse Engineering 22 1 Q1 30V/11.5A, Mosfet MMSF3300R2, ON Semiconductor 23 2 Q2,Q3 100V/3A, BJT MJD31C, ON Semiconductor 24 1 R1 430R, Resistor 0805 Any manufacturer 25 1 R2 100k, Resistor 0805 Any manufacturer 26 5 R3,R9,R10,R11,R12 4.7k, Resistor 0805 Any manufacturer 27 1 R4 22k, Resistor 0805, 1% Any manufacturer 28 1 R5 110R, Resistor 0805, 1% Any manufacturer 29 1 R6 20k, Resistor 0805, 1% Any manufacturer 30 1 R7 100R, Resistor 0805, 1% Any manufacturer 31 1 R8 120R, Resistor 0805 Any manufacturer 32 1 R13 18R, Resistor 0805 Any manufacturer 33 1 R14 15k, Resistor 0805 Any manufacturer 34 1 R15 47k, Resistor 0805 Any manufacturer 35 3 R16,R17,R18 10k, Resistor 0805 Any manufacturer 36 3 R19,R20,R21 2.0R, Resistor 0805 Any manufacturer 37 1 SW1 2–Position DIP Switch BD02, C&K Components 38 1 TP1 Test Point, 0.038 240–333, Farnell 39 1 U1 Integrated Circuit PC33394DWB/ Motorola 34 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 VDDH ! 1 VPP_EN - A - A ! 1 # .. ! ! 1 1 D! - A - A 1 C 1- ! ! D! 1C1++ 1&(6! 1. ) - "*) 2& 0+ 1- ! 1++6 ) PC33394FC 1++ 16 16! 1'63 1'6 , (% 1 ! 1+- 6. D! , (/)#' - *+/$*)' *0/+0/ !$'/ ' ! 1 ! 1 - - 0 $)1 1*(+ 1+1+- 6. 1# 1- ! 1- ! * .'& $ . F! D! - A 1+- 1 C 1# ! D! 1 C 1- ! ! D! - 1# A D! 120R - - 1&( - A - A - A - A * - A .'& - A $ - A . C25 * 1 C 1- ! C27 * ! D! 1+- // -4 ") // -4 ") // -4 ") // -4 ") 1&( .' + 1++ 2& 0+ 1. ) $") 1 - "*) +- . / +- - . / )# #- . / )' )-3 1- ! )/3 1- ! . 1- ! $ 1++6 ) .'& 1# * 1' ") % ! 1+- D! , - ! D! ' 1$") 11&( D! D! 1/ # (0-./ ' SW1 DIP–2 // -4 1&( 1$") &61/ 1/ 1/ .2 .2 .2 **/ .2" ") 1 2 , 1'6! +- - . / #- . / +*- . / )-3 )/3 ") )' )# #-/ .' + JP1 1 C 1' D! , (% , 1'6 , (% 1'63 1' ! - - - 1'6! *) )EJ;I ?I 7 FHEJ;9J?ED :?E:; 7=7?DIJ H;L;HI; 87JJ;HO <7KBJ 9ED:?J?ED $D J>EI; 7FFB?97J?EDI M>?9> :E DEJ H;GK?H; J>?I JOF; E< FHEJ;9J?ED :?E:; 97D 8; ECC?JJ;: )EJ;I 7F79?JEHI 7H; EFJ?ED7B 7D: C7O 8; KI;: <EH ) JH7D9;?L;H ;L7BK7J?ED Figure 21. PC33394 Enhanced Application Circuit Schematic Diagram MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 35 PC33394 Table 5. PC33394FC Evaluation Board Bill of Material Item Qty. 1 2 C1,C18 Part Designator 100nF/16V, Ceramic X7R Value/ Rating Any manufacturer Part Number/ Manufacturer 2 1 C2 100uF/20V TPSD107K016R0125, AVX Corp. 3 3 C3,C26,C29 1.0uF/50V C1812C105K5RACTR, Kemet 4 1 C4 100uF/35V UUB1V101MNR1GS, Nichicon 5 1 C5 1.5nF, Ceramic X7R Any manufacturer 6 1 C6 100pF, Ceramic X7R Any manufacturer 7 1 C7 1.0nF, Ceramic X7R Any manufacturer 8 9 C8,C11,C12,C15,C17,C19,C21,C23,C28 10nF, Ceramic X7R Any manufacturer 9 3 C9,C14,C16 1.0uF/35V Tantalum TPSA105K035R3000, AVX Corp. 10 2 C10,C22 47uF/10V Tantalum TPSC476K010R0350, AVX Corp. 11 1 C13 33uF/10V Tantalum TPSB336K010R0500, AVX Corp. 12 1 C20 100uF/6.3V Tantalum TPSC107K006R0150, AVX Corp. 13 1 C24 22uF/6.3V, Tantalum TPSA226K006R0900, AVX Corp. 14 2 C27,C25 470pF, Ceramic X7R Any manufacturer 15 1 C30 33uF/16V TPSC336K016R0300, AVX Corp. 16 1 D1 30V/ 2A Schottky 20BQ030, International Rectifier 17 1 D2 200V/3A Diode MURS320T3, ON Semiconductor 18 1 D3 SS25 SS25, General Semiconductor 19 1 JP1 2–pin, 0.2 (5.1mm) Terminal Block 20 1 J1 34–pin, 0.1 x 0.1 PCB Header Connector 21 1 L1 47uH PO250.473T, Pulse Engineering 22 1 L2 6.8uH PO751.682T, Pulse Engineering 23 1 L3 Ferrite Bead HF30ACC575032/ TDK 24 1 Q1 30V/20A Mosfet MTD20N03HDL, ON Semiconductor 25 3 Q2,Q3,Q4 100V/3A BJT MJD31C, ON Semiconductor 26 1 R1 680R, Resistor 0805 Any manufacturer 27 1 R2 100k, Resistor 0805 Any manufacturer 28 5 R3,R9,R10,R11,R12 4.7k, Resistor 0805 Any manufacturer 29 1 R4 22k, Resistor 0805, 1% Any manufacturer 30 1 R5 110R, Resistor 0805, 1% Any manufacturer 31 1 R6 20k, Resistor 0805, 1% Any manufacturer 32 1 R7 100R, Resistor 0805, 1% Any manufacturer 33 1 R8 120R, Resistor 0805 Any manufacturer 34 1 R13 18R, Resistor 0805 Any manufacturer 35 1 R14 15k, Resistor 0805 Any manufacturer 36 1 R15 47k, Resistor 0805 Any manufacturer 37 3 R16,R17,R18 10k, Resistor 0805 Any manufacturer 38 1 R19 10R, Resistor 0805 Any manufacturer 39 1 SW1 2–Position DIP Switch BD02, C&K Components 40 1 TP1 Test Point 240–333, Farnell 41 1 U1 Integrated Circuit PC33394DWB/ Motorola 36 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 µ! . *) *!! - A D! 1&(1C D! µ! - A - A 1- !1C D! µ! 1++1C D! 1# µ! 1C D! µ! 1+- , (%# 1'1C D! µ! - - - - +- - . / #- . / +*- . / 1&( - A - A 1/ .2 1/ .2 &61/ .2 1$") **/ 1&( .2" ") 1&(6! $)1 1. ) - "*) 1*(+ 2& 0+ 1+- 1- ! 1++6 ) 1++ PC33394 $DFKJLEBJ7=;1JE1 16 1# 1- ! 1- ! * 1'63 .'& 1'6 $ 1'6! . +- - . / #- . / .' 8 D! D! 1+- 1 (-./ µ! 1 < D! -< - -< A < F! < D! 1+- 6. 16! ' µ! + #-/ +*- . / )# )-3 )' )/3 ") 1#1C 1- !1C 1- !1C µ! D! µ! µ! D! D! -J A - 1# J D! - A Figure 22. PC33394 Buck–Only Application MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 37 PC33394 1C µ! µ! . *) *!! - A D! 1&(1C D! µ! - A - A 1- !1C D! µ! 1++1C D! 1# µ! 1C D! µ! 1+- , (% 1'1C D! µ! - - - - +- - . / #- . / +*- . / 1&( - A - A .2 1/ 1/ .2 &61/ .2 1$") **/ 1&( .2" ") 1&(6! $)1 1. ) - "*) 1*(+ 1- ! 1++6 ) 1++ 16 1+- 6. 1# 1- ! 1- ! * 16! 1'63 .'& 1'6 $ 1'6! . +- - . / #- . / .' + #-/ +*- . / )# )-3 )' )/3 ") µ! 1C 1+- 1 / 8 D! (-./ µ! -< - < D! -< A < F! 1+- 2& 0+ PC33394 $DFKJLEBJ7=;1JE1 < D! 1#1C 1- !1C 1- !1C µ! D! µ! µ! D! D! -J A - 1# J D! - A Figure 23. PC33394 Flyback Converter Provides Symmetrical Voltages 38 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 PACKAGE DIMENSIONS DH SUFFIX 44–LEAD HSOP PLASTIC PACKAGE CASE 1291–01 ISSUE O PIN ONE ID h X 45 E3 E2 E5 4X D1 D3 e 42X D2 4X D EXPOSED HEATSINK AREA B E1 E 888 ( E4 A 22X BOTTOM VIEW Y H ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ b1 A A2 c1 c C b 777 SECTION W–W L1 W W L A1 888 ( )*/ . *)/-*''$)" $( ).$*) ($''$( / - $( ).$*). ) /*' -) . + - .( 4( /0( +') # $. '*/ / *//*( *! ' ) $. *$)$ )/ 2$/# /# ' 2# - /# ' 3$/. /# +'./$ *4 / /# *//*( *! /# +-/$)" '$) $( ).$*). ) * )*/ $)'0 (*' +-*/-0.$*) ''*2' +-*/-0.$*) $. + - .$ $( ).$*). ) * $)'0 (*' ($.(/# ) / -($) / /0( +') # $( ).$*) 8 * . )*/ $)'0 (+-*/-0.$*) ''*2' (+-*/-0.$*) .#'' /*/' $) 3 .. *! /# 8 $( ).$*) / (3$(0( (/ -$' *)$/$*) /0(. ) /* / -($) / /0( +') # $( ).$*) * . )*/ $)'0 /$ +-*/-0.$*). ''*2' /$ +-*/-0.$*). - + - .$ . . DETAIL Y MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 39 PC33394 PACKAGE DIMENSIONS FC SUFFIX 44–LEAD QFN PLASTIC PACKAGE CASE 1310–01 ISSUE D PIN 1 INDEX AREA 9 A 2X M G 2X 1.0 1.00 0.8 0.75 9 (0.325) (0.65) 0.05 0.00 C 5 DETAIL G VIEW ROTATED 90 ° CLOCKWISE M B 6.85 6.55 DETAIL M PIN 1 IDENTIFIER EXPOSED DIE ATTACH PAD )*/ . '' $( ).$*). - $) ($''$( / -. $( ).$*)$)" ) /*' -)$)" + - .( 4( /# *(+' / % .$")/*- !*- /#$. +&" $. #! +,!+ ) *-) - #(! - (4 )*/ +- . )/ $( ).$*). *! *+/$*)' ! /0- . - !*- ! - ) *)'4 *+')-$/4 ++'$ . /* ' . *-) ' . ) $ //# + !*- )1$' .$)"0'/ ,!) +&" . (3$(0( -!/ )"' $. ° 6.85 6.55 0.65 44X 0.75 0.50 40X N 44X 0.37 0.23 VIEW M–M ( ( (45 ° ) (3.53) 44X 0.065 0.015 0.60 0.24 0.60 0.24 (0.25) DETAIL N DETAIL N PREFERRED CORNER CONFIGURATION CORNER CONFIGURATION OPTION 4 4 ° 3.4 3.3 DETAIL T (90 ) BACKSIDE PIN 1 INDEX 0.475 0.425 2X 0.39 0.31 R 0.25 0.15 40 2X 0.1 0.0 DETAIL M DETAIL M DETAIL T PREFERRED BACKSIDE PIN 1 INDEX BACKSIDE PIN 1 INDEX OPTION PREFERRED BACKSIDE PIN 1 INDEX MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 PACKAGE DIMENSIONS DWB SUFFIX 54–LEAD SOICW–EP PLASTIC PACKAGE CASE 1377–01 ISSUE B 10.3 5 7.6 7.4 9 C B 2.65 2.35 0.65 4 9 B 18.0 17.8 ' B A 5.15 )*/ . '' $( ).$*). - $) ($''$( / -. $( ).$*)$)" ) /*' -)$)" + - .( 4( /0(. ) /* / -($) / /# +') 2# - /# *//*( *! /# ' . 3$/ /# +'./$ *4 /#$. $( ).$*) * . )*/ $)'0 (*' !'.# +-*/-0.$*) *- "/ 0--. (*' !'.# +-*/-0.$*) *- "/ 0--. .#'' )*/ 3 (( + - .$ /#$. $( ).$*) $. / -($) / /# +') 2# - /# *//*( *! /# ' . 3$/ /# +'./$ *4 /#$. $( ).$*) * . )*/ $)'0 $)/ -' !'.# *- +-*/-0.$*). $)/ -' !'.# ) +-*/-0.$*). .#'' )*/ 3 (( + - .$ /#$. $( ).$*) $. / -($) / /# +') 2# - /# *//*( *! /# ' . 3$/ /# +'./$ *4 /#$. $( ).$*) * . )*/ $)'0 (+-*/-0.$*) ''*2' (+-*/-0.$*) .#'' )*/ 0. /# ' 2$/# /* 3 (( (- ))*/ '*/ *) /# '*2 - -$0. *- /# !**/ ($)$(0( .+ /2 ) +-*/-0.$*) ) % )/ ' .#'' )*/ ' .. /#) (( 3/ .#+ *! # *-) - $. *+/$*)' /# . $( ).$*). ++'4 /* /# !'/ . /$*) *! /# ' /2 ) (( ) (( !-*( /# ' /$+ /# +&" /*+ (4 .('' - /#) /# +&" *//*( /#$. $( ).$*) $. / -($) / /# *0/ -(*./ 3/- ( . *! /# +'./$ *4 3'0.$1 *! (*' !'.# /$ - 0--. "/ 0--. ) $)/ - ' !'.# 0/ $)'0$)" )4 ($.(/# /2 ) /# /*+ ) *//*( *! /# +'./$ *4 A R0.08 MIN C C 0 ° 0.25 (1.43) A 8° 0° 6.6 5.9 0.9 0.5 SECTION B–B 0.1 0.0 ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ (0.29) 4.8 4.3 0.30 0.25 BASE METAL (0.25) 0.38 0.22 6 ( PLATING 8 SECTION A–A ROTATED 90 CLOCKWISE VIEW C–C MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 41 PC33394 NOTES 42 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394 NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 43 PC33394 Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ 44 ◊ MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PC33394/D