Freescale Semiconductor Advance Information Document Number: MM908E624 Rev. 8.0, 3/2007 Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers 908E624 HIGH-SIDE SWITCH The 908E624 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides three high-side outputs with diagnostic functions, voltage regulator, watchdog, current sense operational amplifier, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-current motors applications using relays (e.g., window lifts, fans, and sun roofs). Features • High-Performance M68HC908EY16 Core • 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM • Internal Clock Generator Module • Two 16-Bit, 2-Channel Timers • 10-Bit Analog-to-Digital Converter (ADC) • LIN Physical Layer Interface • Low Dropout Voltage Regulator • Three High-Side Outputs • Two Wake-Up Inputs • 16 Microcontroller I / Os • Pb-Free Packaging Designated by Suffix Code EW DWB SUFFIX EW (Pb-FREE) SUFFIX 98ASA99294D 54-TERMINAL SOICW ORDERING INFORMATION Temperature Range (TA) Device MM908E624ACDWB/ R2 *MM908E624ACEW/ R2 *MM908E624AYEW/ R2 908E624 VSUP1 +5.0 V LIN VREFH VDDA EVDD VCC VDD VREFL VSSA EVSS AGND GND VSUP2 HS3 L1 L2 HS1 RXD PTE1/RXD RST RST_A IRQ IRQ_A M HS2 +E PTD0/TACH0 PWMIN Microcontroller Ports PTA0-4 PTB1; 3-7 PTC2-4 PTD1/TACH1 OUT -E To Microcontroller A/D Channel WDCONF Figure 1. 908E624 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. - 40°C to 125°C Notes* Recommended for new designs VBAT LIN Interface - 40°C to 85°C Package 54 SOICW Monitor ROM, 310 Bytes VSS VDD VSSA VREFL VDDA VREFH IRQ RST OSC1 OSC2 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6/TBCH0 PTB7/AD7/TBCH1 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTA5/SPSCK PTA6/SS Security Module Power-On Reset Module POWER 10 Bit Analog-to-Digital Converter Module Single External IRQ Module 24 Internal System Integration Module Internal Clock Generator Module User Flash Vector Space, 36 Bytes FLASH programming (burn in) ROM, 1024 Bytes PTE1/RXD MCU Die PTA5/SPSCK PTC1/MOSI PTC0/MISO PTA6/SS PTE0/TXD SPSCK MOSI MISO SS TXD Analog Die RXD SPI & Mode Control Reset Control Module Window Watchdog LIN Physical Layer VSUP1 Figure 2. 908E624 Simplified Internal Block Diagram PTE0/TxD PTE1/RxD PTD0/TACH0 PTD1/TACH1 PTC0/MISO PTC1/MOSI PTC2/MCLK PTC3/OSC2 PTC4/OSC1 BEMF Module Prescaler Module Arbiter Module Periodic Wakeup Timebase Module Configuration Register Module Serial Pheripheral Interface Module Computer Operating Properly Module Enhanced Serial Communication Interface Module 2-channel Timer Interface Module B 2-channel Timer Interface Module A 5-Bit Keyboard Interrupt Module Single Breakpoint Break Module PWMIN PWMIN Amplifier Wake Up Input 2 Wake Up Input 1 High Side Driver & Diagnostic High Side Driver & Diagnostic High Side Driver & Diagnostic Voltage Regulator VSUP2 FLSVPP PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 User RAM, 512 Bytes User Flash, 15,872 Bytes Control and Status Register, 64 Bytes ALU PORT A 2 CPU Registers VDDA PTA1/KBD1 EVDD PORT B PTA0/KBD0 EVSS Internal Bus VSSA DDRC VREFL DDRA RST DDRB PTD0/TACH0 PORT C LIN DDRD PWMIN PORT D VSUP1 DDRE VSUP2 VSUP2 VSUP2 GND PORT E WDCONF M68HC08 CPU OUT -E +E VCC L2 L1 HS3 HS2 HS1 VDD INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM AGND RST_A IRQ_A IRQ VREFH 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18. Die Terminal Terminal Name Formal Name Definition MCU 1 2 6 7 8 11 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 3 4 5 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input MCU 10 RST External Reset MCU 12 13 PTD0/TACH0 PTD1/TACH1 Port D I /Os These terminals are special-function, bidirectional I /O port terminals that are shared with other functional modules in the MCU. — 14, 15, 16, 20, 21, 22, 32, 41 NC No Connect Not connected. MCU 42 PTE1/ RXD Port E I /O This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18. Die Terminal Terminal Name Formal Name Definition MCU 43 48 VREFL VREFH ADC References These terminals are the reference voltage terminals for the analog-todigital converter (ADC). MCU 44 47 VSSA VDDA ADC Supply Terminals These terminals are the power supply terminals for the analog-to-digital converter. MCU 45 46 EVSS EVDD MCU Power Supply Terminals MCU 49 50 52 53 54 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I /Os MCU 51 FLSVPP Test Terminal Analog 17 PWMIN Direct High-Side Control Input Analog 18 RST_A Internal Reset Output Analog 19 IRQ_A Internal Interrupt Output This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. Analog 23 24 L1 L2 Wake-Up Inputs These terminals are the wake-up inputs of the analog chip. Analog 25 26 27 HS3 HS2 HS1 High-Side Output These output terminals are low RDS(ON) high-side switches. Analog 31 28 VSUP1 VSUP2 Power Supply Terminals Analog 29 LIN LIN Bus Analog 30 34 GND AGND Power Ground Terminals Analog 33 VDD Voltage Regulator Output Analog 35 VCC Amplifier Power Supply This terminal is the single +5.0 V power supply for the current sense operational amplifier. Analog 36 OUT Amplifier Output This terminal is the output of the current sense operational amplifier. Analog 37 38 -E +E Amplifier Inputs These terminals are the current sense operational amplifier inverted and non-inverted inputs. Analog 39 WDCONF Window Watchdog Configuration Terminal Analog 40 RXD LIN Transceiver Output These terminals are the ground and power supply terminals, respectively. The MCU operates from a single-power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For test purposes only. Do not connect in the application. This terminal allows the enabling and PWM control of the high-side HS1 and HS2 terminals. This terminal is the reset output terminal of the analog die. These terminals are device power supply terminals. This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. The + 5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This input terminal is for configuration of the watchdog period and allows the disabling of the watchdog. This terminal is the output of LIN transceiver. 908E624 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit Analog Chip Supply Voltage under Normal Operation (Steady-State) VSUP(SS) - 0.3 to 27 Analog Chip Supply Voltage under Transient Conditions VSUP(PK) - 0.3 to 40 VDD - 0.3 to 5.5 VIN (ANALOG) - 0.3 to VDD +0.3 VIN (MCU) VSS - 0.3 to VDD +0.3 All Terminals except VDD, VSS, PTA0:PTA6 , PTC0:PTC1 IPIN(1) ±15 PTA0:PTA6, PTC0:PTC1 Terminals IPIN(2) ± 25 Maximum Microcontroller VSS Output Current IMVSS 100 mA Maximum Microcontroller VDD Input Current IMVDD 100 mA Maximum Input Voltage, +E, -E Terminals V + E-E - 0.3 to 7.0 V Maximum Input Current, +E, -E Terminals I + E-E ± 20 mA VOUT - 0.3 to VCC + 0.3 V IOUT ± 20 mA Normal Operation (Steady-State) VBUS(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) VBUS(PK) -150 to 100 Normal Operation with a 33 kΩ resistor (Steady-State) VWAKE(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) VWAKE(PK) -100 to 100 VESD1 ± 2000 ELECTRICAL RATINGS Supply Voltage V MCU Chip Supply Voltage Input Terminal Voltage V Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal mA Current Sense Operational Amplifier Maximum Output Voltage, OUT Terminal Maximum Output Current, OUT Terminal LIN Supply Voltage V L1 and L2 Terminal Voltage V ESD Voltage Human Body Model V (1) Machine Model (1) Charge Device Model (1) VESD2 ±100 VESD3 ± 500 Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model, Robotic (CZAP = 4.0 pF). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit THERMAL RATINGS Package Operating Ambient Temperature (4) Operating Junction Temperature (2)(4) - 40 to 85 - 40 to 125 TJ MM908E624ACDWB and MM908E624ACEW MM908E624AYEW Storage Temperature Peak Package Reflow Temperature During Solder Mounting (3) °C TA MM908E624ACDWB and MM908E624ACEW MM908E624AYEW TSTG °C - 40 to 125 - 40 to 125 - 40 to 150 °C °C TSOLDER DWB Suffix 245 EW (Pb-Free) Suffix 260 Notes 2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150°C under these conditions. 3. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 4. Independent of TA, device parametrics are only guaranteed for - 40 < TJ < 125°C . Please see note 2. TJ is a factor of power dissipation, package thermal resistance, and available heat sinking. 908E624 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 5.5 — 18 V VSUPOP — — 27 V IRUN — 20 — mA VSUP = 13.5 V, LIN in recessive state ISTOP — 60 75 µA VSUP = 13.5 V, LIN in recessive state ISLEEP — 35 45 µA VOL — — 0.4 V SUPPLY VOLTAGE RANGE Nominal Operating Voltage Functional Operating Voltage (5) SUPPLY CURRENT RANGE Normal Mode (6) VSUP = 13.5 V, Analog Chip in Normal Mode, MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode (6), (7) Sleep Mode (6), (7) DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Terminal RST_A Low-State Output Voltage (IOUT = - 1.5 mA) IOH — 250 — µA IOL_MAX -1.5 — -8.0 mA Low-State Output Voltage (IOUT = - 1.5 mA) VOL — — 0.4 High-State Output Voltage (IOUT = 250 µA) VOH 3.85 — — Low-State Output Voltage (IOUT = - 1.5 mA) VOL — — 0.4 High-State Output Voltage (IOUT = 250 µA) VOH 3.85 — — V CIN — 4.0 — pF Input Logic Low Voltage VIL — — 1.5 V Input Logic High Voltage VIH 3.5 — — V IIN -10 — 10 µA CIN — 4.0 — pF IPU — 40 — µA High-State Output Current (VOUT > 3.5 V) Pulldown Current Limitation Output Terminal IRQ_A V Output Terminal RXD Capacitance (8) V Input Terminal PWMIN Input Current Capacitance (8) Terminal TXD, SS – Pullup Current Notes 5. Device is fully functional. All functions are operating. Overtemperature may occur. 6. Total current (IVSUP1 + IVSUP2) measured at GND terminal. 7. Stop and Sleep mode current will increase if VSUP exceeds 15 V. 8. This parameter is guaranteed by process monitoring but is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 3.6 4.0 4.4 Unit SYSTEM RESETS AND INTERRUPTS Low-Voltage Reset (LVR) V V LVRON Threshold Low-Voltage Interrupt (LVI) V Threshold V LVI 5.7 6.0 6.6 Hysteresis V LVI_HYS — 1.0 — Threshold V HVI 18 19.25 20.5 V Hysteresis V HVI_HYS — 220 — mV High-Voltage Interrupt (HVI) VOLTAGE REGULATOR (9) Normal Mode Output Voltage Normal Mode Output Current Limitation V V DDRUN 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V (10) IDDRUN Dropout Voltage 4.75 5.0 5.25 50 110 200 — 0.1 0.2 V V DDDROP VSUP = 4.9 V, IDD = 50 mA mA Stop Mode Output Voltage (11) V DDSTOP 4.75 5.0 5.25 V Stop Mode Regulator Current Limitation IDDSTOP 4.0 8.0 14 mA Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA VLRRUN — 20 150 Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLR STOP — 10 100 Line Regulation mV Load Regulation mV Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V VLRRUN — 40 150 Stop Mode, 1.0 mA < IDD < 5.0 mA, VSUP = 18 V VLDSTOP — 40 150 T PRE 120 135 160 °C T SD 155 170 — °C 20 30 45 Overtemperature Pre-Warning (Junction) (12) Thermal Shutdown Temperature (Junction) Temperature Threshold Difference TSD - TPRE (12) ∆T SD-T PRE °C Notes 9. Specification with external capacitor 2.0 µF< C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Capacitor value up to 47 µF can be used. 10. Total VDD regulator current. A 5.0 mA current for current sense operational amplifier is included. Digital output supplied from VDD. 11. 12. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. This parameter is guaranteed by process monitoring but not production tested 908E624 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit REXT 10 — 100 kΩ -15 — 15 WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (13) WDCACC % LIN PHYSICAL LAYER LIN Transceiver Output Voltage V Recessive State, TXD HIGH, IOUT = 1.0 µA V LIN_REC VSUP -1 — — Dominant State, TXD LOW, 500 Ω External Pullup Resistor V LIN_DOM — — 1.4 Normal Mode Pullup Resistor to VSUP R PU 20 30 60 kΩ Stop, Sleep Mode Pullup Current Source IPU — 2.0 — µA IOV-CUR 50 75 150 mA — 1.0 10 0.0 3.0 20 -1.0 — 1.0 Output Current Shutdown Threshold Leakage Current to GND µA IBUS VSUP Disconnected, VBUS at 18 V Recessive State, 8.0 V ≤ VSUP ≤ 18 V, 8.0 V≤ VBUS ≤ 18 V, VBUS ≥ VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V LIN Receiver VSUP Receiver Threshold Dominant V BUS_DOM — — Receiver Threshold Recessive V BUS_REC 0.6 — — V BUS_CNT 0.475 0.5 0.525 V BUS_HYS — — 0.175 Receiver Threshold Center Receiver Threshold Hysteresis 0.4 Notes 13. Watchdog timing period calculation formula: PWD = 0.991 * REXT + 0.648 (REXT in kΩ and PWD in ms). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max — 2.0 2.5 Unit HIGH-SIDE OUTPUTS HS1 AND HS2 Switch On Resistance TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V Ω RDS(ON) TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V — — 4.5 TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V — 3.0 — ILIM 300 — 600 mA THSSD 155 — 190 °C ILEAK — — 10 µA - 6.0 — — — — 7.0 TJ = 125°C, ILOAD = 50 mA, VSUP > 9.0 V — — 10 TJ = 125°C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V — — 14 ILIM 60 100 200 mA Overtemperature Shutdown (14), (15) THSSD 155 — 190 °C Leakage Current ILEAK — — 10 µA Output Current Limit Overtemperature Shutdown (14), (15) Leakage Current Output Clamp Voltage V VCL IOUT = -100 mA HIGH-SIDE OUTPUT HS3 Switch On Resistance TJ = 25°C, ILOAD = 50 m A, VSUP > 9.0 V Output Current Limitation Ω RDS(ON) Notes 14. This parameter is guaranteed by process monitoring but it is not production tested 15. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI. 908E624 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIMC - 0.1 — VCC + 0.1 V CURRENT SENSE OPERATIONAL AMPLIFIER Rail-to-Rail Input Voltage Output Voltage Range V Output Current ± 1.0 mA VOUT1 0.1 — VCC - 0.1 Output Current ± 5.0 mA VOUT2 0.3 — VCC - 0.3 Input Bias Current IB — — 250 nA Input Offset Current IO -100 — 100 nA Input Offset Voltage VIO - 25 — 25 mV L1 AND L2 INPUTS Low Detection Threshold VTHL V 5.5 V < VSUP < 6.0 V 2.0 2.5 3.0 6.0 V < VSUP < 18 V 2.5 3.0 3.5 18 V < VSUP < 27 V 2.7 3.2 3.7 5.5 V < VSUP < 6.0 V 2.7 3.3 3.8 6.0 V < VSUP < 18 V 3.0 4.0 4.5 18 V < VSUP < 27 V 3.5 4.2 4.7 0.5 — 1.3 -10 — 10 High Detection Threshold Hysteresis VTHH - 0.2 V < VIN < 40 V V VHYS 5.5 V < VSUP < 27 V Input Current V µA IIN 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Dominant Propagation Delay TXD to LIN t DOM-MIN — — 50 µs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 50 µs Recessive Propagation Delay TXD to LIN t REC-MIN — — 50 µs Recessive Propagation Delay TXD to LIN t REC-MAX — — 50 µs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX dt1 -10.44 — — µs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN dt2 — — 11 µs Dominant Propagation Delay TXD to LIN t DOM-MIN — — 100 µs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 100 µs Recessive Propagation Delay TXD to LIN t REC-MIN — — 100 µs Recessive Propagation Delay TXD to LIN t REC-MAX — — 100 µs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX dt1s - 22 — — µs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN dt2s — — 23 µs SRFAST — 15 — V / µs Receiver Dominant Propagation Delay (19) t RL — 3.5 6.0 µs Receiver Recessive Propagation Delay (19) t RH — 3.5 6.0 µs t R-SYM - 2.0 — 2.0 µs t PROPWL 35 — 150 µs t WAKE — 20 — µs LIN PHYSICAL LAYER Driver Characteristics for Normal Slew Rate (16), (17) Driver Characteristics for Slow Slew Rate (16), (18) Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-Up Timings Receiver Propagation Delay Symmetry Bus Wake-Up Deglitcher Bus Wake-Up Event Reported (20) Notes 16. VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 17. See Figure 6, page 15. 18. See Figure 7, page 16. 19. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 20. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD terminal. 908E624 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit tOV-DELAY — 10 — µs f SPIOP 0.25 — 4.0 MHz t WUF 8.0 20 38 µs LIN PHYSICAL LAYER (CONTINUED) Output Current Shutdown Delay SPI INTERFACE TIMING SPI Operating Recommended Frequency L1 AND L2 INPUTS Wake-Up Filter Time (21) WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) Watchdog Period t PWD ms External Resistor REXT = 10 kΩ (1%) — 10.558 External Resistor REXT = 100 kΩ (1%) — 99.748 — Without External Resistor REXT (WDCONF Terminal Open) 97 150 205 — STATE MACHINE TIMING Reset Low-Level Duration after VDD High (25) t RST 0.65 1.0 1.35 ms Interrupt Low-Level Duration t INT 7.0 10 13 µs t NR TOUT 97 150 205 ms t S-HSON — 3.0 10 µs t S-HSOFF — 3.0 10 µs t S-NR2N 6.0 35 70 µs 15 40 80 90 — N/A t S-1STSPI 30 — N/A µs t 2SS 15 — — µs Normal Request Mode Timeout (25) Delay Between SPI Command and HS1 / HS2 / HS3 Turn On (22) , (23) Delay Between SPI Command and HS1 / HS2 / HS3 Turn Off (22) , (23) Delay Between Normal Request and Normal Mode After W/ D Trigger Command (24) Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) t W-SS Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command t W-SPI Delay Between Interrupt Pulse and First SPI Command Accepted Minimum Time Between Two Rising Edges on SS Notes 21. 22. 23. 24. 25. µs µs This parameter is guaranteed by process monitoring but is not production tested. Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load. Delay between the end of the SPI command (rising edge of the SS) and start of device activation / deactivation. This parameter is guaranteed by process monitoring but it is not production tested. Also see Figure 10 on page 17 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS MICROCONTROLLER PARAMETRICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Supply Voltage Rejection Ratio (26) SVR 60 — — dB (26) CMR 70 — — dB GBP 1.0 — — MHz SR 0.5 — — V/ µs PHMO 40 — — ° OLG — 85 — dB CURRENT SENSE OPERATIONAL AMPLIFIER Common Mode Rejection Ratio Gain Bandwidth (26) Slew Rate Phase Margin (for Gain = 1, Load 100 pF / 5.0 kΩ (26) Open Loop Gain Notes 26. This parameter is guaranteed by process monitoring but it is not production tested. MICROCONTROLLER PARAMETRICS Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet. Module Description Core High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with 2 Channels (TIM A and TIM B) Flash 16 K Bytes RAM 512 Bytes ADC 10-Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module 908E624 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Transient Pulse Generator LIN, L1, and L2 10 kΩ 10k 1.0 nF 1nF Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b. Figure 4. Test Circuit for Transient Test Pulses VSUP VSUP R0 TXD LIN RXD C0 R0R0 and C0C0 Combinations: and combinations: • 1.0 kΩ and 1.0 nF - 1k Ohm and 1nF • 600 Ω Ohm and 6.8 - 660 andnF 6.8nF • 500 Ω Ohm and 10 - 500 andnF10nF Figure 5. Test Circuit for LIN Timing Measurements TXD tREC-MAX LIN tDOM-MIN 58.1% VSUP VLIN_REC 74.4% VSUP 40% VSUP 60% VSUP 28.4% VSUP 42.2% VSUP tDOM-MAX tREC-MIN RXD tRL tRH Figure 6. LIN Timing Measurements for Normal Slew Rate 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tREC-MAX LIN t DOM-MIN VLIN_REC 61.6% VSUP 77.8% VSUP 40% Vsup 60% VSUP 25.1% VSUP 38.9% VSUP t DOM-MAX tREC-MIN RXD t RL t RH Figure 7. LIN Timing Measurements for Slow Slew Rate LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level VDD t PROPWL TpropWL t WAKE Twake Figure 8. Wake-Up Sleep Mode Timing LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level IRQ_A t PROPWL TpropWL tTwake WAKE Figure 9. Wake-Up Stop Mode Timing 908E624 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VDD RST_A tRST tNRTOUT Figure 10. Power On Reset and Normal Request Time-out Timing 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high-side outputs. Other ports are also provided, which include a current sense operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I /O TERMINALS (PTA0:4) PORT D I /O TERMINALS (PTD:0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are specialfunction, bidirectional I /O port terminals that can also be programmed to be timer terminals. For details, refer to the 68HC908EY16 data sheet. PORT E I /O TERMINAL (PTE1) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt terminals KBD0 : KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details, refer to the 68HC908EY16 data sheet. PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/ TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details, refer to the 68HC908EY16 data sheet. PORT B I/O TERMINALS (PTB1:7) EXTERNAL INTERRUPT TERMINAL (IRQ) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6 : PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details, refer to the 68HC908EY16 data sheet. The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details, refer to the 68HC908EY16 data sheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details, refer to the 68HC908EY16 data sheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details, refer to the 68HC908EY16 data sheet. 908E624 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a singlepower supply. Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details, refer to the 68HC908EY16 data sheet. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details, refer to the 68HC908EY16 data sheet. ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details, refer to the 68HC908EY16 data sheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. Do not connect in the application or connect to GND. PWMIN TERMINAL (PWMIN) This terminal is the direct PWM input for high-side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). RESET TERMINAL (RST_A) RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU. Important To ensure proper operation, do not add any external pullup resistor. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU. WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND. POWER SUPPLY TERMINALS (VSUP1 AND VSUP2) This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high-side switches. POWER GROUND TERMINAL (GND) This terminal is the device ground connection. HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2) These terminals are high-side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (overcurrent). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability. HIGH-SIDE OUTPUT TERMINAL (HS3) This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with overtemperature and current limit (overcurrent). The output is controlled only by SPI. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. WAKE-UP TERMINALS (L1 AND L2) These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI. Important If unused these terminals should be connected to VSUP or GND to avoid parasitic transitions. In Low Power Mode this could lead to random wakeup events. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION CURRENT SENSE OPERATIONAL AMPLIFIER TERMINALS (E+, E-, OUT, VCC) These are the terminals of the single-supply current sense operational amplifier. • The E+ and E- input terminals are the non-inverting and inverting inputs of the current sense operational amplifier, respectively. • The OUT terminal is the output terminal of the current sense operational amplifier. • The VCC terminal is the + 5.0 V single-supply connection. Note If the operational amplifier is not used, it is possible to connect all terminals (E+, E-, OUT and VCC) to GND - in this case all of the four terminals must be grounded. + 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR AND CURRENT SENSE AMPLIFIER GROUND TERMINAL (AGND) The AGND terminal is the ground terminal of the voltage regulator and the current sense operational amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together. NO CONNECT TERMINALS (NC) The NC terminals are not connected internally. Note Each of the NC terminals can be left open or connected to ground (recommended). The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is 908E624 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E624 ANALOG DIE MODES OF OPERATION Wake-up from Stop mode is initiated by a wake-up interrupt. Wakeup from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MODE1:2 bits in the SPI Control register. Figure 11 describes how transitions are done between the different operating modes and Table 6, page 22, gives an overview of the operating mode. The 908E624 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Normal Request Timeout Expired (t NRTOUT ) Normal Request timeout expired (NR TOUT) VVDD Low DD Low VDD High and Normal Request VVDDLow Low DD VVDD LOW (>t NRTOUT ) expired) Expired DD Low (>NRTOUT and and VSUVLVF =0 =0 Wake-Up (Reset) Wake-Up (Reset) Sleep Command SLEEP Command Sleep Stop STOPCommand Command Normal WD Failed WD failed Wake-Up Interrupt Wake-Up Interrupt Reset Reset Delay (t Delay VDD High and Reset RST) expired RST) (tExpired WD Disabled WD disabled Power Up WDtrigger Trigger WD Power Down Stop VDD VDD Low Low Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF terminal connected to GND) WD - meansisWatchdog WD Trigger: Watchdog triggered by SPI command WD means or Watchdog disabled (WDCONF terminal connected to GND) WD Failed: No disabled watchdog- trigger trigger occurs in closed window WD trigger – means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed – means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP command sent via SPI Wake-Up: L1 or L2 state change or LIN bus wake-up or SS rising edge SLEEP Command - means SLEEP command send via SPI Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 11. Operating Modes and Transitions 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 6. Operating Modes Overview Device Mode Voltage Regulator Wake-Up Capabilities Output Watchdog Function HS1, HS2, and HS3 LIN Interface Sense Amplifier Reset VDD ON N/A LOW Disabled Disabled Recessive only Not active Normal Request VDD ON N/A HIGH 150 ms time out if WD enabled Enabled Transmit and receive Not active Normal (Run) VDD ON N/A HIGH Window WD if enabled Enabled Transmit and receive Active Stop VDD ON with limited current capability LIN wake-up, L1, L2 state change, SS rising edge HIGH Disabled Disabled Recessive state with wake-up capability Not active Sleep VDD OFF LIN wake-up L1, L2 state change LOW Disabled Disabled Recessive state with wake-up capability Not active RST_A INTERRUPTS Wake-Up Interrupts In Normal (Run) mode the 908E624 has four different interrupt sources. An interrupt pulse on the IRQ_A terminal is generated to report a fault to the MCU. All interrupts are not maskable and cannot be disabled. After an Interrupt the INTSRC bit in the SPI Status register is set, indicating the source of the event. This interrupt source information is only transferred once, and the INTSRC bit is cleared automatically. In Stop mode the IRQ_A terminal reports wake-up events on the L1, L2, or the LIN bus to the MCU. All wake-up interrupts are not maskable and cannot be disabled. After a wake-up interrupt, the INTSRC bit in the Serial Peripheral Interface (SPI) Status register is set, indicating the source of the event. This wake-up source information is only transferred once, and the INTSRC bit is cleared automatically. Figure 12, page 23, describes the Stop / Wake-Up procedure. Low-Voltage Interrupt Low-voltage interrupt (LVI) is related to external supply voltage VSUP1. If this voltage falls below the LVI threshold, it will set the LVF bit in the SPI Status register and an interrupt will be initiated. The LVF bit remains set as long as the Lowvoltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled. High-Voltage Interrupt High-voltage interrupt (HVI) is related to external supply voltage VSUP1. If this voltage rises above the HVI threshold, it will set the HVF bit in the SPI Status register and an interrupt will be initiated. The HVF bit remains set as long as the high-voltage condition is present. During Sleep and Stop mode the high-voltage interrupt circuitry is disabled. Voltage Regulator Temperature Prewarning (VDDT) Voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold. It will set the VDDT bit in the SPI Status register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop mode the voltage regulator temperature prewarning circuitry is disabled. High-Side Switch Thermal Shutdown (HSST) The high-side switch thermal shutdown HSST is generated if one of the high-side switches HS1 : HS3 is above the HSST threshold, it will shutdown all high-side switches, set the HSST flag in the SPI Status register and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop mode the high-side switch thermal shutdown circuitry is disabled. 908E624 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU Power Die From Reset initialize operate SPI: 2x STOP Command Switch to VREG low current mode STOP Wake Up on LIN or L1, L2? IRQ interrupt ? Assert IRQ SPI: reason for interrupt Switch to VREG high current mode operate Figure 12. Stop Mode / Wake-Up Procedure 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES ANALOG DIE INPUTS / OUTPUTS HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. High-Side Output Terminals HS1 and HS2 Sleep and Stop Mode These are two high-side switches used to drive loads such as relays or lamps. They are protected with overtemperature and current limit (overcurrent) and include an active internal clamp circuitry for inductive load drive. Control is done using the SPI Control register. PWM capability is offered through the PWMIN input terminal. The high-side switch is turned on if both the HSxON bit in the SPI Control register is set and the PWMIN input is HIGH (refer to Figure 13, page 24). In order to have HS1 on, the PWMIN must be HIGH and bit HS1ON must be set. The same applies to the HS2 output. If no PWM control is required, PWMIN must be connected to the VDD terminal. This high-side feature switch feature current limit to protect it against overcurrent and short circuit conditions. Current Limit (Overcurrent) Protection Overtemperature Protection These high-side switches feature current limit to protect them against overcurrent and short circuit conditions. If an overtemperature condition occurs on any of the three high-side switches, all high-side switches (HS1, HS2 and HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. Overtemperature Protection If an overtemperature condition occurs on any of the three high-side switches, all high-side switches (HS1, HS2 and In Sleep and Stop modes the high-sides are disabled. High-Side Output HS3 This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. Control is done using the SPI Control register. No direct PWM control is possible on this terminal (refer to Figure 14, page 25). Current Limit (Overcurrent) Protection Sleep and Stop Mode In Sleep and Stop mode the high-side is disabled. . PWMIN VSUP2 MODE1:2 HSxON Control On/Off High-Side Driver Status Charge Pump, Current Limit Protection, Overtemperature Protection HSx Figure 13. High-Side HS1 and HS2 Circuitry 908E624 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES . MODE1:2 VSUP2 HS3ON Control On/Off High-Side Driver Status Charge Pump, Current Limit Protection, Overtemperature Protection HS3 Figure 14. High-Side HS3 Circuitry LIN PHYSICAL LAYER The LIN bus terminal provides a physical layer for singlewire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with over current protection and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The slew rate can be selected for optimized operation at 10 and 20kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LINSL2:1 in the SPI Control Register. The initial slew rate is optimized for 20kBit/s. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled in Normal and Normal Request mode. An over current condition (e.g. LIN bus short to Vbat) or a over temperature in the output low-side FET will shutdown the transmitter and set the LINFAIL flag in the SPI Status Register. For improved performance and safe behavior in case of LIN bus short to Ground or LIN bus leakage during low power mode the internal pull-up resistor on the LIN terminal can be disconnected, with the LIN-PU bit in the SPI Control Register, and a small current source keeps the LIN bus at recessive level. In case of a LIN bus short to GND, this feature will reduce the current consumption in STOP and SLEEP modes. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MODE2:1 LINSL2:1 LIN-PU VSUP1 LINWU LINFAIL Control 2µA 30k LIN bus TXD Slope Control WakeUp Filter Receiver GND RXD Figure 15. LIN Interface TXD Terminal The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 2, page 2). When TXD is LOW, the LIN terminal is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off (recessive state). The TXD terminal has an internal pullup current source in order to set the LIN bus to recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP Mode and Wake-up Feature During STOP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Stop mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN terminal in recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than TpropWL followed by an rising edge will generate a wake-up interrupt and set the LINWF flag in the SPI Status Register. Also see Figure 9, page 16. SLEEP Mode and Wake-up Feature During SLEEP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Sleep mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN terminal in recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than TpropWL followed by an rising edge will generate a system wake-up (reset) and set the LINWF flag in the SPI Status Register . Also see Figure 8, page 16). 908E624 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES WINDOW WATCHDOG Overtemperature Protection The window watchdog is configurable using an external resistor at the WDCONF terminal. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 29). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A terminal and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window. The voltage regulator also features an overtemperature protection having an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown. Window closed no watchdog clear allowed Window open for watchdog clear WD timing x 50% WD timing x 50% WD period (t (PPWD WD) ) WD timing selected by resistor on WDCONF terminal. Figure 16. Window Watchdog Operation Watchdog Configuration If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: t PWD [ms] = 0.991 * REXT [kΩ] + 0.648 VOLTAGE REGULATOR The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Current Limit (Overcurrent) Protection The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. Stop Mode During Stop mode, the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” (0xFF) state: • 0xFD80 :0xFDDF Trim and Calibration Values • 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values, located in the flash memory, is explained in the following. Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate for these dependencies, an ICG trim value is located at address $FDC2. After trimming the ICG, a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~23°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 data sheet. To trim the ICG, these values have to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 data sheet. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 908E624 SPI INTERFACE AND CONFIGURATION • MOSI — Master-Out Slave-In • MISO — Master-In Slave-Out • SPSCK — Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data. The serial peripheral interface creates the communication link between the microcontroller and the analog die of the 908E624. The interface consists of four terminals (see Figure 17): • SS — Slave Select SS Register write data MOSI D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Register read data MISO D7 D6 D5 D4 D3 SPSCK Read data latch Rising edge of SPSCK Change MISO/MOSI Output Write data latch Falling edge of SPSCK Sample MISO/MOSI Input Figure 17. SPI Protocol During the inactive phase of the SS (HIGH), the new data The data transfer is only valid if exactly 8 sample clock transfer is prepared. edges are present in the active (low) phase of SS. The falling edge of the SS indicates the start of a new data The rising edge of the slave select SS indicates the end of transfer and puts the MISO in the low-impedance state and the transfer and latches the write data (MOSI) into the latches the analog status data (Register read data). register The SS high forces MISO to the high impedance state. With the rising edge of the SPI clock, SPSCK the data is moved to MISO/MOSI terminals. With the falling edge of the SPI clock SPSCK the data is sampled by the Receiver. 908E624 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition. . Table 7. SPI Register Overview Bit Read / Write Information D7 D6 D5 D4 D3 D2 D1 D0 Write LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 INTSRC (27) LINWU or LINFAIL HVF LVF or BATFAIL (28) VDDT HSST L2 L1 Write Reset Value 0 0 0 0 0 0 — — Write Reset Condition POR, RESET POR, RESET POR POR, RESET POR, RESET POR, RESET — — Read Notes 27. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source. 28. The first SPI read after reset returns the BATFAIL flag state on bit D4. SPI Control Register (Write) Table 8 shows the SPI Control register bits by name. an erroneous short of the LIN bus to ground this will significantly reduce the power consumption, e.g. in combination with STOP/SLEEP mode. Table 8. Control Bits Function (Write Operation) HS3ON : HS1ON — High-Side H3 : HS1 Enable Bits D7 D6 D5 D4 D3 D2 D1 D0 LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 LINSL2 : 1 — LIN Baud Rate and Low-Power Mode Selection Bits These bits select the LIN slew rate and requested lowpower mode in accordance with Table 9. Reset clears the LINSL2 : 1 bits. Table 9. LIN Baud Rate and Low-Power Mode Selection Bits These bits enable the HSx. Reset clears the HSxON bit. • 1 = HSx switched on (refer to Note below). • 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal. MODE2 : 1 — Mode Section Bits The MODE2 : 1 bits control the operating modes and the watchdog in accordance with Table 10. Table 10. Mode Selection Bits LINSL2 LINSL1 Description MODE2 MODE1 Description 0 0 Baud Rate up to 20 kbps (normal) 0 0 Sleep Mode (29) 0 1 Baud Rate up to 10 kbps (slow) 0 1 Stop Mode (29) 1 0 Fast Program Download Baud Rate up to 100 kbps 1 0 Watchdog Clear (30) 1 1 Run (Normal) Mode 1 1 Low-Power Mode (Sleep or Stop) Request LIN-PU — LIN Pullup Enable Bit This bit controls the LIN pullup resistor during Sleep and Stop modes. • 1 = Pullup disconnected in Sleep and Stop modes. • 0 = Pullup connected in Sleep and Stop modes. In case the Pullup is disconnected a small current source is used to pull the LIN terminal in recessive state. In case of Notes 29. To enter Sleep and Stop mode, a special sequence of SPI commands is implemented. 30. The device stays in Run (Normal) mode. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep / Stop commands require two SPI transmissions. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Sleep Mode Sequence The Sleep command, as shown in Table 11, must be sent twice. Table 11. Sleep Command Bits LINSL2 LINSL1 1 1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 0/1 0 0 0 0 0 Stop Mode Sequence The Stop command, as shown in Table 12, must be sent twice. Table 12. Stop Command Bits LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 1 1 0/1 0 0 0 0 1 SPI Status Register (Read) Table 13 shows the SPI Status register bits by name. Table 13. Control Bits Function (Read Operation) D7 D6 D5 D4 D3 D2 D1 D0 INTSRC LINWU or LINFAIL HVF LVF or BATFAIL VDDT HSST L2 L1 INTSCR — Register Content Flags or Interrupt Source This bit indicates if the register contents reflect the flags or an interrupt / wake-up interrupt source. • 1 = D6 : D0 reflects the interrupt or wake-up source. • 0 = No interrupt occurred. Other SPI bits report real time status. LINWU / LINFAIL — LIN Status Flag Bit This bit indicates a LIN wake-up condition. • 1 = LIN bus wake-up occurred or LIN overcurrent/ overtemperature occurred. • 0 = No LIN bus wake-up occurred. In case of a LIN overcurrent/overtemperature condition the LIN transmitter is disabled. To reenable the LIN transmitter, the error condition must be GONE and the LINWU/LINFAIL flag must be cleared. The flag is cleared by reading the flag when it is set (SPI command). HVF — High-Voltage Flag Bit This flag is set on an overvoltage (VSUP1) condition. • 1 = High-voltage condition has occurred. • 0 = no High-voltage condition. LVF / BATFAIL — Low-Voltage Flag Bit This flag is set on an undervoltage (VSUP1) condition. • 1 = Low-voltage condition has occurred. • 0 = No low-voltage condition. VDDT — Voltage Regulator Status Flag Bit This flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. • 1 = Voltage regulator overtemperature condition, prewarning. • 0 = No overtemperature detected. HSST — High-Side Status Flag Bit This flag is set on overtemperature conditions on one of the high-side outputs. • 1 = HSx off due to overtemperature. • 0 = No overtemperature. In case one of the high-sides has an overtemperature condition all high-side switches are disabled. To reenable the high-side switches, the flags have to be cleared, by reading the flag when it is set and by writing a one to high-side HSxON bit (two SPI commands are necessary). L2:L1— Wake-Up Inputs L1, L2 Status Flag Bit These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source. • 1 = L2 : L1 input high or wake-up by L2 : L1 (first register read after wake-up indicated with INTSRC = 1). • 0 = L2 : L1 input low. 908E624 30 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E624 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12 V supply voltage some additional items have to be considered: • nominal 12 V rather than 5.0 V or 3.0 V supply • high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal • MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 data sheet section development support. The programming is principally possible at two stages in the manufacturing process — first on chip level, before the IC is soldered onto a PCB board and second after the IC is soldered onto the PCB board. Chip Level Programming On Chip level the easiest way is to only power the MCU with +5.0 V (see Figure 18) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:2]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 data sheet - section development support. VSUP[1:2] VDD GND AGND +5V VREFH RST VDDA RST_A EVDD VDD 100nF 1 1µF C1- GND C2+ V+ + 5 2 VTST + 4 RS232 DB-9 16 + 3 1µF VCC C1+ C2- MAX232 V- 1µF 15 VDD 5 8 R2IN R2OUT 9 10k 9.8304MHz CLOCK 1µF PTB4/AD4 CLK T2IN 10 6 10k 10k 5 +5V PTC4/OSC1 PTA1/KBD1 DATA 10k PTA0/KBD0 4 3 2 VSSA IRQ_A 6 + 4.7µF VREFL EVSS + 2 74HC125 3 MM908E624 1µF 74HC125 7 T2OUT IRQ PTB3/AD3 WDCONF 1 Figure 18. Normal Monitor Mode Circuit (MCU only) Of course it is also possible to supply the whole system with VSUP (12 V) instead as described in Figure 19, page 32. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 31 TYPICAL APPLICATIONS system has to be powered up providing VSUP (see Figure 19). PCB Level Programming If the IC is soldered onto the PCB board it is typically not possible to separately power the MCU with +5.0 V, the whole VDD VSUP[1:2] VSUP 47µF + VDD GND 100nF AGND VREFH RST VDDA RST_A EVDD VDD 100nF 1 1µF C1- GND C2+ V+ + 5 C2- MAX232 V- 1µF + IRQ_A VDD R2OUT 9 PTB4/AD4 CLK T2IN 10 8 R2IN 10k 9.8304MHz CLOCK 1µF 6 74HC125 3 VSSA EVSS 6 + 7 T2OUT MM908E624 1µF 2 VDD PTC4/OSC1 10k 10k PTA1/KBD1 5 DATA 10k PTA0/KBD0 4 PTB3/AD3 WDCONF 3 2 4.7µF VREFL 2.2k 15 74HC125 2 IRQ VTST + 4 RS232 DB-9 16 + 3 1µF VCC C1+ 1 5 Figure 19. Normal Monitor Mode Circuit Table 14 summarizes the possible configurations and the necessary setups. Table 14. Monitor Mode Signal Requirements and Options Mode IRQ RST WDCONF Normal Monitor Forced Monitor VTST VDD GND X GND $FFFF (blank) VDD VDD Reset Vector Serial Communication Mode Selection PTA0 PTA1 PTB3 PTB4 1 0 0 1 1 0 X VDD VDD REXT not $FFFF (not blank) X X X ICG COP OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6MHz Nominal 6300 ON enabled enabled — Nominal 1.6MHz Nominal 6300 X GND User Communication Speed Normal Request Bus Timeout External Frequenc Baud Rate Clock y X Notes 31. PTA0 must have a pullup resistor to VDD in monitor mode. 32. 33. 34. 35. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256. X = don’t care. VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V. 908E624 32 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS MCU Digital Supply Terminals (EVDD and EVSS) This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale website www.freescale.com. VSUP Terminals (VSUP1 and VSUP2) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behavior. MCU Analog Supply Terminals (VREFH, VDDA and VREFL, VSSA) LIN Terminal For DPI (Direct Power Injection) and ESD (Electro Static Discharge) it is recommended to place a high-quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator Output Terminals (VDD and AGND) To avoid noise on the analog supply terminals it is important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 20 and Figure 21 show the recommendations on schematics and layout level and Table 15 indicates recommended external components and layout considerations. Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VDD VSUP2 AGND VREFH VDDA L1 LIN LIN EVDD V1 C5 C3 MM908E624 C4 VREFL VSSA GND EVSS Figure 20. EMC/EMI recommendations 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 33 TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 50 6 49 7 VREFH 48 8 VDDA 47 9 EVDD 46 10 EVSS 45 11 VSSA 44 12 VREFL 43 13 42 908E624 41 15 40 16 39 17 38 18 37 19 36 20 35 21 AGND 34 22 VDD 33 23 NC 24 VSUP1 31 25 GND 30 Comment: Terminal 32 NC - used for signal routing C4 26 LIN 29 27 VSUP2 28 C1 32 C2 14 C3 5 D1 LIN L1 V1 C5 VBAT Figure 21. PCB Layout Recommendations . Table 15. Component Value Recommendation Component Recommended Value(36) D1 Comments / Signal routing Reverse battery protection C1 Bulk Capacitor C2 100 nF, SMD Ceramic Close (<5 mm) to VSUP1, VSUP2 terminals with good ground return C3 100 nF, SMD Ceramic Close (<3 mm) to digital supply terminals (EVDD, EVSS) with good ground return. The positive analog (VREFH, VDDA) and the digital (EVDD) supply should be connected right at the C3. C4 4.7 µF, SMD Ceramic or Low ESR C5 180 pF, SMD Ceramic Bulk Capacitor Close (<5 mm) to LIN terminal. Total Capacitance per LIN node has to be below 220 pF. (Ctotal = CLIN-Terminal + C5 + CVaristor ~ 10 pF + 180 pF + 15 pF) V1(37) Varistor Type TDK AVR-M1608C270MBAAB Optional (close to LIN connector) L1(37) SMD Ferrite Bead Type TDK MMZ2012Y202B Optional, (close to LIN connector) Notes 36. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. 37. Components are recommended to improve EMC and ESD performance. 908E624 34 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. 10.3 5 7.6 7.4 9 C 1 2.65 2.35 B 52X 54 0.65 PIN 1 INDEX 4 9 B 27 18.0 17.8 CL B 28 A 5.15 54X 2X 27 TIPS 0.3 SEATING PLANE 0.10 A A B C (0.29) A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. BASE METAL R0.08 MIN 0.30 0.25 (0.25) 0 ° MIN 0.25 0.29 0.13 GAUGE PLANE 0.38 0.22 6 A 0.13 M PLATING A B C 8 SECTION A-A ROTATED 90 ° CLOCKWISE DWB SUFFIX EW SUFFIX (Pb-FREE) CASE 1365-01 54-TERMINAL SOIC ISSUE OWIDE BODY PLASTIC PACKAGE 98ASA99294D ISSUE O 8° 0° 0.9 0.5 SECTION B-B DATE 09/19/01 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 35 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) ADDITIONAL DOCUMENTATION 908E624 THERMAL ADDENDUM (REV 3.0) INTRODUCTION This thermal addendum is provided as a supplement to the MM908E624 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. 54-TERMINAL SOICW Packaging and Thermal Considerations The MM908E624 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. TJ1 TJ2 RθJA11 RθJA12 RθJA21 RθJA22 = . P1 P2 DWB SUFFIX EW (Pb-FREE) SUFFIX 98ASA99294D 54-TERMINAL SOICW Note For package dimensions, refer to the MM908E624 datasheet. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below Standards Table 16. Thermal Performance Comparison 1 = Power Chip, 2 = Logic Chip [°C/ W] Thermal Resistance m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 RθJAmn (1)(2) 40 31 36 (2)(3) 25 16 21 RθJAmn (1)(4) 57 47 52 RθJCmn (5) 21 12 16 RθJBmn Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad. 54 Terminal SOIC 0.65 mm Pitch 17.9 mm x 7.5 mm Body 908E624 36 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) A PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 908E624 Terminal Connections 54-Terminal SOICW 0.65 mm Pitch 17.9 mm x 7.5 mm Body Figure 22. Surface Mount for SOIC Wide Body non-Exposed Pad Device on Thermal Test Board Material: Outline: Area A: Ambient Conditions: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 17. Thermal Resistance Performance 1 = Power Chip, 2 = Logic Chip (°C/W) Terminal Resistance RθJAmn Area A (mm2) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 58 48 53 300 56 46 51 600 54 45 50 RθJAmn is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 37 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0) θJA Thermal Resistance [ºC/W] 70 60 50 40 30 20 RθJA11 R x 10 0 0 θJA11 RθJA22 RθJA22 RθJA12 = RθJA21 RθJA12=RθJA21 300 600 Heat spreading area A [mm²] Figure 23. Device on Thermal Test Board Thermal Resistance [ºC/W] 100 10 x 1 0.1 1.00E-03 1.00E-02 RθJA11 RθJA22 RθJA12 = RθJA21 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 24. Transient Thermal Resistance RθJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2) 908E624 38 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 7.0 8.0 DATE 5/2006 3/2007 DESCRIPTION OF CHANGES • Implemented Revision History page • Added Pb-Free package option (Suffix EW) and higher Soldering temperature • Added “Y” temperature (TJ - 40°C to 125°C) code option (MM908E624AYEW) and updated condition statement for Static and Dynamic Electrical Characteristics • Corrected Figure 11, Operating Modes and Transitions (“STOP command” for transition from Normal to Stop state) • Updated Figure 21, PCB Layout Recommendations, comment NC Terminal used for signal routing • Updated Table 15, Component Value Recommendation • Corrected Figure 23, Device on Thermal Test Board • Removed reference to Note 11, Voltage Regulator - Dropout Voltage • Added comment “LIN in recessive state” to Supply Current Range in Stop Mode and Sleep Mode • Updated format to match current data sheet standard. • Added Figure 10, Power On Reset and Normal Request Time-out Timing • Added LIN P/L details • Made clarifications on Max Ratings Table for TA and TJ Thermal Ratings and the accompanying Note • Removed “Advance Information” watermark from first page. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 39 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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