FREESCALE DSP56F803E

56F807
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F807
Rev. 15
01/2007
freescale.com
56F807 General Description
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Up to 40 MIPS at 80MHz core frequency
•
Two 6 channel PWM Modules
•
DSP and MCU functionality in a unified,
C-efficient architecture
•
Four 4 channel, 12-bit ADCs
•
Two Quadrature Decoders
•
Hardware DO and REP loops
•
CAN 2.0 B Module
•
MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
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Two Serial Communication Interfaces (SCIs)
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Serial Peripheral Interface (SPI)
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60K × 16-bit words (120KB) Program Flash
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Up to four General Purpose Quad Timers
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2K × 16-bit words (4KB) Program RAM
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JTAG/OnCETM port for debugging
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8K × 16-bit words (16KB) Data Flash
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14 Dedicated and 18 Shared GPIO lines
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4K × 16-bit words (8KB) Data RAM
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160-pin LQFP or 160 MAPBGA Packages
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2K × 16-bit words (4KB) Boot Flash
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Up to 64K × 16- bit words (128KB) each of external
Program and Data memory
6
3
4
3
4
4
4
4
4
PWM Outputs
Current Sense Inputs
PWMA
RSTO
Fault Inputs
6
PWM Outputs
Current Sense Inputs
A/D1
A/D2
VPP
IRQA
A/D1
A/D2
ADCB
VREF2
4
Quadrature
Decoder 1
/Quad Timer B
PWMB
Quad Timer D
/ Alt Func
CAN 2.0A/B
2
2
SCI0
or
GPIO
2
SCI1
or
GPIO
4
SPI
or
GPIO
Dedicated
GPIO
2
8
JTAG/
OnCE
Port
Interrupt
Controller
Program Memory
61440 x 16 Flash
2048 x 16 SRAM
Quad Timer C
2
VCAPC VDD
6
ADCA
VREF
4
14
IRQB
Fault Inputs
Quadrature
Decoder 0
/Quad Timer
4
EXTBOOT
RESET
•
•
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
16-Bit
56800
Core
•
CGDB
XAB1
XAB2
•
XTAL
Clock Gen
EXTAL
•
IPBB
CONTROLS
16
MODULE CONTROLS
ADDRESS BUS [8:0]
CLKO
•
COP RESET
Application-Specific
Memory &
Peripherals
Bit
Manipulation
Unit
PLL
•
INTERRUPT
CONTROLS
16
COP/
Watchdog
Analog Reg
Low Voltage
Supervisor
XDB2
•
VSSA
3
PAB
PDB
Boot Flash
2048 x 16 Flash
Data Memory
8192 x 16 Flash
4096 x 16 SRAM
VDDA
3
Digital Reg
Address
Generation
Unit
Program Controller
and
Hardware Looping Unit
VSS
10*
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
DATA BUS [15:0]
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
A[00:05]
6
10
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
16
PS Select
DS Select
WR Enable
RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
56F807 Block Diagram
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
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Part 1 Overview
1.1 56F807 Features
1.1.1
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•
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1.1.2
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Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 60K × 16-bit words of Program Flash
— 2K × 16-bit words of Program RAM
— 8K × 16-bit words of Data Flash
— 4K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3
•
•
•
Peripheral Circuits for 56F807
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
56F807 Technical Data Technical Data, Rev. 15
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Freescale Semiconductor
56F807 Description
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1.1.4
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•
•
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Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with
four pins
CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
Computer-Operating Properly (COP) Watchdog timer
Two dedicated external interrupt pins
14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
External reset input pin for hardware reset
External reset output pin for system reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F807 Description
The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F807 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external
dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each
programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
5
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas. Both
Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.
The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM
outputs) to enhance motor control functionality. Complementary operation permits programmable dead
time insertion, distortion correction via current sensing by software, and separate top and bottom output
polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both
BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance
Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. A patented PWM waveform distortion
correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit
integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to
synchronize the analog-to-digital converters.
The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on
the two-phase inputs, permitting generation of a number proportional to actual position. Speed
computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer
in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is
detected. Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and
14 dedicated GPIO lines are also included on the 56F807.
1.3 State of the Art Development Environment
•
•
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56F807 Technical Data Technical Data, Rev. 15
6
Freescale Semiconductor
Product Documentation
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F807. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices,
Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Table 1-1 56F807 Chip Documentation
Topic
Description
Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
56800EFM
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F801, 56F803, 56F805, and
56F807
DSP56F801-7UM
56F807
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56F807
56F807
Errata
Details any chip issues that might be present
56F807E
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-19, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of
Pins
Detailed
Description
Power (VDD or VDDA)
11
Table 2-2
Ground (VSS or VSSA)
13
Table 2-3
Supply Capacitors & VPP
4
Table 2-4
PLL and Clock
3
Table 2-5
Address Bus1
16
Table 2-6
Data Bus
16
Table 2-7
Bus Control
4
Table 2-8
Interrupt and Program Control
5
Table 2-9
Dedicated General Purpose Input/Output
14
Table 2-10
Pulse Width Modulator (PWM) Ports
26
Table 2-11
Serial Peripheral Interface (SPI) Port1
4
Table 2-12
Quadrature Decoder Ports2
8
Table 2-13
Serial Communications Interface (SCI) Ports1
4
Table 2-15
CAN Port
2
Table 2-16
Analog to Digital Converter (ADC) Ports
20
Table 2-17
Quad Timer Module Ports
6
Table 2-18
JTAG/On-Chip Emulation (OnCE)
6
Table 2-19
Functional Group
1. Alternately, GPIO pins
2. Alternately, Quad Timer pins
56F807 Technical Data Technical Data, Rev. 15
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Freescale Semiconductor
Introduction
Power Port
Ground Port
Power Port
Ground Port
VDD
8
VSS
10*
VDDA
3
VSSA
3
Other
Supply
Ports
VCAPC
PLL
and
Clock
EXTAL
VPP
XTAL
CLKO
A0-A5
External
Address Bus or
GPIO
External
Data Bus
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
D0–D15
PS
DS
External
Bus Control
RD
WR
PHASEA0 (TA0)
Quadrature
Decoder or
Quad Timer A
Quadrature
Decoder1 or
Quad Timer B
PHASEB0 (TA1)
2
GPIOB0–7
6
GPIOD0–5
6
PWMA0-5
3
ISA0-2
4
FAULTA0-3
6
PWMB0-5
3
ISB0-2
4
FAULTB0-3
1
SCLK (GPIOE4)
1
MOSI (GPIOE5)
1
MISO (GPIOE6)
1
SS (GPIOE7)
1
TXD0 (GPIOE0)
1
RXD0 (GPIOE1)
1
TXD1 (GPIOD6)
1
RXD1 (GPIOD7)
8
ANA0-7
2
VREF
8
ANB0-7
1
MSCAN_RX
1
MSCAN_TX
2
TC0-1
4
TD0-3
Dedicated
GPIO
PWMA
Port
2
1
1
56F807
PWMB
Port
1
6
2
8
16
SPI Port
or GPIO
SCI0 Port
or GPIO
1
1
1
SCI1 Port
or GPI0
1
1
1
INDEX0 (TA2)
1
HOME0 (TA3)
1
PHASEA1 (TB0)
1
PHASEB1 (TB1)
1
INDEX1 (TB2)
1
HOME1 (TB3)
1
TCK
1
TMS
1
TDI
1
TDO
1
TRST
DE
JTAG/OnCE™
Port
8
1
IRQA
1
IRQB
1
RESET
1
1
RSTO
1
1
EXTBOOT
ADCA
Port
ADCB
Port
CAN
Quad
Timers
C&D
Interrupt/
Program
Control
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 2-1 56F807 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
9
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins
Signal Name
Signal Description
8
VDD
Power—These pins provide power to the internal structures of the chip, and should
all be attached to VDD.
3
VDDA
Analog Power—These pins is a dedicated power pin for the analog portion of the
chip and should be connected to a low noise 3.3V supply.
Table 2-3 Grounds
No. of Pins
Signal Name
Signal Description
9
VSS
GND—These pins provide grounding for the internal structures of the chip and should
all be attached to VSS.
3
VSSA
Analog Ground—This pin supplies an analog ground.
1
TCS
TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
Table 2-4 Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
2
VCAPC
Supply
Supply
VCAPC—Connect each pin to a 2.2uF or greater bypass capacitor in
order to bypass the core logic voltage regulator (required for proper chip
operation). For more information, please refer to Section 5.2
2
VPP
Input
Input
VPP—This pin should be left unconnected as an open circuit for normal
functionality.
Signal Description
56F807 Technical Data Technical Data, Rev. 15
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Freescale Semiconductor
Clock and Phase Locked Loop Signals
2.3 Clock and Phase Locked Loop Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
EXTAL
Input
Input
1
XTAL
Input/
Output
Chip-driven
Signal Description
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.4.
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to Section 3.4.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.4.2.
1
CLKO
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to XTAL and
a version of the device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
6
A0–A5
Output
Tri-stated
Address Bus—A0–A5 specify the address for external Program or
Data memory accesses.
2
A6–A7
Output
Tri-stated
Address Bus—A6–A7 specify the address for external Program or
Data memory accesses.
GPIOE2GPIOE3
Input/O
utput
Input
Signal Description
Port E GPIO—These two General Purpose I/O (GPIO) pins can
individually be programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
Output
Tri-stated
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
GPIOA0GPIOA7
Input/O
utput
Input
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
11
Table 2-7 Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
16
D0–D15
Input/O
utput
Tri-stated
Signal Description
Data Bus— D0–D15 specify the data for external program or data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pullups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
PS
Output
Tri-stated
Program Memory Select—PS is asserted low for external program
memory access.
1
DS
Output
Tri-stated
Data Memory Select—DS is asserted low for external data memory
access.
1
WR
Output
Tri-stated
Write Enable—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the device
puts data on the bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it qualifies the
A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of
a Static RAM.
1
RD
Output
Tri-stated
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device’s data bus. When RD is deasserted high, the
external data is latched inside the device. When RD is asserted, it qualifies
the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin
of a Static RAM or ROM.
Signal Description
2.5 Interrupt and Program Control Signals
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered.
1
IRQB
Input
(Schmitt)
Input
External Interrupt Request B—The IRQB input is an external
interrupt request that indicates that an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
Signal Description
56F807 Technical Data Technical Data, Rev. 15
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Freescale Semiconductor
GPIO Signals
Table 2-9 Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
RSTO
Output
Output
1
RESET
Input
(Schmitt)
Input
Signal Description
Reset Output—This output reflects the internal reset state of the
chip.
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is
latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed number
of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1
EXTBOOT
Input
(Schmitt)
Input
External Boot—This input is tied to VDD to force device to boot from
off-chip memory. Otherwise, it is tied to VSS.
2.6 GPIO Signals
Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
8
GPIOB0GPIOB7
Input
or
Output
Input
Signal Description
Port B GPIO—These eight pins are dedicated General Purpose I/O
(GPIO) pins that can individually be programmed as input or output
pins.
After reset, the default state is GPIO input.
6
GPIOD0GPIOD5
Input
or
Output
Input
Port D GPIO—These six pins are dedicated GPIO pins that can
individually be programmed as an input or output pins.
After reset, the default state is GPIO input.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
13
2.7 Pulse Width Modulator (PWM) Signals
Table 2-11 Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
6
PWMA0-5
Output
Tri- stated
3
ISA0-2
Input
(Schmitt)
Input
ISA0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
4
FAULTA0-3
Input
(Schmitt)
Input
FAULTA0-3— These Fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions originate
off-chip.
6
PWMB0-5
Output
Tri- stated
3
ISB0-2
Input
(Schmitt)
Input
ISB0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
4
FAULTB0-3
Input
(Schmitt)
Input
FAULTB0-3— These four Fault input pins are used for disabling
selected PWMB outputs in cases where fault conditions originate
off-chip.
Signal Description
PWMA0-5— Six PWMA output pins.
PWMB0-5— Six PWMB output pins.
56F807 Technical Data Technical Data, Rev. 15
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Freescale Semiconductor
Serial Peripheral Interface (SPI) Signals
2.8 Serial Peripheral Interface (SPI) Signals
Table 2-12 Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
MISO
Input/
Output
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
GPIOE6
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
Signal Description
After reset, the default state is MISO.
1
MOSI
Input/
Output
Input
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the
slave device uses to latch the data.
GPIOE5
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
Input/Outp
ut
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
GPIOE4
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SCLK.
1
SS
Input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
GPIOE7
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SS.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
15
2.9 Quadrature Decoder Signals
Table 2-13 Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
PHASEA0
Input
Input
Phase A—Quadrature Decoder #0 PHASEA input
TA0
Input/Output
Input
TA0—Timer A Channel 0
PHASEB0
Input
Input
Phase B—Quadrature Decoder #0 PHASEB input
TA1
Input/Output
Input
TA1—Timer A Channel 1
INDEX0
Input
Input
Index—Quadrature Decoder #0 INDEX input
TA2
Input/Output
Input
TA2—Timer A Channel 2
HOME0
Input
Input
Home—Quadrature Decoder #0 HOME input
TA3
Input/Output
Input
TA3—Timer A Channel 3
PHASEA1
Input
Input
Phase A—Quadrature Decoder #1 PHASEA input
TB0
Input/Output
Input
TB0—Timer B Channel 0
PHASEB1
Input
Input
Phase B—Quadrature Decoder #1 PHASEB input
TB1
Input/Output
Input
TB1—Timer B Channel 1
INDEX1
Input
Input
Index—Quadrature Decoder #1 INDEX input
TB2
Input/Output
Input
TB2—Timer B Channel 2
HOME1
Input
Input
Home—Quadrature Decoder #1 HOME input
TB3
Input/Output
Input
TB3—Timer B Channel 3
1
1
1
1
1
1
1
Signal Description
56F807 Technical Data Technical Data, Rev. 15
16
Freescale Semiconductor
Serial Communications Interface (SCI) Signals
2.10 Serial Communications Interface (SCI) Signals
Table 2-14 Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
MISO
Input/
Output
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
GPIOE6
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
Signal Description
After reset, the default state is MISO.
1
MOSI
Input/
Output
Input
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the
slave device uses to latch the data.
GPIOE5
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
Input/Outp
ut
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
GPIOE4
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SCLK.
1
SS
Input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
GPIOE7
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
After reset, the default state is SS.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
17
Table 2-15 Serial Communications Interface (SCI0 and SCI1) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
TXD0
Output
Input
Transmit Data (TXD0)—transmit data output
GPIOE0
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
Signal Description
After reset, the default state is SCI output.
1
RXD0
Input
Input
Receive Data (RXD0)— receive data input
GPIOE1
Input/Outp
ut
Input
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SCI input.
1
TXD1
Output
Input
Transmit Data (TXD1)—transmit data output
GPIOD6
Input/Outp
ut
Input
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SCI output.
1
RXD1
Input
Input
Receive Data (RXD1)— receive data input
GPIOD7
Input/Outp
ut
Input
Port D GPIO—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
After reset, the default state is SCI input.
2.11 CAN Signals
Table 2-16 CAN Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
MSCAN_ RX
Input
(Schmitt)
Input
1
MSCAN_ TX
Output
Output
Signal Description
MSCAN Receive Data—MSCAN input. This pin has an internal
pull-up resistor.
MSCAN Transmit Data—MSCAN output. CAN output is
open-drain output and pull-up resistor is needed.
56F807 Technical Data Technical Data, Rev. 15
18
Freescale Semiconductor
Analog-to-Digital Converter (ADC) Signals
2.12 Analog-to-Digital Converter (ADC) Signals
Table 2-17 Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
4
ANA0-3
Input
Input
ANA0-3—Analog inputs to ADCA channel 1
4
ANA4-7
Input
Input
ANA4-7—Analog inputs to ADCA channel 2
2
VREF
Input
Input
VREF—Analog reference voltage for ADC. Must be set to
VDDA-0.3V for optimal performance.
4
ANB0-3
Input
Input
ANB0-3—Analog inputs to ADCB, channel 1
4
ANB4-7
Input
Input
ANB4-7—Analog inputs to ADCB, channel 2
Signal Description
2.13 Quad Timer Module Signals
Table 2-18 Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal Type
State During
Reset
2
TC0-1
Input/Output
Input
TC0-1—Timer C Channels 0 and 1
4
TD0-3
Input/Output
Input
TD0-3—Timer D Channels 0, 1, 2, and 3
Signal Description
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
19
2.14 JTAG/OnCE
Table 2-19 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
TCK
Input
(Schmitt)
Input, pulled
low internally
1
TMS
Input
(Schmitt)
Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG
high internally TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
Signal Description
Test Clock Input—This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.
Note:
1
TDI
Input
(Schmitt)
1
TDO
Output
1
TRST
Input
(Schmitt)
Always tie the TMS pin to VDD through a 2.2K resistor.
Input, pulled Test Data Input—This input pin provides a serial input data stream to
high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Tri-stated
Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
Input, pulled Test Reset—As an input, a low signal on this pin provides a reset signal
high internally to the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted at power-up and whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware
device reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
Note: For normal operation, connect TRST directly to VSS. If the design is to
be used in a debugging environment, TRST may be tied to VSS through a 1K
resistor.
1
DE
Output
Output
Debug Event—DE provides a low pulse on recognized debug events.
Part 3 Specifications
3.1 General Characteristics
The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
56F807 Technical Data Technical Data, Rev. 15
20
Freescale Semiconductor
General Characteristics
damage to the device.
The 56F807 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
VSS – 0.3
VSS + 4.0
V
All other input voltages, excluding Analog inputs
VIN
VSS – 0.3
VSS + 5.5V
V
Voltage difference VDD to VDDA
ΔVDD
- 0.3
0.3
V
Voltage difference VSS to VSSA
ΔVSS
- 0.3
0.3
V
Analog inputs, ANA0-7 and VREF
VIN
VSSA– 0.3
VDDA+ 0.3
V
Analog inputs EXTAL and XTAL
VIN
VSSA– 0.3
VSSA+ 3.0
V
I
—
10
mA
Current drain per pin excluding VDD, VSS, PWM
outputs, TCS, VPP, VDDA, VSSA
Table 3-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Supply voltage, digital
VDD
3.0
3.3
3.6
V
Supply Voltage, analog
VDDA
3.0
3.3
3.6
V
Voltage difference VDD to VDDA
ΔVDD
-0.1
-
0.1
V
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
21
Table 3-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Voltage difference VSS to VSSA
ΔVSS
-0.1
-
0.1
V
ADC reference voltage
VREF
2.7
–
VDDA
V
TA
–40
–
85
°C
Ambient operating temperature
Table 3-3 Thermal Characteristics6
Value
Characteristic
Comments
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)
Symbol
Unit
Notes
63.4
°C/W
2
35.4
60.3
°C/W
2
160-pin
LQFP
160
MBGA
RθJA
38.5
RθJMA
Junction to ambient
Natural convection
Four layer
board (2s2p)
RθJMA
(2s2p)
33
49.9
°C/W
1,2
Junction to ambient (@1m/sec)
Four layer
board (2s2p)
RθJMA
31.5
46.8
°C/W
1,2
Junction to case
RθJC
8.6
8.1
°C/W
3
Junction to center of case
ΨJT
0.8
0.6
°C/W
4, 5
I/O pin power dissipation
P I/O
User Determined
W
Power dissipation
PD
P D = (IDD x VDD + P I/O)
W
PDMAX
(TJ - TA) /RθJA
W
Junction to center of case
7
Notes:
1.
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2.
Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where “s” is the number of signal layers and “p” is the
number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with
the non-single layer boards is Theta-JMA.
3.
Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
56F807 Technical Data Technical Data, Rev. 15
22
Freescale Semiconductor
DC Electrical Characteristics
4.
Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6.
See Section 5.1 from more details on thermal design considerations.
7.
TJ = Junction Temperature
TA = Ambient Temperature
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
VIHC
2.25
—
2.75
V
Input low voltage (XTAL/EXTAL)
VILC
0
—
0.5
V
Input high voltage (Schmitt trigger inputs)1
VIHS
2.2
—
5.5
V
Input low voltage (Schmitt trigger inputs)1
VILS
-0.3
—
0.8
V
Input high voltage (all other digital inputs)
VIH
2.0
—
5.5
V
Input low voltage (all other digital inputs)
VIL
-0.3
—
0.8
V
Input current high (pullup/pulldown resistors disabled, VIN=VDD)
IIH
-1
—
1
μA
Input current low (pullup/pulldown resistors disabled, VIN=VSS)
IIL
-1
—
1
μA
Input current high (with pullup resistor, VIN=VDD)
IIHPU
-1
—
1
μA
Input current low (with pullup resistor, VIN=VSS)
IILPU
-210
—
-50
μA
Input current high (with pulldown resistor, VIN=VDD)
IIHPD
20
—
180
μA
Input current low (with pulldown resistor, VIN=VSS)
IILPD
-1
—
1
μA
Nominal pullup or pulldown resistor value
RPU, RPD
30
KΩ
Output tri-state current low
IOZL
-10
—
10
μA
Output tri-state current high
IOZH
-10
—
10
μA
Input current high (analog inputs, VIN=VDDA)2
IIHA
-15
—
15
μA
Input current low (analog inputs, VIN=VSSA)3
IILA
-15
—
15
μA
Output High Voltage (at IOH)
VOH
VDD – 0.7
—
—
V
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
23
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Output Low Voltage (at IOL)
VOL
—
—
0.4
V
Output source current
IOH
4
—
—
mA
Output source current
IOL
4
—
—
mA
PWM pin output source current3
IOHP
10
—
—
mA
PWM pin output sink current4
IOLP
16
—
—
mA
Input capacitance
CIN
—
8
—
pF
Output capacitance
COUT
—
12
—
pF
VDD supply current
IDDT5
Run 6
—
195
220
mA
Wait7
—
170
200
mA
Stop
—
115
145
mA
Low Voltage Interrupt, external power supply8
VEIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply9
VEIC
2.0
2.2
2.4
V
Power on Reset10
VPOR
—
1.7
2.0
V
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3, TCK, TRST, TMS,
TDI, and MSCAN_RX
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via
separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless
the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,
this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally
regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.
56F807 Technical Data Technical Data, Rev. 15
24
Freescale Semiconductor
AC Electrical Characteristics
250
IDD Analog
IDD Digital
IDD Total
200
IDD (mA)
150
100
50
0
10
20
30
40
60
50
70
80
Freq. (MHz)
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
VIH
Input Signal
Low
High
90%
50%
10%
Midpoint1
Fall Time
VIL
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
25
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 3-3 Signal States
Table 3-5 Flash Memory Truth Table
Mode
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
1. X address enable, all rows are disabled when XE=0
2. Y address enable, YMUX is disabled when YE=0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE=0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode
IFREN=1
IFREN=0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both block
Erase main memory block
56F807 Technical Data Technical Data, Rev. 15
26
Freescale Semiconductor
AC Electrical Characteristics
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Figure
Program time
Tprog*
20
–
–
us
Figure 3-4
Erase time
Terase*
20
–
–
ms
Figure 3-5
Mass erase time
Tme*
100
–
–
ms
Figure 3-6
Endurance1
ECYC
10,000
20,000
–
cycles
Data Retention1
DRET
10
30
–
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
Tnvs*
–
5
–
us
Figure 3-4,
Figure 3-5,
Figure 3-6
NVSTR hold time
Tnvh*
–
5
–
us
Figure 3-4,
Figure 3-5
NVSTR hold time (mass erase)
Tnvh1*
–
100
–
us
Figure 3-6
NVSTR to program set up time
Tpgs*
–
10
–
us
Figure 3-4
Recovery time
Trcv*
–
1
–
us
Figure 3-4,
Figure 3-5,
Figure 3-6
Cumulative program
HV period2
Thv
–
3
–
ms
Figure 3-4
Program hold time3
Tpgh
–
–
–
Figure 3-4
Address/data set up time3
Tads
–
–
–
Figure 3-4
Address/data hold time3
Tadh
–
–
–
Figure 3-4
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
27
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
Tnvs
Tprog
Tpgh
NVSTR
Tpgs
Tnvh
Trcv
Thv
Figure 3-4 Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
Tnvs
NVSTR
Tnvh
Terase
Trcv
Figure 3-5 Flash Erase Cycle
56F807 Technical Data Technical Data, Rev. 15
28
Freescale Semiconductor
External Clock Operation
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
Tnvs
NVSTR
Tnvh1
Tme
Trcv
Figure 3-6 Flash Mass Erase Cycle
3.4 External Clock Operation
The 56F807 system clock can be derived from an external crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pins.
3.4.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, since
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL
and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-8 no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
29
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
CL1 * CL2
CL =
CL1 + CL2
12 * 12
+ Cs =
+ 3 = 6 + 3 = 9pF
12 + 12
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
EXTAL XTAL
Rz
Recommended External Crystal
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
fc
Figure 3-7 Connecting to a Crystal Oscillator
3.4.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is
shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-7 no external load capacitors should be used.
EXTAL XTAL
Rz
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
fc
Figure 3-8 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
56F807 Technical Data Technical Data, Rev. 15
30
Freescale Semiconductor
External Clock Operation
3.4.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-9. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
56F807
XTAL
EXTAL
External
Clock
VSS
Figure 3-9 Connecting an External Clock Signal
Table 3-8 External Clock Operation Timing Requirements5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
fosc
0
—
80
MHz
Clock Pulse Width2, 3
tPW
6.25
—
—
ns
1. See Figure 3-9 for details on using the recommended connection of an external clock driver.
2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
3. Parameters listed are guaranteed by design.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
tPW
tPW
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-10 External Clock Timing
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
31
3.4.4
Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
fosc
4
8
10
MHz
fout/2
40
—
110
MHz
PLL stabilization time3 0o to +85oC
tplls
—
1
10
ms
PLL stabilization time3 -40o to 0oC
tplls
—
100
200
ms
External reference crystal frequency for the PLL1
PLL output frequency2
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.2.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
56F807 Technical Data Technical Data, Rev. 15
32
Freescale Semiconductor
External Bus Asynchronous Timing
3.5 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing1,2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Symbol
Min
Max
Unit
Address Valid to WR Asserted
tAWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS)+7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
tWRD
—
T + 4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
—
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS)+6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
tRDA
0
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
Input Data Hold to RD Deasserted
tDRD
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
Characteristic
—
18.7
(T*WS) + 18.7
Address Valid to RD Asserted
tARDA
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
ns
ns
0
—
ns
19
(T*WS)+19
—
—
ns
ns
—
—
1
(T*WS)+1
ns
ns
-4.4
—
ns
—
—
2.4
(T*WS) + 2.4
ns
ns
WR Deasserted to RD Asserted
tWRRD
6.8
—
ns
RD Deasserted to RD Asserted
tRDRD
0
—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
—
ns
RD Deasserted to WR Asserted
tRDWR
12.8
—
ns
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
33
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
tARDD
tRDA
tARDA
RD
tRDRD
tRD
tAWR
tWRWR
tWR
tWRRD
tRDWR
WR
tWRD
tDRD
tDOS
D0–D15
tRDD
tAD
tDOH
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 3-11 External Bus Asynchronous Timing
56F807 Technical Data Technical Data, Rev. 15
34
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
21
ns
3-12
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET Deassertion to First External Address Output
tRDA
33T
34T
ns
3-12
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
3-13
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
15T
—
ns
3-14
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
16T
—
ns
3-14
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
—
ns
3-15
IRQA Width Assertion to Recover from Stop State4
tIW
2T
—
ns
3-16
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
3-12
3-16
—
—
275,000T
12T
ns
ns
3-17
tIRQ
—
—
275,000T
12T
ns
ns
3-17
tII
—
—
275,000T
12T
ns
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
35
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
PS, DS,
RD, WR
First Fetch
Figure 3-12 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 3-14 External Level-Sensitive Interrupt Timing
56F807 Technical Data Technical Data, Rev. 15
36
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 3-15 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
RSTO
tRSTO
Figure 3-18 Reset Output Timing
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
37
3.7 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Cycle time
Master
Slave
Min
Max
Unit
50
25
—
—
ns
ns
—
25
—
—
ns
ns
—
100
—
—
ns
ns
17.6
12.5
—
—
ns
ns
24.1
25
—
—
ns
ns
20
0
—
—
ns
ns
0
2
—
—
ns
ns
tC
Enable lead time
Master
Slave
tELD
Enable lag time
Master
Slave
tELG
Clock (SCK) high time
Master
Slave
tCH
Clock (SCK) low time
Master
Slave
tCL
Data set-up time required for inputs
Master
Slave
tDS
Data hold time required for inputs
Master
Slave
tDH
Access time (time to data active from
high-impedance state)
Slave
tA
Disable time (hold time to high-impedance state)
Slave
tD
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Data invalid
Master
Slave
tDI
Rise time
Master
Slave
tR
Fall time
Master
Slave
tF
See Figure
3-19-3-22
3-22
3-22
3-19, 3-20, 3-21,
3-22
3-22
3-19, 3-20, 3-21,
3-22
3-19, 3-20, 3-21,
3-22
3-22
4.8
15
ns
3.7
15.2
ns
—
—
4.5
20.4
ns
ns
0
0
—
—
ns
ns
—
—
11.5
10.0
ns
ns
—
—
9.7
9.0
ns
ns
3-22
3-19, 3-20, 3-21,
3-22
3-19, 3-20, 3-21,
3-22
3-19, 3-20, 3-21,
3-22
3-19, 3-20, 3-21,
3-22
1. Parameters listed are guaranteed by design.
56F807 Technical Data Technical Data, Rev. 15
38
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
SS is held High on master
(Input)
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
tDI
MOSI
(Output)
LSB in
tDV
Master MSB out
Bits 14–1
tDI(ref)
Master LSB out
tR
tF
Figure 3-19 SPI Master Timing (CPHA = 0)
SS
SS is held High on master
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
MISO
(Input)
MSB in
tDV(ref)
MOSI
(Output)
tDI
Master MSB out
tDH
Bits 14–1
tDV
Bits 14– 1
tF
LSB in
tDI(ref)
Master LSB out
tR
Figure 3-20 SPI Master Timing (CPHA = 1)
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
39
SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tDS
tF
tR
tD
Bits 14–1
Slave LSB out
tDV
tDI
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 3-21 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
MOSI
(Input)
tD
tF
tDH
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 3-22 SPI Slave Timing (CPHA = 1)
56F807 Technical Data Technical Data, Rev. 15
40
Freescale Semiconductor
Quad Timer Timing
3.8 Quad Timer Timing
Table 3-13 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
PIN
4T + 6
—
ns
Timer input high/low period
PINHL
2T + 3
—
ns
Timer output period
POUT
2T
—
ns
POUTHL
1T
—
ns
Timer input period
Timer output high/low period
1.
In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
Timer Outputs
Figure 3-23 Timer Timing
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
41
3.9 Quadrature Decoder Timing
Table 3-14 Quadrature Decoder Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
Quadrature input period
PIN
8T + 12
—
ns
Quadrature input high/low period
PHL
4T + 6
—
ns
Quadrature phase period
PPH
2T + 3
—
ns
1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. VSS = 0V, VDD = 3.0–3.6V,
TA = –40° to +85°C, CL ≤ 50pF.
2. Parameters listed are guaranteed by design.
PPH
PPH
PPH
PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 3-24 Quadrature Decoder Timing
56F807 Technical Data Technical Data, Rev. 15
42
Freescale Semiconductor
Serial Communication Interface (SCI) Timing
3.10 Serial Communication Interface (SCI) Timing
Table 3-15 SCI Timing4
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
BR
—
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 3-25 RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 3-26 TXD Pulse Width
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
43
3.11 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal performance),
ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
VADCIN
01
—
VREF2
V
Resolution
RES
12
—
12
Bits
Integral Non-Linearity3
INL
—
+/- 2.5
+/- 4
LSB4
Differential Non-Linearity
DNL
—
+/- 0.9
+/- 1
LSB4
ADC input voltages
Monotonicity
GUARANTEED
ADC internal clock5
fADIC
0.5
—
5
MHz
Conversion range
RAD
VSSA
—
VDDA
V
Conversion time
tADC
—
6
—
tAIC cycles6
Sample time
tADS
—
1
—
tAIC cycles6
Input capacitance
CADI
—
5
—
pF6
Gain Error (transfer gain)5
EGAIN
0.93
1.00
1.08
—
Total Harmonic Distortion5
THD
60
64
—
VOFFSET
-90
-25
+10
mV
Signal-to-Noise plus Distortion5
SINAD
55
60
—
—
Effective Number of Bits5
ENOB
9
10
—
bit
Spurious Free Dynamic Range5
SFDR
65
70
—
dB
Bandwidth
BW
—
100
—
KHz
ADC Quiescent Current (each dual ADC)
IADC
—
50
—
mA
VREF Quiescent Current (each dual ADC)
IVREF
—
12
16.5
mA
Offset Voltage5
1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital
output code of 0.
2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to
VDDA-0.3V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC
56F807 Technical Data Technical Data, Rev. 15
44
Freescale Semiconductor
Controller Area Network (CAN) Timing
.
ADC analog input
3
1
2
4
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)
Figure 3-27 Equivalent Analog Input Circuit
3.12 Controller Area Network (CAN) Timing
Table 3-17 CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL < 50pF, MSCAN Clock = 30MHz
Characteristic
Baud Rate
Bus Wakeup detection 1
Symbol
Min
Max
Unit
BRCAN
—
1
Mbps
T WAKEUP
5
—
μs
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection
takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact
that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2. Parameters listed are guaranteed by design
MSCAN_RX
CAN receive
data pin
(Input)
T WAKEUP
Figure 3-28 Bus Wakeup Detection
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
45
3.13 JTAG Timing
Table 3-18 JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
fOP
DC
10
MHz
TCK cycle time
tCY
100
—
ns
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data set-up time
tDS
0.4
—
ns
TMS, TDI data hold time
tDH
1.2
—
ns
TCK low to TDO data valid
tDV
—
26.6
ns
TCK low to TDO tri-state
tTS
—
23.5
ns
tTRST
50
—
ns
tDE
4T
—
ns
TCK frequency of
operation2
TRST assertion time
DE assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation,
T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VM
VM
VIH
TCK
(Input)
VM = VIL + (VIH – VIL)/2
VIL
Figure 3-29 Test Clock Input Timing Diagram
56F807 Technical Data Technical Data, Rev. 15
46
Freescale Semiconductor
JTAG Timing
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 3-30 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-31 TRST Timing Diagram
DE
tDE
Figure 3-32 OnCE—Debug Event
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
47
Part 4 Packaging
4.1 Package and Pin-Out Information 56F807
DE
VSS
ISA2
ISA1
ISA0
TCK
TCS
TRST
TC1
TC0
TD3
TD2
TD1
TD0
VCAPC2
TDO
TDI
TMS
SCLK
SS
MSCAN_RX
VSS
VDD
MSCAN_TX
INDEX0
PHB0
PHA0
MOSI0
MISO0
HOME0
PHB1
PHA1
INDEX1
VDD
VPP
HOME1
CLKO
VSS
RXD0
TXD0
This section contains package and pin-out information for the 56F807. This device comes in two case
types: low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA).
Figure 4-1 shows the package outline for the LQFP case, Figure 4-2 shows the mechanical parameters
for the LQFP case, and Table 4-1 lists the pinout for the LQFP case. Figure 4-3 shows the mechanical
parameters for the MAPBGA case, and Table 4-2 lists the pinout for the MAPBGA package.
Orientation Mark
A0
A1
A2
A3
A4
ANB7
121
Pin 1
ANB6
ANB5
ANB4
ANB3
A5
A6
A7
VDD
A8
A9
ANB2
ANB1
ANB0
A10
A11
A12
A13
A14
ANA7
ANA6
ANA5
ANA4
ANA3
A15
VSS
PS
DS
WR
RD
D0
D1
D2
D3
D4
ANA2
ANA1
ANA0
VSSA
VDDA
VREF
RESET
RSTO
VDD
VSS
VDD
D5
D6
D7
D8
D9
D10
VDD
D11
D12
EXTAL
XTAL
VSS
VSS
VDD
VDDA
VSSA
EXTBOOT
FAULTA3
VSSA
VDDA
VREF2
D13
FAULTA2
81
41
PWMA3
PWMA4
PWMA2
VPP2
IRQA
IRQB
FAULTB0
FAULTB1
FAULTB2
FAULTB3
PWMA0
VSS
PWMB0
PWMB1
PWMB2
PWMB3
PWMB4
PWMB5
VDD
ISB0
VCAPC1
ISB1
ISB2
GPIOD3
GPIOD4
GPIOD5
TXD1
RXD1
GPIOB6
GPIOB7
VSS
GPIOD0
GPIOD1
GPIOD2
GPIOB1
FAULTA1
FAULTA0
PWMA5
GPIOB2
GPIOB3
GPIOB4
GPIOB5
D15
GPIOB0
PWMA1
D14
Figure 4-1 Top View, 56F807 160-pin LQFP Package
56F807 Technical Data Technical Data, Rev. 15
48
Freescale Semiconductor
Package and Pin-Out Information 56F807
160X
0.20 C A-B D
D
D
2
b
GG
c1
D
c
6
SECTION G-G
E
2
E1
2
E
E1
B
A
(b)
D1
2
D1
4X
0.20 H A-B D
DETAIL F
0.08 C
e
e/2
156X
C
4X
SEATING
PLANE
160X
e
0.08
M
C A-B D
θ1
R1
R2
A2
A
θ2
θ3
A1
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED
WHERE THE LEADS EXIT THE PLASTIC BODY
AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25mm PER SIDE.
DIMENSIONS D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS
INCLUDING MOLD MISMATCH.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b
DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN A PROTRUSION AND AN
ADJACENT LEAD IS 0.07mm.
6. EXACT SHAPE OF CORNERS MAY VARY.
H
θ
S
L
(L1)
0.25
GAGE
PLANE
DETAIL F
MILLIMETERS
DIM MIN MAX
A
--1.60
A1
0.05
0.15
A2
1.35
1.45
b
0.17
0.27
b1
0.17
0.23
c
0.09
0.20
c1
0.09
0.16
D
26.00 BSC
D1
24.00 BSC
e
0.50 BSC
E
26.00 BSC
E1
24.00 BSC
L
0.45
0.75
L1
1.00 REF
R1
0.08
--R2
0.08
0.20
S
0.20
--θ
0°
7°
θ1
0°
--θ2
11 °
13 °
θ3
11 °
13 °
CASE 1259-01
ISSUE O
Figure 4-2 160-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
49
Table 4-1 56F807 LQFP Package Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
A0
41
GPIOB1
81
PWMA5
121
DE
2
A1
42
GPIOB2
82
FAULTA0
122
VSS
3
A2
43
GPIOB3
83
FAULTA1
123
ISA0
4
A3
44
GPIOB4
84
FAULTA2
124
ISA1
5
A4
45
GPIOB5
85
FAULTA3
125
ISA2
6
A5
46
GPIOB6
86
EXTBOOT
126
TD0
7
A6
47
GPIOB7
87
VSSA
127
TD1
8
A7
48
VSS
88
VDDA
128
TD2
9
VDD
49
GPIOD0
89
VDD
129
TD3
10
A8
50
GPIOD1
90
VSS
130
TC0
11
A9
51
GPIOD2
91
VSS
131
TC1
12
A10
52
GPIOD3
92
XTAL
132
TRST
13
A11
53
GPIOD4
93
EXTAL
133
TCS
14
A12
54
GPIOD5
94
VDD
134
TCK
15
A13
55
TXD1
95
VSS
135
TMS
16
A14
56
RXD1
96
VDD
136
TDI
17
A15
57
PWMB0
97
RSTO
137
TDO
18
VSS
58
PWMB1
98
RESET
138
VCAPC2
19
PS
59
PWMB2
99
VREF
139
MSCAN_TX
20
DS
60
PWMB3
100
VDDA
140
VDD
21
WR
61
PWMB4
101
VSSA
141
VSS
22
RD
62
PWMB5
102
ANA0
142
MSCAN_RX
23
D0
63
VDD
103
ANA1
143
SS
24
D1
64
ISB0
104
ANA2
144
SCLK
25
D2
65
VCAPC1
105
ANA3
145
MISO
26
D3
66
ISB1
106
ANA4
146
MOSI
27
D4
67
ISB2
107
ANA5
147
PHA0
28
D5
68
VPP2
108
ANA6
148
PHB0
29
D6
69
IRQA
109
ANA7
149
INDEX0
30
D7
70
IRQB
110
VREF2
150
HOME0
56F807 Technical Data Technical Data, Rev. 15
50
Freescale Semiconductor
Package and Pin-Out Information 56F807
Table 4-1 56F807 LQFP Package Pin Identification by Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
31
D8
71
FAULTB0
111
VDDA
151
PHA1
32
D9
72
FAULTB1
112
VSSA
152
PHB1
33
D10
73
FAULTB2
113
ANB0
153
VDD
34
VDD
74
FAULTB3
114
ANB1
154
INDEX1
35
D11
75
PWMA0
115
ANB2
155
HOME1
36
D12
76
VSS
116
ANB3
156
VPP
37
D13
77
PWMA1
117
ANB4
157
VSS
38
D14
78
PWMA2
118
ANB5
158
CLKO
39
D15
79
PWMA3
119
ANB6
159
TXD0
40
GPIOB0
80
PWMA4
120
ANB7
160
RXD0
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
51
D
X
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
Y
M
K
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
E
MILLIMETERS
DIM MIN MAX
A
1.32
1.75
A1
0.27
0.47
A2
1.18 REF
b
0.35
0.65
D
15.00 BSC
E
15.00 BSC
e
1.00 BSC
S
0.50 BSC
0.20
13X
e
S
14 13 12 11 10
9
6
5
4
3
2
METALIZED MARK FOR
PIN 1 IDENTIFICATION
IN THIS AREA
1
A
B
C
13X
5
D
S
E
e
F
A
0.30 Z
A2
G
H
J
A1
K
L
M
160X
Z
0.15 Z
4
DETAIL K
ROTATED 90 ° CLOCKWISE
N
P
3
160X
b
0.30 Z X Y
VIEW M-M
0.10 Z
CASE 1268-01
ISSUE O
Figure 4-3 160 MAPBGA Mechanical Information
Please see www.freescale.com for the most current case outline.
56F807 Technical Data Technical Data, Rev. 15
52
Freescale Semiconductor
Package and Pin-Out Information 56F807
Table 4-2 160 MAPBGA Package Pin Identification by Pin Number
Solder
Ball
Signal Name
Solder
Ball
Signal Name
Solder
Ball
Signal Name
Solder
Ball
Signal Name
C3
A0
N4
GPIOB5
K12
VSSA
E10
TC1
B2
A1
P4
GPIOB6
K13
VDDA
D9
TRST
D3
A2
M4
GPIOB7
L14
VDD
B9
TCS
C2
A3
L5
VSS
K11
VSS
E9
TCK
B1
A4
N5
GPIOD0
K14
VSS
A9
TMS
D2
A5
P5
GPIOD1
J13
XTAL
D8
TDI
C1
A6
K5
GPIOD2
J12
EXTAL
B8
TDO
D1
A7
N6
GPIOD3
J14
VDD
A8
VCAPC2
E3
VDD
L6
GPIOD4
J11
VSS
E8
MSCAN_TX
E2
A8
K6
GPIOD5
H13
VDD
D7
VDD
E1
A9
P6
TXD1
H12
RSTO
E7
VSS
F3
A10
N7
RXD1
H14
RESET
D6
MSCAN_RX
F2
A11
L7
PWMB0
H11
VREF
H1
D1
F1
A12
P7
PWMB1
G12
VDDA
H2
D2
G3
A13
K7
PWMB2
G11
VSSA
J3
D3
G2
A14
L8
PWMB3
G14
ANA0
J1
D4
G1
A15
K8
PWMB4
B13
DE
J2
D5
F4
VSS
P8
PWMB5
A14
VSS
K3
D6
G4
PS
L9
VDD
B12
ISA0
K1
D7
H4
DS
N8
ISB0
A13
ISA1
L1
D8
J4
WR
P14
PWMA5
A12
ISA2
K2
D9
K4
RD
M13
FAULTA0
B11
TD0
L3
D10
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
53
Table 4-2 160 MAPBGA Package Pin Identification by Pin Number (Continued)
Solder
Ball
Signal Name
Solder
Ball
Signal Name
Solder
Ball
Signal Name
Solder
Ball
Signal Name
P1
GPIOB1
L12
FAULTA1
A11
TD1
M1
VDD
N3
GPIOB2
N14
FAULTA2
D10
TD2
L2
D11
P2
GPIOB3
L13
FAULTA3
B10
TD3
N1
D12
P3
GPIOB4
M14
EXTBOOT
A10
TC0
M2
D13
N2
D14
N11
VSS
D14
VSSA
D5
PHB0
M3
D15
P13
PWMA1
D11
ANA8
B6
INDEX0
L4
GPIOB0
N12
PWMA2
D12
ANA9
A5
HOME0
K10
VCAPC1
N13
PWMA3
D13
ANA10
E4
PHA1
K9
ISB1
M12
PWMA4
C14
ANA11
B5
PHB1
P9
ISB2
F11
ANA1
C13
ANA12
A4
VDD
L10
VPP2
G13
ANA2
C11
ANA13
D4
INDEX1
N9
IRQA
F12
ANA3
B14
ANA14
C4
HOME1
P10
IRQB
F14
ANA4
C12
ANA15
B4
VPP
P11
FAULTB0
E11
ANA5
A7
SS
A2
CLKO
N10
FAULTB1
F13
ANA6
E5
SCLK
B3
TXD0
L11
FAULTB2
E12
ANA7
B7
MISO
A1
RXD0
M11
FAULTB3
E14
VREF2
A6
MOSI
A3
VSS
P12
PWMA0
E13
VDDA
E6
PHA0
H3
D0
56F807 Technical Data Technical Data, Rev. 15
54
Freescale Semiconductor
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
T J = T A + ( P D × R θJA )
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
R θJA = R θJC + R θCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
55
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS pin.
•
The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
performance tolerances.
56F807 Technical Data Technical Data, Rev. 15
56
Freescale Semiconductor
Electrical Design Considerations
•
•
•
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins
are less than 0.5 inch per capacitor lead.
Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
•
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
•
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
57
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 6-1 56F807 Ordering Information
Pin
Count
Ambient
Frequency
(MHz)
Order Number
Low-Profile Quad Flat Pack (LQFP)
160
80
DSP56F807PY80
3.0–3.6 V
Mold Array Process Ball Grid Array
(MAPBGA)
160
80
DSP56F807VF80
56F807
3.0–3.6 V
Low-Profile Quad Flat Pack (LQFP)
160
80
DSP56F807PY80E*
56F807
3.0–3.6 V
Mold Array Process Ball Grid Array
(MAPBGA)
160
80
DSP56F807VF80E*
Part
Supply
Voltage
56F807
3.0–3.6 V
56F807
Package Type
*This package is RoHS compliant.
56F807 Technical Data Technical Data, Rev. 15
58
Freescale Semiconductor
Electrical Design Considerations
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
59
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F807
Rev. 15
01/2007