FREESCALE HCS12H

Freescale Semiconductor
Product Brief
S12HFAMPP
Rev. 11.1, 17-Aug-2004
16-bit Microcontroller HCS12H
Family
Introduction
Designed for automotive instrumentation applications, all members of the MCS12H-Family of
microcontroller units (MCU) are composed of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, up to 4K
bytes of EEPROM on Flash parts, one or two asynchronous serial communications interfaces (SCI), a
serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel,
10-bit analog-to-digital converter (ADC), up to six-channel pulse width modulator (PWM), and up to two
CAN 2.0 A, B software compatible modules. In addition, they feature a 32x4 liquid crystal display (LCD)
controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited
to drive up to six stepper motors, and on selected devices, up to four stepper stall detectors (SSD) to
simulataneously calibrate the pointer reset position of each motor. The MCS12H-Family has full 16-bit
data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 14
I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
PRELIMINARY
Feature Detail
Feature Detail
NOTE
Not all features listed here are available in all configurations. For a quick
overview refer to Table 1.
•
HCS12 Core
– HCS12 16-bit CPU
• Upward compatible with M68HC11 instruction set
• Interrupt stacking and programmer’s model identical to M68HC11
• Instruction queue
• Enhanced indexed addressing
–
–
–
–
–
HCS12 MEBI (Multiplexed Expanded Bus Interface)
HCS12 MMC (Module Mapping Control)
HCS12 INT (Interrupt Control)
HCS12 BKP (On-chip Breakpoints)
HCS12 BDM (Single-wire Background Debug™ Mode)
•
Memory options
– 32K, 64K, 128K, 256K byte Flash EEPROM or 64K, 128K, 192K and 256K byte ROM
– 2K, 4K, 6K, 8K, 12K byte RAM
– 2K, 4K byte EEPROM on Flash versions only
•
8-bit and 4-bit ports with Interrupt capability
– Digital filtering
– Programmable rising or falling edge trigger
•
Clock Reset Generator (CRG)
– Low current Colpitts or Pierce oscillator (0.5 to 16Mhz reference clock)
– Phase-locked loop clock frequency multiplier
– Windowed COP watchdog and Clock Monitor resets
– Real Time Interrupt
•
Up to 16-channels Analog-to-Digital Converter (ADC)
– 10-bit resolution
– External conversion trigger capability
•
Up to two 1M bit per second, CAN 2.0 A, B software compatible modules (MSCAN12)
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
•
Timer (TIM)
– 16-bit main counter with 7-bit prescaler
– Eight programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
•
Up to six Pulse Width Modulator (PWM) channels
16-bit Microcontroller HCS12H Family, Rev. 11.1
2
Freescale Semiconductor
PRELIMINARY
Feature Detail
–
–
–
–
–
Programmable period and duty cycle for each channel
Pairs of 8-bit channels can be concatenated as one 16-bit channel
Center-aligned or left-aligned outputs
Wide range of programmable clock frequencies
Fast emergency shutdown input
•
Serial interfaces
– Up to two asynchronous Serial Communications Interfaces (SCI)
– Synchronous Serial Peripheral Interface (SPI)
– Inter-IC Bus Interface (IIC)
•
Liquid Crystal Display (LCD) driver
– Up to 32 frontplanes and 4 backplanes
– 5 modes of operation allow for different display sizes to meet application requirements
– Programmable frame clock generator and bias voltage level
•
16 or 24 high current drivers suited for PWM motor control
– Each PWM channel switchable between two drivers in an H-bridge configuration
– Support for sine and cosine drive
– 11-bit resolution with selectable dithering function
– Left, right or center aligned outputs
– Slew rate control
•
Up to four Stepper Stall Detectors (SSD) - available on selected devices
– Flexible full step and polarity set up to return the pointer to its reset position in clockwise or
counter clockwise direction.
– Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of
unpowered coil during full step (only one of the two motor coils is powered) operation.
– 16-Bit Down Counter to monitor blanking and integration time to support stepper motors with
different gear ratios.
– 16-Bit accumulator register to read integration value, compare to a threshold at the end of
integration time, and decide if the motor is stalled under this value or moving above this value.
•
Operating Frequency
– 32Mhz equivalent to 16Mhz Bus Speed (Only 9S12H256)
– 50Mhz equivalent to 25Mhz Bus Speed (Except 9S12H256)
•
80-Pin, 112-Pin or 144-Pin QFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
3
PRELIMINARY
Feature Detail
Table 1 List of MCS12H-Family members
Flash ROM RAM EEPROM
Device
Package
CAN SCI SPI IIC A/D PWM TIM LCD Motor SSD KWU I/O
256K
0
12K
4K
9S12H256
144 LQFP
2
2
1
1
16
6
8
32x4
24/6
0
12
117
256K
0
12K
4K
9S12H256(1)
112 LQFP
2
1
1
0
8
2
8
28x4
24/6
0
0
85
128K
0
6K
2K
9S12H128(1) 112 LQFP
2
1
1
0
8
2
8
28x4
24/6
0
0
85
256K
0
12K
2K
9S12HZ256
112 LQFP
2
2
1
1
16
6
8
32x4
16/4
4
8
85
128K
0
6K
2K
9S12HZ128
112 LQFP
2
2
1
1
16
6
8
32x4
16/4
4
8
85
64K
0
4K
1K
9S12HZ64
112 LQFP
1
1
1
0
8
4
8
24x4
16/4
2
8
69
64K
0
4K
1K
9S12HN64
112 LQFP
0
1
1
0
8
4
8
24x4
16/4
2
8
69
64K
0
4K
1K
9S12HZ64
80 QFP
1
1
0
0
7
4
4
20x4
16/4
2
7
60
64K
0
4K
1K
9S12HN64
80 QFP
0
1
0
0
7
4
4
20x4
16/4
2
7
60
0
256K
12K
0
3S12HZ256
112 LQFP
2
2
1
1
16
6
8
32x4
16/4
4
8
85
0
192K
8K
0
3S12HZ192
112 LQFP
2
2
1
1
16
6
8
32x4
16/4
4
8
85
0
128K
6K
0
3S12HZ128
112 LQFP
1
2
1
1
8
6
8
32x4
16/4
4
8
85
0
128K
6K
0
3S12HN128
112 LQFP
0
2
1
1
8
6
8
32x4
16/4
4
8
85
0
64K
4K
0
3S12HZ64
112 LQFP
1
1
1
0
8
4
8
24x4
16/4
2
8
69
0
64K
4K
0
3S12HN64
112 LQFP
0
1
1
0
8
4
8
24x4
16/4
2
8
69
0
32K
2K
0
3S12HZ32
80 QFP
1
1
0
0
7
4
4
20x4
16/4
2
7
60
0
32K
2K
0
3S12HN32
80 QFP
0
1
0
0
7
4
4
20x4
16/4
2
7
60
NOTES:
1. Not recommended for new designs.
•
Flash emulation of ROM versions
– ROM versions 3S12HZ256, 3S12HZ192, 3S12HZ128 and 3S12HN128 should use the
9S12HZ256 for Flash emulation.
– ROM versions 3S12HZ64, 3S12HN64, 3S12HZ32 and 3S12HN32 should use the 9S12HZ64
for Flash emulation.
•
Pin out explanations:
– A/D is the number of A/D channels.
– PWM is the number of TIM channels.
– LCD denotes the number of front planes times the number of back planes.
– Motor denotes the number of high current drive pins / number of stepper motors which can be
driven
– SSD denotes whether this device features a Stepper Stall Detection Circuit
– Versions with one SCI will use SCI0
– Versions with one CAN will use CAN0
– I/O is the sum of ports capable to act as digital input or output.
144 Pin Package:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 5, L = 8, M = 6, P = 6, S = 8, T = 8, U
= 8, V = 8, W = 8, PAD = 16 input only.
14 inputs provide Interrupt capability (H = 8, J = 4, IRQ, XIRQ).
112 Pin Package for H Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 4, M = 4, P = 2, S = 6, T = 8, U = 8, V = 8, W
= 8, PAD = 8 input only.
16-bit Microcontroller HCS12H Family, Rev. 11.1
4
Freescale Semiconductor
PRELIMINARY
Feature Detail
2 inputs provide Interrupt capability (IRQ, XIRQ).
112 Pin Package for 9HZ256, 9HZ128, 3HZ128 and 3HN128 Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 8, M = 5, P = 6, S = 6, T = 8, U = 8, V = 8,
PAD = 8.
10 inputs provide Interrupt capability (AD = 8, IRQ, XIRQ).
112 Pin Package for 9HZ64, 9HN64, 3HZ64 and 3HN64 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, L = 4, M = 2, P = 4, S = 5, T = 8, U = 8, V = 8,
PAD = 8.
9 inputs provide Interrupt capability (AD = 8, XIRQ).
80 Pin Package for 9HZ64, 9HN64, 3HZ32 and 3HN32 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, M = 2, P = 4, S = 5, T = 4, U = 8, V = 8, PAD = 7.
8 inputs provide Interrupt capability (AD = 7, XIRQ).
•
Compatibility Considerations
– Pins associated with Motors 0 and 5 should be left unconnected to ensure compatibility with
versions featuring 4 Motors.
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
5
PRELIMINARY
Block Diagram
System
Integration
Module
Clock Monitor
Breakpoints
VLCD
Pins
shown
in
BOLD are not available in the 112 QFP
PE2
PE3
PE7
PK7
FP8
FP9
FP10
FP11
FP12
FP13
FP14
FP15
LCD
Driver
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
PPAGE
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
Multiplexed Address/Data Bus
PTK
DDRK
DDRB
PTB
PTA
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
DDRA
Multiplexed Multiplexed
Narrow
Wide
Bus
Bus
PTL
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PIX0
PIX1
PIX2
PIX3
DDRL
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PTE
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
BP0
BP1
BP2
BP3
DDRE
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
VLCD
PTK
PK0
PK1
PK2
PK3
DDRK
XADDR14
XADDR15
XADDR16
XADDR17
FP20
FP21
FP22
SDA
SCL
IIC
CAN0
CAN1
RXCAN1
TXCAN1
SCI0
RXD0
TXD0
PS0
PS1
SCI1
RXD1
TXD1
MISO
MOSI
SCK
SS
PS2
PS3
SPI
M0C0M
M0C0P
M0C1M
M0C1P
PWM0
MOTOR0
PWM1
M1C0M
M1C0P
M1C1M
M1C1P
PWM3
ECS/ROMCTL
FP24
FP25
FP26
FP27
IOC0
IOC1
IOC2
IOC3
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
KWJ0
KWJ1
KWJ2
KWJ3
PU4
PU5
PU6
PU7
VDDM2
VSSM2
PWM4
PV0
PV1
PWM5
M2C1M
M0C1P
PV2
PV3
PWM6
M3C0M
M3C0P
PWM7
M3C1M
M3C1P
MOTOR2
MOTOR3
PV4
PV5
PV6
PV7
VDDM3
VSSM2
MOTOR4 and MOTOR5 Supply
PWM8
M4C0M
M4C0P
PW0
PW1
PWM9
M4C1M
M4C1P
PW2
PW3
PWM10
M5C0M
M5C0P
PWM11
M5C1M
M5C1P
MOTOR5
Supply pins
Pin
Interrupt
Logic
PU0
PU1
PU2
PU3
M2C0M
M2C0P
MOTOR4
Input Capture and
Output Compare
Timer
PS4
PS5
PS6
PS7
VDDM1
VSSM1
MOTOR2 and MOTOR3 Supply
R/W
LSTRB/TAGLO
NOACC/XCLKS
PM2
PM3
PM4
PM5
MOTOR0 and MOTOR1 Supply
MOTOR1
FP23
IOC4
IOC5
IOC6
IOC7
PM0
PM1
RXCAN0
TXCAN0
PWM2
FP16
FP17
FP18
FP19
FP28
FP29
FP30
FP31
PP0
PP1
PP2
PP3
PP4
PP5
PW0
PW1
PW2
PW3
PW4
PW5
Pulse
Width
Modulator
PTV
PTE
PE0
PE1
PE4
PE5
PE6
DDRE
TEST
DDRS
PTS
XIRQ
IRQ
ECLK
MODA
MODB
RESET
COP Watchdog
PTU
Periodic Interrupt
DDRV
PLL
CPU12
Clock and
Reset
Generation
Module
A/D Converter 5V &
Voltage Regulator
Reference
VDDA
VSSA
PTW
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
DDRW
BKGD
Analog to
Digital
Converter
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
DDRU
6K, 12K Bytes RAM
Single-Wire Background
Debug Module
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PTAD
2K, 4K Bytes EEPROM
VDDA
VSSA
VRH
VRL
PTP
128K, 256K Bytes Flash or ROM
VDDA
VSSA
VRH
VRL
PTM
Voltage Regulator
VDD1
VSS1,2
DDRM
VDDR
DDRP
Block Diagram
PW4
PW5
PW6
PW7
I/O Driver 5V
Internal Logic 2.5V
VDD1
VDDX1,2
VSS1,2
VSSX1,2
PLL 2.5V
VDDPLL
VSSPLL
Vreg Input 5V
VDDR
Figure 1. MC9S12H-Family Block Diagram
16-bit Microcontroller HCS12H Family, Rev. 11.1
6
Freescale Semiconductor
PRELIMINARY
Block Diagram
VDDR
PTAD
CAN0
RXCAN0
TXCAN0
PM2
PM3
CAN1
RXCAN1
TXCAN1
Clock Monitor
Breakpoints
RESET
SDA
SCL
IIC
PTE
DDRE
TEST
VLCD
PE2
PE3
PE7
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
FP8
FP9
FP10
FP11
FP12
FP13
FP14
FP15
FP16
FP17
FP18
FP19
FP28
FP29
FP30
FP31
LCD
Driver
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
FP20
FP21
FP22
R/W
LSTRB/TAGLO
NOACC/XCLKS
FP23
ECS/ROMCTL
FP24
FP25
FP26
FP27
IOC4
IOC5
IOC6
IOC7
SCI0
RXD0
TXD0
SPI
MISO
MOSI
SCK
SS
PPAGE
DDRK
PTK
PTB
DDRB
DDRA
PTA
PTL
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
DDRL
Multiplexed Multiplexed
Wide
Narrow
Bus
Bus
PTE
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PIX0
PIX1
PIX2
PIX3
DDRE
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
PTK
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
BP0
BP1
BP2
BP3
DDRK
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
VLCD
PTT
PK0
PK1
PK2
PK3
DDRT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
XADDR14
XADDR15
XADDR16
XADDR17
System
Integration
Module
XIRQ
IRQ
ECLK
MODA
MODB
Multiplexed Address/Data Bus
PE0
PE1
PE4
PE5
PE6
PW0
PW1
Pulse
PW2
Width
Modulator PW3
IOC0
IOC1
IOC2
IOC3
DDRP
RXD1
DDRAD
PTP
PW4
PW5
PP0
PP1
PP2
PP3
PP4
PP5
TXD1
SCI1
PTM
COP Watchdog
DDRM
Periodic Interrupt
PS0
PS1
SSD1
M0COSM
M0COSP
M0SINM
M0SINP
M1COSM
M1COSP
M1SINM
M1SINP
PWM0
M0C0M
M0C0P
PWM1
M0C1M
M0C1P
PWM2
M1C0M
M1C0P
PWM3
M1C1M
M1C1P
SSD2
SSD3
M3COSM
M3COSP
M3SINM
M3SINP
Supply pins
A/D Converter 5V &
Voltage Regulator
Reference
VDDA
VSSA
PU0
PU1
PU2
PU3
PU4
PU5
PU6
PU7
VDDM2,3
VSSM2,3
MOTOR2 and MOTOR3 Supply
M2COSM
M2COSP
M2SINM
M2SINP
PS4
PS5
PS6
PS7
VDDM1,2
VSSM1,2
MOTOR0 and MOTOR1 Supply
SSD0
PM4
PM5
DDRS
PTS
PLL
CPU12
Clock and
Reset
Generation
Module
PTU
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
DDRU
12K, 8K, 6K Bytes RAM
Single-Wire Background
Debug Module
KWAD0
KWAD1
KWAD2
KWAD3
KWAD4
KWAD5
KWAD6
KWAD7
PWM4
M2C0M
M2C0P
PV0
PV1
PWM5
M2C1M
M2C1P
PV2
PV3
PWM6
M3C0M
M3C0P
PWM7
M3C1M
M3C1P
PTV
2K Bytes EEPROM
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
DDRV
256K, 128K Bytes Flash EEPROM or ROM
BKGD
VDDA1,2
VSSA1,2
VRH
VRL
VDDA
Analog to VSSA
VRH
Digital
Converter VRL
Voltage Regulator
VDD1
VSS1,2
PV4
PV5
PV6
PV7
I/O Driver 5V
Internal Logic 2.5V
VDD1
VDDX1,2
VSS1,2
VSSX1,2
PLL 2.5V
VDDPLL
VSSPLL
Vreg Input 5V
VDDR
Input Capture and
Output Compare
Timer
Figure 2. MC9S12H-Family “Z” Version Block Diagram
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
7
PRELIMINARY
Pin Assignments
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
PJ3/KWJ3
PJ2/KWJ2
PJ1/KWJ1
PJ0/KWJ0
VSSX1
VDDX1
PK7/ECS/ROMCTL/FP23
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PE2/R/W/FP20
PL7/FP31
PL6/FP30
PL5/FP29
PL4/FP28
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
9S12H256
144 LQFP
Pins shown in BOLD are not available in the 112 QFP package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD15/AN15
PAD7/AN7
PAD14/AN14
PAD6/AN6
PAD13/AN13
PAD5/AN5
PAD12/AN12
PAD4/AN4
PAD11/AN11
PAD3/AN3
PAD10/AN10
PAD2/AN2
PAD9/AN9
PAD1/AN1
PAD8/AN8
PAD0/AN0
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
PWM2/PP2
PWM3/PP3
PWM4/PP4
PWM5/PP5
RXD0/PS0
TXD0/PS1
RXD1/PS2
TXD1/PS3
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SDA/PM0
SCL/PM1
RXCAN0/PM2
TXCAN0/PM3
RXCAN1PM4
TXCAN1/PM5
MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
KWH0/PH0
KWH1/PH1
KWH2/PH2
KWH3/PH3
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
KWH4/PH4
KWH5/PH5
KWH6/PH6
KWH7/PH7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VSSM3
M5C0M/PW4
M5C0P/PW5
Figure 1. 144-Pin Package Signal Assignments for 9S12H256
16-bit Microcontroller HCS12H Family, Rev. 11.1
8
Freescale Semiconductor
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
9S12H256,
9S12H128,
3S12H256,
3S12H192
112 LQFP
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD7/AN7
PAD6/AN6
PAD5/AN5
PAD4/AN4
PAD3/AN3
PAD2/AN2
PAD1/AN1
PAD0/AN0
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
RXCAN1/PM4
TXCAN1/PM5
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VSSM3
M5C0M/PW4
M5C0P/PW5
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
VSSX1
VDDX1
PK7/ECS/ROMCTL/FP23
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PE2/R/W/FP20
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
Pin Assignments
Figure 2. 112-Pin Package Signal Assignments for 9S12H256, 3S12H256 and 3S12H192
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
9
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9S12HZ256,
9S12HZ128,
3S12HZ128,
3S12HN128
112 LQFP
Signals shown in BOLD are not available in the 80 QFP package
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD7/KWAD7/AN7
PAD6/KWAD6/AN6
PAD5/KWAD5/AN5
PAD4/KWAD4/AN4
PAD3/KWAD3/AN3
PAD2/KWAD2/AN2
PAD1/KWAD1/AN1
PAD0/KWAD0/AN0
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
RXCAN1/PM4
TXCAN1/PM5
PWM3/PP3
RXD1/PWM2/PP2
TXD1/PWM0/PP0
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
FP28/AN12/PL4
FP29AN13//PL5
FP30/AN14//PL6
FP31/AN15/PL7
VDDM1
VSSM1
M0C0M/M0COSM/PU0
M0C0P/M0COSP/PU1
M0C1M/M0SINM/PU2
M0C1P/M0SINP/PU3
M1C0M/M1COSM/PU4
M1C0P/M1COSP/PU5
M1C1M/M1SINM/PU6
M1C1P/M1SINP/PU7
VDDM2
VSSM2
M2C0M/M2COSM/PV0
M2C0P/M2COSP/PV1
M2C1M/M2SINM/PV2
M2C1P/M2SINP/PV3
M3C0M/M3COSM/PV4
M3C0P/M3COSP/PV5
M3C1M/M3SINM/PV6
M3C1P/M3SINP/PV7
VDDM3
VSSM3
SCL/PWM5/PP5
SDA/PWM4/PP4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
VSSX1
VDDX1
PK7/ECS/ROMCTL/FP23
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PE2/R/W/FP20
PL3/AN11/FP19
PL2/AN10/FP18
PL1/AN9/FP17
PL0/AN8/FP16
PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
Pin Assignments
Figure 3. 112-Pin Package Signal Assignments for 9S12HZ256, 9S12HZ128, 3S12HZ128 and 3S12HN128
16-bit Microcontroller HCS12H Family, Rev. 11.1
10
Freescale Semiconductor
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9S12HZ64,
9S12HN64,
3S12HZ64,
3S12HN64
112 LQFP
Signals shown in BOLD are not available in the 80 QFP package
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PB5/FP5
PB4/FP4
NC
NC
NC
NC
PK0/BP0
PK1/BP1
PK2/BP2
PK3/BP3
VLCD
VSS1
VDD1
PAD7/KWAD7/AN7
PAD6/KWAD6/AN6
PAD5/KWAD5/AN5
PAD4/KWAD4/AN4
PAD3/KWAD3/AN3
PAD2/KWAD2/AN2
PAD1/KWAD1/AN1
PAD0/KWAD0/AN0
VDDA
NC
NC
VSSA
PE0/XIRQ
PE4/ECLK
NC
NC
MISO/PS4
MOSI/PS5
SCK/PS6
NC
NC
NC
NC
PWM3/PP3
NC
NC
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
NC
VDDX2
VSSX2
MODC/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
NC
NC
NC
NC
NC
M0C0M/M0COSM/PU0
M0C0P/M0COSP/PU1
M0C1M/M0SINM/PU2
M0C1P/M0SINP/PU3
M1C0M/M1COSM/PU4
M1C0P/M1COSP/PU5
M1C1M/M1SINM/PU6
M1C1P/M1SINP/PU7
VDDM2
VSSM2
M2C0M/M2COSM/PV0
M2C0P/M2COSP/PV1
M2C1M/M2SINM/PV2
M2C1P/M2SINP/PV3
M3C0M/M3COSM/PV4
M3C0P/M3COSP/PV5
M3C1M/M3SINM/PV6
M3C1P/M3SINP/PV7
NC
NC
PWM5/PP5
PWM4/PP4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
VSSX1
VDDX1
PK7/FP23
PE7/XCLKS/FP22
PE3/FP21
PE2/FP20
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PA7/FP15
PA6/FP14
PA5/FP13
PA4/FP12
PA3/FP11
PA2/FP10
PA1/FP9
PA0/FP8
PB7/FP7
PB6/FP6
Pin Assignments
Figure 4. 112-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ64 and 3S12HN64
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
11
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9S12HZ64,
9S12HN64,
3S12HZ32,
3S12HN32
80 QFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PB5/FP5
PB4/FP4
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD6/KWAD6/AN6
PAD5/KWAD5/AN5
PAD4/KWAD4/AN4
PAD3/KWAD3/AN3
PAD2/KWAD2/AN2
PAD1/KWAD1/AN1
PAD0/KWAD0/AN0
VDDA
VSSA
PE0/XIRQ
PE4/ECLK
PWM3/PP3
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDX2
VSSX2
MODC/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
PS4
PS5
PS6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
M0C0M/M0COSM/PU0
M0C0P/M0COSP/PU1
M0C1M/M0SINM/PU2
M0C1P/M0SINP/PU3
M1C0M/M1COSM/PU4
M1C0P/M1COSP/PU5
M1C1M/M1SINM/PU6
M1C1P/M1SINP/PU7
VDDM2
VSSM2
M2C0M/M2COSM/PV0
M2C0P/M2COSP/PV1
M2C1M/M2SINM/PV2
M2C1P/M2SINP/PV3
M3C0M/M3COSM/PV4
M3C0P/M3COSP/PV5
M3C1M/M3SINM/PV6
M3C1P/M3SINP/PV7
PWM5/PP5
PWM4/PP4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
VSSX1
VDDX1
PK7/FP23
PE7/XCLKS/FP22
PE3/FP21
PE2/FP20
PA7/FP15
PA6/FP14
PA5/FP13
PA4/FP12
PA3/FP11
PA2/FP10
PA1/FP9
PA0/FP8
PB7/FP7
PB6/FP6
Pin Assignments
Figure 5. 80-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ32 and 3S12HN32
16-bit Microcontroller HCS12H Family, Rev. 11.1
12
Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name
Function 4
XTAL






Crystal driver and external clock input pins. On reset all the
device clocks are derived from the EXTAL input frequency.
XTAL is the crystal output
RESET



Active low bidirectional control signal that acts as an input to
initialize the MCU to a known start-up state, and an output
when an internal MCU function causes a reset.
TEST



Test Input
EXTAL
Description
BKGD
TAGHI
MODC

Function 1: Pseudo-open-drain communication pin for the
background debug function.
Function 2: In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling
edge of E-clock tags the high half of the instruction word being
read into the instruction queue.
Function 3: At the rising edge during reset, the state of this pin
is latched to the MODC bit to set the MCU operating mode.
PAD[15:8]
AN[15:8]


Function 1: Port AD general purpose inputs
Function 2: Analog inputs (ATD)

Function 1: Port AD general purpose inputs
Function 2: Analog inputs (ATD)
Function 3: Key wake-up input pins that can generate an interrupt causing the MCU to exit STOP or WAIT mode.

Function 1: Port A general purpose input or output pins.
Function 2: LCD frontplane segment driver output pin.
Function 3: In MCU expanded modes of operation, these pins
are used for the multiplexed external address and data bus.

Function 1: Port B general purpose input or output pins.
Function 2: LCD frontplane segment driver output pin.
Function 3: In MCU expanded modes of operation, these pins
are used for the multiplexed external address and data bus.
NOACC
Function 1: Port E general purpose input or output pin
Function 2: LCD frontplane segment driver output pin
Function 3: The XCLKS signal selects between an external
clock or oscillator configuration during reset. This pin should
be at a logic high during reset if an external clock is used on
the EXTAL input pin. This pin should be at a logic low during
reset if an oscillator circuit is configured on EXTAL and XTAL.
Since this pin is an input with a pull-down device during reset,
if the pin is left floating, the default configuration is an
oscillator circuit on EXTAL and XTAL.
Function 4: During MCU expanded modes of operation, the
NOACC signal, when enabled, is used to indicate that the
current bus cycle is an unused or “free” cycle. This signal will
assert when the CPU is not using the bus.
PAD[7:0]
PA[7:0]
PB[7:0]
PE7
AN[7:0]
KWAD[7:0]
FP[15:8]
ADDR[15:8]/D
ATA[15:8]
FP[7:0]
ADDR[7:0]/DA
TA[7:0]
FP22
XCLKS
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
13
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name
Function 4
Description
PE6
IPIPE1
MODB

PE5
IPIPE0
MODA

PE4
ECLK


Function 1: Port E general purpose input or output pin.
Function 2: Internal bus clock output that can be used as a timing reference.
TAGLO
Function 1: Port E general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
Function 3: In MCU expanded modes of operation, LSTRB is
used for the low-byte strobe function to indicate the type of
bus access.
Function 4: When instruction tagging is on, TAGLO is used to
tag the low half of the instruction word being read into the
instruction queue.

Function 1: Port E general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
Function 3: In MCU expanded modes of operations, performs
the read/write output signal for the external bus. This pin
indicates direction of data on the external bus.

Function 1: Port E general purpose input pin.
Function 2: Maskable interrupt request input provides a
means of applying asynchronous interrupt requests. Will
wake up the MCU from STOP or WAIT mode
PE3
PE2
PE1
FP21
FP20
IRQ
LSTRB
R/W

Function 1: Port E general purpose input or output pins.
Function 2: Instruction queue tracking signals.
Function 3: The state of the MODA and MODB pins during
reset determine the initial operating mode of the MCU
PE0
XIRQ


Function 1: Port E general purpose input pin.
Function 2: Nonmaskable interrupt request input provides a
means of applying asynchronous interrupt requests. Will
wake up the MCU from STOP or WAIT mode.
PH[7:0]
KWH[7:0]


Function 1: Port H general purpose input or output pins.
Function 2: Key wake-up input pins that can generate an
interrupt causing the MCU to exit STOP or WAIT mode.
PJ[3:0]
KWJ[3:0]


Function 1: Port J general purpose input or output pins.
Function 2: Key wake-up input pins that can generate an
interrupt causing the MCU to exit STOP or WAIT mode.
ROMCTL
Function 1: Port K general purpose input or output pin.
Function 2: LCD frontplane segment driver output pin.
Function 3: During MCU expanded modes of operation, this
pin is used to enable the Flash EEPROM memory in the
memory map.
Function 4: During MCU expanded modes of operation, this
pin is used as the emulation chip select signal.
PK7
FP23
ECS
PK[3:0]
BP[3:0]
XADDR[17:14]

Function 1: Port K general purpose input or output pins.
Function 2: LCD backplane segment driver output pins.
Function 3: In MCU expanded modes of operation, expanded
address pins for the external bus.
PL[7:4]
FP[31:28]
AN[15:12]

Function 1: Port L general purpose input or output pins.
Function 2: LCD frontplane segment driver output pins.
Function 3: Analog inputs (ATD).
16-bit Microcontroller HCS12H Family, Rev. 11.1
14
Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name
Function 4
Description
PL[3:0]
FP[19:16]
AN[11:08]

Function 1: Port L general purpose input or output pins.
Function 2: LCD frontplane segment driver output pins.
Function 3: Analog inputs (ATD).
PM5
TXCAN1


Function 1: Port M general purpose input or output pin.
Function 2: Transmit pin for the Motorola Scalable Controller
Area Network controller 1 (MSCAN1).
PM4
RXCAN1


Function 1: Port M general purpose input or output pin.
Function 2: Receive pin for the Motorola Scalable Controller
Area Network controller 1 (MSCAN1).
PM3
TXCAN0


Function 1: Port M general purpose input or output pin.
Function 2: Transmit pin for the Motorola Scalable Controller
Area Network controller 0 (MSCAN0).
PM2
RXCAN0


Function 1: Port M general purpose input or output pin.
Function 2: Receive pin for the Motorola Scalable Controller
Area Network controller 0 (MSCAN0).
PM1
SCL


Function 1: Port M general purpose input or output pin.
Function 2: Serial clock pin for the Inter-IC Bus Interface
(IIC).
PM0
SDA


Function 1: Port M general purpose input or output pin.
Function 2: Serial data pin for the Inter-IC Bus Interface
(IIC).

Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
pins.
Function 3: Serial clock pin for the Inter-IC Bus Interface
(IIC).

Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
pins.
Function 3: Serial data pin for the Inter-IC Bus Interface
(IIC).

Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
pins.
Function 3: Transmit pin of Serial Communication
Interface 1 (SCI1).
PP5
PP4
PP3
PWM5
PWM4
PWM3
SCL
SDA

PP2
PWM2
RXD1

Function 1: Port P general purpose input or output pins.
Function 2: Pulse Width Modulator (PWM) channel output
pins.
Function 3: Receive pin of Serial Communication
Interface 1 (SCI1).
PP1
PWM1


Function 1: General purpose input or output pin.
Function 2: Pulse Width Modulator (PWM) channel output pin.

Function 1: General purpose input or output pin.
Function 2: Pulse Width Modulator (PWM) channel output pin.
Function 3: Transmit pin of Serial Communication Interface 1 (SCI1).
PP0
PWM0
TXD1
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
15
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name
Function 4
Description
PS7
SS


Function 1: Port S general purpose input or output pin.
Function 2: Slave select pin for the Serial Peripheral Interface
(SPI).
PS6
SCK


Function 1: Port S general purpose input or output pin.
Function 2: Serial clock pin for the Serial Peripheral Interface
(SPI).

Function 1: Port S general purpose input or output pin.
Function 2: Master output (during master mode) or slave input
(during slave mode) pin for the Serial Peripheral Interface
(SPI).
PS5
MOSI

PS4
MISO


Function 1: Port S general purpose input or output pin.
Function 2: Master input (during master mode) or slave output
(during slave mode) pin for the Serial Peripheral Interface
(SPI).
PS3
TXD1


Function 1: Port S general purpose input or output pin.
Function 2: Transmit pin of Serial Communication
Interface 1 (SCI1).
PS2
RXD1


Function 1: Port S general purpose input or output pin.
Function 2: Receive pin of Serial Communication
Interface 1 (SCI1).
PS1
TXD0


Function 1: Port S general purpose input or output pin.
Function 2: Transmit pin of Serial Communication Interface 0
(SCI0).
PS0
RXD1


Function 1: Port S general purpose input or output pin.
Function 2: Receive pin of Serial Communication Interface 0
(SCI0).
PT[7:4]
IOC[7:4]


Function 1: Port T general purpose input or output pins.
Function 2: Timer input capture or output compare pins.
PT[3:0]
IOC[3:0]
FP[27:24]

Function 1: Port T general purpose input or output pins.
Function 2: Timer input capture or output compare pins.
Function 3: LCD frontplane segment driver output pins.
PU7
M1C1P


PU6
M1C1M


PU5
M1C0P


PU4
M1C0M


PU3
M0C1P


PU2
M0C1M


Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 1.
PWM output on M1C1M results in a positive current flow
through coil 1 when M1C1P is driven to a logic high state.
Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 1.
PWM output on M1C0M results in a positive current flow
through coil 0 when M1C0P is driven to a logic high state.
Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 0.
PWM output on M0C1M results in a positive current flow
through coil 1 when M0C1P is driven to a logic high state.
16-bit Microcontroller HCS12H Family, Rev. 11.1
16
Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name
Function 4
Description
Function 1: Port U general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 0.
PWM output on M0C0M results in a positive current flow
through coil 0 when M0C0P is driven to a logic high state.
PU1
M0C0P


PU0
M0C0M


PV7
M3C1P


PV6
M3C1M


PV5
M3C0P


PV4
M3C0M


PV3
M2C1P


PV2
M2C1M


PV1
M2C0P


PV0
M2C0M


PW7
M5C1P


PW6
M5C1M


PW5
M3C0P


PW4
M5C0M


PW3
M4C1P


PW2
M4C1M


PW1
M4C0P


PW0
M4C0M


VLCD



Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 3.
PWM output on M3C1M results in a positive current flow
through coil 1 when M3C1P is driven to a logic high state.
Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 3.
PWM output on M3C0M results in a positive current flow
through coil 0 when M3C0P is driven to a logic high state.
Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 2.
PWM output on M2C1M results in a positive current flow
through coil 1 when M2C1P is driven to a logic high state.
Function 1: Port V general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 2.
PWM output on M2C0M results in a positive current flow
through coil 0 when M2C0P is driven to a logic high state.
Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 5.
PWM output on M5C1M results in a positive current flow
through coil 1 when M5C1P is driven to a logic high state.
Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 5.
PWM output on M5C0M results in a positive current flow
through coil 0 when M5C0P is driven to a logic high state.
Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 4.
PWM output on M4C1M results in a positive current flow
through coil 1 when M4C1P is driven to a logic high state.
Function 1: Port W general purpose input or output pins.
Function 2: High current PWM output pins which can be used
for motor drive. These pins interface to the coils of motor 4.
PWM output on M4C0M results in a positive current flow
through coil 0 when M4C0P is driven to a logic high state.
Supply input pin for the LCD driver. Adjusting the voltage on
this pin will change the display contrast.
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
17
PRELIMINARY
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package.
Note: Features shown in Italics are only available for the “Z” versions
Pin Name Pin Name
Function 1 Function 2
VDDA
VSSA
VRH
VRL
VDDM1
VSSM1
VDDM2
VSSM2
VDDM3
VSSM3
VDDPLL
VSSPLL
VDDX1
VSSX1
VDDX2
VSSX2
VDD1
VSS1
VSS2
VDDR




















Pin Name
Function 3
Pin Name
Function 4








































Description
Supply input pins for the voltage regulator and the analog to
digital converter. Tolerance = 5V ± 5%.
Reference voltage input pins for the analog to digital
converter.
Supply input pins for motor 0 and motor 1 output drivers.
Tolerance = 5 V ± 10%.
Supply input pins for motor 2 and motor 3 output drivers.
Tolerance = 5 V ± 10%.
Supply input pins for motor 4 and motor 5 output drivers.
Tolerance = 5 V ± 10%.
PLL supply output pins. No load allowed except for bypass
capacitors.
Supply input pins for input/output drivers. Tolerance = 5V ±
5%.
Core supply output pins. No load allowed except for bypass
capacitors.
Power supply input pin for voltage regulator. Nominal 5V
16-bit Microcontroller HCS12H Family, Rev. 11.1
18
Freescale Semiconductor
PRELIMINARY
Memory Maps
Memory Maps
$0000
1K Register Space
$0000
$0400
$03FF
Mappable to any 2K Boundary
$0000
4K Bytes EEPROM
Initially overlapped by register space
$1000
$0FFF
Mappable to any 4K Boundary
$1000
12K Bytes RAM
Alignable to top ($1000 - $3FFF)
or bottom ($0000 - $2FFF)
$4000
$3FFF
Mappable to any 16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM for MC9S12H256
$0000 - $0FFF: 4K EEPROM (1K not visible) on MC9S12H256 only.
There is no mapping of EEPROM Flash on MC3S12H256.
Figure 6. MC9(3)S12H256 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
19
PRELIMINARY
Memory Maps
$0000
$0400
$0800
$1000
$4000
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0800
2K Bytes EEPROM
$0FFF
Mappable to any 2K Boundary
$1000
12K Bytes RAM
$3FFF
Mappable to any16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM
$0000 - $07FF: 2K EEPROM (1K not visible)
There is no mapping of EEPROM Flash on MC3S12HZ256.
Figure 7. MC9(3)S12HZ256 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
20
Freescale Semiconductor
PRELIMINARY
Memory Maps
$0000
1K Register Space
$0000
$0400
$03FF
Mappable to any 2K Boundary
$2000
$2000
8K Bytes RAM
$3FFF
Mappable to any 8K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Twelve * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (1K not visible)
Figure 8. MC3S12HZ192 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
21
PRELIMINARY
Memory Maps
$0000
1K Register Space
$0000
$0400
$0800
$1000
$03FF
Mappable to any 2K Boundary
$0800
2K Bytes EEPROM
$0FFF
Mappable to any 2K Boundary
$2800
$2800
$3FFF
6K Bytes RAM
Alignable to top ($2800 - $3FFF)
or bottom ($2000 - $37FF) of 8K Boundary
Mappable to any 8K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $1FFF: 6K RAM
$0000 - $07FF: 2K EEPROM (1K not visible)
There is no mapping of EEPROM Flash on MC3S12HZ(N)128.
Figure 9. MC9(3)S12HZ(N)128 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
22
Freescale Semiconductor
PRELIMINARY
Memory Maps
$0000
1K Register Space
$0000
$0400
$0800
$1000
$03FF
Mappable to any 2K Boundary
$0800
$0FFF
1K Bytes EEPROM
(1K mapped twice in 2K Boundary)
Mappable to any 2K Boundary
$3000
$3000
4K Bytes RAM
$3FFF
Mappable to any 4K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (1K not visible)
$0000 - $07FF: 1K EEPROM mapped twice (not visible)
There is no mapping of EEPROM Flash on MC3S12HZ(N)64
Figure 10. MC9(3)S12HZ(N)64 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
23
PRELIMINARY
Memory Maps
$0000
$0400
$0800
$1000
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0800
2K Bytes RAM
$0FFF
Mappable to any 2K Boundary
$8000
16K Fixed Flash EEPROM
$8000
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
Figure 11. MC3S12HZ(N)32 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1
24
Freescale Semiconductor
PRELIMINARY
Mechanical Package Dimensions
Mechanical Package Dimensions
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
1
108
4X
J1
L
J1
M
C
L
B
V
X
140X
B1
VIEW Y
36
V1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT
THE SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
72
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
F
AA
C2
0.05
R2
θ
R1
D
0.08
M
0.25
BASE
METAL
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90 ° )
144 PL
(K)
C1
(Y)
VIEW AB
G
VIEW Y
73
37
P
E
MILLIMETERS
DIM MIN MAX
A
20.00 BSC
A1
10.00 BSC
B
20.00 BSC
B1
10.00 BSC
C
1.40
1.60
C1
0.05
0.15
C2
1.35
1.45
D
0.17
0.27
E
0.45
0.75
F
0.17
0.23
G
0.50 BSC
J
0.09
0.20
K
0.50 REF
P
0.25 BSC
R1
0.13
0.20
R2
0.13
0.20
S
22.00 BSC
S1
11.00 BSC
V
22.00 BSC
V1
11.00 BSC
Y
0.25 REF
Z
1.00 REF
AA
0.09
0.16
θ
0°
θ1
0°
7°
θ2
11°
13 °
θ1
(Z)
Figure 3. 144-pin LQFP Mechanical Dimensions (case no. 918-03)
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
25
PRELIMINARY
Mechanical Package Dimensions
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
C
L
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
V
B
L
M
28
B1
AA
J
V1
57
29
F
D
56
0.13
N
M
BASE
METAL
T L-M N
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
S1
A
S
C2
C
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING
PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED
AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE
DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
θ1
(Y)
VIEW AB
(Z)
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--- 1.600
0.050 0.150
1.350 1.450
0.270 0.370
0.450 0.750
0.270 0.330
0.650 BSC
0.090 0.170
0.500 REF
0.325 BSC
0.100 0.200
0.100 0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090 0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure 4. 112-pin LQFP Mechanical Dimensions (case no. 987)
16-bit Microcontroller HCS12H Family, Rev. 11.1
26
Freescale Semiconductor
PRELIMINARY
Mechanical Package Dimensions
L
60
41
61
D
S
V
0.20 M C A-B
B
B
0.05 D
L
D
-B-
0.20 M H A-B
-A-
B
S
S
S
40
P
-A-,-B-,-DDETAIL A
DETAIL A
21
80
1
A
0.20 M H A-B
S
F
20
-DD
S
0.05 A-B
J
S
0.20 M C A-B
S
D
N
S
E
M
D
DETAIL C
0.20 M C A-B
C
-CSEATING
PLANE
-H-
DATUM
PLANE
0.10
H
S
D
S
SECTION B-B
VIEW ROTATED 90 °
M
G
U
T
DATUM -HPLANE
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
13.90 14.10
13.90 14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10°
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95 17.45
0.13
--0°
--16.95 17.45
0.35
0.45
1.6 REF
Figure 5. 80-pin QFP Mechanical Dimensions (case no. 841B)
16-bit Microcontroller HCS12H Family, Rev. 11.1
Freescale Semiconductor
27
PRELIMINARY
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