Freescale Semiconductor Product Brief MC9S12CFAMPB Rev. 5, 03/2006 MC9S12C-Family 16-Bit Microcontroller Based on Freescale’s market-leading flash technology, members of the MC9S12C-Family deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications. MC9S12C-Family members are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM or ROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and up to one CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wakeup capability from STOP or WAIT mode. The MC9S12C-Family is available in 48-pin and 52-pin LQFP, and in 80-pin QFP packages (all RoHS Compliant J-STD-020C); the 80-pin version is pin-compatible with the HCS12B- and D-Family derivatives. The C-Family includes ROM versions MC3S12C128/96/64/32/16 of all devices which provide a further cost reduction path for applications with high volume and stable code. 1 Features • 16-Bit HCS12 CORE — HCS12 CPU — MMC (memory map and interface) — INT (interrupt control) — BDM (background debug mode) — DBG12 (enhanced debug12 module including breakpoints and change-of-flow trace buffer) — Multiplexed Expansion Bus (available only in 80-pin package version) © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Features • 16-Bit HCS12 CPU — Upward compatible with M68HC11 instruction set — Interrupt stacking and programmer’s model identical to M68HC11 — Instruction queue — Enhanced indexed addressing • Wake-up Interrupt Inputs — Up to 10-port bits available for wake up interrupt function • Memory Options — 16K, 32K, 64K, 96K and 128K Byte Flash EEPROM (erasable in 512-byte sectors) or — 16K, 32K, 64K, 96K and 128K Byte ROM — 1K, 2K, and 4K Byte RAM • Analog-to-Digital Converters — One 8-channel module with 10-bit resolution. — External conversion trigger capability • Up to One 1M Bit Per Second, CAN 2.0 A, B Software Compatible Modules — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit — Four separate interrupt channels for receive, transmit, error and wake-up — Low-pass filter wake-up function — Loop-back for self test operation • Timer Module (TIM) — 16-bit Counter with 7-bit Prescaler — 8 programmable input capture or output compare channels — Simple PWM Mode — Modulo Reset of Timer Counter — 16-Bit Pulse Accumulator — External Event Counting — Gated Time Accumulation • 6 PWM Channels — Programmable period and duty cycle — 8-bit 6-channel or 16-bit 3-channel — Separate control for each pulse width and duty cycle — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input MC9S12C-Family, Rev. 5 2 Freescale Semiconductor Features • Serial Interfaces — One asynchronous serial communications interface (SCI) — One synchronous serial peripheral interface (SPI) • CRG (Clock Reset Generator Module) — Windowed COP watchdog, — Real time interrupt, — Clock monitor, — Clock generation — Reset Generation — Phase-locked loop clock frequency multiplier — Limp home mode in absence of external clock — Low power 0.5 to 16 MHz crystal oscillator reference clock • Operation Frequency — 32MHz equivalent to 16MHz Bus Speed for single chip — 32MHz equivalent to 16MHz Bus Speed in expanded bus modes — Option: 50MHz equivalent to 25MHz Bus Speed — Internal 2.5V Regulator — Supports an input voltage range from 3.3V-10% to 5.5V — Low power mode capability — Includes low voltage reset (LVR) circuitry — Includes low voltage interrupt (LVI) circuitry • 48-pin LQFP, 52-pin LQFP, or 80-pin QFP Package (all RoHS Compliant J-STD-020C) — Up to 58 I/O lines with 5V input and drive capability — Up to 2 dedicated 5V input only lines (IRQ, XIRQ) — 5V A/D converter inputs and 5V I/O • Development Support — Single-wire background debug™ mode (BDM) — On-chip hardware breakpoints — Enhanced DBG12 debug features MC9S12C-Family, Rev. 5 Freescale Semiconductor 3 MC9S12C-Family Members 2 MC9S12C-Family Members Table 1. List of MC9S12C-Family Members Flash 128K 96K 64K 32K 32K 16K 0 0 0 0 0 0 ROM 0 0 0 0 0 0 128K 96K 64K 32K 32K 16K RAM 4K 4K 4K 2K 2K 1K 4K 4K 4K 2K 2K 1K CAN SCI SPI A/D PWM Timer I/O 48LQFP Package MC9S12C128 Device 1 1 1 8ch 6ch 8ch 31 52LQFP MC9S12C128 1 1 1 8ch 6ch 8ch 35 80QFP MC9S12C128 1 1 1 8ch 6ch 8ch 60 48LQFP MC9S12C96 1 1 1 8ch 6ch 8ch 31 52LQFP MC9S12C96 1 1 1 8ch 6ch 8ch 35 80QFP MC9S12C96 1 1 1 8ch 6ch 8ch 60 48LQFP MC9S12C64 1 1 1 8ch 6ch 8ch 31 52LQFP MC9S12C64 1 1 1 8ch 6ch 8ch 35 80QFP MC9S12C64 1 1 1 8ch 6ch 8ch 60 48LQFP MC9S12C32 1 1 1 8ch 6ch 8ch 31 52LQFP MC9S12C32 1 1 1 8ch 6ch 8ch 35 80QFP MC9S12C32 1 1 1 8ch 6ch 8ch 60 48LQFP MC9S12GC32 0 1 1 8ch 6ch 8ch 31 52LQFP MC9S12GC32 0 1 1 8ch 6ch 8ch 35 80QFP MC9S12GC32 0 1 1 8ch 6ch 8ch 60 48LQFP MC9S12GC16 0 1 1 8ch 6ch 8ch 31 52LQFP MC9S12GC16 0 1 1 8ch 6ch 8ch 35 80QFP MC9S12GC16 0 1 1 8ch 6ch 8ch 60 48LQFP MC3S12C128 1 1 1 8ch 6ch 8ch 31 52LQFP MC3S12C128 1 1 1 8ch 6ch 8ch 35 80QFP MC3S12C128 1 1 1 8ch 6ch 8ch 60 48LQFP MC3S12C96 1 1 1 8ch 6ch 8ch 31 52LQFP MC3S12C96 1 1 1 8ch 6ch 8ch 35 80QFP MC3S12C96 1 1 1 8ch 6ch 8ch 60 48LQFP MC3S12C64 1 1 1 8ch 6ch 8ch 31 52LQFP MC3S12C64 1 1 1 8ch 6ch 8ch 35 80QFP MC3S12C64 1 1 1 8ch 6ch 8ch 60 48LQFP MC3S12C32 1 1 1 8ch 6ch 8ch 31 52LQFP MC3S12C32 1 1 1 8ch 6ch 8ch 35 80QFP MC3S12C32 1 1 1 8ch 6ch 8ch 60 48LQFP MC3S12GC32 0 1 1 8ch 6ch 8ch 31 52LQFP MC3S12GC32 0 1 1 8ch 6ch 8ch 35 80QFP MC3S12GC32 0 1 1 8ch 6ch 8ch 60 48LQFP MC3S12GC16 0 1 1 8ch 6ch 8ch 31 52LQFP MC3S12GC16 0 1 1 8ch 6ch 8ch 35 80QFP MC3S12GC16 0 1 1 8ch 6ch 8ch 60 MC9S12C-Family, Rev. 5 4 Freescale Semiconductor Pin Out Explanations 3 Pin Out Explanations I/O is the sum of ports capable to act as digital input or output. • For 80 Pin Versions: — Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 8, S = 4, T = 8, PAD = 8. — 12 inputs provide Interrupt capability (P = 8, J = 2, IRQ, XIRQ) • For 52 Pin Versions: — Port A = 3, B = 1, E = 2 + 2 input only, M = 6, P = 3, S = 2, T = 8, PAD = 8. — 5 inputs provide Interrupt capability (P = 3, IRQ, XIRQ) • For 48 Pin Versions: — Port A = 1, B = 1, E = 2 + 2 input only, M = 6, P = 1, S = 2, T = 8, PAD = 8. — 3 inputs provide Interrupt capability (P = 1, IRQ, XIRQ) MC9S12C-Family, Rev. 5 Freescale Semiconductor 5 Block Diagram Block Diagram TEST/VPP Multiplexed Address/Data Bus SCI DDRA DDRB PTA PTB ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Multiplexed Wide Bus DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 MSCAN Internal Logic 2.5V VDD1,2 VSS1,2 PLL 2.5V VDDPLL VSSPLL SPI RXD TXD RXCAN TXCAN MISO SS MOSI SCK PTAD PTT PTP DDRAD PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PTJ PWM Module PW0 PW1 PW2 PW3 PW4 PW5 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PJ6 PJ7 PTS XIRQ IRQ System R/W Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PS0 PS1 PS2 PS3 PTM COP Watchdog Clock Monitor Periodic Interrupt MUX DDRT Timer Module Clock and Reset Generation Module IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 DDRP PLL HCS12 CPU AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Keypad Interrupt Single-wire Background Debug12 Module VDDA VSSA VRH VRL DDRJ PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 1K, 2K, 4K Byte RAM VDDA VSSA VRH VRL Key Int XFC VDDPLL VSSPLL EXTAL XTAL RESET 32K, 64K, 96K, 128K Byte Flash/ROM DDRE BKGD Voltage Regulator PTE VDD2 VSS2 VDD1 VSS1 ATD DDRS VSSR VDDR VDDX VSSX DDRM 4 PM0 PM1 PM2 PM3 PM4 PM5 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package I/O Driver 5V VDDX VSSX A/D Converter 5V VDDA VSSA VRL is bonded internally to VSSA for 52 and 48 Pin packages Voltage Regulator 5V & I/O VDDR VSSR Figure 1. Block Diagram MC9S12C-Family, Rev. 5 6 Freescale Semiconductor User Configurable Memory Maps 5 User Configurable Memory Maps $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $0000 16K Fixed Flash EEPROM/ROM $3FFF $3000 $4000 $3000 4K Bytes RAM $3FFF Mappable to any 4K Boundary $4000 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 8 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 2. MCxS12C128 User Configurable Memory Map MC9S12C-Family, Rev. 5 Freescale Semiconductor 7 User Configurable Memory Maps $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $0000 16K Fixed Flash EEPROM/ROM $3FFF $3000 $4000 $3000 4K Bytes RAM $3FFF Mappable to any 4K Boundary $4000 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 6 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 3. MCxS12C96 User Configurable Memory Map MC9S12C-Family, Rev. 5 8 Freescale Semiconductor User Configurable Memory Maps $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $0000 16K Fixed Flash EEPROM/ROM $3FFF $3000 $4000 $3000 4K Bytes RAM $3FFF Mappable to any 4K Boundary $4000 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 4 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 512 Bytes Figure 4. MCxS12C64 User Configurable Memory Map MC9S12C-Family, Rev. 5 Freescale Semiconductor 9 User Configurable Memory Maps $0000 $0400 $3800 $0000 1K Register Space $03FF Mappable to any 2K Boundary $3800 2K Bytes RAM $3FFF Mappable to any 2K Boundary $4000 $8000 $8000 16K Page Window 2 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 5. MCxS12C32 User Configurable Memory Map MC9S12C-Family, Rev. 5 10 Freescale Semiconductor User Configurable Memory Maps $0000 $0400 $3800 $0000 1K Register Space $03FF Mappable to any 2K Boundary $3800 2K Bytes RAM $3FFF Mappable to any 2K Boundary $4000 $8000 $8000 16K Page Window 1 * 16K Flash EEPROM/ROM Page EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 6. MCxS12C16 User Configurable Memory Map MC9S12C-Family, Rev. 5 Freescale Semiconductor 11 User Configurable Memory Maps $0000 $0400 $3C00 $0000 1K Register Space $03FF Mappable to any 2K Boundary $3C00 1K Bytes RAM $3FFF Mappable to any 2K Boundary $4000 $8000 $8000 16K Page Window 1 * 16K Flash EEPROM/ROM Page EXT $BFFF $C000 $C000 $FFFF $FF00 $FF00 $FFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP $FFFF 16K Fixed Flash EEPROM/ROM BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0C00 - $0FFF: 1K RAM Flash Erase Sector Size is 512 Bytes Figure 7. MCxS12GC16 User Configurable Memory Map MC9S12C-Family, Rev. 5 12 Freescale Semiconductor Pin Assignments Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12C-Family 80 QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PW4 PP5/KWP5/PW5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMONE PS3 PS2 PS1/TXD PS0/RXD VSSA VRL 6 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package Figure 8. Pin Assignments for 80-pin QFP for MC9S12C-Family !!! Pin-out is Subject to Change !!! MC9S12C-Family, Rev. 5 Freescale Semiconductor 13 PP4/KWP4/PW4 PP5/KWP5/PW5 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 52 51 50 49 48 47 46 45 44 43 42 41 40 Pin Assignments 39 VRH 2 38 VDDA PW1/IOC1/PT1 3 37 PAD07/AN07 PW2/IOC2/PT2 4 36 PAD06/AN06 PW3/IOC3/PT3 5 35 PAD05/AN05 VDD1 6 34 PAD04/AN04 VSS1 7 33 PAD03/AN03 PW4/IOC4/PT4 8 32 PAD02/AN02 IOC5/PT5 9 31 PAD01/AN01 IOC6/PT6 10 30 PAD00/AN00 IOC7/PT7 11 29 PA2 MODC/BKGD 12 28 PA1 PB4 13 27 PA0 MC9S12C-Family 19 20 21 22 23 24 25 26 VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP IRQ/PE1 XIRQ/PE0 17 VDDR 18 16 VSSR RESET 15 52 LQFP ECLK/PE4 PW0/IOC0/PT0 14 1 XCLKS/PE7 PW3/KWP3/PP3 * Signals shown in Bold are not available on the 48 Pin Package Figure 9. Pin Assignments for 52-pin LQFP for MC9S12C-Family MC9S12C-Family, Rev. 5 14 Freescale Semiconductor VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 46 45 44 43 42 41 40 39 38 37 PW1/IOC1/PT1 47 1 PP5/KWP5 PW0/IOC0/PT0 48 Pin Assignments 36 VRH 2 35 VDDA PW2/IOC2/PT2 3 34 PAD07/AN07 PW3/IOC3/PT3 4 33 PAD06/AN06 VDD1 5 32 PAD05/AN05 VSS1 6 31 PAD04/AN04 30 PAD03/AN03 MC9S12C-Family 48 LQFP XIRQ/PE0 IRQ/PE1 TEST/VPP XTAL 24 25 23 12 22 PB4 EXTAL PA0 21 26 20 11 VSSPLL MODC/BKGD 19 PAD00/AN00 XFC 27 18 10 VDDPLL IOC7/PT7 17 PAD01/AN01 RESET 28 16 9 VDDR IOC6/PT6 15 PAD02/AN02 VSSR 29 14 8 ECLK/PE4 IOC5/PT5 13 7 XCLKS/PE7 PW4/IOC4/PT4 Figure 10. Pin Assignments for 48-pin LQFP for MC9S12C-Family MC9S12C-Family, Rev. 5 Freescale Semiconductor 15 Package Mechanical Information 7 Package Mechanical Information Refer to the following pages for detailed package dimensions. MC9S12C-Family, Rev. 5 16 Freescale Semiconductor Package Mechanical Information MC9S12C-Family, Rev. 5 Freescale Semiconductor 17 Package Mechanical Information MC9S12C-Family, Rev. 5 18 Freescale Semiconductor Package Mechanical Information MC9S12C-Family, Rev. 5 Freescale Semiconductor 19 Package Mechanical Information MC9S12C-Family, Rev. 5 20 Freescale Semiconductor Package Mechanical Information MC9S12C-Family, Rev. 5 Freescale Semiconductor 21 Package Mechanical Information MC9S12C-Family, Rev. 5 22 Freescale Semiconductor Package Mechanical Information MC9S12C-Family, Rev. 5 Freescale Semiconductor 23 Package Mechanical Information MC9S12C-Family, Rev. 5 24 Freescale Semiconductor Package Mechanical Information MC9S12C-Family, Rev. 5 Freescale Semiconductor 25 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] MC9S12CFAMPB Rev. 5, 03/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved.