FREESCALE MC33984BPNAR2

Freescale Semiconductor
Advance Information
Document Number: MC33984
Rev. 9.0, 1/2007
Dual Intelligent High-Current
Self-Protected Silicon
High-Side Switch (4.0 mΩ)
33984B
The 33984 is a dual self-protected 4.0 mΩ silicon switch used to
replace electromechanical relays, fuses, and discrete devices in
power management applications. The 33984 is designed for harsh
environments, and it includes self-recovery features. The device is
suitable for loads with high inrush current, as well as motors and all
types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the
Serial Peripheral Interface (SPI). A dedicated parallel input is
available for alternate and pulse-width modulation (PWM) control of
each output. SPI-programmable fault trip thresholds allow the device
to be adjusted for optimal performance in the application.
The 33984 is packaged in a power-enhanced 12 x 12 nonleaded
PQFN package with exposed tabs.
HIGH-SIDE SWITCH
BOTTOM VIEW
PNA SUFFIX
98ARL10521D
16-PIN PQFN
Features
• Dual 4.0 mΩ Max High-Side Switch with Parallel Input or SPI
Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control,
Watchdog Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, FailSafe Pin Status, and Program Status
• Enhanced -16 V Reverse Polarity VPWR Protection
VDD
VDD
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33984BPNA/R2
- 40°C to 125°C
16 PQFN
VDD
VPWR
33984B
VDD
I/O
FS
I/O
WAKE
SO
SI
SCLK
MCU
GND
HS1
SCLK
CS
CS
SI
SO
I/O
RST
I/O
INO
I/O
IN1
A/D
VPWR
HS0
LOAD
LOAD
CSNS
FSI
GND
Figure 1. 33984 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
Internal
Regulator
IUP
VIC
Overvoltage
Protection
CS
Programmable
Switch Delay
0 ms –525 ms
SO
SPI
3.0 MHz
Selectable Slew
Rate Gate Drive
HS0
Selectable Overcurrent
High Detection
100 A or 75 A
SI
SCLK
FS
IN[0:1]
RST
WAKE
Logic
Selectable Overcurrent Low Detection
Blanking Time
0.15 ms–155 ms
Selectable Overcurrent
Low Detection
7.5 A –25 A
Open Load
Detection
IDWN
Overtemperature
Detection
RDWN
HS0
HS1
HS1
Programmable
Watchdog
310 ms–2500 ms
VIC
IUP
Selectable
Output Current
Recopy
1/20500 or 1/41000
FSI
CSNS
GND
Figure 2. 33984 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
4
3 2
CSNS
RST
WAKE
FS
IN0
CS
FSI
SI
SCLK
SO
6 5
VDD
7
IN1
12 11 10 9 8
1
13
GND
TRANSPARENT
TOP VIEW
14
VPWR
15
HS1
16
HS0
Figure 3. 33984 Pin Connections (Transparent Top View)
Table 1. Pin Definitions
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin
Pin Name
Pin
Function
Formal Name
1
CSNS
Output
Output Current Monitoring
2
WAKE
Input
Wake
3
RST
Input
Reset (Active Low)
4
IN0
Input
Direct Input 0
5
FS
Output
Fault Status (Active Low)
This is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
6
FSI
Input
Fail-Safe Input
The value of the resistance connected between this pin and ground
determines the state of the outputs after a watchdog timeout occurs.
7
CS
Input
Chip Select (Active Low)
8
SCLK
Input
Serial Clock
This input pin is connected to the MCU providing the required bit shift
clock for SPI communication.
9
SI
Input
Serial Input
This is a command data input pin connected to the SPI Serial Data
Output of the MCU or to the SO pin of the previous device of a daisy
chain of devices.
10
VDD
Input
Digital Drain Voltage
(Power)
This is an external voltage input pin used to supply power to the SPI
circuit.
Definition
This pin is used to output a current proportional to the designated
HS0-1 output.
This pin is used to input a Logic [1] signal so as to enable the
watchdog timer function.
This input pin is used to initialize the device configuration and fault
registers, as well as place the device in a low current sleep mode.
This input pin is used to directly control the output HS0.
This input pin is connected to a chip select output of a master
microcontroller (MCU).
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PIN CONNECTIONS
Table 1. Pin Definitions (continued)
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin
Pin Name
Pin
Function
Formal Name
Definition
11
SO
Output
Serial Output
This output pin is connected to the SPI Serial Data Input pin of the
MCU or to the SI pin of the next device of a daisy chain of devices.
12
IN1
Input
Direct Input 1
This input pin is used to directly control the output HS1.
13
GND
Ground
Ground
This pin is the ground for the logic and analog circuitry of the device.
14
VPWR
Input
Positive Power Supply
This pin connects to the positive power supply and is the source input
of operational power for the device.
15
HS1
Output
High-Side Output 1
Protected 4.0 mΩ high-side power output to the load.
16
HS0
Output
High-Side Output 0
Protected 4.0 mΩ high-side power output to the load.
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
VPWR
Steady-State
V
-16 to 41
VDD Supply Voltage
VDD
-0.3 to 5.5
V
VIN[0:1], RST, FSI
- 0.3 to 7.0
V
VSO
- 0.3 to VDD + 0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
10
mA
Input/Output Voltage (1)
CSNS, SI, SCLK,
CS, FS
SO Output Voltage
(1)
Output Voltage
Positive
VHS
V
41
Negative
-15
Output Current (2)
IHS[0:1]
30
A
ECL[0:1]
0.75
J
Human Body Model (HBM)
VESD1
± 2000
Charge Device Model (CDM)
VESD3
Output Clamp Energy
ESD Voltage
(3)
(4)
V
Corner Pins (1, 12, 15, 16)
±750
All Other Pins (2, 11, 13, 14)
±500
Notes
1. Exceeding this voltage limit may cause permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4.
ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω); ESD3 testing is
performed in accordance with the Charge Device Model (CDM), Robotic (Czap=4.0pF).
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Ambient
TA
- 40 to 125
Junction
TJ
- 40 to 150
TSTG
- 55 to 150
RθJC
<1.0
RθJA
20
TPPRT
Note 7
Unit
THERMAL RATINGS
°C
Operating Temperature
Storage Temperature
Junction-to-Case
Junction-to-Ambient
Peak Package Reflow Temperature During Reflow
°C
°C/W
Thermal Resistance (5)
(6), (7)
°C
Notes
5. Device mounted on a 2s2p test board according to JEDEC JESD51-2.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
VPWR
Full Operational
VPWR Operating Supply Current
V
6.0
–
27
–
–
20
IPWR(ON)
Output ON, IHS0 and IHS1 = 0 A
VPWR Supply Current
mA
IPWR(SBY)
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
RST = VLOGIC HIGH
mA
–
–
5.0
TJ = 25°C
–
–
10
TJ = 85°C
–
–
50
4.5
5.0
5.5
No SPI Communication
–
–
1.0
3.0 MHz SPI Communication
–
–
5.0
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
µA
IPWR(SLEEP)
VDD Supply Voltage
VDD(ON)
VDD Supply Current
IDD(ON)
V
mA
VDD Sleep State Current
IDD(SLEEP)
–
–
5.0
µA
Overvoltage Shutdown Threshold
VPWR(OV)
28
32
36
V
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
5.0
5.5
6.0
V
Undervoltage Hysteresis (9)
VPWR(UVHYS)
–
0.25
–
V
Undervoltage Power-ON Reset
VPWR(UVPOR)
–
–
5.0
V
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown Threshold
(8)
Notes
8. This applies to all internal device logic supplied by VPWR and assumes the external VDD supply is within specification.
9.
This applies when the undervoltage fault is not latched (IN[0 : 1] = 0).
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VPWR = 6.0 V
–
–
6.0
VPWR = 10 V
–
–
4.0
VPWR = 13 V
–
–
4.0
Unit
POWER OUTPUT
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 25°C)
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 150°C)
RDS(ON)
mΩ
RDS(ON)
mΩ
VPWR = 6.0 V
–
–
10.2
VPWR = 10 V
–
–
6.8
VPWR = 13 V
–
–
6.8
Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25°C (10)
RDS(ON)
VPWR = -12 V
mΩ
–
–
8.0
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
SOCH = 0
IOCH0
80
100
120
SOCH = 1
IOCH1
60
75
90
000
IOCL0
21
25
29
001
IOCL1
18
22.5
27
010
IOCL2
16
20
24
011
IOCL3
14
17.5
21
IOCL4
12
15
18
IOCL5
10
12.5
15
IOCL6
8.0
10
12
IOCL7
6.0
7.5
9.0
DICR D2 = 0
CSR0
–
1/20500
–
DICR D2 = 1
CSR1
–
1/41000
–
Overcurrent Low Detection Levels (SOCL[2:0])
100
101
110
111
A
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
Current Sense Ratio (CSR0) Accuracy
–
CSR0_ACC
%
Output Current
5.0 A
- 20
–
20
10 A
-14
–
14
12.5 A
-13
–
13
15 A
-12
–
12
20 A
-13
–
13
25 A
-13
–
13
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (CONTINUED)
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
5.0 A
- 25
–
25
10 A
-19
–
19
12.5 A
-18
–
18
15 A
-17
–
17
20 A
-18
–
18
25 A
-18
–
18
4.5
6.0
7.0
30
–
100
2.0
3.0
4.0
- 20
–
-15
TSD
160
175
190
°C
TSD(HYS)
5.0
–
20
°C
Current Sense Clamp Voltage
VCL(CSNS)
CSNS Open; IHS[0:1] = 29 A
Open Load Detection Current (11)
IOLDC
Output Fault Detection Threshold
VOLD(THRES)
Output Programmed OFF
Output Negative Clamp Voltage
Overtemperature Shutdown (12)
(12)
µA
V
VCL
0.5 A < IHS[0:1] < 2.0 A, Output OFF
Overtemperature Shutdown Hysteresis
V
V
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of
an open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIH
0.7 VDD
–
–
V
VIL
–
–
0.2 VDD
V
VIN[0:1] (HYS)
100
600
1200
mV
Input Logic Pull-down Current (SCLK, IN, SI)
IDWN
5.0
–
20
µA
RST Input Voltage Range
VRST
4.5
5.0
5.5
V
SO, FS Tri-State Capacitance (15)
CSO
–
–
20
pF
RDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
7.0
–
14
- 2.0
–
- 0.3
Control Interface
Input Logic High Voltage (13)
Input Logic Low Voltage
(13)
Input Logic Voltage Hysteresis
(14)
Input Logic Pull-Down Resistor (RST) and WAKE
Input Capacitance (15)
(16)
WAKE Input Clamp Voltage
VCL(WAKE)
ICL(WAKE) < 2.5 mA
WAKE Input Forward Voltage
VF(WAKE)
ICL(WAKE) = - 2.5 mA
SO High-State Output Voltage
V
VSOH
IOH = 1.0 mA
V
0.8 VDD
FS, SO Low-State Output Voltage
0
5.0
µA
IUP
CS, VIN[0:1] > 0.7 VDD
FSI Disabled, HS[0:1] Indeterminate
0.4
µA
- 5.0
FSI Input Pin External Pull-down Resistance
0.2
ISO(LEAK)
CS > 0.7 VDD
(17)
–
V
–
SO Tri-State Leakage Current
–
VSOL
IOL = -1.6 mA
Input Logic Pull-Up Current
V
5.0
–
20
RFS
kΩ
RFSdis
–
0
1.0
FSI Enabled, HS[0:1] OFF
RFSoffoff
6.0
6.5
7.0
FSI Enabled, HS0 ON, HS1 OFF
RFSonoff
15
17
19
FSI Enabled, HS[0:1] ON
RFSonon
40
Infinite
–
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage reference to VPWR.
14.
15.
16.
17.
No hysteresis on FSI and wake pins. Parameter is guaranteed by processing monitoring but is not production tested.
Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (18)
SRRA_SLOW
9.0 V < VPWR < 16 V
0.2
(19)
Output Rising Slow Slew Rate B (DICR D3 = 0)
1.2
V/µs
0.2
0.6
1.2
SRFB_SLOW
9.0 V < VPWR < 16 V
V/µs
0.03
(18)
0.1
0.3
SRFA_FAST
9.0 V < VPWR < 16 V
V/µs
0.8
(19)
2.0
4.0
SRFB_FAST
9.0 V < VPWR < 16 V
(20)
Output Turn-OFF Delay Time in Slow Slew Rate Mode (21)
0.1
0.35
1.2
1.0
15
100
20
230
500
10
60
200
–
300
–
µs
µs
t DLY_SLOW(OFF)
DICR = 0
Output Turn-OFF Delay Time in Fast Slew Rate Mode (21)
V/µs
t DLY(ON)
DICR = 0, DICR = 1
µs
t DLY_FAST(OFF)
DICR = 1
Direct Input Switching Frequency (DICR D3 = 0)
0.1
SRFA_SLOW
(19)
Output Turn-ON Delay Time in Fast/Slow Slew Rate
4.0
V/µs
0.03
(18)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1)
1.0
SRRB_FAST
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate A (DICR D3 = 1)
0.3
V/µs
0.4
Output Falling Slow Slew Rate B (DICR D3 = 0)
0.1
SRRA_FAST
(19)
Output Falling Slow Slew Rate A (DICR D3 = 0)
1.2
V/µs
0.03
(18)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1)
0.6
SRRB_SLOW
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1)
V/µs
f PWM
Hz
Notes
18. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR - 3.5 V. These parameters are
guaranteed by process monitoring.
19. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = VPWR - 3.5 V to VPWR - 0.5 V. These parameters
are guaranteed by process monitoring.
20. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive
load.
21. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR - 0.5 V with RL = 5.0 Ω resistive load.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
t OCL0
t OCL1
t OCL2
t OCL3
108
155
202
Unit
POWER OUTPUT TIMING (CONTINUED)
Overcurrent Detection Blanking Time (OCLT [1:0])
00
01
10
11
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time
(22)
ms
7.0
10
13
0.8
1.2
1.6
0.08
0.15
0.25
t OCH
1.0
10
20
µs
t CNSVAL
–
–
10
µs
t OSD0
t OSD1
t OSD2
t OSD3
t OSD4
t OSD5
t OSD6
t OSD7
–
0
–
55
75
95
110
150
190
165
225
285
220
300
380
275
375
475
330
450
570
385
525
665
HS0 Switching Delay Time (OSD[2:0])
000
001
010
011
100
101
110
111
ms
HS1 Switching Delay Time (OSD[2:0])
000
001
010
011
100
101
110
111
ms
t OSD0
t OSD1
t OSD2
t OSD3
t OSD4
t OSD5
t OSD6
t OSD7
–
0
–
0
–
–
110
150
190
110
150
190
220
300
380
220
300
380
330
450
570
330
450
570
434
620
806
Watchdog Timeout (WD [1:0]) (23)
00
01
10
11
ms
t WDTO0
t WDTO1
t WDTO2
t WDTO3
207
310
403
1750
2500
3250
875
1250
1625
Notes
22. Time necessary for the CSNS to be within ±5% of the targeted value.
23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured
watchdog time-outs.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
3.0
MHz
t WRST
–
50
350
ns
t CS
–
–
300
ns
t ENBL
–
–
5.0
µs
t LEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (25)
t WSCLKh
–
–
167
ns
(25)
t WSCLKl
–
–
167
ns
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
Required Low State Duration for
RST (24)
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
(25)
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (25)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
(25)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (25)
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
(26)
t SI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time)
(26)
t SI(HOLD)
–
25
83
ns
–
25
50
–
25
50
t RSI
–
–
50
ns
t RSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (27)
t SO(EN)
–
–
145
ns
(28)
t SO(DIS)
–
65
145
ns
–
65
105
SO Rise Time
t RSO
CL = 200 pF
SO Fall Time
t FSO
CL = 200 pF
SI, CS, SCLK, Incoming Signal Rise Time (26)
SI, CS, SCLK, Incoming Signal Fall Time
(26)
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid (29)
0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF
Notes
24.
25.
26.
27.
28.
29.
ns
ns
t VALID
ns
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR
VPWR
0.5V V
VVPWR
PWR --0.5
SRfB
SRFB_SLOW & SRFB_FAST
SRRB_SLOW & SRRB_FAST
SRrB
VPWR
-3.5
VPWR
- 3V V
SRfA
SRFA_SLOW & SRFA_FAST
SRRA_SLOW & SRRA_FAST
SRrA
HS
0.5V 0.5
V
t DLY_SLOW(OFF) & tDLY_FAST(OFF)
Tdly(off)
t DLY(ON)
Tdly
(on)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load
Current
IOCLx
t OCH
Time
t OCLx
Figure 5. Overcurrent Shutdown
IOCH0
IOCH1
IOCL0
IOCL1
Load
Current
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
Time
t OCHx
t OCL3 t OCL2
t OCL1
t OCL0
Figure 6. Overcurrent Low and High Detection
33984
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
• During tochx, the device can reach up to Ioch0 overcurrent
level.
• During tocl3 or tocl2 or tocl1 or tocl0, the device can be
programmed to detect up to Iocl0.
Figure 6 illustrates the overcurrent detection level (Ioclx,
Iochx) the device can reach for each overcurrent detection
blanking time (tochx, toclx):
VIH
V
IH
RSTB
RST
0.2
VDD
0.2
VDD
VIL
VIL
TwRSTB
t ENBL
t WRST
tTCSB
CS
TENBL
VIH
V
0.7
VDD
0.7VDD
CS
CSB
IH
0.2
VDD
0.7VDD
VIL
V
t WSCLKh
TwSCLKh
tTlead
LEAD
IL
t RSI
TrSI
t LAG Tlag
0.70.7VDD
VDD
SCLK
SCLK
VIH
VIH
0.2 VDD
0.2VDD
VIL
V
IL
t TSIsu
SI(SU)
t WSCLKl
TwSCLKl
tTfSI
FSI
t SI(HOLD)
TSI(hold)
SI
SI
VIH
V
IH
0.7
0.7 V
VDD
DD
0.2VDD
0.2
VDD
Don’t Care
Don’t Care
Valid
Don’t Care
Valid
VIH
VIL
Figure 7. Input Timing Switching Characteristics
t FSI
t RSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
0.7 V
VDD
DD
0.20.2
VDD
VDD
VOH
VOH
VOL
VOL
Low-to-High
Low
to High
TrSO
t RSO
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
0.7VDD
VDD
High to Low 0.7
High-to-Low
0.2VDD
0.2 VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33984 is a dual self-protected 4.0 mΩ silicon switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes selfrecovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented
via the Serial Peripheral Interface (SPI). A dedicated parallel
input is available for alternate and Pulse Width Modulation
(PWM) control of each output. SPI-programmable fault trip
thresholds allow the device to be adjusted for optimal
performance in the application.
The 33984 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the
designated HS0-1 output. That current is fed into a groundreferenced resistor and its voltage is monitored by an MCU's
A/D. The channel to be monitored is selected via the SPI.
This pin can be tri-stated through SPI.
is ON. When the FSI pin is connected to GND, the watchdog
circuit and fail-safe operation are disabled. This pin
incorporates an active internal pull-up current source.
CHIP SELECT (CS)
This pin is used to input a Logic [1] signal so as to enable
the watchdog timer function. An internal clamp protects this
pin from high damaging voltages when the output is current
limited with an external resistor. This input has a passive
internal pull-down.
This input pin is connected to a chip select output of a
master microcontroller (MCU). The MCU determines which
device is addressed (selected) to receive data by pulling the
CS pin of the selected device Logic LOW, enabling SPI
communication with the device. Other unselected devices on
the serial link having their CS pins pulled-up Logic HIGH
disregard the SPI communication data sent. This pin
incorporates an active internal pull-up current source.
RESET (RST)
SERIAL CLOCK (SCLK)
This input pin is used to initialize the device configuration
and fault registers, as well as place the device in a low current
sleep mode. The pin also starts the watchdog timer when
transitioning from Logic LOW to Logic HIGH. This pin should
not be allowed to be Logic HIGH until VDD is in regulation.
This pin has a passive internal pull-down.
This input pin is connected to the MCU providing the
required bit shift clock for SPI communication. It transitions
one time per bit transferred at an operating frequency, fSPI,
defined by the communication interface. The 50 percent duty
cycle CMOS-level serial clock signal is idle between
command transfers. The signal is used to shift data into and
out of the device. This input has an active internal pull-down
current source.
WAKE (WAKE)
DIRECT IN 0 & 1 (INx)
This input pin is used to directly control the output HS0 and
1. This input has an active internal pull-down current source
and requires CMOS logic levels. This input may be
configured via SPI.
SERIAL INPUT (SI)
This is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. When a
device fault condition is detected, this pin is active LOW.
Specific device diagnostic faults are reported via the SPI SO
pin.
This is a command data input pin connected to the SPI
Serial Data Output of the MCU or to the SO pin of the
previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an active
internal pull-down current source. Device control is facilitated
by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the
falling edge of SCLK. The logic state of SI present upon the
rising edge of SCLK loads that bit command into the internal
command shift register.
FAIL-SAFE INPUT (FSI)
DIGITAL DRAIN VOLTAGE (VDD)
The value of the resistance connected between this pin
and ground determines the state of the outputs after a
watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HS0 only
This is an external voltage input pin used to supply power
to the SPI circuit. In the event VDD is lost, an internal supply
provides power to a portion of the logic, ensuring limited
FAULT STATUS (FS)
33984
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
functionality of the device. All device configuration registers
are reset.
edge of SCLK and transitions immediately on the rising edge
of SCLK.
SERIAL OUTPUT (SO)
POSITIVE POWER SUPPLY (VPWR)
This output pin is connected to the SPI Serial Data Input
pin of the MCU or to the SI pin of the next device of a daisy
chain of devices. This output will remain tri-stated (high
impedance OFF condition) so long as the CS pin of the device
is Logic HIGH. SO is only active when the CS pin of the device
is asserted Logic LOW. The generated SO output signals are
CMOS logic levels. SO output data is available on the falling
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
HIGH-SIDE OUTPUT 0 & 1 (HSx)
This pin protects 4.0 mΩ high-side power output to the
load.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33984 has four operating modes: Sleep, Normal,
Fault, and Fail-Safe. Table 5 summarizes details contained in
succeeding paragraphs.
Table 5. Fail-Safe Operation and Transitions to Other
33984 Modes
Mode
FS
WAKE
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
Normal
1
x
1
No
Normal mode. Watchdog
is active if enabled.
Fault
0
1
x
No
0
x
1
The device is currently in
Fault mode. The faulted
output(s) is (are) OFF.
1
0
1
Yes
1
1
1
1
1
0
Watchdog has timed out
and the device is in FailSafe mode. The outputs
are as configured with
the RFS resistor
connected to FSI. RST
and WAKE must be
transitioned to Logic [0]
simultaneously to bring
the device out of the FailSafe mode or
momentarily tied the FSI
pin to ground.
FailSafe
RST WDTO
Comments
x = Don’t care.
SLEEP MODE
The default mode of the 33984 is the Sleep mode. This is
the state of the device after first applying battery voltage
(VPWR), prior to any I/O transitions. This is also the state of
the device when the WAKE and RST are both Logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to Logic [0]. The device will transition to the
Normal or Fail-Safe operating modes based on the WAKE
and RST inputs as defined in Table 5.
NORMAL MODE
The 33984 is in Normal mode when:
• VPWR is within the normal voltage range.
• RST pin is Logic [1].
• No fault has occurred.
FAIL-SAFE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input pin
transitions from Logic [0] to Logic [1]. The WAKE input is
capable of being pulled up to VPWR with a series of limiting
resistance that limits the internal clamp current according to
the specification.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 14. As long as the WD bit (D7) of an
incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the
programmed value of the WDR the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-Safe mode until the
device is reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 6). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and
timing, which are reset to their default value (SOCL, SOCH,
and OCLT). Then the watchdog, overvoltage,
overtemperature, and overcurrent circuitry (with default
value) are fully operational.
Table 6. Output State During Fail-Safe Mode
RFS (kΩ)
High-Side State
0
Fail-Safe Mode Disabled
6.0
Both HS0 and HS1 OFF
15
HS0 ON, HS1 OFF
30
Both HS0 and HS1 ON
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is Logic [1] when the
device is in fail-safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST pins
from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0].
Table 5 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI pin is tied to GND, the Watchdog fail-safe
operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The two
outputs can still be driven by the direct inputs IN 1:IN0. The
33984 uses the battery input to power the output MOSFETrelated current sense circuitry and any other internal logic
providing fail-safe device operation with no VDD supplied. In
this state, the watchdog, overvoltage, overtemperature, and
overcurrent circuitry are fully operational with default values.
33984
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
FAULT MODE
The 33984 indicates the following faults as they occur by
driving the FS pin to Logic [0]:
• Overtemperature fault
• Open load fault
• Overcurrent fault (high and low)
• Overvoltage and undervoltage fault
The FS pin will automatically return to Logic [1] when the
fault condition is removed, except for Overcurrent and in
some cases Undervoltage.
Fault information is retained in the fault register and is
available (and reset) via the SO pin during the first valid SPI
communication (refer to Table 16).
PROTECTION AND DIAGNOSIS FEATURES
OVERTEMPERATURE FAULT (NON-LATCHING)
The 33984 incorporates overtemperature detection and
shutdown circuitry in each output structure. Overtemperature
detection is enabled when an output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or
until the offending load is removed.
When experiencing this fault, the OTF fault bit will be set
in the status register and cleared after either a valid SPI read
or a power reset of the device.
OVERVOLTAGE FAULT (NON-LATCHING)
The 33984 shuts down the output during an overvoltage
fault (OVF) condition on the VPWR pin. The output remains in
the OFF state until the overvoltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the bit
OD1 and cleared after either a valid SPI read or a power reset
of the device.
The overvoltage protection and diagnostic can be disabled
trough SPI (bit OV_dis).
UNDERVOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
The output(s) will latch off at some battery voltage below
6.0 V. As long as the VDD level stays within the normal
specified range, the internal logic states within the device will
be sustained.
In the case where battery voltage drops below the
undervoltage threshold (VPWRUV) output will turn off, FS will
go to Logic [0], and the fault register UVF bit will be set to 1.
Two cases need to be considered when the battery level
recovers :
• If output(s) command is (are) low, FS will go to Logic [1]
but the UVF bit will remain set to 1 until the next read
operation.
• If the output command is ON, then FS will remain at
Logic [0]. The output must be turned OFF and ON again
to re-enable the state of output and release FS . The
UVF bit will remain set to 1 until the next read operation.
The undervoltage protection can be disabled through SPI
(bit UV_dis = 1). In this case, the FS and UVF bit do not report
any undervoltage fault condition and the output state will not
be changed as long as battery voltage does not drop any
lower than 2.5 V.
OPEN LOAD FAULT (NON-LATCHING)
The 33984 incorporates open load detection circuitry on
each output. Output open load fault (OLF) is detected and
reported as a fault condition when that output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
The open load protection can be disabled trough SPI (bit
OL_dis). It is recommended to disable the open load
detection circuitry (OL_dis bit sets to logic [1]) in case
of permanent open load fault condition.
OVERCURRENT FAULT (LATCHING)
The device has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent
high detection levels (IOCH) for maximum device protection.
The two selectable, simultaneously active overcurrent
detection levels, defined by IOCH and IOCL, are illustrated in
Figure 6. The eight different overcurrent low detect levels
(IOCL0 : IOCL7) are likewise illustrated in Figure 6.
If the load current level ever reaches the selected
overcurrent low detect level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the effected output OFF.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCL driver.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
REVERSE BATTERY
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gates are
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
GROUND DISCONNECT PROTECTION
disconnection. A 10K resistor needs to be added between the
wake pin and the rest of the circuitry in order to ensure that
the device turns off in case of ground disconnect and to
prevent this pin to exceed its maximum ratings
In the event the 33984 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
.
Table 7. Device Behavior in Case of Undervoltage
SPD4
(VPWR Batter Voltage) ∗∗
VPWR > VPWRUV
State
Output State
OFF
ON
OFF
OFF
FS State
1
1
1
0
1
SPI Fault Register UVF Bit
0
1 until next read
0
1
0
OFF
OFF
OFF
OFF
OFF
FS State
0
0
0
0
1
SPI Fault Register UVF Bit
1
1 until next read
1
1
0
OFF
OFF
OFF
OFF
OFF
1
1
1
1
1
Output State
FS State
SPI Fault Register UVF Bit 1 until next read 1 until next read 1 until next read 1 until next read
2.5 V > VPWR > 0V
UV Disable
IN=X
(Falling or
Rising
VPWR)
OFF
VPWRUV > VPWR > UVPOR Output State
UVPOR > VPWR > 2.5 V ∗
UV Enable
UV Enable
UV Enable
UV Enable
IN=0
IN=0
IN=1
IN=1
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
Output State
FS State
OFF
OFF
OFF
OFF
OFF
1
1
1
1
1
SPI Fault Register UVF Bit 1 until next read 1 until next read 1 until next read 1 until next read
Comments
0
UV fault is
not latched
UV fault is
not latched
0
UV fault
is latched
∗ = Typical value; not guaranteed
∗∗ = While VDD remains within specified range.
33984
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI PROTOCOL DESCRIPTION
to D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 8. Register addressing and configuration are described
in Table 9. The SI input has an active internal pull-down,
IDWN.
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI / SO pins of the 33984 follow a first-in first-out (D7/
D0) protocol with both input and output words transferring the
most significant bit (MSB) first. All inputs are compatible with
5.0 V CMOS logic levels.
The SPI lines perform the following functions:
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high impedance state until
the CS pin is put into a Logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes states on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and Input Status descriptions are provided in
Table 5.
SERIAL CLOCK (SCLK)
Serial clocks (SCLK) the internal shift registers of the
33984 device. The serial input (SI) pin accepts data into the
input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic low state whenever
CS makes any transition. For this reason, it is recommended
that the SCLK pin be in a Logic [0] state whenever the device
is not accessed (CS Logic [1] state). SCLK has an active
internal pull-down, IDWN. When CS is Logic [1], signals at the
SCLK and SI pins are ignored and SO is tri-stated (high
impedance). See Figure 9 and Figure 10.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a Logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device
latches in data from the Input shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS
is Logic [0]. CS should transition from a Logic [1] to a Logic [0]
state only when SCLK is a Logic [0]. CS has an active internal
pull-up, IUP.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. SI
instruction is read on the falling edge of SCLK. An 8-bit
stream of serial data is required on the SI pin, starting with D7
CSB
CS
SCLK
SI
SO
SO
NOTES:
1.
D7
OD7
D6
OD6
D5
OD5
D4
OD4
D3
OD3
D2
OD2
D1
OD1
D0
OD0
RSTB
RST is in a logic 1 state during the above operation.
Logic
[1] relate
state to
during
therecent
above
operation.
Notes
2. 1.
D0,RST
D1, is
D2,a ...,
and D7
the most
ordered
entry of data into the SPSS
D7:D0
to and
the OD7
mostrelate
recent
ordered
entry
of datafault
intoand
thestatus
device.
3. 2.
OD0,
OD1,relate
OD2, ...,
to the
first 8 bits
of ordered
data out
of
the
device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 9. Single 8-Bit Word SPI Communication
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
C S B
CS
SSCLK
C L K
SI
S I
D 7
SSO
O
O D 7
D 6
D 5
O D 6
D 2
O D 5
O D 2
D 1
D 0
O D 1
O D 0
D 7 *
D 6 *
D 7
D 5 *
D 6
D 2 *
D 5
D 1 *
D 2
D 0 *
D 1
D 0
.
ST T B i s i n a l o g i c 1 s t a t e d u r i n g t h e a b o v e o p e r a t i o n .
RRSis
Notes 1.12 RST
a Logic [1] state during the above operation.
.
D 0 , D 1 , D 2 , . .., a n d D 7 r e la t e t o t h e m o s t r e c e n t o r d e r e d e n tr y o f d a ta in to th e S P S S
.
O D 0 , O D 1 , O D 2 , . . ., a n d O D 7 r e la t e t o t h e fir s t 8 b it s o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic e .
2.34 D7:D0
relate to the most recent ordered entry of data into the device.
.
O D 0 , O D 1 , O D 2 , .. ., a n d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the Ffirst
8 bits of ordered fault and status data out of the device.
I G U R E 4 b . M U L T I P L E 8 b it W O R D S P I C O M M U N I C A T I O N
N O T E S :
Figure 10. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit
messages. A message is transmitted by the MCU starting
with the MSB, D7, and ending with the LSB, D0 (Table 8).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB (D7)
is the watchdog bit and in some cases a register address bit
common to both outputs or specific to an output; the next
three bits, D6 : D4, are used to select the command register;
and the remaining four bits, D3 : D0, are used to configure and
control the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 9, summarizes the SI registers. The registers are
addressed via D6 : D4 of the incoming SPI word (Table 8).
Table 8. SI Message Bit Assignment(continued)
LSB
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
D0
Table 9. Serial Input Address and Configuration Bit Map
SI
Register D7 D6 D5 D4
MSB
Message Bit Description
D3
D2
D1
D0
SOA2
SOA1
SOA0
STATR
s
0
0
0
0
OCR
x
0
0
1
CSNS1
IN1_SPI CSNS0 IN0_SPI
EN
EN
SOCHLR s
0
1
0
SOCHs SOCL2s SOCL1s SOCL0s
CDTOLR s
0
1
1
OL_DIS CD_DIS OCLT1s OCLT0 s
s
s
DICR
s
1
0
0
FAST
SR s
CSNS
high s
IN DIS s
A/Os
OSDR
0
1
0
1
0
OSD2
OSD1
OSD0
WDR
1
1
0
1
0
0
WD1
WD0
Table 8. SI Message Bit Assignment
Bit Sig SI Msg Bit
Serial Input Data
Register address bit for output selection.
Also used for Watchdog: toggled to satisfy
watchdog requirements.
NAR
0
1
1
0
0
0
0
0
UOVR
1
1
1
0
0
0
UV_dis
OV_dis
D6 : D4
Register address bits.
TEST
x
1
1
1
D3 : D1
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
D7
Freescale Internal Use (Test)
x = Don’t care.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =
HS1.
33984
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
Address x000 — Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2:D0, determine the content of the first eight bits of SO data.
When register content is specific to one of the two outputs, bit
D7 is used to select the desired output (SOA3). In addition to
the device status, this feature provides the ability to read the
content of the OCR, SOCHLR, CDTOLR, DICR, OSDR,
WDR, NAR, and UOVR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data).)
Address x001 — Output Control Register (OCR)
The OCR register allows the MCU to control the outputs
through the SPI. Incoming message bit D0 reflects the
desired states of the high-side output HS0 (IN0_SPI): a
Logic [1] enables the output switch and a Logic [0] turns it
OFF. A Logic [1] on message bit D1 enables the Current
Sense (CSNS) pin. Similarly, incoming message bit D2
reflects the desired states of the high-side output HS1
(IN1_SPI): Logic [1] enables the output switch and a Logic [0]
turns it OFF. A Logic [1] on message bit D3 enables the
CSNS pin. In the event that the current sense is enabled for
both outputs, the current will be summed. Bit D7 is used to
feed the watchdog if enabled.
Address x010— Select Overcurrent High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels,
respectively. Each output is independently selected for
configuration based on the state of the D7 bit; a write to this
register when D7 is Logic [0] will configure the current
detection levels for the HS0. Similarly, if D7 is Logic [1] when
this register is written, HS1 is configured. Each output can be
configured to different levels. In addition to protecting the
device, this slow blow fuse emulation feature can be used to
optimize the load requirements matching system
characteristics. Bits D2 : D0 set the overcurrent low detection
level to one of eight possible levels, as shown in Table 10.
Bit D3 sets the overcurrent high detection level to one of two
levels, which is described inTable 11.
Table 10. Overcurrent Low Detection Levels
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
0
0
0
25
0
0
1
22.5
0
1
0
20
0
1
1
17.5
1
0
0
15
1
0
1
12.5
1
1
0
10
1
1
1
7.5
Table 11. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection
(Amperes)
0
100
1
75
Address x011 — Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state
of the D7 bit. A write to this register when bit 7 is Logic [0] will
configure the timeout for the HS0. Similarly, if D7 is Logic [1]
when this register is written, then HS1 is configured. Bits
D1: D0 allow the MCU to select one of four fault blanking
times defined in Table 12. Note that these time-outs apply
only to the overcurrent low detection levels. If the selected
overcurrent high level is reached, the device will latch off
within 20 µs.
Table 12. Overcurrent Low Detection Blanking Time
OCLT [1:0]
Timing
00
155 ms
01
10 ms
10
1.2 ms
11
150 µs
A Logic [1] on bit D2 disables the overcurrent low (CD_dis)
detection timeout feature. A Logic [1] on bit D3 disables the
open load (OL) detection feature.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address x100 — Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of each output. Each
output is independently selected for configuration based on
the state of bit D7. A write to this register when bit D7 is
Logic [0] will configure the direct input control for the HS0.
Similarly, if D7 is Logic [1] when this register is written, then
HS1 is configured.
A Logic [0] on bit D1 will enable the output for direct control
by the IN pin. A Logic [1] on bit D1 will disable the output from
direct control. While addressing this register, if the input was
enabled for direct control, a Logic [1] for the D0 bit will result
in a Boolean AND of the IN pin with its corresponding D0
message bit when addressing the OCR register. Similarly, a
Logic [0] on the D0 pin results in a Boolean OR of the IN pin
with the corresponding message bits when addressing the
OCR register.
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d
at the same frequency and duty cycle with only one PWM
signal. This type of operation can be accomplished by
connecting the pertinent direct IN pins of several devices to a
PWM output port from the MCU and configuring each of the
outputs to be controlled via their respective direct IN pin. The
DICR is then used to Boolean AND the direct IN(s) of each of
the outputs with the dedicated SPI bit that also controls the
output. Each configured SPI bit can now be used to enable
and disable the common PWM signal from controlling its
assigned output.
A Logic [1] on bit D2 is used to select the high ratio (CSR1,
1/41000) on the CSNS pin for the selected output. The
default value [0] is used to select the low ratio (CSR0,
1/20500). A Logic [1] on bit D3 is used to select the high
speed slew rate for the selected output. The default value [0]
corresponds to the low speed slew rate.
Address 0101 — Output Switching Delay Register (OSDR)
The OSDR register configures the device with a
programmable time delay that is active during Output ON
transitions initiated via SPI (not via direct input).
A write to this register configures both outputs for different
delay. Whenever the input is commanded to transition from
Logic [0] to Logic [1], both outputs will be held OFF for the
time delay configured in the OSDR. The programming of the
contents of this register have no effect on device fail-safe
mode operation. The default value of the OSDR register is
000, equating to no delay. This feature allows the user a way
to minimize inrush currents, or surges, thereby allowing loads
to be switched ON with a single command. There are eight
selectable output switching delay times that range from 0 ms
to 525 ms. Refer to Table 13.
Table 13. Switching Delay
OSD [2:0] (D2 : D0)
Turn ON Delay (ms) Turn ON Delay (ms)
HS0
HS1
000
0
0
001
75
0
010
150
150
011
225
150
100
300
300
101
375
300
110
450
450
111
525
450
Address 1101 — Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1:D0. When D1:D0 bits are programmed for the desired
watchdog timeout period, the WD bit (D7) should be toggled
as well, ensuring the new timeout period is programmed at
the beginning of a new count sequence. Refer to Table 14.
Table 14. Watchdog Timeout
WD [1:0] (D1: D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
Address 0110 — No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows
devices to not be affected by commands being clocked over
a daisy-chained SPI configuration, and by toggling the WD bit
(D7), the watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
Address 1110 — Undervoltage/Overvoltage Register
(UOVR)
The UOVR register can be used to disable or enable
overvoltage and/or undervoltage protection. By default
(Logic [0]), both protections are active. When disabled, an
undervoltage or overvoltage condition fault will not be
reported in the output fault register.
Address x111 — TEST
The TEST register is reserved for test and is not
accessible with SPI during normal operation.
33984
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SERIAL OUTPUT COMMUNICATION
(DEVICE STATUS RETURN DATA)
to the MCU during the first SPI communication following
this condition should be ignored.
When the CS pin is pulled low, the output status register is
loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI pin. The first
eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI
word.
Any bits clocked out of the SO pin after the first eight will
be representative of the initial message bits clocked into the
SI pin since the CS pin first transitioned to a Logic [0]. This
feature is useful for daisy chaining devices as well as
message verification.
A valid message length is determined following a CS
transition of Logic [0] to Logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A
valid message length is a multiple of eight bits. At this time,
the SO pin is tri-stated and the fault status register is now
able to accept new fault status information.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a Logic [0] during SPI communication and / or for the
period of time since the last valid SPI communication, with
the following exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
communication following an undervoltage VPWR
condition should be ignored.
• The RST pin transition from a Logic [0] to Logic [1] while
the WAKE pin is at Logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted
SERIAL OUTPUT BIT ASSIGNMENT
The 8 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 15 summarizes the SO register content.
Bit OD7 reflects the state of the watchdog bit (D7)
addressed during the prior communication. The value of the
previous D7 will determine which output the status
information applies to for the Fault (FLTR), SOCHLR,
CDTOLR, and DICR registers. SO data will represent
information ranging from fault status to register contents,
user selected by writing to the STATR bits D2:D0. Note that
the SO data will continue to reflect the information for each
output (depending on the previous D7 state) that was
selected during the most recent STATR write until changed
with an updated STATR write.
Previous Address SOA[2:0] = 000
If the previous three MSBs are 000, bits OD6 : OD0 will
reflect the current state of the Fault register (FLTR)
corresponding to the output previously selected with the bit
OD7 (Table 16).
Previous Address SOA[2:0] = 001
Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI
programmed bits, respectively. Data in bits OD3:OD2 contain
CSNS0 EN and IN0_SPI programmed bits, respectively.
Previous Address SOA[2:0] = 010
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to Table 11), and the data in bits
OD2:OD0 contain the programmed overcurrent low detection
levels (refer to Table 12).
Table 15. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
0
0
0
s
OTFs
OCHFs
OCLFs
OLFs
UVF
OVF
FAULTs
x
0
0
1
x
0
0
1
CSNS1 EN
IN1_SPI
CSNS0 EN
IN0_SPI
s
0
1
0
s
0
1
0
SOCHs
SOCL2s
SOCL1s
SOCL0s
s
0
1
1
s
0
1
1
OL_DIS s
CD_DIS s
OCLT1s
OCLT0s
s
1
0
0
s
1
0
0
FAST SR s CSNS high s
0
1
0
1
0
1
0
1
FSM_HS0
1
1
0
1
1
1
0
1
FSM_HS1
WDTO
WD1
WD0
0
1
1
0
0
1
1
0
IN1 Pin
IN0 Pin
FSI Pin
WAKE Pin
1
1
1
0
1
1
1
0
–
–
UV_dis
OV_dis
x
1
1
1
–
–
–
–
–
–
–
–
OSD2
IN DIS s
A/O s
OSD1
OSD0
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
x = Don’t care.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Previous Address SOA[2:0] = 101
Table 16. Fault Register
OD7
OD6
s
OTF
OD5
OD4
OCHFs OCLFs
OD3
OD2
OD1
OD0
OLFs
UVF
OVF
FAULTs
OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
OD6 (OTF) = Overtemperature Flag.
OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.)
OD3 (OLFs) = Open Load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULTs) = This flag reports a fault and is reset by a read
operation.
Note The FS pin reports a fault. For latched faults, this pin is reset by
a new Switch ON command (via SPI or direct input IN).
Previous Address SOA[2:0] = 011
Data returned in bits OD1 and OD0 are current values for
the overcurrent fault blanking time, illustrated in Table 12. Bit
OD2 reports if the overcurrent detection timeout feature is
active. OD3 reports if the open load circuitry is active.
Previous Address SOA[2:0] =100
The returned data contain the programmed values in the
DICR.
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS0) reflects the
state of the output HS0 in the Fail-Safe mode after a
watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status
of the watchdog circuitry. If WDTO bit is Logic [1], the
watchdog has timed out and the device is in Fail-Safe
mode. If WDTO is Logic [0], the device is in Normal
mode (assuming the device is powered and not in Sleep
mode), with the watchdog either enabled or disabled.
Bit OD3 (FSM_HS1) reflects the state of the output HS1
in the Fail-Safe mode after a watchdog timeout occurs.
Previous Address SOA[2:0] = 110
• SOA3 = 0. OD3:OD0 return the state of the IN1, IN0,
FSI, and WAKE pins, respectively (Table 17).
Table 17. Pin Register
OD3
OD2
OD1
OD0
IN1 Pin
IN0 Pin
FSI Pin
WAKE Pin
• SOA3 = 1. The returned data contain the programmed
values in the UOVR. Bit OD1 reflects the state of the
undervoltage protection and bit OD0 reflects the state of
the overvoltage protection. Refer to Table 15).
Previous Address SOA[2:0] =111
Null Data. No previous register Read Back command
received, so bits OD2:OD0 are null, or 000.
33984
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
VPWR
VDD
Voltage
Regulator
VDD
VDD NC VPWR
2.2 k
VDD
VPWR
10 k
MCU
10
100nF
10k
4
10k
12
10k
10k
8
10k
7
3
11
10k
9
5
1
6
1k
VPWR
14
2.5µF
2
I/O
I/O
SCLK
CS
I/O
SI
SO
I/O
A/D
VDD
10µF
WAKE
IN0
IN1
SCLK
CS
HS1
10nF
15
33984B
RST
SO
SI
FS
CSNS
FSI
HS0
16
LOAD
GND
LOAD
13
RFSI
Figure 11. Typical Applications
OUTPUT CURRENT MONITORING
This section relates to the output current monitoring for
33984, Dual 4mΩ High-Side Switch. This device is a selfprotected silicon switch used to replace electromechanical
relays, fuses, and discrete circuits in power management
applications. The MC33984 features a current recopy which
is proportional to the load current. It can be configured
between 2 ratios via SPI (CSR0 and CSR1).
This section presents the current recopy tolerance of the
device and the improvement of this feature with the
calibration practice.
CURRENT RECOPY TOLERANCE
The Current Sense Ratio Accuracies described page 8
and 9 (CSR0_ACC and CSR1_ACC) take into account:
• part to part deviation due to manufacturing,
• ambient temperature derating (from -40°C to 125°C),
• battery voltage range (from 9V to 16V).
Thanks to statistical data analysis performed on 3
production lots (initial testing only), the effect of each
contributor has been demonstrated.
Figure 12 shows the CSR0 tolerance in function to 3
previous listed contributors in comparison to the minimum
and maximum specified values.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
OUTPUT CURRENT MONITORING
tolerance will be about 8.5% versus 10% when all
contributors are considered.
Current Recopy at Vbat=9V/16V from -40°C to
125°C
24000
Spec_max
22000
21000
Current Recopy at Vbat=9V at 25°C
Max(Data_9V) at 6 sigmas
24000
Max(Data_16V) at 6 sigmas
10%
Spec_max
23000
Max(Data) at 6 sigmas
Average (Data)
20000
Min(Data_16V) at 6 sigmas
19000
Min(Data_9V) at 6 sigmas
18000
Spec_min
17000
16000
10
15
20
Output current (A)
CSNS ratio (CSR0)
CSNS ratio (CSR0)
23000
22000
8.5%
21000
Average (Data)
20000
19000
Min(Data) at 6 sigmas
18000
Spec_min
25
17000
Figure 12. CSR0 ratio deviation in function all
contributors
Lower VPWR Voltage causes more error. 9.0V
corresponding to the worst case. Figure 13 shows the CSR0
tolerance without battery variation effect.
16000
10
15
20
25
Output current (A)
Figure 14. CSR0 ratio deviation in function
manufacturing
PART CALIBRATION
With a calibration strategy, the part to part contribution can
be removed.
An experiment was done on low output current values
(below 5.0A). The relative CSR0 deviation based on only one
calibration point per output (5.0A, VPWR=16V at 25°C) has
been performed on 3 production lots. Those parts have
tested at initial and after High Temperature Operating Life
test in order to take into account the ageing of devices.
Table 18 summaries test results covering 99.74% of parts.
Current Recopy at Vbat=9V from -40°C to 125°C
24000
CSNS ratio (CSR0)
23000
22000
21000
20000
19000
Table 18. CSR0 Precision for Several Output Current
Values with One Calibration Point at 5.0A
18000
17000
16000
10
15
20
Output current (A)
CSR0 ratio
Min
Max
0.5A
-25%
25%
1.0A
-12%
12%
2.5A
-8.0%
8.0%
5.0A
-5.0%
5.0%
25
Figure 13. CSR0 ratio deviation in function
manufacturing and temperature
The main contributor is the manufacturing deviation, as
described in Figure 14. At 15A of output current, the
33984
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
SOLDERING INFORMATION
The 33984 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The 33984 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
• Convection: 225°C +5 .0/ -0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR) / Convection: 225°C +5.0 / -0°C
The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 s to 40 s maximum.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10521D.
PNA SUFFIX
16-PIN PQFN
NONLEADED PACKAGE
98ARL10521D
ISSUE C
33984
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33984
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33984 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
HIGH-SIDE SWITCH
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to RθJ21
and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
.
RθJA21 RθJA22
P1
P2
PNA SUFFIX
98ARL10521D
16-PIN PQFN
12 mm x 12 mm
Note For package dimensions, refer to
the 33984 data sheet.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 1. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RθJAmn (1) (2)
20
16
39
(2) (3)
6.0
2.0
26
RθJAmn (1) (4)
53
40
72
<0.5
0.0
1.0
1.0
0.2
RθJBmn
RθJCmn (5)
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7 and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad; “infinite” heat sink attached to exposed pad.
1.0
0.2
* All measurements
are in millimeters
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
Figure 1. Surface Mount for Power PQFN
with Exposed Pads
33984
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
AA
Transparent Top View
RST
WAKE
CSNS
FS
CS
FSI
IN0
SCLK
SI
SO
6 5
VDD
7
IN1
12 11 10 9 8
4
3
2
1
13
GND
A
14
VPWR
15
HS1
16
HS0
33984 Pin Connections
16-Pin PQFN
0.90 mm Pitch
12.0 mm x 12.0 mm Body
Figure 2. Thermal Test Board
Device on Thermal Test Board
Material:
Outline:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
80 mm x 100 mm board area,
including edge connector for
thermal testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Table 2. Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (°C/W)
Thermal
Resistance
RθJAmn
Area A
(mm2)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
55
42
74
300
41
31
66
600
38
29
64
RθJA is the thermal resistance between die junction and
ambient air.
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
80
Thermal Resistance [ºC/W]
70
60
50
40
30
x
20
RθJA11
RθJA22
RθJA12 = RθJA21
10
0
0
300
600
Heat spreading area A [mm²]
Figure 3. Device on Thermal Test Board RθJA
Thermal Resistance [ºC/W]
100
10
x
1
0.1
1.00E-03
1.00E-02
RθJA11
RθJA22
RθJA12 = RθJA21
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 4. Transient Thermal Resistance RθJA (1 W Step Response)
Device on Thermal Test Board Area A = 600 (mm2)
33984
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
•
•
•
•
•
•
Implemented Revision History page
Deletion of MC33984 part number, replaced with MC33984B.
Corrected Pin Connections to the proper case outline
Added final sentence to Open Load Fault (Non-Latching)
Corrected heading labels on Input Timing Switching Characteristics
Changed labels in the Typical Applications drawing
Corrected Package Dimensions to Revision C
Added Thermal Addendum (rev 2.0).
6.0
2/2006
7.0
5/2006
8.0
1/2007
• Added RoHS logo
9.0
1/2007
• Changed several names on the Typical Applications on page 27
• Added section Output current monitoring on page 27
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
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MC33984
Rev. 9.0
1/2007
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