MOTOROLA MC33982

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33982/D
Rev 7.0, 03/2004
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33982
Single Intelligent High-Current
Self-Protected Silicon High-Side
Switch (2.0 mΩ)
SINGLE HIGH-SIDE SWITCH
2.0 mΩ
Freescale Semiconductor, Inc...
The 33982 is a self-protected silicon 2.0 mΩ high-side switch used to
replace electromechanical relays, fuses, and discrete devices in power
management applications. The 33982 is designed for harsh environments,
and it includes self-recovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and pulse width modulation (PWM) control of the output. SPI programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.
The 33982 is packaged in a power-enhanced 12 x 12 PQFN package with
exposed tabs.
PNA SUFFIX
CASE 1402-02
16-TERMINAL
PQFN
SCALE 1:1
Features
• Single 2.0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring Output with Two SPI-Selectable Current
Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature Shutdown, Undervoltage and Overvoltage Shutdown,
Fail-Safe Terminal Status, and Program Status
• Enhanced 16 V Reverse Polarity VPWR Protection
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33982PNA/R2
-40°C to 125°C
16 PQFN
Simplified
Application
Diagram Diagram
33982
Simplified
Application
VDD
VDD
VPWR
VDD
33982
VDD
I/O
I/O
SO
SCLK
MCU
CS
SI
I/O
I/O
A/D
VPWR
FS
WAKE
SI
SCLK
CS
HS
SO
RST
IN
CSNS
FSI GND
GND
GND
LOAD
PWRGND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
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VDD
VPWR
Internal
Regulator
Programmable
Switch Delay
0 ms–525 ms
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CS
SCLK
SO
SI
RST
WAKE
IN
FS
Overvoltage
Protection
Selectable Slew
Rate Gate Drive
HS
SPI
3.0 MHz
Logic
Selectable Current
Limit
150 A or 100 A
Selectable Current
Detection Time
0.15 ms–155 ms
Selectable Overcurrent Detection
15 A–50 A
Open Load
Detection
FSI
Programmable
Watchdog
310 ms–2500 ms
Overtemperature
Detection
Selectable
Output Current
Recopy
1/5400 or 1/40000
GND
CSNS
Figure 1. 33982 Simplified Internal Block Diagram
33982
2
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Transparent Top View of Package
CSNS
WAKE
RST
IN
FS
FSI
CS
SCLK
SI
VDD
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SO
NC
1
2
3
4
5
13
6
7 GND
8
9
10
11
12
16
HS
15
HS
14
VPWR
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
Definition
1
CSNS
Output Current Monitoring
This terminal is used to output a current proportional to the high-side output current and
used externally to generate a ground-referenced voltage for the microcontroller to
monitor output current.
2
WAKE
Wake
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects this terminal from high damaging voltages when the
output is current limited with an external resistor. This input has an internal passive
pull-down.
3
RST
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers, as
well as place the device in a low current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should
not be allowed to be logic HIGH until VDD is in regulation. This terminal has an internal
passive pull-down.
4
IN
Serial Input
The Input terminal is used to directly control the output. This input has an internal active
pull-down and requires CMOS logic levels. This input may be configured via SPI.
5
FS
Fault Status (Active Low)
This is an open drain configured output requiring an external pull-up resistor to VDD for
fault reporting. When a device fault condition is detected, this terminal is active LOW.
Specific device diagnostic faults are reported via the SPI SO terminal.
6
FSI
Fail-Safe Input
The value of the resistance connected between this terminal and ground determines
the state of the output after a watchdog timeout occurs. Depending on the resistance
value, either the output is OFF or ON. When the FSI terminal is connected to GND, the
watchdog circuit and fail-safe operation are disabled. This terminal incorporates an
active internal pull-up.
7
CS
Chip Select (Active Low)
This is an input terminal connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the CS terminal of the selected device logic LOW, enabling SPI communication
with the device. Other unselected devices on the serial link having their CS terminals
pulled up logic HIGH disregard the SPI communication data sent.
8
SCLK
Serial Clock
This input terminal is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level
serial clock signal is idle between command transfers. The signal is used to shift data
into and out of the device.
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal
Name
Formal Name
Definition
9
SI
Serial Input
This is a command data input terminal connected to the SPI Serial Data Output of the
MCU or to the SO terminal of the previous device in a daisy chain of devices. The input
requires CMOS logic level signals and incorporates an internal active pull-down. Device
control is facilitated by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the falling edge of SCLK. The logic
state of SI present upon the rising edge of SCLK loads that bit command into the
internal command shift register.
10
VDD
Digital Drain Voltage
(Power)
This is an external voltage input terminal used to supply power to the SPI circuit. In the
event VDD is lost, an internal supply provides power to a portion of the logic, ensuring
limited functionality of the device.
11
SO
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the MCU
or to the SI terminal of the next device in a daisy chain of devices. This output will
remain tri-stated (high impedance OFF condition) so long as the CS terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data is
available on the falling edge of SCLK and transitions immediately on the rising edge of
SCLK.
12
NC
No Connect
This terminal may not be connected.
13
GND
Ground
14
VPWR
Positive Power Supply
This terminal connects to the positive power supply and is the source input of
operational power for the device. The VPWR terminal is a backside surface mount tab
of the package.
15, 16
HS
High-Side Output
Protected high-side power output to the load. Output terminals must be connected in
parallel for operation.
33982
4
This terminal is the ground for the logic and analog circuitry of the device.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Operating Voltage Range
Value
VPWR
V
-16 to 41
Steady-State
VDD Supply Voltage
VDD
0 to 5.5
V
VIN, RST, FSI,
CSNS, SI, SCLK,
CS, FS
-0.3 to 7.0
V
SO Output Voltage (Note 1)
VSO
-0.3 to VDD +0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
10
mA
Output Current (Note 2)
IOUT
60
A
Output Clamp Energy (Note 3)
ECL
1.5
J
Storage Temperature
TSTG
-55 to 150
°C
TJ
-40 to 150
°C
Junction to Case
RθJC
<1.0
Junction to Ambient
RθJA
20
Human Body Model (Note 5)
VESD1
±2000
Machine Model (Note 6)
VESD2
±200
TSOLDER
240
Input/Output Voltage (Note 1)
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Unit
Operating Junction Temperature
°C/W
Thermal Resistance (Note 4)
ESD Voltage
V
Terminal Soldering Temperature (Note 7)
°C
Notes
1. Exceeding voltage limits on IN, RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to the
device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4.
5.
Device mounted on a 2s2p test board according to JEDEC JESD51-2.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
6.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from HS to GND.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
6.0
–
27
–
–
20
Unit
POWER INPUT
Battery Supply Voltage Range
VPWR
Full Operational
IPWR(ON)
VPWR Operating Supply Current
Output ON, IOUT = 0 A
VPWR Supply Current
mA
IPWR(SBY)
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
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V
RST = VLOGIC HIGH
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
mA
–
–
5.0
–
–
10
–
–
50
4.5
5.0
5.5
µA
IPWR(SLEEP)
TJ = 25°C
TJ = 85°C
VDD Supply Voltage
VDD(ON)
VDD Supply Current
IDD(ON)
V
mA
No SPI Communication
–
–
1.0
3.0 MHz SPI Communication
–
–
5.0
VDD Sleep State Current
IDD(SLEEP)
–
–
5.0
µA
Overvoltage Shutdown
VPWR(ON)
28
32
36
V
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
5.0
5.5
6.0
V
Undervoltage Hysteresis (Note 9)
VPWR(UVHYS)
–
0.25
–
V
Undervoltage Power-ON Reset
VPWR(UVPOR)
–
–
5.0
V
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown (Note 8)
Notes
8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
9.
33982
6
This applies when the undervoltage fault is not latched (IN = 0).
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT
Output Drain-to-Source ON Resistance (IOUT = 30 A, TJ = 25°C)
mΩ
VPWR = 6.0 V
–
–
3.0
VPWR = 10 V
–
–
2.0
VPWRR = 13 V
–
–
2.0
Output Drain-to-Source ON Resistance (IOUT = 30 A, TJ = 150°C)
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RDS(ON)25
mΩ
RDS(ON)150
VPWR = 6.0 V
–
–
5.1
VPWR = 10 V
–
–
3.4
VPWR = 13 V
–
–
3.4
–
2.0
4.0
Output Source-to-Drain ON Resistance (IOUT = 30 A, TJ = 25°C) (Note 10)
RDS(ON)
VPWR = -12 V
mΩ
A
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
SOCH = 0
IOCH0
120
150
180
SOCH = 1
IOCH1
80
100
120
A
Overcurrent Low Detection Levels (SOCL[2:0])
000
IOCL0
41
50
59
001
IOCL1
36
45
54
010
IOCL2
32
40
48
011
IOCL3
29
35
41
100
IOCL4
25
30
35
101
IOCL5
20
25
30
110
IOCL6
16
20
24
111
IOCL7
12
15
18
DICR D2 = 0
CSR0
–
1/5400
–
DICR D2 = 1
CSR1
–
1/40000
–
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
%
CSR0_ACC
Current Sense Ratio (CSR0) Accuracy
Output Current
-20
–
20
20 A
-14
–
14
25 A
-13
–
13
30 A
-12
–
12
40 A
-13
–
13
50 A
-13
–
13
10 A
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (continued)
Output Current
-25
–
25
20 A
-19
–
19
25 A
-18
–
18
30 A
-17
–
17
40 A
-18
–
18
50 A
-18
–
18
4.5
6.0
7.0
30
–
100
2.0
3.0
4.0
-20
–
–
160
175
190
5.0
–
20
10 A
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%
CSR1_ACC
Current Sense Ratio (CSR1) Accuracy
Maximum Current Sense Clamp Voltage
V
VCL(MAXCSNS)
ICSNS = 15 mA
Open Load Detection Current (Note 11)
IOLDC
Output Fault Detection Threshold
VOLD(THRES)
Output Programmed OFF
V
VCL
Output Negative Clamp Voltage
0.5 A < = IOUT < = 2.0 A, Output OFF
V
°C
TSD
Overtemperature Shutdown (Note 12)
TA = 125°C, Output OFF
Overtemperature Shutdown Hysteresis (Note 12)
TSD(HYS)
µA
°C
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
33982
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic High Voltage (Note 13)
VIH
0.7VDD
–
–
V
Input Logic Low Voltage (Note 13)
VIL
–
–
0.2VDD
V
VIN(HYS)
100
350
750
mV
Input Logic Pull-Down Current (SCLK, IN, SI)
IDWN
5.0
–
20
µA
RST Input Voltage Range
VRST
4.5
5.0
5.5
V
SO, FS Tri-State Capacitance (Note 15)
CSO
–
–
20
pF
Input Logic Pull-Down Resistor (RST) and WAKE
IDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
7.0
–
14
-2.0
–
-0.3
CONTROL INTERFACE
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Input Logic Voltage Hysteresis (Note 14)
Input Capacitance (Note 15)
WAKE Input Clamp Voltage (Note 16)
VCL(WAKE)
ICL(WAKE) < 2.5 mA
WAKE Input Forward Voltage
V
VF(WAKE)
ICL(WAKE) = -2.5 mA
SO High-State Output Voltage
V
VSOH
V
0.8VDD
IOH = 1.0 mA
FS, SO Low-State Output Voltage
–
–
VSOL
IOL = -1.6 mA
V
–
0.2
0.4
-5.0
0
5.0
5.0
–
20
µA
ISO(LEAK)
SO Tri-State Leakage Current
CS > 0.7 VDD
µA
IUP
Input Logic Pull-Up Current (Note 17)
CS, VIN > 0.7VDD
FSI Input Pin External Pull-Down Resistance
RFS
kΩ
FSI Disabled, HS Indeterminate
RFSdis
–
0
1.0
FSI Enabled, HS OFF
RFSoff
6.0
10
14
FSI Enabled, HS ON
RFSon
30
–
–
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals may
be supplied by a derived voltage reference to VPWR.
14.
15.
16.
17.
Parameter is guaranteed by process monitoring but is not production tested.
Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.2
0.6
1.2
0.03
0.1
0.3
Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18)
SRRA_SLOW
9.0 V < VPWR < 16 V
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19)
SRRB_SLOW
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18)
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V/µs
SRRA_FAST
9.0 V < VPWR < 16 V
V/µs
0.4
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19)
0.6
1.2
SRFB_SLOW
V/µs
0.03
9.0 V < VPWR < 16 V
0.1
0.3
SRFA_FAST
V/µs
0.8
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19)
1.2
V/µs
0.2
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18)
0.1
SRFA_SLOW
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19)
4.0
V/µs
0.03
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18)
1.0
SRRB_FAST
9.0 V < VPWR < 16 V
9.0 V < VPWR < 16 V
V/µs
2.0
4.0
SRFB_FAST
V/µs
0.1
0.35
1.2
Notes
18. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are
guaranteed by process monitoring.
19. Rise and Fall Slow Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are
guaranteed by process monitoring.
33982
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
1.0
18
100
20
230
500
10
60
200
–
300
–
Unit
POWER OUTPUT TIMING (continued)
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20)
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21)
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µs
tDLY_FAST(OFF)
DICR = 1
Direct Input Switching Frequency (DICR D3 = 0)
µs
tDLY_SLOW(OFF)
DICR = 0
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21)
µs
tDLY(ON)
DICR = 0, DICR = 1
fPWM
Overcurrent Detection Blanking Time (OCLT[1:0])
00
01
10
11
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 22)
Hz
ms
tOCL0
tOCL1
tOCL2
tOCL3
108
155
7.0
10
202
13
0.8
1.2
1.6
0.08
0.15
0.25
tOCH
1.0
10
20
µs
CNSVAL
–
–
10
µs
Output Switching Delay Time (OSD[2:0])
ms
000
tOSD0
–
0
–
001
tOSD1
52
75
95
010
tOSD2
105
150
195
011
tOSD3
157
225
293
100
tOSD4
210
300
390
101
tOSD5
262
375
488
110
tOSD6
315
450
585
111
tOSD7
367
525
683
00
tWDTO0
434
620
806
01
tWDTO1
207
310
403
10
tWDTO2
1750
2500
3250
11
tWDTO3
875
1250
1625
Watchdog Timeout (WD[1:0]) (Note 23)
ms
Notes
20. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VOUT = 0.5 V with RL = 5.0 Ω
resistive load.
21. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VOUT = VPWR -0.5 V with
RL = 5.0 Ω resistive load.
22.
23.
Time necessary for the CSNS to be within ±5% of the targeted value.
Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
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11
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fSPI
–
–
3.0
MHz
tWRST
–
50
167
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25)
tCS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25)
tENBL
–
–
5.0
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
tLEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (Note 25)
tWSCLKh
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time) (Note 25)
tWSCLKl
–
–
167
ns
tLAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 26)
tSI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time) (Note 26)
tSI(HOLD)
–
25
83
ns
–
25
50
–
25
50
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
Freescale Semiconductor, Inc...
Required Low State Duration for RST (Note 24)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25)
tRSO
SO Rise Time
CL = 200 pF
ns
tFSO
SO Fall Time
CL = 200 pF
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 26)
tRSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 26)
tFSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 27)
tSO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance (Note 28)
tSO(DIS)
–
65
145
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 29)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
Notes
24.
25.
26.
27.
28.
29.
33982
12
tVALID
ns
–
65
105
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33982 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Timing Diagrams
CS
VPWR
VPWR
- 0.5V
VVPWR
PWR -0.5 V
VPWR
- 3VV
VPWR -3.5
SRFB
SRfB
SRRB
SRrB
SR
SRfA
FA
SRRA
SRrA
Freescale Semiconductor, Inc...
0.5V
0.5
V
t DLY(OFF)
Tdly(off)
tDLY(ON)
Tdly
(on)
Figure 2. Output Slew Rate and Time Delays
IOCHx
Load
Current
ILOAD1
ILOAD1
IOCLx
tOCH
Time
tOCLx
Figure 3. Overcurrent Shutdown
IOCH0
IOCH1
IOCL0
IOCL1
Load
Current
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
Time
tOCHx
tOCL3
tOCL2
tOCL1
tOCL0
Figure 4. Overcurrent Low and High Detection
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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13
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VIH
V
IH
RSTB
RST
0.2
VDD
0.2
VDD
VIL
VIL
TwRSTB
tWRST
tENBL
tTCSB
CS
TENBL
VIH
V
0.7
VDD
0.7VDD
CS
CSB
IH
0.7
VDD
0.7VDD
tWSCLKh
TwSCLKh
tTlead
LEAD
VIL
V
IL
tRSI
TrSI
tLAG Tlag
0.70.7VDD
VDD
SCLK
SCLK
VIH
VIH
0.2 VDD
0.2VDD
VIL
V
Freescale Semiconductor, Inc...
tSI(SU)
TSIsu
IL
tWSCLKl
TwSCLKl
tTfSI
FSI
tSI(HOLD)
TSI(hold)
SI
SI
Don’t Care
VIH
V
0.7
0.7 V
VDD
DD
0.2VDD
0.2
VDD
Don’t Care
Valid
Don’t Care
Valid
IH
VIH
VIL
Figure 5. Input Timing Switching Characteristics
tFSI
tRSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
tSO(EN)
TdlyLH
SO
SO
0.7 V
VDD
DD
0.20.2
VDD
VDD
Low-to-High
Low
to High
TrSO
tRSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
tFSO
SO
VOH
VOH
VDD
VDD
High to Low 0.70.7
High-to-Low
0.2VDD
0.2 VDD
TdlyHL
VOL
VOL
tSO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
33982
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33982 is a self-protected silicon 2.0 mΩ high-side switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33982 is
designed for harsh environments, and it includes self-recovery
features. The device is suitable for loads with high inrush
current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented via
the Serial Peripheral Interface (SPI). A dedicated parallel input
is available for alternate and pulse width modulation (PWM)
control of the output. SPI programmable fault trip thresholds
allow the device to be adjusted for optimal performance in the
application.
The 33982 is packaged in a power-enhanced 12 x 12 PQFN
package with exposed tabs.
Freescale Semiconductor, Inc...
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Clock
(SCLK), Serial Input (SI), Serial Output (SO), and Chip Select
(CS).
The SI/SO terminals of the 33982 follow a first-in first-out
(D7/D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33982 device. The serial input terminal (SI) accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output terminal (SO) shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK terminal be in a logic LOW state
whenever CS makes any transition. For this reason, it is
recommended that the SCLK terminal be in a logic [0] state
whenever the device is not accessed (CS logic [1] state). SCLK
has an internal pull-down, IDWN. When CS is logic [1], signals at
the SCLK and SI terminals are ignored and SO is tri-stated
(high impedance). (See Figure 7 and Figure 8 on page 16.)
Serial Interface (SI)
This is a serial interface (SI) command data input terminal. SI
instruction is read on the falling edge of SCLK. An 8-bit stream
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
of serial data is required on the SI terminal, starting with D7 to
D0. The internal registers of the 33982 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 1, page 16. Register addressing and configuration are
described in Table 2, page 17. The SI input has an internal pulldown, IDWN.
Serial Output (SO)
The SO terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Table 8, page 19.
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to and
receiving information from the MCU. The 33982 latches in data
from the input shift registers to the addressed registers on the
rising edge of CS. The device transfers status information from
the power output to the shift register on the falling edge of CS.
The SO output driver is enabled when CS is logic [0]. CS should
transition from a logic [1] to a logic [0] state only when SCLK is
a logic [0]. CS has an internal pull-up, IUP.
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15
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CSB
CS
SCLK
SI
D7
Freescale Semiconductor, Inc...
SO
SO
D6
OD7
D5
OD6
D4
OD5
D3
OD4
D2
OD3
D1
OD2
OD1
D0
OD0
1. RST
[1] 1state
theabove
above
operation.
Notes 1.
RSTis a
RSTB
is logic
in a logic
stateduring
during the
operation.
NOTES:
2.
D0, D1,relate
D2, ..., to
and
D7most
relaterecent
to the most
recententry
ordered
entry of
data
the SPSS
2. D7–D0
the
ordered
of data
into
theinto
device.
3.
OD0, OD1, OD2,
theordered
first 8 bitsfault
of ordered
fault and
status
outdevice.
3. OD7–OD0
relate...,toand
theOD7
firstrelate
8 bitsto of
and status
data
out data
of the
of the device.
Figure 7. Single 8-Bit Word SPI Communication
C
S B
CS
SCLK
S
C L K
SIS
I
S O
SO
D 7
O D 7
D 6
O D 6
D 5
D 2
O D 5
D 1
O D 2
D 0
O D 1
O D 0
D 7 *
D 6 *
D 7
D 5 *
D 6
D 2 *
D 5
D 1 *
D 2
D 1
D 0 *
D 0
R
T Tlogic
1 .
R SSa
B i s i[1]
n a state
l o g i c during
1 s t a t e the
d u r above
i n g t h e operation.
a b o v e o p e r a t io n .
N O T E S 1.
: RST
Notes
is
2 .
D 0 , D 1 , D 2 , . .. , a n d D 7 r e la t e t o t h e m o s t r e c e n t o r d e r e d e n t r y o f d a t a in t o t h e S P S S
3 .
O D relate
0 , O D 1
D 2most
, . . . , arecent
n d O D ordered
7 r e l a t e tentry
o t h e of
f i r sdata
t 8 b iinto
t s o f the
o r d device.
e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic e .
2. D7–D0
to, Othe
4 .
O D 0 , O D 1 , O D 2 , .. ., a n d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S
3. D7*–D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7–OD0 relate to the first 8 bits of ordered fault and status data out of the device.
F IG U R E
4 b .
M U L T IP L E
8 b it W O R D
S P I C O M M U N IC A T IO N
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
Table 1. SI Message Bit Assignment
SPI communication is accomplished using 8-bit messages.
A message is transmitted by the MCU starting with the MSB,
D7, and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB (D7) is the watchdog bit
and in some cases a register address bit; the next three bits,
D6–D4, are used to select the command register; and the
remaining four bits, D3–D0, are used to configure and control
the output and its protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable or to confirm transmitted data as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D7
Watchdog in: toggled to satisfy watchdog
requirements; also used as a register address
bit.
LSB
D6–D4
Register address bits.
D3–D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
The 33982 has defined registers, which are used to
configure the device and to control the state of the output.
Table 2, page 17, summarizes the SI registers. The registers
are addressed via D6–D4 of the incoming SPI word (Table 1).
33982
16
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Table 2. Serial Input Address and Configuration Bit Map
Freescale Semiconductor, Inc...
SI
Register D7 D6 D5 D4
Serial Input Data
Table 3. Overcurrent Low Detection Levels
D3
D2
D1
D0
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
SOA1
SOA0
0
0
0
50
CSNS EN IN_SPI
0
0
1
45
STATR
x
0
0
0
0
SOA2
OCR
x
0
0
1
0
0
SOCHLR
x
0
1
0
SOCH
SOCL2
SOCL1
SOCL0
0
1
0
40
CDTOLR
x
0
1
1
OL dis
CD dis
OCLT1
OCLT0
0
1
1
35
DICR
x
1
0
0
FAST
SR
CSNS
high
IN dis
A/O
1
0
0
30
1
0
1
25
OSDR
0
1
0
1
0
OSD2
OSD1
OSD0
1
1
0
20
WDR
1
1
0
1
0
0
WD1
WD0
1
1
1
15
NAR
0
1
1
0
0
0
0
0
UOVR
1
1
1
0
0
0
UV_dis
OV_dis
TEST
x
1
1
1
Motorola Internal Use (Test)
x = Don’t care.
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address x000—Status Register (STATR)
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits D2,
D1, and D0 determine the content of the first eight bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR, SOCHLR, CDTOLR,
DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the
section entitled Serial Output Communication (Device Status
Return Data) beginning on page 18.)
Table 4. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection
(Amperes)
0
150
1
100
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times defined
in Table 5. Note that these timeouts apply only to the
overcurrent low detection levels. If the selected overcurrent
high level is reached, the device will latch off within 20 µs.
Table 5. Overcurrent Low Detection
Blanking Time
OCLT[1:0]
Timing
Address x001—Output Control Register (OCR)
00
155 ms
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects the
desired states of the high-side output: a logic [1] enables the
output switch and a logic [0] turns it OFF. A logic [1] on
message bit D1 enables the Current Sense (CSNS) terminal.
Bits D2 and D3 must be logic [0]. Bit D7 is used to feed the
watchdog if enabled.
01
10 ms
Address x010—Select Overcurrent High and Low Register
(SOCHLR)
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
In addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2–D0 are
used to set the overcurrent low detection level to one of eight
possible levels are shown in Table 3. Bit D3 is used to set the
overcurrent high detection level to one of two levels as outlined
in Table 4.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10
1.2 ms
11
150 µs
A logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A logic [1] on bit D3 disables the open
load (OL) detection feature.
Address x100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of the output. A logic [0]
on bit D1 will enable the output for direct control by the IN
terminal. A logic [1] on bit D1 will disable the output from direct
control. While addressing this register, if the input was enabled
for direct control, a logic [1] for the D0 bit will result in a Boolean
AND of the IN terminal with its corresponding D0 message bit
when addressing the OCR register. Similarly, a logic [0] on the
D0 terminal will result in a Boolean OR of the IN terminal with
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the corresponding message bits when addressing the OCR
register.
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The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d at
the same frequency and duty cycle with only one PWM signal.
This type of operation can be accomplished by connecting the
pertinent direct IN terminals of several devices to a PWM output
port from the MCU and configuring each of the outputs to be
controlled via their respective direct IN terminal. The DICR is
then used to Boolean AND the direct IN(s) of each of the
outputs with the dedicated SPI bit that also controls the output.
Each configured SPI bit can now be used to enable and disable
the common PWM signal from controlling its assigned output.
A logic [1] on bit D2 is used to select the high ratio (CSR1,
1/40000) on the CSNS terminal. The default value [0] is used to
select the low ratio (CSR0, 1/5400). A logic [1] on bit D3 is used
to select the high-speed slew rate. The default value [0]
corresponds to the low speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register is used to configure the device with a
programmable time delay that is active during Output On
transitions that are initiated via SPI (not via direct input).
Whenever the input is commanded to transition from [0] to [1],
the output will be held OFF for the time delay configured in the
OSDR register.
The programming of the contents of this register has no
effect on device Fail-Safe mode operation. The default value of
the OSDR register is 000, equating to no delay, since the
switching delay time is 0 ms. This feature allows the user a way
to minimize inrush currents, or surges, thereby allowing loads to
be synchronously switched ON with a single command.
Table 6 shows the eight selectable output switching delay
times, which range from 0 ms to 525 ms.
Table 6. Switching Delay
OSD[2:0] (D2, D1, D0)
Timing (ms)
000
0
001
75
010
150
011
225
100
300
101
375
110
450
111
525
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1 and D0 (Table 7). When bits D1and D0 are programmed for
the desired watchdog timeout period, the WD bit (D7) should be
33982
18
toggled as well to ensure that the new timeout period is
programmed at the beginning of a new count sequence.
Table 7. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows devices
to not be affected by commands being clocked over a daisychained SPI configuration, and by toggling the WD bit (D7) the
watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
Address 1110—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register can be used to disable or enable the
overvoltage and/or undervoltage protection. By default ([0]),
both protections are active. When disabled, an undervoltage or
overvoltage condition fault will not be reported in bits D1 and D0
of the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output status register
is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI terminal. The
first eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI word.
Any bits clocked out of the SO terminal after the first eight will
be representative of the initial message bits clocked into the SI
terminal since the CS terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of eight bits. At this time, the SO terminal is tristated and the fault status register is now able to accept new
fault status information.
The output status register correctly reflects the status of the
STATR-selected register data at the time the CS is pulled to a
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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• The RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted to
the MCU during the first SPI communication following this
condition should be ignored.
logic [0] during SPI communication and/or for the period of time
since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
Serial Output Bit Assignment
The eight bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 8 summarizes the SO register content.
Freescale Semiconductor, Inc...
Table 8. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3
SOA2
SOA1
SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
x
0
0
0
WDin
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
x
0
0
1
WDin
0
0
1
0
0
CSNS EN
IN_SPI
x
0
1
0
WDin
0
1
0
SOCH
SOCL2
SOCL1
SOCL0
x
0
1
1
WDin
0
1
1
OL dis
CD dis
OCLT1
OCLT0
x
1
0
0
WDin
1
0
0
Fast SR
CSNS high
IN dis
A/O
0
1
0
1
0
1
0
1
FSM_HS
OSD2
OSD1
OSD0
1
1
0
1
1
1
0
1
0
WDTO
WD1
WD0
0
1
1
0
0
1
1
0
0
IN Terminal
FSI Terminal
WAKE Terminal
1
1
1
0
1
1
1
0
0
0
UV_dis
OV_dis
x
1
1
1
WDin
–
–
–
–
–
–
–
x = Don’t care.
Bit OD7 reflects the state of the watchdog bit (D7) addressed
during the prior communication. The contents of bits OD[6:0]
depend upon the bits D[2:0] from the most recent STATR
command SOA[2:0].
Table 9. Fault Register
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
x
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
OD7 (x) = Don’t care.
Previous Address SOA[2:0]=000
OD6 (OTF) = Overtemperature Flag.
If the previous three MSBs are 000, bits OD6–OD0 reflect
the current state of the fault register (FLTR) (Table 9).
OD5 (OCHF) = Overcurrent High Flag. (This fault is latched.)
Previous Address SOA[2:0]=001
OD3 (OLF) = Open Load Flag.
The data in bits OD1 and OD0 contain CSNS EN and IN_SPI
programmed bits, respectively.
OD4 (OCLF) = Overcurrent Low Flag. (This fault is latched.)
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULT) = This flag reports a fault and is reset by a read operation.
Previous Address SOA[2:0]=010
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to Table 4, page 17), and the data in
bits OD2, OD1, and OD0 contain the programmed overcurrent
low detection levels (refer to Table 3, page 17).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Note The FS terminal reports a fault and is reset by a new Switch-ON
command (via SPI or direct input IN).
Previous Address SOA[2:0]=011
The data returned in bits OD1 and OD0 are current values for
the overcurrent fault blanking time, illustrated in Table 5,
page 17. Bit OD2 reports when the overcurrent detection
timeout feature is active. OD3 reports whether the open load
circuitry is active.
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19
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Previous Address SOA[2:0]=100
Previous Address SOA[2:0]=110
The returned data contain the programmed values in the
DICR.
• SOA3 = 0. OD2 to OD0 return the state of the IN, FSI, and
WAKE terminals, respectively (Table 10).
Table 10. Terminal Register
Freescale Semiconductor, Inc...
Previous Address SOA[2:0]=101
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS) reflects the state
of the output in the Fail-Safe mode after a watchdog
timeout occurs.
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status of
the watchdog circuitry. If WDTO bit is [1], the watchdog
has timed out and the device is in Fail-Safe mode. If
WDTO is [0], the device is in Normal mode (assuming
device is powered and not in the Sleep mode), with the
watchdog either enabled or disabled.
OD2
OD1
OD0
IN Terminal
FSI Terminal
WAKE Terminal
• SOA3 = 1. The returned data contains the programmed
values in the UOVR register. Bit OD1 reflects the state of
the undervoltage protection, while bit OD0 reflects the
state of the overvoltage protection (refer to Table 8,
page 19).
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2, OD1, and OD0 are null, or 000.
MODES OF OPERATION
The 33982 has four operating modes. They are Sleep,
Normal, Fault, and Fail-Safe. Table 11 summarizes details
contained in succeeding paragraphs.
Table 11. Fail-Safe Operation and Transitions
to Other 33982 Modes
Mode
FS
WAKE
RST
WDTO
Comments
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
Normal
1
x
1
No
Normal mode. Watchdog
is active if enabled.
0
1
x
Fault
FailSafe
0
x
1
1
0
1
1
1
1
1
0
1
1
1
0
x = Don’t care.
No
The device is currently in
fault mode. The faulted
output is OFF.
Yes
Watchdog has timed out
and the device is in FailSafe mode. The output is
as configured with the
RFS resistor connected to
FSI. RST and WAKE must
be transitioned to logic [0]
simultaneously to bring
the device out of the FailSafe mode or momentarily
tied the FSI terminal to
ground.
Sleep Mode
The default mode of the 33982 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR),
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
Normal Mode
The 33982 is in Normal mode when:
• VPWR is within the normal voltage range.
• RST terminal is logic [1].
• No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to [1]. The WAKE input is capable of
being pulled up to VPWR with a series of limiting resistance that
limits the internal clamp current.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 7, page 18. As long as the WD bit (D7)
of an incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the programmed
value of the WDR the device will operate normally. If an internal
watchdog timeout occurs before the WD bit, the device will
revert to a Fail-Safe mode until the device is reinitialized.
33982
20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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During the Fail-Safe mode, the output will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(Table 12). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, OCLT).
The watchdog, overvoltage, overtemperature, and overcurrent
circuitry (with default value for this one) are fully operational.
Freescale Semiconductor, Inc...
Table 12. Output State During
Fail-Safe Mode
The 33982 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or until
the offending load is removed.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or a
power reset of the device.
RFS (kΩ)
High-Side State
0
Fail-Safe Mode Disabled
10
HS OFF
Overvoltage Fault (Non-Latching)
30
HS ON
The 33982 shuts down the output during an overvoltage fault
(OVF) condition on the VPWR terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in bit OD1 and
cleared after either a valid SPI read or a power reset of the
device.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WDR register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST
terminals from logic [1] to logic [0] or forcing the FSI terminal to
logic [0]. Table 11, page 20, summarizes the various methods
for resetting the device from the latched Fail-Safe mode.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
Loss of VDD
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The output can still
be driven by the direct input IN. The 33982 uses the battery
input to power the output MOSFET-related current sense
circuitry and any other internal logic, providing fail-safe device
operation with no VDD supplied. In this state, the watchdog,
overvoltage, overtemperature, and overcurrent circuitry are
fully operational with default values.
Fault Mode
The 33982 indicates the following faults as they occur by
driving the FS terminal to [0]:
•
•
•
•
Overtemperature Fault (Non-Latching)
Overtemperature fault
Overvoltage and undervoltage fault
Open load fault
Overcurrent fault (high and low)
The FS terminal will automatically return to [1] when the fault
condition is removed, except for overcurrent and in some cases
undervoltage.
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 9, page 19).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
The overvoltage protection and diagnostic can be disabled
through SPI (bit OV_dis).
Undervoltage Shutdown (Latching or Non-Latching)
The output latches OFF at some battery voltage between
5.0 V and 6.0 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
level then returns above 6.0 V, the device can be returned to
the state that it was in prior to the low VPWR excursion. Once the
output latches OFF, the outputs must be turned OFF and ON
again to re-enable them. In the case IN=0, this fault is nonlatched.
The undervoltage protection and diagnostic can be disabled
through SPI (bit UV_dis).
Open Load Fault (Non-Latching)
The 33982 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.
The open load protection can be disabled through SPI (bit
OL_dis).
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Overcurrent Fault (Latching)
The 33982 has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The two
selectable, simultaneously active overcurrent detection levels,
defined by IOCH and IOCL, are illustrated in Figure 4, page 13.
The eight different overcurrent low detection levels (IOCL0,
IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are likewise
illustrated in Figure 4.
Freescale Semiconductor, Inc...
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the output OFF.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF the
output, regardless of the selected tOCL driver.
33982
22
For both cases, the device output will stay off indefinitely until
the device is commanded OFF and then ON again.
Reverse Battery
The output survives the application of reverse voltage as low
as -16 V. Under these conditions, the output’s gate is enhanced
to keep the junction temperature less than 150°C. The ON
resistance of the output is fairly similar to that in the Normal
mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33982 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
disconnection.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PACKAGE DIMENSIONS
PNA SUFFIX
16-TERMINAL PQFN
NON-LEADED PACKAGE
CASE 1402-02
ISSUE B
12
A
12
1
M
2X
Freescale Semiconductor, Inc...
0.1 C
PIN 1
INDEX AREA
12
15
B
16
M
0.1 C
2X
PIN NUMBER
REF. ONLY
0.1 C
2.2 2.20
2.0 1.95
DETAIL G
0.6
0.2
0.1
M
C A B
0.05
M
C
10X
2X
0.95
0.55
0.1
0.05
6X
M
C A B
M
C
0.05
0.00
DETAIL G
0.1 C A B
5.0
4.6
2X 1.075
12
2.5
2.1
2.05
1.55
13
3.55
1.85
1.45
4X
1.05
5.5
5.1
0.1 C A B
14
(2)
6X
16
15
(2X 0.75)
(10X 0.4)
0.1 C A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. MINIMUM METAL GAP SHOULD BE 0.25MM.
0.8
0.4
2X
2.25
1.75
SEATING PLANE
0.9
6X
(10X 0.25)
C
4
VIEW ROTATED 90˚ CLOCKWISE
9X
1
1.1
0.6
0.05 C
(0.5)
(10X 0.5)
10.7
10.3
0.1 C A B
1.28
0.88
0.15
0.05
6 PLACES
11.2
10.8
0.1 C A B
VIEW M-M
CASE 1402-02
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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23
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MC33982/D